TW202306035A - 具有減少的摻質損失及增加的尺寸之接觸件結構及其形成方法 - Google Patents

具有減少的摻質損失及增加的尺寸之接觸件結構及其形成方法 Download PDF

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TW202306035A
TW202306035A TW111113301A TW111113301A TW202306035A TW 202306035 A TW202306035 A TW 202306035A TW 111113301 A TW111113301 A TW 111113301A TW 111113301 A TW111113301 A TW 111113301A TW 202306035 A TW202306035 A TW 202306035A
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TWI830190B (zh
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周孟翰
蕭宜瑄
劉書豪
張惠政
育佳 楊
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台灣積體電路製造股份有限公司
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Abstract

本揭露有關於一種形成方法，其包含形成源極/汲極區域；形成介電層於源極/汲極區域上；以及蝕刻介電層，以形成接觸開口。源極/汲極區域曝露於接觸開口。形成方法更包含沉積延伸至接觸開口內之介電間隙層；蝕刻介電間隙層，以形成接觸間隙壁在接觸開口內；在沉積介電間隙層後，透過接觸開口佈植摻質至源極/汲極區域；以及形成接觸插塞，以填充接觸開口。

Description

具有減少的摻質損失及增加的尺寸之接觸件及其形成方法
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隨著積體電路之尺寸逐漸變得更小，對應之形成製程亦逐漸變得更困難，且傳統上未發生過的問題可能發生。舉例而言，在形成鰭式場效電晶體(鰭式FETs)中，源極/汲極區域之尺寸逐漸變得更小，此使得接觸電阻逐漸增高。
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為了實施本揭露之不同特徵，以下揭露提供許多不同的實施例或實例。以下描述組件及配置之具體實例以簡化本揭露。當然，此些組件及配置僅為實例，而非意指進行限制。例如，形成第一特徵於第二特徵之上方或在其上，於後續描述可包括以直接接觸的方式形成第一特徵與第二特徵之實施例，且亦可包括可在第一特徵與第二特徵之間形成附加的特徵之實施例，以使第一特徵與第二特徵可不直接接觸。此外，本揭露可於各種實例中重複元件符號及/或元件名稱。此重複是為了簡化及清楚的目的，其本身並不規定所討論的各種實施例及/或組態之間的關係。
進一步，在本文中可使用空間相對術語(諸如「在…之下(underlying)」、「在…下方(below)」、「下方的(lower)」、「在…之上(overlying)」、「上方的(upper)」及類似術語)來描述如圖式中所繪示之一個元件或特徵與另一個(另一些)元件或特徵之關係。除了圖式中所描繪之定向之外，空間相對術語意欲涵蓋裝置在使用中或操作中的不同定向。可使用其他方位(旋轉90度或以其他方位)來定向設備，且同樣可相應地解釋本文所使用之空間相對描述詞。
根據多個實施例，提供一種用於電晶體之接觸插塞及其形成方法。根據一些實施例，形成電晶體。然後，形成接觸開口，以露出電晶體之源極/汲極區域。然後，形成共形的介電間隙層，且其延伸至接觸開口，並接著被蝕刻，以形成接觸間隙壁。之後，進行佈植製程，以佈植摻質至源極/汲極區域及接觸間隙壁。然後，形成矽化區域及接觸插塞於接觸開口內。藉由在形成接觸間隙壁後進行佈植製程，由於佈植，接觸插塞之橫向尺寸未實質減小。再者，減少在源極/汲極區域內之摻質損失。根據一些實施例，繪示形成電晶體之中間階段。在一些繪示的實施例中，鰭式場效電晶體(鰭式FETs)用於做為例子，以解釋本揭露之概念。如平面電晶體及環繞式閘極(GAA)電晶體等之其他電晶體亦可採用本揭露之概念。討論一些實施例之一些變化。透過多種視圖及繪示之實施例，相似元件符號用於表示相似元件。
圖1至圖6、圖7A、圖7B、圖8A、圖8B及圖9至圖15係繪示根據本揭露之一些實施例於形成電晶體(例如，其可為鰭式FETs)之中間階段的剖面圖及透視圖。製程亦示意性反映在圖19所示之製程流程300中。
圖1係繪示初始結構之透視圖。初始結構包含晶圓10，其更包含基材20。晶圓10包含裝置區域100及裝置區域200，個別用以形成電晶體。根據本揭露之一些實施例，於裝置區域100及裝置區域200內形成之電晶體為相反的導電型。舉例而言，於裝置區域100內形成之電晶體可為p型電晶體，且於裝置區域200內形成之電晶體可為n型電晶體。根據其他實施例，於裝置區域100內形成之電晶體可為n型電晶體，且於裝置區域200內形成之電晶體可為p型電晶體。根據另一些實施例，於裝置區域100及裝置區域200內形成之電晶體為如p型或n型之相同的導電型。
基材20可為半導體基材，其可為矽基材、矽鍺基材或由其他半導體材料所形成之基材。根據一些實施例，基材20包含塊體矽基材，以及在此塊體矽基材上之磊晶矽鍺(SiGe)層或鍺層(於其內沒有矽)。基材20可以p型或n型雜質摻雜。如淺溝槽隔離(STI)區域之隔離區域22可形成為延伸至基材20。在相鄰的STI區域22間之部分基材20分別係稱作半導體條帶124及224，且此些半導體條帶124及224在裝置區域100和200內。
STI區域22可包含襯墊氧化物(liner oxide)(未顯示)。襯墊氧化物可由熱氧化物來形成，且此熱氧化物係透過基材20的表面層之熱氧化所形成。襯墊氧化物亦可為使用如原子層沉積(ALD)、高密度電漿化學氣相沉積(HDPCVD)或化學氣相沉積(CVD)所形成之沉積的氧化矽。此些STI區域22亦可包含在此襯墊氧化物上之介電材料，其中介電材料可使用可流動式化學氣相沉積(FCVD)、旋轉塗佈或其類似方法所形成。
參照圖2，凹陷此些STI區域22，以使半導體條帶124和224之頂部突伸高於相鄰STI區域22之頂表面122A和222A，以分別形成複數個突伸鰭片124’和224’。相應的製程繪製為如圖19所示之製程流程300中之製程302。可使用乾式蝕刻製程進行蝕刻，此乾式蝕刻製程例如可使用做為蝕刻氣體之NH 3及NF 3進行。於蝕刻製程之期間，可產生電漿，以用於蝕刻。蝕刻製程亦可包含氬氣。根據本揭露之替代的實施例，使用濕式製程進行STI區域22之凹陷。舉例而言，蝕刻化學品可包含稀釋的HF溶液。
於上述之實施例中，可藉由任何適合的方法圖案化鰭片。舉例而言，可使用一或多道微影製程圖案化鰭片，微影製程包含雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。通常，雙重圖案化或多重圖案化製程結合微影及自對準製程，以例如使所創造之圖案相較於其他使用單一且直接微影製程可獲得之圖案，具有更小的間距。舉例而言，在一實施例中，犧牲層係形成於基材上，且使用微影製程來圖案化。使用自對準製程沿著圖案化後的犧牲層形成間隙壁。然後，移除犧牲層，且剩餘的間隙壁或心軸可接著用以圖案化鰭片。
參照圖3，虛設閘極堆疊130和230分別形成於突伸鰭片124’和224’之頂表面及側壁上。相應的製程繪製為如圖19所示之製程流程300中之製程304。虛設閘極堆疊130可包含虛設閘極介電質132，以及於此虛設閘極介電質132上之虛設閘極電極134。虛設閘極堆疊230可包含虛設閘極介電質232，以及於虛設閘極介電質232上之虛設閘極電極234。虛設閘極介電質132和232可透過熱氧化、化學氧化或沉積製程所形成，且舉例而言，可由氧化矽所形成或包含氧化矽。圖3係繪示沉積的閘極介電質132和232，其包含於STI區域22上延伸之複數個水平部分。此外，當透過氧化形成虛設閘極介電質132和232時，虛設閘極介電質132和232係形成於突伸鰭片124’和224’之表面上，且不包含STI區域22上之水平部分。
舉例而言，可使用非結晶矽或多晶矽形成虛設閘極電極134和234，且如非結晶碳之其他材料亦可使用。虛設閘極堆疊130和230亦分別可包含硬遮罩層136和236。硬遮罩層136和236可由氮化矽、碳氮化矽或其類似物質，或者此些物質之多層所形成。虛設閘極堆疊130和230之每一者分別橫越單一或多個突伸鰭片124’和224’。
接著，閘極間隙壁138和238分別形成於虛設閘極堆疊130和230之側壁上。與此同時，鰭間隙壁(未顯示)亦可形成於突伸鰭片124’和224’之側壁上。根據本揭露之一些實施例，閘極間隙壁138和238由如氮氧化矽(SiON)、碳氮氧化矽(SiOCN)、氮化矽或其類似物之介電材料所形成，或者包含前述之介電材料，且可具有單一層結構或包含複數個介電層之多層結構。舉例而言，閘極間隙壁138和238可包含低k值之介電子層(sub-layer)及非低k值之介電子層。閘極間隙壁138和238之形成可包含一或多個共形沉積製程，且接著一或多個非等向蝕刻製程。共形沉積製程可使用ALD、CVD或其類似方法進行。
然後，進行蝕刻製程，以蝕刻部分之突伸鰭片124’和224’，此些部分未被對應之虛設閘極堆疊130和230及閘極間隙壁138和238所覆蓋，且此造成圖4所示之結構。相應的製程繪製為如圖19所示之製程流程300中之製程306。蝕刻製程可為非等向，且因此直接位於相應的虛設閘極堆疊130與230及閘極間隙壁138與238下方的鰭片124’和224’之此些部分係被保護，且不被蝕刻。根據一些實施例，凹陷之半導體條帶124和224之頂部可低於相鄰STI區域22之頂表面。凹陷140和240相應地形成於此些STI區域22間。裝置區域100和200內之凹陷可以一般的蝕刻製程或以多個分割製程來進行，且此些凹陷140之深度可等於或不同於凹陷240之深度。
接著，藉由從此些凹陷140和240選擇性成長半導體材料來形成磊晶區域(源極/汲極區域)，此造成圖5中之結構。相應的製程繪製為如圖19所示之製程流程300中之製程308。磊晶區域之材料係關於對應的裝置區域是用以形成p型電晶體或者n型電晶體。根據一些實施例，當相應的電晶體為p型電晶體時，對應的磊晶區域142或242可包含以硼摻雜的矽鍺(SiGeB)、硼化矽(SiB)或其類似物質，或者此些物質之多層，且其為p型的。根據一些實施例，當相應的電晶體為n型電晶體時，對應的磊晶區域142或242可由磷化矽(SiP)、碳磷化矽(SiCP)、砷化矽(SiAs)或其類似物質，或者此些物質之多層所形成，或者包含前述之物質，且其為n型的。當磊晶區域142和242為相反的導電型時，以分割製程，且使用不同的遮罩(未顯示)進行磊晶區域142和242之形成。
在以磊晶半導體材料填充凹陷140和240後，磊晶區域142和242進一步的磊晶成長導致磊晶區域142和242水平延伸，且可能形成刻面(facets)。從相鄰的凹陷成長的此些磊晶區域可合併，以形成一個大的磊晶區域，或者當它們沒有合併時，可保持為分離的磊晶區域。磊晶區域142和242形成相應的電晶體之源極/汲極區域，且亦可分別稱作源極/汲極區域142和242。
圖6係繪示用以沉積接觸蝕刻停止層(CESL)46及層間介電層(ILD)48之透視圖。此透視圖繪示為如圖19所示之製程流程300之製程310。根據本揭露之一些實施例，CESL 46係由氮化矽、碳氮化矽或其類似物質所形成。舉例而言，可透過如ALD或CVD之共形沉積製程形成CESL 46。ILD 48形成於CESL 46上，且可使用如FCVD、旋轉塗佈、CVD或其類似方法所形成。ILD 48可由磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜磷酸矽酸鹽玻璃(BPSG)、四乙氧基矽烷(TEOS)或其類似物質所形成。可進行如化學機械研磨(CMP)製程或機械研磨(grinding)製程之平坦化製程，以相互平整CESL 46、ILD 48、虛設閘極堆疊130和230及閘極間隙壁138和238之多個頂表面。
在形成圖6所示之結構後，以金屬閘極及取代閘極介電質取代包含硬遮罩層136和236、虛設閘極電極134和234及虛設閘極介電質132和232之虛設閘極堆疊130和230，此形成取代閘極堆疊。相應的製程繪製為如圖19所示之製程流程300中之製程312。為了形成取代閘極，透過蝕刻製程移除如圖6所示之取代閘極堆疊130和230，以分別形成在多個閘極間隙壁138之間與在多個閘極間隙壁238之間的溝槽。因此，突伸鰭片124’和224’之頂表面及側壁係曝露於所製得之此些溝槽。
如繪示晶圓10之多個部分的透視圖及剖面圖之圖7A及圖7B所示，之後，取代閘極堆疊150和250係形成於此些溝槽內。根據本揭露之一些實施例，取代閘極堆疊150包含閘極介電質152，以及在對應之閘極介電質152上之閘極電極158。取代閘極堆疊250包含閘極介電質252，以及在對應之閘極介電質252上之閘極電極258。如圖7B所示，閘極介電質152和252分別包含界面層(ILs)154和254及其上的高k值介電質156和256。ILs 154和254分別形成於突伸鰭片124’和224’之曝露表面上。ILs 154和254個別可包含如氧化矽之氧化層，且此氧化層係透過熱氧化突伸鰭片124’和224’的表面層、化學氧化製程或沉積製程所形成。
圖7B繪示如圖7A所示之剖面7B-7B。如圖7B所示，閘極介電質152和252可更分別包含形成於ILs 154和254上之高k值介電層156和256。高k值介電層156和256可由如氧化鉿、氧化鑭、氧化鋁、氧化鋯、氮化矽或其類似物質之介電材料所形成，或包含前述之介電材料。高k值介電材料之介電常數(k值)高於3.9，且可更高於約7.0。高k值介電層156和256形成為共形層，且於突伸鰭片124’和224’之側壁及閘極間隙壁138和238之側壁上延伸。根據本揭露之一些實施例，使用ALD或CVD形成高k值介電層156和256。
理解的是，雖然圖7B繪示磊晶區域142和242之頂表面成為共平面於突伸鰭片124’和224’之頂表面，但磊晶區域142和242之頂表面可高於相應的突伸鰭片124’和224’之頂表面。
閘極電極158和258(圖7B)可包含複數個堆疊的導電子層。閘極電極158和258之形成可包含如ALD或CVD之共形沉積製程，以使此些堆疊的導電子層之垂直部分的厚度與其水平部分的厚度實質彼此相等。
閘極電極158和258可分別包含金屬層158A和258A，其每一者包含擴散阻障層，以及在此擴散阻障層上之一個(或多個)功函數層(未個別顯示)。擴散阻障層可由氮化鈦(TiN)所形成，且氮化鈦可以(或未以)矽摻雜。功函數層決定對應之閘極的功函數，且包含由不同的材料所形成之至少一層或複數層。根據相應的鰭式FET為n型FET或p型FET來選擇功函數層之材料。舉例而言，當裝置區域100為p型裝置區域時，在金屬層158A內之功函數層可包含TiN層。當裝置區域200為n型裝置區域時，在金屬層258A內之相應的功函數層可包括含鋁之金屬層(如TiAl、TiAlC、TiAlN或其類似材料)。在沉積功函數層後，形成可為另一個TiN層之阻障層。
若溝槽未被相應的金屬層158A和258A全部填充，閘極電極158和258亦可包含填充於剩餘的溝槽內之相應的填充金屬158B和258B。舉例而言，填充金屬可由鎢或鈷所形成。在形成填充材料後，進行如CMP製程或化學研磨製程之平坦化製程，以移除ILD 48上之部分沉積層。閘極介電質152與252及閘極電極158與258之剩餘部分以下合併稱作取代閘極堆疊150和250。
根據一些實施例，然後形成自對準閘極遮罩160和260。相應的製程亦繪製為如圖19所示之製程流程300中之製程312。自對準閘極遮罩160和260係自對準於其下之取代閘極堆疊150和250，且由如ZrO 2、Al 2O 3、SiON、SiCN、SiO 2或其類似材料之介電材料所形成。形成製程可包含透過蝕刻凹陷取代閘極堆疊150和250，以形成複數個凹陷；填充介電材料至此些凹陷內；以及進行平坦化製程，以移除多餘部分的介電材料。閘極遮罩160和260、閘極間隙壁138和238、CESL 46及ILD 48之頂表面於此時實質係共平面。
參照圖8A及圖8B，蝕刻ILD 48及CESL 46，以形成源極/汲極接觸開口162和262。相應的製程繪製為如圖19所示之製程流程300中之製程314。圖8B繪製如圖8A所示之剖面8B-8B。CESL 46做為於蝕刻ILD 48時之蝕刻停止層，且然後蝕刻CESL 46，以曝露下方之源極/汲極區域142和242。接觸開口162和262可同時形成或可分開形成。如圖8B所示，由於過蝕刻，開口162和262可稍微延伸至源極/汲極區域142和242中。
根據一些實施例，參照圖8B，在形成接觸開口162和262後，部分的CESL 46及ILD 48留在相應的接觸開口162和262之一側或兩側上。CESL 46及ILD 48之相應的剩餘部分亦在後續摻質佈植及矽化製程中作為間隙壁的一部分。據此，在接觸開口162和262之相反的兩側上之CESL 46及ILD 48之剩餘部分稱作間隙壁163和263。根據替代的實施例，完全移除在相鄰閘極間隙壁138間及在相鄰閘極間隙壁238間之部分的CESL 46及ILD 48之此些部分。因此，閘極間隙壁138和238之側壁分別曝露於對應的接觸開口162和262。
舉例而言，由於曝露於開放的空氣或其他含有氧氣之氣體及/或含有水氣之氣體中，源極/汲極區域142和242之曝露的表面可能被氧化。由於清潔製程在形成接觸開口162和262後進行，所以亦可能導致氧化，其中清潔製程之清潔溶液可包含水。氧化造成氧化層164和264分別形成於源極/汲極區域142和242之曝露表面上。取決於下方之源極/汲極區域142和242的材料，氧化層164和264可包含氧化矽、氧化矽鍺或其類似物質。根據一些實施例，氧化層164和264具有範圍約2nm至約4nm之厚度。
根據一些實施例，接觸開口162和262具有如相同長度、寬度、直徑等之相同的橫向尺寸。舉例而言，接觸開口162之寬度W1可等於接觸開口262之寬度W2。寬度W1和W2可分別在閘極堆疊150和250之中間高度測得。再者，接觸開口162可形成在相鄰閘極間隙壁138間之中間，且接觸開口262可形成在相鄰閘極間隙壁238間之中間。相應地，間隙壁163之厚度T1可等於間隙壁263之厚度T2，其中厚度T1和T2亦可分別在閘極堆疊150和250之中間高度測得。
參照圖9，介電間隙壁層66形成以分別延伸至接觸開口162和262內，以及在CESL 46及ILD 48之側壁上。相應的製程繪製為如圖19所示之製程流程300中之製程316。如從如圖8A所示之源極/汲極區域142和242之形狀所能理解的，介電間隙層66亦延伸於源極/汲極區域142和242之側壁上。根據本揭露之一些實施例，使用如CVD或ALD之共形沉積製程形成介電間隙層66。介電間隙層66可為具有大於3.9的k值之高k值介電層，以使其具備良好的絕緣能力。候選材料包含SiN、SiOCN、Al xO y、HfO 2或其類似材料。舉例而言，介電間隙層66之厚度可約2nm至約6nm之範圍內。
參照圖10，進行非等向蝕刻製程，以使在接觸開口162和262內部之介電間隙層66之水平部分被移除，且使介電間隙層66之垂直部分被保留，以分別形成接觸間隙壁166和266。相應的製程繪製為如圖19所示之製程流程300中之製程318。當從晶圓10之頂部俯視時，接觸間隙壁166和266個別可形成一個環狀物。由於在接觸開口162和262內之介電間隙層66之部分具有相同的厚度，且進一步，因為寬度W1和W2(排除接觸間隙壁166和266之接觸開口162和262之寬度)彼此相等，所以接觸開口162之寬度W3可等於接觸開口262之寬度W4。寬度W3和W4可分別在閘極堆疊150和250之中間高度測得。
參照圖11，形成佈植遮罩270。佈植遮罩270可包含光阻，且可為單一層遮罩、三層遮罩、四層遮罩或其類似遮罩。相應的製程繪製為如圖19所示之製程流程300中之製程320。以覆蓋於裝置區域200內的結構之剩餘的部分圖案化佈植遮罩270，而使得在裝置區域100內的結構曝露。
再者，進行佈植製程172，以佈植摻質至裝置區域100。相應的製程繪製為如圖19所示之製程流程300中之製程322。摻質為與在裝置區域100內所形成之電晶體的導電型之相同的導電型。舉例而言，當p型電晶體將形成於裝置區域100內(且源極/汲極區域142為p型)時，佈植的摻質亦為p型，且可包含硼、BF 2、鎵、銦或其類似物質，或者其組合。當n型電晶體將形成於裝置區域100內(且源極/汲極區域142為n型)時，佈植的摻質可包含砷、磷、銻或其組合。藉由選擇性遮罩裝置區域200，以及佈植至源極/汲極區域142，在裝置區域100和200內之裝置可經不同的處理。舉例而言，當p型電晶體及n型電晶體將分別形成於裝置區域100和200內時，可佈植p型摻質，以增加在源極/汲極區域142內之p型摻質濃度(以使源極/汲極區域電阻可降低)，而保留在源極/汲極區域242內之n型摻質濃度不改變。當在裝置區域100和200內之裝置為如p型或n型之相同的導電型時，選擇性佈植亦可用以微調在裝置區域100和200內之電晶體的裝置性能，以使電晶體可具備優異的性能。
佈植製程172之佈植能量可約0.3kev至約50kev之範圍內。佈植製程172造成源極/汲極區域142之頂部被佈植，以內含摻質，而使源極/汲極區域142之底部未被佈植。佈植劑量可約5E13 /cm 2至約1E16 /cm 2之範圍內。佈植可為垂直的或傾斜的，且傾斜角度可小於約60度。在佈植期間，可提高晶圓溫度，例如約100℃至500℃之範圍內。
圖11示意繪示經佈植的區域，其中經佈植的區域使用對應的符號表示，在其後面標註「’」。舉例而言，經佈植的源極/汲極區域142、接觸間隙壁166及閘極遮罩160之頂部可分別替代以142’、166’及160’表示。間隙壁163亦可為經佈植的。由於佈植，經佈植的部分因佈植損害及因加入佈植的摻質而體積膨脹。間隙壁163和166的厚度分別以T1’及T3’表示，其中厚度T’大於厚度T1(圖10)，且厚度T3’大於厚度T3(圖10)。厚度T1和T3分別為間隙壁163和166在進行佈植製程前的厚度。再者，厚度T1’可大於間隙壁263之厚度T2，且厚度T3’可大於間隙壁266之厚度T4。
根據一些實施例，總厚度(T1’+T3’)大於總厚度(T1+T3)(圖10，在佈植製程前)約2Å至約1nm之範圍內的差值。再者，間隙壁263和266亦具有總厚度(T2+T4)，此總厚度可等於總厚度(T1+T3))。據此，接觸間隙壁163’和166’之總厚度(T1’+T3’)亦大於接觸間隙壁263和266之總厚度(T2+T4)。接觸間隙壁163’和166’之膨脹可導致後續形成的接觸插塞的寬度不利的縮減，並且導致接觸電阻不利的增加。
在佈植製程172期間，由於遮罩裝置區域200，接觸間隙壁266和接觸間隙壁263(以及在間隙壁263內之ILD 48及CESL 46)可不具如硼、鎵、銦或其類似物質之摻雜的摻質，取決於在佈植製程172中所摻雜的摻質。再者，裝置區域200可不以具有相同於源極/汲極區域242的導電型之任何摻質來佈植。舉例而言，當源極/汲極區域242為n型區域時，在由其所製得之鰭式FET 290(圖15)內的接觸間隙壁266及接觸間隙壁263可不具磷、砷、銻或其類似物質。
在佈植製程後，移除佈植遮罩270。所製得之結構繪示於圖12中。相應的製程繪製為如圖19所示之製程流程300中之製程324。曝露出氧化層164和264。由於佈植，接觸間隙壁163和163’橫向擴張，而接觸間隙壁263和266沒有擴張，所以接觸開口162之寬度W3’小於接觸開口262之寬度W4。
在後續製程中，進行清潔製程，以移除氧化層164和264，並露出源極/汲極區域142和242。相應的製程繪製為如圖19所示之製程流程300中之製程326。所製得之結構繪示於圖13中。根據一些實施例，當使用乾式清潔時，清潔製程可使用NF 3與NH 3之混合物、HF與NH 3之混合物或其類似物進行。當使用濕式清潔時，亦可使用稀釋的HF溶液進行清潔製程。在清潔製程期間，雖然接觸間隙壁166’和266以低於相應的氧化層164和264的蝕刻速度被薄化，但接觸間隙壁166’和266曝露於清潔化學品而亦被薄化。在圖11中，接觸間隙壁166’和266之所製得的厚度分別稱作厚度T3’’和厚度T4’’，此二厚度分別小於厚度T3’和T4’(未顯示，圖11中未顯示)。根據一些實施例，間隙壁166’和266之厚度可縮減約0.5nm至約2nm之範圍內的數值。
經佈植的接觸間隙壁166’具有大於接觸間隙壁266的蝕刻速度。據此，由於接觸間隙壁166’所增加的蝕刻速度大於接觸間隙壁266的蝕刻速度，所以抵銷(更減少)接觸間隙壁166’(由於佈植)所增加的厚度。藉由進行佈植製程，在形成接觸間隙壁166’(接觸間隙壁166)之後(而不是之前)，至少減弱，或者實質消除佈植對於接觸間隙壁166’的厚度效應。舉例而言，厚度T3’’小於厚度T3’(圖11)，且可等於、小於或大於厚度T3(圖10)。
再者，藉由在形成接觸間隙壁166’(接觸間隙壁166)後進行佈植製程，厚度差值((T1’+T3’’)-(T2+T4’’))減小，且可被消除，其中(T1’+T3’’)為接觸間隙壁163和166’之總厚度，且(T2+T4’’)為接觸間隙壁263和266之總厚度。舉例而言，厚度差值可小於約0.5nm，且可小於約0.2nm。再者，於圖13中，接觸開口162之寬度W3’’可等於、小於或大於接觸開口262之寬度W4’’。換句話說，由於佈植，開口162之寬度減少第一數量，且清潔及薄化製程導致開口162之寬度增加第二數量。第二數量可等於、大於或小於第一數量。根據一些實施例，調整清潔製程(如化學品及/或時間區間)，以使寬度W3’’等於寬度W4’’，且最大化所製得之接觸插塞的寬度，而不犧牲由接觸間隙壁166所提供之保護。此外，厚度T1’可大於厚度T2，且厚度T3’’將小於厚度T4’’。
圖14及圖15繪示源極/汲極矽化區域之形成。參照圖14，舉例而言，使用物理氣相沉積(PVD)沉積金屬層76(如鈦層或鈷層)。然後，阻障層78可為如氮化鈦層及氮化鉭層之金屬氮化層，且阻障層78沉積於金屬層76上。相應的製程繪製為如圖19所示之製程流程300中之製程328。藉由氮化金屬層76之頂層，及保留金屬層76之底層不進行氮化來形成阻障層78。此外，透過如CVD製程或ALD製程之沉積製程形成阻障層78。金屬層76及阻障層78皆可為共形的，且延伸至接觸開口162和262。
然後，進行退火製程，以使用在源極/汲極區域142和242內之矽(及鍺(若有鍺的話))與金屬層76進行反應。如圖15所示，因而形成源極/汲極矽化區域180和280。相應的製程繪製為如圖19所示之製程流程300中之製程330。退火製程可透過快速熱退火(RTA)、爐退火或其類似方法進行。在矽化製程後，保留金屬層76之一些側壁部分。
根據一些實施例，如圖15所示，移除阻障層78及剩餘的金屬層76，接著形成額外阻障層182和282。根據一些實施例，阻障層182和282亦由氮化鈦、氮化鉭或其類似物質所形成。接著，沉積金屬材料於阻障層182和282上且與阻障層182和282接觸。金屬材料可包含鎢、鈷或其類似材料。然後，進行如CMP製程或機械研磨製程之平坦化製程，以移除阻障層182和282及金屬材料之多餘的部分。金屬材料之剩餘部分稱作金屬區域184和284。擴散阻障層182及金屬區域184共統形成源極/汲極插塞186，且擴散阻障層282及金屬區域284共統形成源極/汲極插塞286。相應的製程繪製為如圖19所示之製程流程300中之製程332。因此，形成鰭式FETs 190和290。
根據替代的實施例，取代移除阻障層78及剩餘的金屬層76，可透過蝕刻往後拉阻障層78，以使其頂表面低於ILD 48之頂表面，並因此開口具有更寬的頂部，以易於填充間隙。額外阻障層182和282係形成於被往後拉的阻障層78及金屬層76的剩餘部份上(未顯示)。金屬區域184和284係更形成於額外阻障層182和282上。
圖16及圖17繪示根據本揭露之替代的實施例於形成鰭式FETs及對應的接觸插塞之中間階段的剖面圖。除了在非等向蝕刻用以形成接觸間隙壁的間隙層之前(非之後)進行佈植之外，此些實施例相似於先前的實施例。除非另有明確規定，在此些實施例中之組成的材料及形成製程基本上相同於其類似者，其以與先前圖式中所示之先前實施例相似之元件符號表示。因此，可在先前實施例之討論中找到關於圖16及圖17中所示之形成製程及組成的材料之細節。
此些實施例之初始製程相同於圖1至圖6、圖7A、圖7B、圖8A、圖8B及圖9所示之製程。接著，取代蝕刻間隙層66來形成接觸間隙壁，製程進行到圖16所示之製程。形成佈植遮罩270，且進行佈植製程172，以摻雜摻質至裝置區域100。在佈植期間，間隙層66之未被移除的水平部分可助於減少對於下方之源極/汲極區域142的損害。在佈植製程172後，移除佈植遮罩270，接續非等向蝕刻間隙層66，以使接觸間隙壁166’和266形成。所製得之結構繪示於圖17中。後續製程基本上相同於如圖13至圖15所示之製程，且於此不重複。所製得之鰭式FETs 190和290亦基本上相同於如圖15所示之鰭式FET。
圖18示意繪示根據一些實施例之於間隙壁163、接觸間隙壁166’及接觸插塞186內所佈植之摻質的分佈。在閘極堆疊150之中間高度獲得分佈。曲線191代表一種可能的分佈。由於在如圖13中所示之清潔製程中蝕刻間隙壁166’，所以(在圖11所示之製程中被導入之)摻質的尖峰濃度可在清潔製程後被曝露於側壁。因此，由於後續的擴散，在最後結構(圖15)中之摻質的尖峰濃度可在接觸間隙壁166’及接觸插塞186間之界面。當進行傾斜佈植，且更深入佈植摻質至接觸間隙壁166’及間隙壁163時，摻質的尖峰濃度可在如曲線192、193或194所示之位置。
本揭露之實施例具有一些優越的特徵。藉由採用本揭露之實施例，相較於傳統製程，由於用以形成接觸插塞之多個製程，所以降低來自於源極/汲極區域之摻質損失。在傳統製程中，在形成接觸開口後，且在沉積及非等向蝕刻用以形成接觸間隙壁之間隙壁層前，進行佈植摻質。據此，因為非等向蝕刻間隙層導致已經佈植的摻質發生摻質損失，所以摻質損失嚴重。在本揭露之實施例中，因為在非等向蝕刻後，進行佈植，所以沒有由非等向蝕刻所導致之摻質損失。因此，在本揭露之實施例中，摻質損失低於傳統製程之摻質損失。舉例而言，多個實驗例子已揭示，在根據本揭露之一些實施例所形成之例子的源極/汲極區域內之最後摻質濃度高於使用傳統製程所形成之例子的源極/汲極區域內之最後摻質濃度約6百分比。
進一步，因為在清潔製程期間，經佈植的接觸間隙壁具有高於未經佈植的接觸間隙壁的蝕刻速度，所以抵銷由佈植製程所導致之接觸間隙壁之膨脹，且相較於若未經佈植之接觸間隙壁，可更減少膨脹的接觸間隙壁之厚度。因此，所製得之接觸插塞186的寬度(臨界尺寸)可恢復到相同於接觸插塞(如接觸插塞286)之數值，並且改善接觸插塞的寬度於晶片內之均勻性。舉例而言，採用本揭露之實施例形成一些示例性晶圓。在接觸插塞186和286之寬度間的平均差值小於約0.2nm(或小於約0.1nm)，且小於約2百分比或1百分比之平均寬度。相較之下，若使用傳統製程，接觸插塞186之平均寬度小於接觸插塞286之平均寬度，接觸插塞186和286之寬度的平均差值為約1nm，且可高達約7百分比之平均寬度。
根據一些實施例，形成方法包含形成第一源極/汲極區域；形成介電層於第一源極/汲極區域上；蝕刻介電層以形成第一接觸開口，其中第一源極/汲極區域曝露於第一接觸開口；沉積延伸至第一接觸開口之介電間隙層；蝕刻介電間隙層，以形成第一接觸間隙壁在第一接觸開口內；在沉積介電間隙層後，透過第一接觸開口佈植摻質至第一源極/汲極區域；以及形成第一接觸插塞，以填充第一接觸開口。
在一實施例中，摻質係佈植於第一接觸間隙壁上。在一實施例中，摻質穿透過介電間隙層之底部，以到達第一源極/汲極區域。在一實施例中，形成第一源極/汲極區域包含原位摻雜p型摻質，且其中佈植所導入之摻質亦為p型摻質。在一實施例中，佈植摻質導致第一接觸開口之寬度減少第一數量，且形成方法包含：每次在佈植摻質至第一源極/汲極區域後且在形成第一接觸插塞以填充第一接觸開口前，進行清潔製程，以移除在第一源極/汲極區域上之氧化層，其中於清潔製程導致第一接觸開口之寬度增加第二數量，且第二數量等於或大於第一數量。
在一實施例中，第二數量大於第一數量。在一實施例中，蝕刻介電層包含蝕刻層間介電質及蝕刻層間介電質下之接觸蝕刻停止層。在一實施例中，在蝕刻介電層，以形成第一接觸開口後，介電層之一部分殘留於第一接觸開口之相對的兩側，以形成額外間隙壁。在一實施例中，形成方法更包含：形成第二源極/汲極區域；蝕刻介電層，以形成第二接觸開口，其中第二源極/汲極區域曝露於第二接觸開口；蝕刻介電間隙層，以形成第二接觸間隙壁在第二接觸開口內，其中當佈植摻質時，遮蔽第二接觸間隙壁，以避免被佈植；以及形成第二接觸插塞，以填充第二接觸開口。在一實施例中，第一源極/汲極區域為p型的，且第二源極/汲極區域為n型的。
根據本揭露之一些實施例，形成方法包含蝕刻層間介電及在層間介電質下之接觸蝕刻停止層，以形成第一接觸開口及第二接觸開口，其中第一源極/汲極區域及第二源極/汲極區域分別位於第一接觸開口及第二接觸開口之下，且曝露於第一接觸開口及第二接觸開口；沉積延伸至第一接觸開口及第二接觸開口內之介電間隙層；蝕刻介電間隙層，以形成第一接觸間隙壁於第一接觸開口內，且形成第二接觸間隙壁於第二接觸開口內；形成佈植遮罩於第二接觸間隙壁及第二源極/汲極區域上；透過第一接觸開口佈植摻質至第一源極/汲極區域；以及移除佈植遮罩。
在一實施例中，形成方法更包含在移除佈植遮罩後，進行蝕刻製程，以移除在第一源極/汲極區域上之第一氧化層，並移除在第二源極/汲極區域上之第二氧化層。在一實施例中，在佈植摻質前，第一接觸間隙壁具有第一厚度，且在佈植後，第一接觸間隙壁具有大於第一厚度之第二厚度，且其中在蝕刻製程後，第一接觸間隙壁具有等於或小於第一厚度之第三厚度。在一實施例中，第一源極/汲極區域及第二源極/汲極區域為相反的導電型。在一實施例中，第一源極/汲極區域及第二源極/汲極區域為相同的導電型。在一實施例中，佈植所佈植之摻質具有相同於第一源極/汲極區域之導電型。在一實施例中，佈植所佈植之摻質具有相反於第二源極/汲極區域之導電型。
根據本揭露之一些實施例，結構包含第一半導體區域；於此第一半導體區域上之第一閘極堆疊；於此第一閘極堆疊之一側上之第一源極/汲極區域，其中第一源極/汲極區域為第一導電型；於此第一源極/汲極區域上之第一矽化區域；於第一矽化區域上之第一接觸插塞；環繞並接觸第一接觸插塞之第一接觸間隙壁；以及在第一接觸插塞及第一接觸間隙壁內之第一導電型之摻質，其中摻質具有在第一接觸間隙壁內，或在第一接觸間隙壁與第一接觸插塞間之界面之尖峰濃度。
在一實施例中，尖峰濃度在界面。在一實施例中，結構更包含第二半導體區域；於此第二半導體區域上之第二閘極堆疊；於此第二閘極堆疊之一側上之第二源極/汲極區域，其中第二源極/汲極區域為相反於第一導電型之第二導電型；於此第二源極/汲極區域上之第二矽化區域；於此第二矽化區域上之第二接觸插塞，其中第一接觸插塞及第二接觸插塞實質具有相同的寬度；環繞並接觸第二接觸插塞之第二接觸間隙壁；其中第一接觸間隙壁及第二接觸間隙壁係由相同的介電材料所形成，且其中第二觸接間隙壁薄於第一接觸間隙壁。
前述內容概述數個實施例之特徵，以致於本揭露所屬技術領域中具有通常知識者可更好地理解本揭露之態樣。本揭露所屬技術領域中具有通常知識者應瞭解的是，他們可容易地以本揭露做為設計或修改而用於實施本文所介紹之實施例之相同目的及/或達成相同優點的其他製程及結構之基礎。本揭露所屬技術領域中具有通常知識者亦應認知的是，此類等效構造不脫離本揭露之精神及範疇，且他們可在不脫離本揭露之精神及範疇的情況下對本文作出各種改變、替換及變更。
10:晶圓 100,200:裝置區域 124,224:半導體條帶 124’,224’:突伸鰭片 122A,222A:頂表面 130,230,150,250:閘極堆疊 132,232,152,252:閘極介電質 134,234,158,258:閘極電極 136,236:硬遮罩層 138,238:閘極間隙壁 140,240:凹陷 142,142’,242:源極/汲極區域 154,254:界面層 156,256:介電層,介電質 158A,258A:金屬層 158B,258B:填充金屬 160,160’,260:閘極遮罩 162,262:開口 164,264:氧化層 163,163’,263:間隙壁 166,166’,266:接觸間隙壁 172:佈植製程 180,280:矽化區域 184,284:金屬區域 186:插塞 190,290:鰭式FET 191,192,193,194:曲線 20:基材 22:隔離區域,STI區域 270:佈植遮罩 290:鰭式FET 302,304,306,308,310,312,314,316,318,320,322,324,326,328,330,332:製程 46:接觸蝕刻停止層 48:層間介電層 66:間隙層 76:金屬層 78,182,282:阻障層 W1,W2,W3,W3”,W4,W4”:寬度 T1,T1’,T2,T3,T3’,T3”,T4,T4’,T4”:厚度
當結合圖式閱讀時，從以下詳細描述中，可最佳地理解本揭露的態樣。注意的是，根據業界之標準慣例，各種特徵並未按比例繪製。事實上，為了清楚討論，可任意放大或縮小各種特徵之尺寸。 圖1至圖6、圖7A、圖7B、圖8A、圖8B及圖9至圖15係繪示根據一些實施例於形成鰭式場效電晶體(鰭式FETs)及接觸插塞之中間階段的剖面圖及透視圖。 圖16及圖17係繪示根據一些實施例於形成鰭式FETs及接觸插塞之中間階段的剖面圖。 圖18係繪示根據一些實施例之於鰭式FET內所佈植之摻質的分佈。 圖19係繪示根據一些實施例之用以形成鰭式FETs的製程流程圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
300:製程流程
302,304,306,308,310,312,314,316,318,320,322,324,326,328,330,332:製程

Claims (20)

  1. 一種接觸件結構之形成方法，包含： 形成一第一源極/汲極區域； 形成一介電層於該第一源極/汲極區域上； 蝕刻該介電層，以形成一第一接觸開口，其中該第一源極/汲極區域曝露於該第一接觸開口； 沉積一介電間隙層，其中該介電間隙層延伸至該第一接觸開口； 蝕刻該介電間隙層，以形成一第一接觸間隙壁在該第一接觸開口內； 在該沉積該介電間隙層之操作後，透過該第一接觸開口佈植一摻質至該第一源極/汲極區域；以及 形成一第一接觸插塞，以填充該第一接觸開口。
  2. 如請求項1所述之接觸件結構之形成方法，其中該摻質係佈植於該第一接觸間隙壁上。
  3. 如請求項1所述之接觸件結構之形成方法，其中該摻質穿透過該介電間隙層之一底部，並到達至該第一源極/汲極區域。
  4. 如請求項1所述之接觸件結構之形成方法，其中該形成該第一源極/汲極區域之操作包含原位摻雜一p型摻質，且該佈植之操作所導入之該摻質亦為一p型摻質。
  5. 如請求項1所述之接觸件結構之形成方法，其中該佈植該摻質之操作導致該第一接觸開口之一寬度縮減一第一數量，且該形成方法包含： 每次在該佈植該摻質至該第一源極/汲極區域之操作後，且在該形成該第一接觸插塞，以填充該第一接觸開口之操作前，進行一清潔製程，以移除在該第一源極/汲極區域上之一氧化層，其中該清潔製程導致該第一接觸開口之該寬度增加一第二數量，且該第二數量等於或大於該第一數量。
  6. 如請求項5所述之接觸件結構之形成方法，其中該第二數量大於該第一數量。
  7. 如請求項1所述之接觸件結構之形成方法，其中該蝕刻該介電層之操作包含蝕刻一層間介電質及蝕刻該層間介電質下之一接觸蝕刻停止層。
  8. 如請求項1所述之接觸件結構之形成方法，其中在該蝕刻該介電層，以形成該第一接觸開口之操作後，該介電層之一部分殘留於該第一接觸開口之相對的兩側，以形成複數個額外間隙壁。
  9. 如請求項1所述之接觸件結構之形成方法，更包含： 形成一第二源極/汲極區域； 蝕刻該介電層，以形成一第二接觸開口，其中該第二源極/汲極區域曝露於該第二接觸開口； 蝕刻該介電間隙層，以形成一第二接觸間隙壁在該第二接觸開口內，其中當佈植該摻質時，遮擋該第二接觸間隙壁，以避免被佈植；以及 形成一第二接觸插塞，以填充該第二接觸開口。
  10. 如請求項9所述之接觸件結構之形成方法，其中該第一源極/汲極區域為p型的，且該第二源極/汲極區域為n型的。
  11. 一種接觸件結構之形成方法，包含： 蝕刻一層間介電質及在該層間介電質下之一接觸蝕刻停止層，以形成一第一接觸開口及一第二接觸開口，其中一第一源極/汲極區域及一第二源極/汲極區域分別位於該第一接觸開口及該第二接觸開口之下，且曝露於該第一接觸開口及該第二接觸開口； 沉積一介電間隙層，其中該介電間隙層延伸至該第一接觸開口及該第二接觸開口； 蝕刻該介電間隙層，以形成一第一接觸間隙壁於該第一接觸開口內，且形成一第二接觸間隙壁於該第二接觸開口內； 形成一佈植遮罩於該第二接觸間隙壁及該第二源極/汲極區域上； 透過該第一接觸開口佈植一摻質至該第一源極/汲極區域；以及 移除該佈植遮罩。
  12. 如請求項11所述之接觸件結構之形成方法，更包含在該移除該佈植遮罩之操作後，進行一蝕刻製程，以移除在該第一源極/汲極區域上之一第一氧化層，並移除在該第二源極/汲極區域上之一第二氧化層。
  13. 如請求項12所述之接觸件結構之形成方法，其中在該佈植該摻質之操作前，該第一接觸間隙壁具有一第一厚度，且在該佈植該摻質之操作後，該第一接觸間隙壁具有一第二厚度，該第二厚度大於該第一厚度，且其中在該蝕刻製程後，該第一接觸間隙壁具有一第三厚度，該第三厚度等於或小於該第一厚度。
  14. 如請求項11所述之接觸件結構之形成方法，其中該第一源極/汲極區域及該第二源極/汲極區域為相反的導電型。
  15. 如請求項11所述之接觸件結構之形成方法，其中該第一源極/汲極區域及該第二源極/汲極區域為相同的導電型。
  16. 如請求項11所述之接觸件結構之形成方法，其中該佈植之操作所佈植之該摻質具有相同於該第一源極/汲極區域之一導電型。
  17. 如請求項16所述之接觸件結構之形成方法，其中該佈植之操作所佈植之該摻質具有相反於該第二源極/汲極區域之一導電型。
  18. 一接觸件結構，包含： 一第一半導體區域； 一第一閘極堆疊，於該第一半導體區域上； 一第一源極/汲極區域，於該第一閘極堆疊之一側上，其中該第一源極/汲極區域為一第一導電型； 一第一矽化區域，於該第一源極/汲極區域上； 一第一接觸插塞，於該第一矽化區域上； 一第一接觸間隙壁，環繞並接觸該第一接觸插塞；以及 該第一導電型的一摻質，於該第一接觸插塞及該第一接觸間隙壁內， 其中該摻質具有一尖峰濃度，該尖峰濃度在該第一接觸間隙壁內，或在該第一接觸間隙壁與該第一接觸插塞間之一界面。
  19. 如請求項18所述之接觸件結構，其中該尖峰濃度在該界面。
  20. 如請求項18所述之接觸件結構，更包含： 一第二半導體區域； 一第二閘極堆疊，於該第二半導體區域上； 一第二源極/汲極區域，於該第二閘極堆疊之一側上，其中該第二源極/汲極區域為一第二導電型，且該第二導電型係相反於該第一導電型； 一第二矽化區域，於該第二源極/汲極區域上； 一第二接觸插塞，於該第二矽化區域上，其中該第一接觸插塞及該二接觸插塞實質具有相同的一寬度；以及 一第二接觸間隙壁，環繞並接觸該第二接觸插塞，其中該第一接觸間隙壁及該第二接觸間隙壁係由相同的一介電材料所形成，且其中該第二接觸間隙壁係薄於該第一接觸間隙壁。
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