TW202240665A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202240665A
TW202240665A TW110123650A TW110123650A TW202240665A TW 202240665 A TW202240665 A TW 202240665A TW 110123650 A TW110123650 A TW 110123650A TW 110123650 A TW110123650 A TW 110123650A TW 202240665 A TW202240665 A TW 202240665A
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Taiwan
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channel layer
layer
epitaxial
channel
source
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TW110123650A
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English (en)
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林育如
陳書涵
李一劭
陳俊紘
志安 徐
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台灣積體電路製造股份有限公司
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Publication of TW202240665A publication Critical patent/TW202240665A/zh

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Abstract

一種裝置包含第一通道層、第二通道層、閘極結構、源極/汲極磊晶結構及源極/汲極接觸。第一通道層及配置在第一通道層上的第二通道層係以間隔分開的方式在基材上。閘極結構圍繞第一通道層及第二通道層。源極/汲極磊晶結構連接至第一通道層及第二通道層。源極/汲極接觸連接至源極/汲極磊晶結構。第二通道層比第一通道層更靠近源極/汲極接觸，且第一通道層比第二通道層更厚。

Description

半導體裝置及其製造方法
半導體積體電路(integrated circuit，IC)已經歷指數性成長。IC材料和設計的技術進步已生產出許多世代的IC，且每一世代都比前一代具有較小和更複雜的電路。在IC進化的過程中，功能密度(即每個晶片面積中內連接裝置的數目)普遍隨著幾何尺寸[即利用一次製程所能創造最小的組件(或線)]的減小而增加。尺度縮小製程一般提供增加生產效率和減少相關成本的效益。
以下揭露提供許多不同實施例或例示，以實施發明的不同特徵。以下敘述之成份和排列方式的特定例示是為了簡化本揭露。這些當然僅是做為例示，其目的不在構成限制。舉例而言，元件的尺寸並不限於所揭露之範圍或數值，而是可取決於製程條件及/或裝置所要的特性。再者，第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接接觸的實施例，也包含有其他特徵形成在第一特徵和第二特徵之間，以致第一特徵和第二特徵沒有直接接觸的實施例。除此之外，本揭露在各種具體例中重覆參考數值及/或字母。此重覆的目的是為了使說明簡化且清晰，並不表示各種討論的實施例及/或配置之間有關係。
再者，空間相對性用語，例如「下方(beneath)」、「在…之下(below)」、「低於(lower)」、「在…之上(above)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使用或操作時的不同方向。裝置可以其他方式定向(旋轉90度或在其他方向)，而本文所用的空間相對性描述也可以如此解讀。
如本文所使用的「大約(around)」、「約(about)」、「近乎 (approximately)」或「實質上(substantially)」一般係代表在所述之數值或範圍的百分之20以內、或百分之10以內、或百分之5以內。本文所述之數量值係近似值，表示即使未明確指出，仍可推斷用語「大約(around)」、「約(about)」、「近乎 (approximately)」或「實質上(substantially)」。
環繞式閘極(gate all around，GAA)電晶體結構可藉由任何合適的方法來圖案化。舉例而言，結構可利用一或多種光微影製程來圖案化，其係包含雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影及自對準製程，使圖案可製作為例如具有的間距小於利用單一且直接的光微影製程所獲得的圖案之間距。舉例而言，在一實施例中，犠牲層係形成在基材上，且利用光微影製程來圖案化。間隙壁係利用自對準製程而沿著被圖案化的犠牲層來形成。然後，犠牲層係被移除，且剩下的間隙壁可接著被用以圖案化環繞式閘極結構。
本揭露係關於積體電路結構及其製造方法。更特別地，本揭露的一些實施例係關於包含具有不同厚度之通道的環繞式閘極裝置。在此配置之下，流過不同通道的驅動電流可以調整。
圖1至圖13B係繪示根據一些實施例之積體電路結構100的形成中間階段的透視視圖及剖面視圖。除了積體電路結構之外，圖1至圖4A、圖5A、圖6A及圖7A繪示X軸、Y軸及Z軸方向。根據一些例示實施例，形成的電晶體可包含p型電晶體(例如p型環繞式閘極場效電晶體)及/或n型電晶體(例如n型環繞式閘極場效電晶體)。透過各種視圖及說明的實施例，類似的參考數值係用以指示類似的元件。須理解的是，對於本方法的另一些實施例，可在圖1至圖13B所示的製程之前、期間及之後提供額外的操作，且以下所述之一些操作可以被取代或減少。操作/製程的順序可以互相交換。
圖1至圖4A、圖5A、圖6A及圖7A係一些實施例的積體電路100在製程中間階段的透視圖。圖4B、圖5B、圖6B、圖7B至圖11A、圖12及圖13A係一些實施例的積體電路100沿著第一切線(例如圖4A中的切線X-X)的剖面視圖，其係沿著通道的縱向方向且垂直於基材之頂表面。圖11B係一些實施例之在製程中間階段的積體電路100沿著第二切線(例如圖4A中的切線Y-Y)的剖面視圖，其係在閘極區域內且垂直於通道的縱向方向。圖13B係圖13A之區域A的放大視圖。
請參閱圖1，磊晶堆疊120係形成在基材110上。在一些實施例中，基材110可包含矽(Si)。另一方面，基材110可包含鍺(Ge)、矽鍺(SiGe)、III-V族材料(例如GaAs、GaP、GaAsP、AlInAs、AlGaAs、GaInAs、InAs、GaInP、InP、InSb及/或GaInAsP；或前述之組合)或其他合適的半導體材料。在一些實施例中，基材110可包含絕緣體上覆半導體(semiconductor-on-insulator，SOI)結構，例如埋藏介電層。再另一方面，基材110可包含埋藏介電層，例如埋藏氧化物(buried oxide，BOX)層，其係例如藉由分離植入氧(separation by implantation of oxygen，SIMOX)技術、晶圓接合(wafer bonding)、選擇性磊晶成長(selective epitaxial growth，SEG)或其他合適的方法。
磊晶堆疊120包含具有第一組成物的磊晶層122插入在具有第二組成物的磊晶層124a、磊晶層124b及磊晶層124c之間。第一組成物與第二組成物可為不同。在一些實施例中，磊晶層122為SiGe，而磊晶層124a、磊晶層124b及磊晶層124c為矽(Si)。然而，其他實施例可能包含提供為第一組成物及第二組成物者具有不同的氧化速率及/或蝕刻選擇性。在一些實施例中，磊晶層122包含SiGe，而磊晶層124a、磊晶層124b及磊晶層124c包含Si，SiGe，且磊晶層124a、磊晶層124b及磊晶層124c的矽氧化速率係小於磊晶層122的SiGe氧化速率。
磊晶層124a、磊晶層124b及磊晶層124c或其部分可形成多閘極電晶體的奈米片(nanosheet)通道。本文所述之用語「奈米片」係指具奈米尺度的任何材料部分，或甚至微米尺寸，且具有拉長的形狀，無論此部分的剖面形狀。因此，此用語係指圓形及實質圓形且剖面拉長的材料部分，且束狀或棒狀材料部分包含例如圓柱狀或實質矩形剖面。磊晶層124a、磊晶層124b及磊晶層124c用以定義裝置的一個通道或多個通道會進一步在下文中說明。
須注意的是，圖1中係繪示三層磊晶層122及三層磊晶層124a、磊晶層124b及磊晶層124c係交替地配置，其僅是為了說明的目的而無意對申請專利範圍做出限制。須理解的是，任何數目的磊晶層可形成為磊晶堆疊120；層數係取決於電晶體所要的通道區域數。在一些實施例中，磊晶層124a、磊晶層124b及磊晶層124c的數目係介於2及10之間。
如下更詳細的描述，磊晶層124a、磊晶層124b及磊晶層124c可做為後續形成之多閘極裝置的(多個)通道區域，且其厚度係基於考量裝置效能來選擇。(多個)通道區域中的磊晶層122最終可被移除且用以定義後續形成之多閘極裝置的相鄰(多個)通道區域之間的垂直距離，且其厚度係基於考量裝置效能來選擇。因此，磊晶層122亦可當作犠牲層，且磊晶層124a、磊晶層124b及磊晶層124c亦可當作通道層。
舉例而言，磊晶堆疊120之層的磊晶成長可藉由分子束磊晶(molecular beam epitaxy，MBE)製程、有機金屬化學氣相沉積(metalorganic chemical vapor deposition，MOCVD)製程及/或其他合適的磊晶成長製程來進行。在一些實施例中，磊晶成長層(例如磊晶層124a、磊晶層124b及磊晶層124c)包含與基材110相同的材料。在一些實施例中，磊晶成長層122、磊晶成長層124a、磊晶成長層124b及磊晶成長層124c包含與基材110不同的材料。如上所述，在至少一些具體例中，磊晶層122包含磊晶成長矽鍺(SiGe)層，且磊晶層124a、磊晶層124b及磊晶層124c包含磊晶成長矽(Si)層。另一方面，在一些實施例中，磊晶層124a、磊晶層124b及磊晶層124c之任一者可包含其他材料，例如鍺、化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(例如SiGe、GaAsP、AlInAs、AlGaAs、InGaAs、GaInP及/或GaInAsP)或前述之組合。如前述，磊晶層122及磊晶層124a、磊晶層124b及磊晶層124c的材料可基於提供不同氧化性及/或蝕刻選擇性的性質來選擇。在一些實施例中，磊晶層122及磊晶層124a、磊晶層124b及磊晶層124c係實質不同摻質(即，具有的外在摻質濃度為約0 cm -3至約1×10 18cm -3)，舉例而言，沒有在磊晶成長製程中進行有意的摻雜。
每一個磊晶層122具有厚度T。磊晶層122可具有實質固定的厚度T。在一些實施例中，厚度T之範圍為約2 nm至約30 nm。(底部的)磊晶層124a具有厚度Ta，(中間的)磊晶層124b具有厚度Tb，且(頂部的)磊晶層124c具有厚度Tc。在一些實施例中，在厚度Ta、厚度Tb及厚度Tc中，厚度Ta具有最大的厚度值，及/或在厚度Ta、厚度Tb及厚度Tc中，厚度Tc具有最小的厚度值。舉例而言，厚度Ta大於厚度Tb及厚度Tc，及/或厚度Tb大於厚度Ta。在另一些實施例中，厚度Ta大於厚度Tb及厚度Tc，且厚度Tb與厚度Ta係實質相同。在再一些實施例中，厚度Ta與厚度Tb係實質相同，且厚度Tb係大於厚度Tc。再者，二個相鄰磊晶層122之間的厚度差係小於二個相鄰磊晶層124a、磊晶層124b及磊晶層124c之間的厚度差。只要厚度Ta大於厚度Tc即落在本揭露的實施例。
在一些實施例中，厚度Ta、厚度Tb及厚度Tc可藉由調整磊晶成長製程的沉積時間/持續時間來控制。舉例而言，用以沉積磊晶層124a的沉積時間/持續時間大於用以沉積磊晶層124b及/或磊晶層124c的沉積時間/持續時間。當沉積時間/持續時間增加，磊晶層的厚度增加。另一方面，用以沉積磊晶層122的沉積時間/持續時間係實質相同。
請參閱圖2，形成自基材110延伸的複數個半導體鰭片130。在各種實施例中，每一個鰭片130包含自基材110形成的基材部分112以及包含磊晶層122及磊晶層124a、磊晶層124b及磊晶層124c之磊晶堆疊的每一個磊晶層的部分。鰭片130可利用包含雙重圖案化或多重圖案化製程的合適製程來製造。在一些實施例中，雙重圖案化或多重圖案化製程結合光微影及自對準製程，其使圖案被創作為具有例如具有的間距小於利用單一且直接的光微影製程所獲得的圖案之間距。舉例而言，在一實施例中，犠牲層係形成在基材上且係利用光微影製程來圖案化。間隙壁係沿著被圖案化的犠牲層並利用自對準製程來形成。然後，犠牲層係被移除，且剩下的間隙壁或心軸可接著而被用以藉由蝕刻初始的磊晶堆疊120來圖案化鰭片130。蝕刻製程可包含乾式蝕刻、溼式蝕刻、反應性離子蝕刻(reactive ion etching，RIE)及/或其他合適的製程。
如圖1及圖2所繪示的說明實施例中，在圖案化鰭片130之前，硬罩幕(hard mask，HM)層910係形成在磊晶堆疊120上。在一些實施例中，硬罩幕層包含氧化層912(例如墊氧化層，其可包含SiO 2)及形成在氧化層上的氮化層914(例如墊氮化層，其可包含Si 3N 4)。氧化層912可做為磊晶堆疊120及氮化層914之間的黏著層，且可做為用以蝕刻氮化層914的蝕刻中止層。在一些具體例中，硬罩幕氧化層912包含熱成長氧化物、化學氣相沉積(chemical vapor deposition，CVD)沉積氧化物及/或原子層沉積(atomic layer deposition，ALD)沉積氧化物。在一些實施例中，硬罩幕氮化層914係藉由化學氣相沉積及/或其他合適的技術沉積在硬罩幕氧化層912上。
鰭片130可接著利用包含光微影及蝕刻製程的合適製程來製造。光微影製程可包含形成光阻層(圖未繪示)在硬罩幕層910上、暴露光阻成圖案、進行後曝光烘烤製程及顯影光阻以形成包含光阻的圖案化罩幕。在一些實施例中，圖案化光阻以形成圖案化罩幕元件可利用電子束(electron beam，e-beam)微影製程或極紫外光(extreme ultraviolet，EUV)微影製程，其利用極紫外光區域內的光線(波長為例如約1 nm至約200 nm的)。然後，圖案化罩幕可用以保護基材110的區域及形成於其上的層，而蝕刻製程穿過硬罩幕層910、穿過磊晶堆疊120及至基材110並形成溝渠102在未保護區域內，藉以留下複數個延伸鰭片130。溝渠102可利用乾式蝕刻(例如反應性離子蝕刻)、溼式蝕刻及/或前述組合來蝕刻。用以形成鰭片在基材上之方法的許多其他實施例也可使用，其包含例如定義鰭片區域(例如藉由罩幕或隔離區域)及以鰭片130的方式磊晶成長磊晶堆疊120。
接著，如圖3所示，隔離區域140係形成為插入鰭片130。隔離區域140可包含襯氧化物(圖未繪示)。襯氧化物可由熱氧化物所形成，其係穿過基材110之熱氧化的表面層而形成。襯氧化物亦可為沉積的氧化矽層，其係利用例如原子層沉積、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition，HDPCVD)或化學氣相沉積而形成。隔離區域140也可包含在襯氧化物上的介電材料，且介電材料可利用流動式化學氣相沉積(flowable chemical vapor deposition，FCVD)、旋轉塗佈或相似方法來形成。
隔離區域140係接著被凹陷，以使半導體條120之頂部部分突出至高於相鄰隔離區域140的頂表面，以形成突出鰭片120。蝕刻可利用乾式蝕刻製程來進行，其中NH 3及NF 3係用以做蝕刻氣體。蝕刻製程期間，可產生電漿。亦可包含氬氣。根據本揭露的另一些實施例，隔離區域140的凹陷係利用溼式蝕刻製程來進行。舉例而言，蝕刻化學試劑可包含稀釋HF。
請參閱圖4A及圖4B，虛擬閘極結構150係形成在基材110上，且係至少部分地設置在鰭片130上。在虛擬閘極結構150下方的鰭片130之部分也可當作通道區域。虛擬閘極結構150也可定義鰭片130的源極/汲極(S/D)區域，舉例而言，鰭片130的區域係相鄰及在通道區域的相對側。
虛擬閘極形成操作首先形成虛擬閘極介電層152在鰭片130上。接著，可包含多層156及158(例如氧化層156及氮化層158)的虛擬閘極電極層154及硬罩幕係形成在虛擬閘極介電層152。然後，硬罩幕係被圖案化，接著藉由利用圖案化硬罩幕做為蝕刻罩幕來圖案化虛擬閘極電極層152。在一些實施例中，在圖案化虛擬閘極電極層154之後，虛擬閘極介電層152係自鰭片130的源極/汲極區域中被移除。蝕刻製程可包含溼式蝕刻、乾式蝕刻及/或前述之組合。蝕刻製程係選擇以選擇性地蝕刻虛擬閘極介電層152，而不實質蝕刻鰭片130、虛擬閘極電極層154、氧化罩幕層156及氮化罩幕層158。
閘極介電層152可為任何可接受的介電層，例如氧化矽、氮化矽、相似物或前述之組合，且可利用任何可接受的製程來形成，例如熱氧化、旋塗製程、化學氣相沉積或相似者。虛擬閘極電極154可為任何可接受的電極層，例如包含多晶矽、金屬、相似物或前述之組合。閘極電極層可藉由任何可接受的沉積製程來沉積，例如化學氣相沉積、電漿輔助化學氣相沉積(plasma enhanced CVD，PECVD)或相似者。每一個虛擬閘極結構150跨越單一或複數個鰭片130。虛擬閘極結構150之縱向方向垂直於各鰭片130之縱向方向。
在虛擬閘極結構150的形成完成之後，閘極間隙壁160係形成在虛擬閘極結構150之側壁上。舉例而言，間隙壁材料係沉積在基材110上。間隙壁材料層可為共形層，其係接著被回蝕以形成閘極側壁間隙壁。在說明實施例中，間隙壁材料層160係共形地設置在虛擬閘極結構150之頂部及側壁上。間隙壁材料層160可包含介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽、SiCN膜、碳氧化矽、SiOCN膜及/或前述之組合。在一些實施例中，間隙壁材料層160包含多層，例如第一間隙壁層162及形成在第一間隙壁162上的第二間隙壁層164(如圖4B所繪示)。舉例而言，間隙壁材料層160可藉由利用合適的沉積製程來沉積介電材料在閘極結構150上而形成。然後，異向性蝕刻製程係在沉積的間隙壁材料層160上進行，以暴露鰭片130未被虛擬閘極結構150(例如在鰭片130之源極/汲極區域中)覆蓋的部分。在虛擬閘極結構150正上方的間隙壁材料層之部分可藉由異向性蝕刻製程而完全地被移除。在虛擬閘極結構150之側壁上的間隙壁材料層之部分可維持，形成閘極側壁間隙壁，為了簡化，其係被表示為閘極間隙壁160。須注意的是，雖然閘極間隙壁160在圖4B的剖面視圖中為多層結構，為了簡化，其在圖4A的透視視圖中係被繪示為單層結構。
接著，如圖5A及圖5B所繪示，側向地延伸超過閘極間隙壁160(例如在鰭片130之源極/汲極區域中)之半導體鰭片130之暴露部分係藉由利用例如異向性蝕刻製程(使用虛擬閘極結構150及閘極間隙壁160做為蝕刻罩幕)來蝕刻，造成凹陷R1在半導體鰭片130中且在對應的虛擬閘極結構150之間。在異向性蝕刻之後，磊晶層122及通道層124a、通道層124b及通道層124c之末表面及閘極間隙壁160各別最外面的側壁係實質連續的，其係由於異向性蝕刻。在一些實施例中，異向性蝕刻可藉由以電漿源及反應氣體的乾式化學蝕刻來進行。電漿源可為感應耦合式電漿(inductively coupled plasma，ICR)源、變壓耦合式電漿(transformer coupled plasma，TCP)源、電子迴旋共振(electron cyclotron resonance，ECR)源或相似者，且反應氣體可為例如氟基氣體(例如SF 6、CH 2F 2、 CH 3F、CHF 3或相似者)、氯基氣體(例如Cl 2)、溴化氫氣體(HBr)、氧氣(O 2)、相似者或前述之組合。
在一些實施例中，由於蝕刻製程之異向性蝕刻的特性，凹陷R1具有錐形側壁輪廓。因此，磊晶層(或被當作通道層)124a、磊晶層124b及磊晶層124c的通道長度(在如圖5B所示之x方向上)可略微不同。舉例而言，磊晶層124a的通道長度大於磊晶層124b的通道長度，其中磊晶層124b的通道長度大於磊晶層124c的通道長度。然而，在另一些實施例中，蝕刻製程的蝕刻條件可精細地調整，以使凹陷R1具有垂直的側壁輪廓。再者，每一個凹陷R1具有高度H1及寬度W1。
接著，在圖6A及圖6B中，磊晶層122係藉由利用合適的蝕刻技術而側向地或水平地被凹陷，造成側向凹陷R2之每一者直立地在對應通道層124a、通道層124b及通道層124c之間。此操作可苇由利用選擇性蝕刻製程來進行。做為例示而不構成限制的是，磊晶層122為SiGe且通道層124a、通道層124b及通道層124c為矽允許磊晶層122的蝕刻選擇性。在一些實施例中，選擇性溼式蝕刻包含氨水-過氧化氫蝕刻(例如氨水-過氧化氫-水混合物)，其相較於蝕刻Si，蝕刻SiGe有更快的蝕刻速率。在一些實施例中，選擇性蝕刻包含SiGe氧化，接著SiGeO x的移除。舉例而言，氧化可藉由O 3清洗，然後藉由例如NH 4OH的蝕刻劑來移除SiGeO x，其選擇性地以比蝕刻Si更快的蝕刻速率來蝕刻SiGeO x。再者，因為Si的氧化速率遠慢於(偶爾是30倍的慢於)SiGe的氧化速率，通道層124a、通道層124b及通道層124c不會顯著地被側向凹陷磊晶層122的製程所蝕刻。因此，通道層124a、通道層124b及通道層124c側向地延伸越過磊晶層122相對的末端表面。
在圖7A及圖7B中，內側間隙壁材料層170係形成以填充凹陷R2，其係由磊晶層122的側向蝕刻所剩下，如參閱圖6A及圖6B所述。內側間隙壁材料層170可為低k介電材料，例如SiO 2、SiN、SiCN或SiOCN，且可藉由合適的沉積方法來形成，例如原子層沉積。在內側間隙壁材料層170沉積之後，可進行異向性蝕刻製程以修整被沉積的內側間隙壁材料170，以使僅部分被沉積的內側間隙壁材料170填充由磊晶層122的側向蝕刻所剩下的凹陷R2。為了簡化，在修整製程之後，被沉積的內側間隙壁材料170之剩餘部分係被表示為內側間隙壁170。內側間隙壁170用做使金屬閘極與後續製程中形成的源極/汲極區域隔離。在圖7A及圖7B的具體例中，內側間隙壁170的側壁係對準通道層124a、通道層124b及通道層124c之側壁。
在圖8中，源極/汲極磊晶結構180係形成在半導體鰭片130的源極/汲極區域S/D上。源極/汲極磊晶結構180可藉由進行磊晶成長製程來形成，其係提供磊晶材料在鰭片130上。在磊晶成長製程期間，虛擬閘極結構150、閘極側壁間隙壁160及內側間隙壁170限制源極/汲極磊晶結構180成源極/汲極區域S/D。在一些實施例中，磊晶結構180的晶格常數與磊晶層124a、磊晶層124b及磊晶層124c的晶格常數不同，以使磊晶層124a、磊晶層124b及磊晶層124c可被磊晶結構180伸張或加壓，以優化半導體裝置的載子遷移率並增加裝置效能。磊晶製程包含化學氣相沉積技術[例如電漿輔助化學氣相沉積、氣相磊晶(vapor-phase epitaxy，VPE)及/或超高真空化學氣相沉積(ultra-high vacuum CVD，UHV-CVD)]、分子束磊晶及/或其他合適的製程。磊晶製程可利用氣體及/或液體前驅物，其與半導體鰭片104的組成物互相作用。
在一些實施例中，源極/汲極磊晶結構180可包含Ge、Si、GaAs、AlGaAs、SiGe、GaAsP、SiP或其他合適的材料。源極/汲極磊晶結構180在磊晶製程中可藉由導入物質而被原位摻雜，其物質包含：p型摻質，例如硼或BF 2；n型摻質，例如磷或砷；及/或其他包含前述組合之合適的摻質。若源極/汲極磊晶結構180沒有被原位摻雜，進行佈植製程(即接面植入製程)以摻雜源極/汲極磊晶結構180。在一些例示實施例中，在n型電晶體內的源極/汲極磊晶結構180包含SiP，而在p型電晶體內的源極/汲極磊晶結構180包含GeSnB及/或SiGeSnB。在具有不同裝置型式的實施例中，罩幕(例如光阻)可形成在n型裝置區域上，而暴露p型裝置區域，且p型磊晶結構可形成在p型裝置區域內暴露的基材部分112上。然後，罩幕可被移除。接著，罩幕(例如光阻)可形成在p型裝置區域上，而暴露n型裝置區域，且n型磊晶結構可形成在n型裝置區域內暴露的基材部分112上。然後，罩幕可被移除。
源極/汲極磊晶結構180一旦被形成，可進行退火製程以活化源極/汲極磊晶結構180內的p型摻質或n型摻質。退火製程可為例如快速熱退火(rapid thermal anneal，RTA)、雷射退火、毫秒熱退火(millisecond thermal annealing，MSA)製程或相似者。
在圖9中，層間介電(interlayer dielectric)層210係形成在基材110上。在一些實施例中，接觸蝕刻中止層(contact etch stop layer，CESL)亦係在形成層間介電層210之前被形成。在一些具體例中，接觸蝕刻中止層包含氮化矽層、氧化矽層、氮氧化矽層及/或其他具有與層間介電層210具有不同蝕刻選擇性的合適材料。接觸蝕刻中止層可藉由電漿輔助化學氣相沉積製程及/或合適的沉積或氧化製程。在一些實施例中，層間介電層210包含材料，例如四乙氧基矽烷(tetraethylorthosilicate，TEOS)形成的氧化物、未摻雜矽酸玻璃或摻雜氧化矽[例如硼摻雜磷矽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG) 、熔融石英玻璃(fused silica glass，FSG)、磷矽玻璃(Phospho-Silicate Glass，PSG)、硼矽玻璃(Boro-Silicate Glass，BSG)] 及/或其他與接觸蝕刻中止層具有不同蝕刻選擇性之合適的介電材料。層間介電層210可藉由電漿輔助化學氣相沉積製程或其他合適的沉積技術來沉積。在一些實施例中，在層間介電層210形成之後，晶圓可接受高熱預算製程(high thermal budget process)以退火層間介電層210。
在一些具體例中，在沉積層間介電層210之後，可進行平坦化製程以移除層間介電層210的多餘材料。舉例而言，平坦化製程包含化學機械平坦化(chemical mechanical planarization，CMP)製程，其移除在虛擬閘極結構150上的層間介電層210(及接觸蝕刻中止層，若其存在的話)之部分，並平坦化積體電路結構100的頂表面。在一些實施例中，化學機械平坦化製程亦移除硬罩幕層156及158(如圖8所示)並暴露虛擬閘極電極層154。
然後，虛擬閘極結構150(如圖8及圖9所示)先被移除，接著磊晶層(即犠牲層)122(如圖9所示)係被移除。所得的結構係繪示於圖10中。在一些實施例中，虛擬閘極結構150係藉由利用選擇性蝕刻製程(例如選擇性乾式蝕刻、選擇性溼式蝕刻或前述之組合)來移除，相較於蝕刻其他材料(例如閘極側壁間隙壁160及/或層間介電層210)，其係以較快的蝕刻速率蝕刻虛擬閘極結構150中的材料，因此造成在對應的閘極側壁間隙壁160之間的閘極溝渠GT1，其具有磊晶層122暴露在閘極溝渠GT1內。接著，在閘極溝渠GT1內的磊晶層122係藉由利用其他選擇性蝕刻製程來移除，相較於蝕刻通道層124a、通道層124b及通道層124c，其係以較快的蝕刻速率蝕刻磊晶層122，因此形成在相鄰磊晶層(即通道層)124a、磊晶層124b及磊晶層124c之間的開口O1。如此一來，磊晶層124a、磊晶層124b及磊晶層124c變成懸掛在基材110上的奈米片且在源極/汲極磊晶結構180之間。此操作亦稱為通道釋放製程(channel release process)。在此臨時製程操作中，在磊晶層(即奈米片)124a、磊晶層124b及磊晶層124c之間的開口O1可在一般環境條件(例如空氣、氮氣等)下被填充。在一些實施例中，磊晶層124a、磊晶層124b及磊晶層124c可替換地被稱為奈米線(nanowires)、奈米平板(nanoslabs)、奈米環(nanorings)，其係取決於他們的幾何形狀。舉例而言，在另一些實施例中，磊晶層124a、磊晶層124b及磊晶層124c可被修整為具有實質圓形(即圓柱)，由於用以完全地移除磊晶層122的選擇性蝕刻製程。在此例示中，所得的磊晶層124a、磊晶層124b及磊晶層124c可被稱為奈米線。
在一些實施例中，磊晶層122係藉由利用選擇性溼式蝕刻製程來移除。在一些實施例中，磊晶層122為SiGe，而磊晶層124a、磊晶層124b及磊晶層124c為矽，以使磊晶層122被選擇性移除。在一些實施例中，選擇性移除包含SiGe氧化，接著SiGeO x的移除。舉例而言，氧化可藉由O 3清洗來提供，然後SiGeO x係藉由例如NH 4OH的蝕刻劑來移除，其選擇性地以比蝕刻Si更快的蝕刻速率來蝕刻SiGeO x。再者，由於Si的氧化速率遠慢於(偶爾是30倍的慢於)SiGe的氧化速率，通道層124a、通道層124b及通道層124c不會顯著地被通道釋放製程所蝕刻。須注意的是，通道釋放製程及上述側向凹陷犠牲層的操作(如圖6A及圖6B所示之操作)兩者皆利用選擇性蝕刻製程，其選擇性地以比蝕刻Si更快的蝕刻速率來蝕刻SiGe，且因此在一些實施例中，前述兩種操作可利用相同的蝕刻化學品。在此例示中，通道釋放操作的蝕刻時間/持續時間係比上述側向凹陷犠牲層的操作之蝕刻時間/持續時間更長，藉以完整地移除犠牲SiGe層。
在圖11A及圖11B中，取代閘極結構220係分別地形成在閘極溝渠GT1中，以圍繞每一個懸掛在閘極溝渠GT1內的磊晶層124a、磊晶層124b及磊晶層124c。閘極結構220可為環繞式閘極場效電晶體的最終閘極。最終閘極可為高k/金屬閘極堆疊，然而，可能是其他的組成。在一些實施例中，每一個閘極結構220形成與複數個磊晶層124a、磊晶層124b及磊晶層124c提供之多通道連接的閘極。在各種實施例中，高k/金屬閘極結構220包含形成在磊晶層124a、磊晶層124b及磊晶層124c周圍的閘極介電層222 、形成在閘極介電層222周圍的功函數金屬層224及形成在功函數金屬層224並填充剩餘的閘極溝渠GT1的填充金屬226。閘極介電層222包含層間層(例如氧化矽層)及在層間層上的高k閘極介電層。高k閘極介電質包含具有高介電常數的介電材料，例如介電常數大於熱氧化矽(約3.9)。功函數金屬層224及/或用於高k/金屬閘極結構220中的填充金屬層226可包含金屬、金屬合金或金屬矽化物。高k/金屬閘極結構220可包含沉積以形成各種閘極材料、一或多個襯層，及一或多個化學機械研磨製程，以移除多餘的閘極材料。如圖11B所繪示之沿著高k/金屬閘極結構220之縱軸所取得的剖面視圖，高k/金屬閘極結構220圍繞每一個磊晶層124a、磊晶層124b及磊晶層124c，且因此被當作環繞式閘極場效電晶體的閘極。
在一些實施例中，閘極介電層222的層間層可包含介電材料，例如氧化矽(SiO 2)、HfSiO或氮氧化矽(SiON)。層間層可藉由化學氧化、熱氧化、原子層沉積、化學氣相沉積及/或其他合適的方法來形成。閘極介電層222的高k介電層可包含二氧化鉿(HfO 2)。另外，閘極介電層222可包含其他高k介電質，例如氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON)、氧化鉭鋯(HfTaO)、氧化鈦鉿(HfTiO)、氧化鋯鉿(HfZrO)、氧化鑭(LaO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta 2O 5)、氧化釔(Y 2O 3)、氧化鈦鍶(SrTiO 3，STO)、氧化鈦鋇(BaTiO 3，BTO)、氧化鋯鋇(BaZrO)、氧化鑭鉿(HfLaO)、氧化矽鑭(LaSiO)、氧化矽鋁(AlSiO)、氧化鋁(Al 2O 3)、氮化矽(Si 3N 4)、氮氧化矽(SiON)及前述之組合。
功函數金屬層224可包含功函數金屬，以提供高k/金屬閘極結構220合適的功函數。對於n型鰭式場效電晶體，功函數金屬層224可包含一或多個n型功函數金屬(n-type work function metals，N-metal)。n型功函數金屬可例如包含但不限於鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、碳氮化鉭(TaCN)、鉿(Hf)、鋯(Zr)、鈦(Ti)、鉭(Ta)、鋁(Al)、金屬碳化物[例如碳化鉿(HfC)、碳化鋯(ZrC)、碳化鈦(TiC)、碳化鋁(AlC)]、鋁化合物及/或其他合適的材料。另一方面，對於p型鰭式場效電晶體，功函數金屬層224可包含一或多個p型功函數金屬(p-type work function metals，P-metal)。p型功函數金屬可例如包含但不限於氮化鈦(TiN)、氮化鎢(WN)、鎢(W)、釕(Ru)、鎘(Pd)、鉑(Pt)、鈷(Co)、鎳(Ni)、導電金屬氧化物及/或其他合適的材料。
在一些實施例中，填充金屬226可例如包含但不限於鎢、鋁、銅、鎳、鈷、鈦、鉭、氮化鈦、氮化鉭、矽化鎳、矽化鈷、TaC、TaSiN、TaCN、TiAl、TiAlN或其他合適的材料。
在圖12中，回蝕製程係選擇性地進行以回蝕取代閘極結構220，以在被回蝕的閘極結構220上造成凹陷。在一些實施例中，因為取代閘極結構220的材料具有與閘極間隙壁160不同的蝕刻選擇性，取代閘極結構220之頂表面可低於閘極間隙壁160之頂表面。
介電質蓋230係選擇性地形成在被回蝕的閘極結構220上。介電質蓋230包含SiN x、Al xO y、AlON、 SiO xC y、 SiC xN y、前述之組合或相似者，且係藉由合適的沉積技術來形成，例如化學氣相沉積、電漿輔助化學氣相沉積、原子層沉積、遠距電漿原子層沉積(remote plasma ALD，RPALD)、電漿輔助原子層沉積(plasma-enhanced ALD，PEALD)、前述之組合或相似者。然後，進行化學機械研磨製程以移除在凹陷外的蓋層，留下在凹陷內的介電質蓋層之部分，以做為介電質蓋230。
在圖13A中，源極/汲極接觸240係形成為延伸穿過層間介電層210(及接觸蝕刻中止層，若其存在的話)。源極/汲極接觸240的形成包含例如但不限於，進行一或多次蝕刻製程以形成接觸開口延伸穿過層間介電層210，以暴露源極/汲極磊晶結構180，沉積一或多個金屬材料以過度填充接觸開口，然後進行化學機械研磨製程，以移除在接觸開口外的多餘金屬材料。在一些實施例中，一或多個蝕刻製程係選擇性蝕刻，相對於蝕刻介電質蓋230及閘極間隙壁160，其以較快的蝕刻速率蝕刻層間介電層210。因此，選擇性蝕刻係利用介電質蓋230及閘極間隙壁160做為蝕刻罩幕來進行，以使接觸開口及源極/汲極接觸240係形成為自對準源極/汲極磊晶結構180，而不使用額外的光微影製程。在此例示中，用於形成自對準接觸240的介電質蓋230可被稱為自對準接觸蓋(self-aligned contact caps，SAC caps)230。
圖13B係圖13A中區域A的放大視圖。請參閱圖13A及圖13B。積體電路結構100包含基材110、在基材110上的通道層124a、通道層124b及通道層124c、連接通道層124a、通道層124b及通道層124c的源極/汲極磊晶結構180及分別在源極/汲極磊晶結構180上的源極/汲極接觸240。
通道層124c係靠近源極/汲極接觸240，且通道層124a係遠離源極/汲極接觸240。當施加電壓至源極/汲極接觸240之一者(或源極接觸)時，驅動電流Ia、Ib及Ic的通路係形成在積體電路結構100內。驅動電流Ia流過通道層124a，驅動電流Ib流過通道層124b，且驅動電流Ic流過通道層124c。如圖13B所示，驅動電流Ic的通路係比驅動電流Ia及Ib的通路短。由於電阻隨電流通路的增加而增加，當通道層124a、通道層124b及通道層124c具有相同厚度時，驅動電流Ic係大於驅動電流Ia及Ib。在圖13B中，然而，通道層124a及/或通道層124b的厚度使通道層124a及/或通道層124b的電阻降低，以使驅動電流Ia及Ib可增加。
舉例而言，通道層124a具有厚度Ta，通道層124b具有厚度Tb，且通道層124c具有厚度Tc。在一些實施例中，在厚度Ta、厚度Tb及厚度Tc中，厚度Ta具有最大的厚度值，及/或在厚度Ta、厚度Tb及厚度Tc中，厚度Tc具有最小的厚度值。舉例而言，厚度Ta大於厚度Tb及厚度Tc，及/或厚度Tb大於厚度Ta。在另一些實施例中，厚度Ta大於厚度Tb及厚度Tc，且厚度Tb與厚度Ta係實質相同。在再一些實施例中，厚度Ta與厚度Tb係實質相同，且厚度Tb係大於厚度Tc。只要厚度Ta大於厚度Tc即落在本揭露中的實施例。
在一些實施例中，厚度Ta、厚度Tb及厚度Tc之每一者的範圍為約2 nm至約30 nm。若厚度Ta(Tb、Tc)係小於約2 nm，驅動電流Ia(Ib、Ic)可能太小；若厚度Ta(Tb、Tc)係大於約30 nm，閘極用以關閉通道的截止電壓會太高。在一些實施例中，厚度Ta及厚度Tc之間的差異係大於0 nm，且小於或等於約28 nm，例如在約1 nm至約28 nm之範圍內。若厚度Ta及厚度Tc之間的差異小於0 nm，驅動電流Ia可能遠小於驅動電流Ic；若厚度Ta及厚度Tc之間的差異大於約28 nm，磊晶堆疊120(參照圖1)的總高度可能太高而無法形成低寬高比的凹陷R1(參照圖5B)。相似地，在一些實施例中，厚度Ta及厚度Tb之間的差異係大於0 nm，且小於或等於約28 nm，例如在約1 nm至約28 nm之範圍內，及/或厚度Tb及厚度Tc之間的差異係大於0 nm，且小於或等於約28 nm，例如在約1 nm至約28 nm之範圍內。
在一些實施例中，相鄰通道層之間(通道層124a及通道層124b之間、通道層124b及通道層124c之間及通道層124a及基材部分112之間)的間隙具有高度H(即內層間隙壁170的高度)的範圍為約2 nm至約30 nm。若高度H係大於30 nm，凹陷R1(參照圖7B)的寬高比可能太大；若高度H係小於約2 nm，閘極結構220可能無法填充通道層之間的間隙，而留下孔洞於其間。
在一些實施例中，厚度Ta、厚度Tb、厚度Tc及厚度T係與凹陷R1(參照圖5B)的寬高比(對於凹陷係定義為凹陷的高度H1/寬度W1的比)有關。在一些實施例中，凹陷R1的寬高比係在約1至約5的範圍內。一旦凹陷R1的寬高比及寬度被決定了，則高度H1的最大值亦被決定了。厚度的總和(Ta+Tb+Tc+3T)係小於高度H1的最大值。
圖14至圖15B係繪示根據本揭露另一些實施例之製造積體電路100a之各階段的例示剖面視圖。須理解的是，對於本方法的另一些實施例，可在圖14至圖15B所示的製程之前、期間及之後提供額外的操作，且以下所述之一些操作可以被取代或減少。操作/製程的順序可以互相交換。與如圖1至圖13B所述之相同或相似的配置、材料、製程及/或操作可以在以下的實施例中使用，且可省略其詳細說明。
在如圖10所示之結構形成之後，進行另一蝕刻製程以過度蝕刻通道層124a、通道層124b及通道層124c，以使圖10所示之開口O1被放大為開口O1’。在一些實施例中，通道層124a、通道層124b及通道層124c係藉由異向性化學蝕刻製程310而被蝕刻/凹陷。舉例而言，蝕刻可藉由以電漿源及反應氣體的異向性化學蝕刻來進行。電漿源可為感應耦合式電漿(inductively coupled plasma，ICP)源、變壓耦合式電漿(transformer coupled plasma，TCP)源、電子迴旋共振(electron cyclotron resonance，ECR)源或相似者，且反應氣體可為例如氟基氣體(例如SF 6、CH 2F 2、CH 3F、CHF 3或相似物)、氯基氣體(例如Cl 2)、溴化氫氣體(HBr)、氧氣(O 2)、相似物或前述之組合。
在一些實施例中，藉由調整蝕刻製程中的電漿能量及/或壓力，通道層124a、通道層124b及通道層124c的輪廓可被調整。舉例而言，通道層(例如通道層124c)愈高，通道層的蝕刻量愈多。換言之，通道層124c係被過度蝕刻的比通道層124a更嚴重。在一些實施例中，蝕刻製程可在約450 W至約4800 W的電漿源能量及約20 mTorr至約12000 mTorr的壓力下，利用O 3、O 2、O 2/N 2、O 2/H 2、O 2/Ar及/或O 2/He為蝕刻氣體來進行。若電漿源能量係大於約4800 W，通道層124a、通道層124b及通道層124c可能被過度蝕刻；若電漿源能量係小於約450 W，通道層124a、通道層124b及通道層124c的蝕刻不足。若壓力小於約20 mTorr，通道層124a、通道層124b及通道層124c的蝕刻不足；若壓力大於約12000 mTorr，通道層124a、通道層124b及通道層124c可能被過度蝕刻。
請參閱圖15A，在圖14的蝕刻製程310完成之後，圖14的結構係經過與圖11A至圖13A相似的製程。換言之，閘極結構220係形成在閘極溝渠GT1及開口O1'中，閘極結構220係被回蝕，介電質蓋230係形成在被回蝕的閘極結構220之上，開口係形成在層間介電層210中，以暴露源極/汲極磊晶結構180，且源極/汲極接觸240係形成在開口內。關於前述製程/元件的材料及製程細節係與圖11A至圖13A所示者相似，因此為了簡潔，在此不再重複說明。
圖15B係圖15A中的區域Aa的放大視圖。請參閱圖15A及圖15B。積體電路結構100a包含基材110、在基材110上的通道層124a、通道層124b及通道層124c、包圍通道層124a、通道層124b及通道層124c之每一者的閘極結構220、連接通道層124a、通道層124b及通道層124c的源極/汲極磊晶結構180，及分別在源極/汲極磊晶結構180上的源極/汲極接觸240。
通道層124c係靠近源極/汲極接觸240，且通道層124a係遠離源極/汲極接觸240。如上所述，厚的通道層124a及/或通道層124b降低通道層124a及/或通道層124b的電阻，以使流過通道層124a及/或通道層124b的驅動電流可以增加。
在一些實施例中，通道層124a包含中心部分124ac及在中心部分124ac之相對末端上的二個邊緣部分124ae。換言之，邊緣部分124ae互連中心部分124ac及源極/汲極磊晶結構180。閘極結構220包圍中心部分124ac，且內側間隙壁材料層170接觸邊緣部分124ae。由於圖14所示之蝕刻製程310，邊緣部分124ae比中心部分124ac厚。中心部分124ac具有厚度Ta'，且凹陷之深度D2及D3的總和係中心部分124ac及邊緣部分124ae之間的厚度差。
相似地，通道層124b包含中心部分124bc及在中心部分124bc之相對末端上的二個邊緣部分124be。換言之，邊緣部分124be互連中心部分124bc及源極/汲極磊晶結構180。閘極結構220包圍中心部分124bc，且內側間隙壁材料層170接觸邊緣部分124be。再者，閘極結構220的閘極介電層222係自邊緣部分124ae的內側壁延伸至邊緣部分124be的內側壁。由於圖14所示之蝕刻製程310，邊緣部分124be比中心部分124bc厚。中心部分124bc具有厚度Tb'，且凹陷之深度D4及D5的總和係中心部分124bc及邊緣部分124be之間的厚度差。
同樣地，通道層124c包含中心部分124cc及在中心部分124cc之相對末端上的二個邊緣部分124ce。換言之，邊緣部分124ce互連中心部分124cc及源極/汲極磊晶結構180。閘極結構220包圍中心部分124cc，且內側間隙壁材料層170接觸邊緣部分124ce。再者，閘極結構220的閘極介電層222係自邊緣部分124be的內側壁延伸至邊緣部分124ce的內側壁。由於圖14所示之蝕刻製程310，邊緣部分124ce比中心部分124cc厚。中心部分124cc具有厚度Tc'，且凹陷之深度D6及D7的總和係中心部分124cc及邊緣部分124ce之間的厚度差。在一些實施例中，基材部分112亦被蝕刻，以形成具有深度D1的凹陷，其中深度D1係比深度D2至D7淺。
如上所述，通道層124a、通道層124b及通道層124c的蝕刻量可以調整，以使深度D7(D6)大於深度D5(D4)，其中深度D5(D4)大於深度D3(D2)。因此，厚度Tc'係大於厚度Tb'，其中厚度Tb'大於厚度Ta'。圖15A至圖15B中的積體電路結構之其他相關結構及製程細節似實質相同或相似於圖13A至圖13B中的積體電路結構，因此相關說明將不再重複。
圖16至圖19B係繪示根據本揭露一些實施例之積體電路100b的形成中間階段的透視視圖及剖面視圖。根據一些例示實施例，形成的電晶體可包含p型電晶體(例如p型環繞式閘極場效電晶體)及/或n型電晶體(例如n型環繞式閘極場效電晶體)。透過各種視圖及說明的實施例，類似的參考數值係用以指示類似的元件。須理解的是，對於本方法的另一些實施例，可在圖16至圖19B所示的製程之前、期間及之後提供額外的操作，且以下所述之一些操作可以被取代或減少。操作/製程的順序可以互相交換。
圖16及圖17A係一些實施例之積體電路結構100b在製程中間階段的透視視圖。圖17B、圖18及圖19A係一些實施例之在製程中間階段的積體電路100b沿著第一切線(例如圖17A中的切線X-X)的剖面視圖，其係沿著通道的縱向方向且垂直於基材之頂表面。圖19B係圖190A中的區域Ab的放大視圖。
請參閱圖16，磊晶堆疊120係形成在基材110上。關於磊晶堆疊120之材料及製程細節係相似於圖1中所討論的磊晶堆疊120，因此為了簡潔，不再重複說明。(底部的)磊晶層124a具有厚度Ta，(中間的)磊晶層124b具有厚度Tb，且(頂部的)磊晶層124c具有厚度Tc。在一些實施例中，厚度Ta、厚度Tb及厚度Tc實質相同。在一些實施例中，厚度Ta、厚度Tb及厚度Tc之每一者的範圍為約2 nm至約30 nm。相似地，每一個磊晶層122具有厚度T。磊晶層122可具有實質固定的厚度T。換言之，二個相鄰磊晶層122之間的厚度差與二個相鄰磊晶層124a、磊晶層124b及/或磊晶層124c之間的厚度差實質相同。
請參閱圖17A及圖17B，在圖16中的沉積製程完成之後，圖16的結構經過與圖2至圖7B相似的製程。換言之，磊晶堆疊120係被圖案化為半導體鰭片130，隔離結構140係形成在基材110上，虛擬閘極結構150係形成在基材110上且係至少部分地設置在鰭片130上，閘極間隙壁160係形成在虛擬閘極結構150之側壁上，側向地延伸超過閘極間隙壁160的半導體鰭片之暴露部分係被蝕刻以形成凹陷R1，磊晶層122係側向地或水平地被凹陷以形成凹陷R2，且內側間隙壁材料層170係形成以填充凹陷R2。關於前述製程/元件的材料及製程細節係相似於圖2至圖7B中所示者，因此為了簡潔，在此不再重複說明。
請參閱圖18，在內側間隙壁材料層170沉積之後，圖17A及圖17B經過與圖8至圖10相似的製程。換言之，源極/汲極磊晶結構180係形成凹陷R1中且在半導體鰭片130的源極/汲極區域S/D上，(選擇性的接觸蝕刻中止層及)層間介電層210係形成在基材110上，虛擬閘極結構150(如圖17A所示)係先被移除，然後磊晶層(即犠牲層)122(如圖17B所示)被移除。接著，進行另一蝕刻製程，以過度蝕刻通道層124a、通道層124b及通道層124c，而形成開口O1’。
通道層124a、通道層124b及通道層124c係藉由異向性化學蝕刻製程310而被蝕刻/凹陷。在一些實施例中，蝕刻可藉由以電漿源及反應氣體的異向性化學蝕刻來進行。電漿源可為感應耦合式電漿(ICP)源、變壓耦合式電漿(TCP)源、電子迴旋共振(ECR)源或相似者，且反應氣體可為例如氟基氣體(例如SF 6、CH 2F 2、CH 3F、CHF 3或相似物)、氯基氣體(例如Cl 2)、溴化氫氣體(HBr)、氧氣(O 2)、相似物或前述之組合。
在一些實施例中，藉由調整蝕刻製程中的電漿能量及/或壓力，通道層124a、通道層124b及通道層124c的輪廓可被調整。舉例而言，通道層(例如通道層124c)愈高，通道層的蝕刻量愈多。換言之，通道層124c係被過度蝕刻的比通道層124a更嚴重。在一些實施例中，蝕刻製程可在約450 W至約4800 W的電漿源能量及約20 mTorr至約12000 mTorr的壓力下，利用O 3、O 2、O 2/N 2、O 2/H 2、O 2/Ar及/或O 2/He為蝕刻氣體來進行。若電漿源能量係大於約4800 W，通道層124a、通道層124b及通道層124c可能被過度蝕刻；若電漿源能量係小於約450 W，通道層124a、通道層124b及通道層124c的蝕刻不足。若壓力小於約20 mTorr，通道層124a、通道層124b及通道層124c的蝕刻不足；若壓力大於約12000 mTorr，通道層124a、通道層124b及通道層124c可能被過度蝕刻。
請參閱圖19A，在圖18的蝕刻製程310完成之後，圖18的結構係經過與圖11A至圖13A相似的製程。換言之，閘極結構220係形成在閘極溝渠GT1及開口O1'中，閘極結構220係被回蝕，介電質蓋230係形成在被回蝕的閘極結構220之上，開口係形成在層間介電層210中，以暴露源極/汲極磊晶結構180，且源極/汲極接觸240係形成在開口內。關於前述製程/元件的材料及製程細節係與圖11A至圖13A所示者相似，因此為了簡潔，在此不再重複說明。
圖19B係圖19A中的區域Ab的放大視圖。請參閱圖19A及圖19B。積體電路結構100b包含基材110、在基材110上的通道層124a、通道層124b及通道層124c、包圍通道層124a、通道層124b及通道層124c之每一者的閘極結構220、連接通道層124a、通道層124b及通道層124c的源極/汲極磊晶結構180，及分別在源極/汲極磊晶結構180上的源極/汲極接觸240。
通道層124c係靠近源極/汲極接觸240，且通道層124a係遠離源極/汲極接觸240。如上所述，厚的通道層124a及/或通道層124b降低通道層124a及/或通道層124b的電阻，以使流過通道層124a及/或通道層124b的驅動電流可以增加。
在一些實施例中，通道層124a包含中心部分124ac及在中心部分124ac之相對末端上的二個邊緣部分124ae。邊緣部分124ae比中心部分124ac厚。中心部分124ac具有厚度Ta'，且凹陷之深度D2及D3的總和係中心部分124ac及邊緣部分124ae之間的厚度差。相似地，通道層124b包含中心部分124bc及在中心部分124bc之相對末端上的二個邊緣部分124be。邊緣部分124be比中心部分124bc厚。中心部分124bc具有厚度Tb'，且凹陷之深度D4及D5的總和係中心部分124bc及邊緣部分124be之間的厚度差。同樣地，通道層124c包含中心部分124cc及在中心部分124cc之相對末端上的二個邊緣部分124ce。邊緣部分124ce比中心部分124cc厚。中心部分124cc具有厚度Tc'，且凹陷之深度D6及D7的總和係中心部分124cc及邊緣部分124ce之間的厚度差。在一些實施例中，基材部分112亦被蝕刻，以形成具有深度D1的凹陷，其中深度D1係比深度D2至D7淺。
如上所述，通道層124a、通道層124b及通道層124c的蝕刻量可以調整，以使深度D7(D6)大於深度D5(D4)，其中深度D5(D4)大於深度D3(D2)。因此，厚度Tc'係大於厚度Tb'，其中厚度Tb'大於厚度Ta'。圖19A至圖19B中的積體電路結構之其他相關結構及製程細節似實質相同或相似於圖13A至圖13B及圖15A至圖15B中的積體電路結構，因此相關說明將不再重複。
基於上述討論，可看出本揭露提供優勢。然而，須理解的是，其他實施例可提供不同的優勢，且並非所有優勢都有必要在此揭露，且沒有特別的優勢係對所有實施例皆適用。一個優勢係具有不同厚度的通道層可優化積體電路結構的驅動電流。另一個優勢係通道層的厚度可在沉積通道層時被決定。再另一優勢係可增加過度蝕刻製程，以進一步微調整通道層的厚度。再者，厚度係依據不同應用來決定。
根據一些實施例，裝置包含第一通道層、第二通道層、閘極結構、源極/汲極磊晶結構及源極/汲極接觸。第一通道層及配置在第一通道層上的第二通道層係以間隔分開的方式在基材上。閘極結構圍繞第一通道層及第二通道層。源極/汲極磊晶結構連接至第一通道層及第二通道層。源極/汲極接觸連接至源極/汲極磊晶結構。第二通道層比第一通道層更靠近源極/汲極接觸，且第一通道層比第二通道層更厚。
根據上述實施例，上述半導體裝置更包含在第二通道層上的第三通道層。且第二通道層及第三通道層係以間隔分開的方式在基材上。根據上述實施例，第三通道層比第二通道層更靠近源極/汲極接觸，且第二通道層比第三通道層厚。根據上述實施例，第一通道層及第二通道層之間的距離與第二通道層及第三通道層之間的距離實質相同。根據上述實施例，第一通道層包含中心部分及邊緣部分，中心部分被閘極結構包圍，邊緣部分相互連接第一通道層之中心部分與源極/汲極磊晶結構，且第一通道層之邊緣部分比第一通道層之中心部分更厚。根據上述實施例，第二通道層包含中心部分及邊緣部分，中心部分被閘極結構包圍，邊緣部分相互連接第二通道層之中心部分與源極/汲極磊晶結構，且第二通道層之邊緣部分比第二通道層之中心部分更厚。根據上述實施例，閘極結構包含閘極介電層，其係自第一通道層之邊緣部分之內側壁延伸至第二通道層之邊緣部分之內側壁。根據上述實施例，第一通道層之邊緣部分及中心部分具有第一厚度差，第二通道層之邊緣部分及中心部分具有第二厚度差，且第二厚度差大於第一厚度差。根據上述實施例，上述半導體裝置更包含內側間隙壁，其係在閘極結構及源極/汲極磊晶結構之間，內側間隙壁接觸第一通道層之邊緣部分，並與第一通道層之中心部分分離。根據上述實施例，第一通道層之長度大於第二通道層之長度。
根據一些實施例，方法包含形成磊晶堆疊在基材上。磊晶堆疊包含第一犠牲層、第一通道層、第二犠牲層及第二通道層依序在基材上。第一通道層之厚度大於第二通道層之厚度。磊晶堆疊係被圖案化為鰭片結構。形成虛擬閘極結構穿過鰭片結構，以使虛擬閘極結構覆蓋鰭片結構之第一部分，而使鰭片結構之第二部分被暴露。鰭片結構之被暴露的第二部分係被移除。形成源極/汲極磊晶結構在鰭片結構之第一部分內的第一通道層及第二通道層之相對末端表面上。移除虛擬閘極結構，以暴露鰭片結構之第一部分。移除在鰭片結構之被暴露的第一部分中的第一犠牲層及第二犠牲層，而留下在鰭片結構之被暴露的第一部分中的第一通道層及第二通道層懸掛在基材上。形成閘極結構，以圍繞懸掛的第一通道層及第二通道層之每一者。
根據上述實施例，第一通道層之厚度與第二通道層之厚度之間的厚度差大於0 nm且小於或等於28 nm。根據上述實施例，上述形成磊晶堆疊之步驟包含以第一沉積時間形成第一通道層及以第二沉積時間形成第二通道層。第二沉積時間係小於第一沉積時間。根據上述實施例，上述形成磊晶堆疊之步驟包含以第一沉積時間形成第一通道層及以第二沉積時間形成第二通道層。第二沉積時間與第一沉積時間實質相同。根據上述實施例，上述移除鰭片結構之被暴露的第二部分之步驟係使第一通道層之第一部分的長度大於第二通道層之第一部分的長度。
根據一些實施例，方法包含形成磊晶堆疊在基材上。磊晶堆疊包含第一犠牲層、第一通道層、第二犠牲層及第二通道層依序在基材上。磊晶堆疊係被圖案至沿著第一方向延伸的鰭片結構中。形成虛擬閘極結構以沿著第二方向延伸穿過鰭片結構，其中第二方向實質垂直第一方向。閘極間隙壁係分別在虛擬閘極結構之相對側上。移除虛擬閘極結構，以形成閘極溝渠在閘極間隙壁之間。自閘極溝渠選擇性地移除第一犠牲層及第二犠牲層，而留下第一通道層及第二通道層懸掛在閘極溝渠內。在選擇性地移除第一犠牲層及第二犠牲層之後，形成凹陷分別在第一通道層及第二通道層內。第二通道層內之凹陷的深度大於第一通道層內之凹陷的深度。在形成凹陷分別在第一通道層及第二通道層內之後，形成閘極結構在閘極溝渠及凹陷內。
根據上述實施例，上述形成凹陷分別在第一通道層及第二通道層內的步驟包含進行電漿異向性蝕刻製程，以形成凹陷在第一通道層及第二通道層內。根據上述實施例，上述電漿異向性蝕刻製程係在450 W至4800 W的電漿源能量下進行。根據上述實施例，上述電漿異向性蝕刻製程係在20 mTorr至12000 mTorr的壓力下進行。根據上述實施例，在上述形成凹陷分別在第一通道層及第二通道層內的步驟之前，方法更包含形成內側間隙壁在第一通道層及第二通道層之間。
上述摘要許多實施例的特徵，因此本領域具有通常知識者可更了解本揭露的態樣。本領域具有通常知識者應理解利用本揭露為基礎可以設計或修飾其他製程和結構以實現和所述實施例相同的目的及/或達成相同優勢。本領域具有通常知識者也應了解與此同等的架構並沒有偏離本揭露的精神和範圍，且可以在不偏離本揭露的精神和範圍下做出各種變化、交換和取代。
100,100a,100b:積體電路結構 102:溝渠 110:基材 112:基材部分 120:磊晶堆疊 122:磊晶層 124a,124b,124c:磊晶層/通道層 124ac,124bc,124cc:中心部分 124ae,124be,124ce:邊緣部分 130:鰭片 140:隔離區域 150:虛擬閘極結構 152:虛擬閘極介電層 154:虛擬閘極電極層 156:氧化層 158:氮化層 160:間隙壁材料層 162:第一間隙壁層 164:第二間隙壁層 170:內側間隙壁材料層 180:源極/汲極磊晶結構 210:層間介電層 220:閘極結構 222:閘極介電層 224:功函數金屬層 226:填充金屬 230:介電質蓋 240:源極/汲極接觸 310:蝕刻製程 910:硬罩幕層 912:氧化層 914:氮化層 A,Aa,Ab:區域 D1,D2,D3,D4,D5,D6,D7:深度 GT1:閘極溝渠 H,H1:高度 Ia,Ib,Ic:驅動電流 O1,O1’:開口 R1,R2:凹陷 S/D:源極/汲極區域 T,Ta,Tb,Tc,Ta’,Tb’,Tc’:厚度 W1:寬度 X-X,Y-Y:切線
根據以下詳細說明並配合附圖閱讀，使本揭露的態樣獲致較佳的理解。需注意的是，如同業界的標準作法，許多特徵並不是按照比例繪示的。事實上，為了進行清楚討論，許多特徵的尺寸可以經過任意縮放。 [圖1]至[圖13B]係繪示根據本揭露一些實施例之積體電路結構的形成中間階段的透視視圖及剖面視圖。 [圖14]至[圖15B]係繪示根據本揭露一些實施例之製造積體電路結構之各階段的例示剖面視圖。 [圖16]至[圖19B]係繪示根據本揭露一些實施例之積體電路結構的形成中間階段的透視視圖及剖面視圖。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
100:積體電路結構
110:基材
112:基材部分
124a,124b,124c:磊晶層/通道層
160:間隙壁材料層
162:第一間隙壁層
164:第二間隙壁層
170:內側間隙壁材料層
180:源極/汲極磊晶結構
220:閘極結構
222:閘極介電層
224:功函數金屬層
226:填充金屬
230:介電質蓋
240:源極/汲極接觸
A:區域
S/D:源極/汲極區域

Claims (20)

  1. 一種半導體裝置，包含： 一第一通道層及一第二通道層，其中該第二通道層配置在該第一通道層之上，並以間隔分開的方式在一基材上； 一閘極結構，圍繞該第一通道層及該第二通道層； 一源極/汲極磊晶結構，連接至該第一通道層及該第二通道層；以及 一源極/汲極接觸，連接至該源極/汲極磊晶結構，其中該第二通道層比該第一通道層更靠近該源極/汲極接觸，且該第一通道層比該第二通道層更厚。
  2. 如請求項1所述之半導體裝置，更包含： 一第三通道層，在該第二通道層之上，並以間隔分開的方式在該基材上。
  3. 如請求項2所述之半導體裝置，其中該第三通道層比該第二通道層更靠近該源極/汲極接觸，且該第二通道層比該第三通道層厚。
  4. 如請求項2所述之半導體裝置，其中該第一通道層及該第二通道層之間的一距離與該第二通道層及該第三通道層之間的一距離為實質相同。
  5. 如請求項1所述之半導體裝置，其中該第一通道層包含一中心部分及一邊緣部分，該中心部分被該閘極結構包圍，該邊緣部分相互連接該第一通道層之該中心部分與該源極/汲極磊晶結構，且該第一通道層之該邊緣部分比該第一通道層之該中心部分更厚。
  6. 如請求項5所述之半導體裝置，其中該第二通道層包含一中心部分及一邊緣部分，該中心部分被該閘極結構包圍，該邊緣部分相互連接該第二通道層之該中心部分與該源極/汲極磊晶結構，且該第二通道層之該邊緣部分比該第二通道層之該中心部分更厚。
  7. 如請求項6所述之半導體裝置，其中該閘極結構包含一閘極介電層，自該第一通道層之該邊緣部分之一內側壁延伸至該第二通道層之該邊緣部分之一內側壁。
  8. 如請求項6所述之半導體裝置，其中該第一通道層之該邊緣部分及該中心部分具有一第一厚度差，該第二通道層之該邊緣部分及該中心部分具有一第二厚度差，且該第二厚度差大於該第一厚度差。
  9. 如請求項5所述之半導體裝置，更包含： 一內側間隙壁，在該閘極結構及該源極/汲極磊晶結構之間，其中該內側間隙壁接觸該第一通道層之該邊緣部分，並與該第一通道層之該中心部分分離。
  10. 如請求項1所述之半導體裝置，其中該第一通道層之一長度大於該第二通道層之一長度。
  11. 一種半導體裝置的製造方法，包含： 形成一磊晶堆疊在一基材上，其中該磊晶堆疊包含一第一犠牲層、一第一通道層、一第二犠牲層及一第二通道層依序在該基材上，且該第一通道層之一厚度大於該第二通道層之一厚度； 圖案化該磊晶堆疊為一鰭片結構； 形成一虛擬閘極結構，穿過該鰭片結構，以使該虛擬閘極結構覆蓋該鰭片結構之一第一部分，此時該鰭片結構之複數個第二部分被暴露； 移除該鰭片結構之被暴露的該些第二部分； 形成源極/汲極磊晶結構，在該鰭片結構之該第一部分內的該第一通道層及該第二通道層之相對末端表面上； 移除該虛擬閘極結構，以暴露該鰭片結構之該第一部分； 移除在該鰭片結構之該被暴露的該第一部分中的該第一犠牲層及該第二犠牲層，而留下在該鰭片結構之被暴露的該第一部分中的該第一通道層及該第二通道層懸掛在該基材上；以及 形成一閘極結構，以圍繞懸掛的該第一通道層及該第二通道層之每一者。
  12. 如請求項11所述之方法，其中該第一通道層之該厚度與該第二通道層之該厚度之間的一厚度差大於0 nm且小於或等於28 nm。
  13. 如請求項11所述之方法，其中該形成該磊晶堆疊之步驟包含： 以一第一沉積時間形成該第一通道層及以一第二沉積時間形成該第二通道層，其中該第二沉積時間小於該第一沉積時間。
  14. 如請求項11所述之方法，其中該形成該磊晶堆疊之步驟包含： 以第一沉積時間形成該第一通道層，及以一第二沉積時間形成該第二通道層，且該第二沉積時間與該第一沉積時間實質相同。
  15. 如請求項11所述之方法，其中該移除該鰭片結構之該被暴露的該些第二部分之步驟係使該第一通道層之該第一部分的一長度大於該第二通道層之該第一部分的一長度。
  16. 一種半導體裝置的製造方法，包含： 形成一磊晶堆疊在一基材上，其中該磊晶堆疊包含一第一犠牲層、一第一通道層、一第二犠牲層及一第二通道層依序在該基材； 圖案化該磊晶堆疊至一鰭片結構中，其中該鰭片結構沿著一第一方向延伸； 形成一虛擬閘極結構，沿著一第二方向延伸穿過該鰭片結構，其中該第二方向實質垂直該第一方向； 形成複數個閘極間隙壁，分別在該虛擬閘極結構之相對側上； 移除該虛擬閘極結構，以形成一閘極溝渠在該些閘極間隙壁之間； 自該閘極溝渠選擇性地移除該第一犠牲層及該第二犠牲層，而留下該第一通道層及該第二通道層懸掛在該閘極溝渠內； 在選擇性地移除該第一犠牲層及該第二犠牲層之後，形成複數個凹陷分別在該第一通道層及該第二通道層內，其中該第二通道層內之該凹陷的一深度大於該第一通道層內之該凹陷的一深度；以及 在形成該些凹陷分別在該第一通道層及該第二通道層內之後，形成一閘極結構在該閘極溝渠及該些凹陷內。
  17. 如請求項16所述之方法，其中該形成該些凹陷分別在該第一通道層及該第二通道層內的步驟包含進行一電漿異向性蝕刻製程，以形成該些凹陷在該第一通道層及該第二通道層內。
  18. 如請求項17所述之方法，其中該電漿異向性蝕刻製程係在450 W至4800 W的一電漿源能量下進行。
  19. 如請求項17所述之方法，其中該電漿異向性蝕刻製程係在20 mTorr至12000 mTorr的一壓力下進行。
  20. 如請求項16所述之方法，在該形成該些凹陷分別在該第一通道層及該第二通道層內的步驟之前，更包含： 形成一內側間隙壁，在該第一通道層及該第二通道層之間。
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