TW202236423A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW202236423A TW202236423A TW111103266A TW111103266A TW202236423A TW 202236423 A TW202236423 A TW 202236423A TW 111103266 A TW111103266 A TW 111103266A TW 111103266 A TW111103266 A TW 111103266A TW 202236423 A TW202236423 A TW 202236423A
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Abstract
形成半導體裝置的方法包括:在基底上方形成內連線結構;在內連線結構上方形成第一鈍化層;在第一鈍化層上方形成第一導電特徵且電耦合到內連線結構;在第一導電特徵和第一鈍化層上方共形地形成第二鈍化層;在第二鈍化層上方形成介電層;以及在第一導電特徵上方形成第一凸塊通孔和第一導電凸塊並電耦合到第一導電特徵,其中第一凸塊通孔位於第一導電凸塊和第一導電特徵之間,其中第一凸塊通孔延伸到介電層中,穿過第二鈍化層,且接觸第一導電特徵,其中第一導電凸塊位在介電層上方且電耦合到第一凸塊通孔。
Description
本揭露是關於一種半導體裝置及其製造方法,特別是關於一種在介電層中形成開口以形成導電凸塊的半導體裝置及其製造方法。
例如超大規模積體(very large scale integration;VLSI)電路的高密度積體電路通常由作為三維佈線結構的內連線結構(也稱為內連線)形成。內連線結構的目的是將密集封裝的裝置適當地連接在一起以形成功能電路。隨著整合度的提高,造成電阻電容延遲(RC delay)和串擾(crosstalk)的內連線金屬線之間的寄生電容效應也對應地增加。為了降低寄生電容且提高內連線的傳導速度,通常採用低介電常數(low-k)介電材料來形成層間介電(inter-layer dielectric;ILD)層和金屬間介電(inter-metal dielectric;IMD)層。
金屬線和通孔形成在金屬間介電層中。形成製程可包括在第一導電特徵上方形成蝕刻停止層,以及在蝕刻停止層上方形成低介電常數介電層。圖案化低介電常數介電層和蝕刻停止層以形成溝槽和通孔開口。接著用導電材料填充溝槽和通孔開口,隨後進行平坦化製程以移除多餘的導電材料,進而形成金屬線和通孔。導電凸塊(例如微凸塊(micro-bumps;μ-bumps)和可控塌陷晶片連接凸塊(controlled collapse chip connection Bumps;C4 bumps)等)形成在內連線結構上方,用以與其他裝置連接。
本揭露實施例提供一種半導體裝置的製造方法,包括:在基底上方形成內連線結構;在內連線結構上方形成第一鈍化層;在第一鈍化層上方形成第一導電特徵且電耦合到內連線結構;在第一導電特徵和第一鈍化層上方共形地形成第二鈍化層;在第二鈍化層上方形成介電層;以及在第一導電特徵上方形成第一凸塊通孔和第一導電凸塊並電耦合到第一導電特徵,其中第一凸塊通孔位於第一導電凸塊和第一導電特徵之間,其中第一凸塊通孔延伸到介電層中,穿過第二鈍化層,且接觸第一導電特徵,其中第一導電凸塊位在介電層上方且電耦合到第一凸塊通孔。
本揭露實施例提供一種半導體裝置的製造方法,包括:在內連線結構上方形成第一鈍化層,其中內連線結構位在形成於基底中的電子元件上方且電耦合到形成在基底中的電子元件;在第一鈍化層上方形成導電特徵,其中導電特徵電耦合到內連線結構;在導電特徵和第一鈍化層上方形成第二鈍化層,其中第二鈍化層是共形的且沿著導電特徵的外表面延伸;在第二鈍化層上方形成介電層,其中介電層遠離基底的上表面比導電特徵遠離基底的上表面從基底延伸得更遠;形成從介電層的上表面延伸至導電特徵的上表面的凸塊通孔,其中凸塊通孔的寬度隨著凸塊通孔向導電特徵的延伸而連續變化;以及在凸塊通孔上形成導電凸塊。
本揭露實施例提供一種半導體裝置,包括:基底,包括裝置區域;內連線結構,位在基底上方且電耦合到裝置區域;第一鈍化層,位於內連線結構上方;導電特徵,位於第一鈍化層上方且電耦合到內連線結構;第二鈍化層,位在導電特徵和第一鈍化層上方,其中第二鈍化層是共形的且沿著導電特徵的外表面延伸;介電層,位在第二鈍化層上方,其中介電層比導電特徵從基底延伸得更遠;凸塊通孔,位於介電層中,其中凸塊通孔從介電層遠離基底的上表面延伸至導電特徵,其中凸塊通孔的寬度隨著凸塊通孔向導電特徵延伸而連續地變化;以及導電凸塊,位於凸塊通孔上。
以下的揭露內容提供許多不同的實施例或範例以實施本揭露實施例的不同特徵。以下敘述構件及配置的特定範例,以簡化本揭露實施例的說明。當然,這些特定的範例僅為示範並非用以限定本揭露實施例。舉例而言,在以下的敘述中提及第一特徵形成於第二特徵上或上方,即表示其可包括第一特徵與第二特徵是直接接觸的實施例,亦可包括有附加特徵形成於第一特徵與第二特徵之間,而使第一特徵與第二特徵可能未直接接觸的實施例。
此外,在此可使用與空間相關用詞。例如「底下」、「下方」、「較低的」、「上方」、「較高的」及類似的用詞,以便於描述圖式中繪示的一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外,這些空間相關用詞意欲包括使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位),且在此使用的空間相關詞也可依此做同樣的解釋。在所有揭露內容中,除非另外說明,不同圖式中以相同或相似的參考標號表示以相同或相似的材料透過相同或相似的方法所形成的相同或相似的元件。此外,除非另有說明,具有相同數字和不同字母的圖(例如第8A圖和第8B圖)繪示同一半導體裝置在同一製造階段的不同視圖(例如沿著不同的剖面)。
根據一些實施例,導電凸塊(例如受控塌陷晶片連接凸塊或微凸塊)形成在導電特徵(例如導電墊或導電線)上方的介電層中的對齊式開口或拉入式開口中。共形鈍化層形成在導電特徵上方,且介電層形成在共形鈍化層上方。形成對齊式開口或拉入式開口以延伸穿過介電層和鈍化層以暴露下方的導電特徵,接著在導電特徵上的對齊式開口或拉入式開口中形成導電凸塊。對齊式開口或拉入式開口增加鈍化層與介電層之間的附著力,且降低鈍化層與介電層之間的界面處的應力。如此一來,避免或減少了鈍化層和介電層之間的界面處的分層。透過在鈍化層上方形成介電層作為平坦化層,可避免或減少凸塊種子層階梯覆蓋和不連續性等問題,進而提高裝置可靠性和生產良率。
第1A圖、第1B圖、第2圖至第7圖和第8A圖至第8C圖繪示根據一些實施例之在製造的各個階段的半導體裝置100的剖視圖。半導體裝置100可以是包括主動裝置(例如電晶體)及/或被動裝置(例如電容器、電感器、電阻器等)的裝置晶圓。在一些實施例中,半導體裝置100是中介晶圓,其可以包括或不包括主動裝置及/或被動裝置。根據本揭露的又一實施例,半導體裝置100為一封裝基底帶,其可以是具有芯封裝基底或無芯封裝基底。在後續的說明中,以裝置晶圓作為半導體裝置100的範例。本揭露的教示也可應用於中介晶圓、封裝基底或其他半導體結構,此為本揭露所屬技術領域中具有通常知識者應可容易理解的。
如第1A圖所示,半導體裝置100包括半導體基底101和形成在半導體基底101(也可稱為基底101)上或半導體基底101中的電子元件103。半導體基底101可包括半導體材料,例如摻雜或未摻雜的矽,或者絕緣體上半導體(semiconductor-on-insulator;SOI)基底的主動層。半導體基底101可以包括其他半導體材料,例如鍺、化合物半導體(包括碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP)或前述的組合。也可以使用其他基底,例如多層或梯度基底。
在第1A圖的範例中,電子元件103形成在半導體基底101的裝置區域中。電子元件103的範例包括電晶體(例如互補式金屬氧化物半導體(Complementary Metal-Oxide Semiconductor;CMOS)電晶體)、電阻器、電容器、二極體等。電子元件103可以採用任何適合的方法形成,在此不再贅述。
在一些實施例中,在形成電子元件103之後,在半導體基底101和電子元件103之上形成層間介電(ILD)層。層間介電層可以填充電子元件103的電晶體(未圖示)的閘極堆疊之間的空間。根據一些實施例,層間介電層包括氧化矽、磷矽酸鹽玻璃(phosphosilicate glass;PSG)、硼矽酸鹽玻璃(borosilicate glass;BSG)、摻硼磷矽酸鹽玻璃(boron-doped phosphosilicate glass;BPSG)、摻氟矽酸鹽玻璃(fluorine-doped silicate glass;FSG)等。可以使用旋塗、可流動化學氣相沉積(Flowable Chemical Vapor Deposition;FCVD)、電漿增強化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition;PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition;LPCVD)等來形成層間介電層。
接觸插塞形成在層間介電層中,接觸插塞將電子元件103電耦合到隨後形成的內連線結構106的導電特徵(例如金屬線、通孔)。應注意的是,在本揭露中除非另有說明,導電特徵是指可導電的特徵,而導電材料是指可導電的材料。根據一些實施例,接觸插塞由例如鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、前述的合金及/或前述的多層的導電材料形成。接觸插塞的形成可包括在層間介電層中形成接觸開口,在接觸開口中形成一或多種導電材料,以及進行平坦化製程,例如化學機械拋光(Chemical Mechanical Polish;CMP),以使接觸插塞的頂面與層間介電層的頂面齊平。
仍請參照第1A圖,內連線結構106形成在層間介電層上方和電子元件103上方。內連線結構106包括複數個介電層109和形成在介電層109中的導電特徵(例如金屬線、通孔)。在一些實施例中,內連線結構106與電子元件103互連以形成半導體裝置100的功能電路。
在一些實施例中,每個介電層109(也可被稱為金屬間介電(IMD)層)由介電材料形成,例如氧化矽、氮化矽、碳化矽、氮氧化矽或類似的材料。根據一些實施例,介電層109由具有介電常數(k值)低於3.0(例如約2.5、約2.0或甚至更低)的低介電常數介電材料形成。介電層109可以包括含碳低介電常數介電材料、氫倍半矽氧烷(Hydrogen SilsesQuioxane;HSQ)、甲基倍半矽氧烷(MethylSilsesQuioxane;MSQ)等。舉例而言,每個介電層109的形成可包括在層間介電層上沉積含成孔劑的介電材料,隨後進行固化製程以去除成孔劑,進而形成多孔的介電層109。亦可以使用其他適合的方法來形成介電層109。
如第1A圖所示,例如導電線105和通孔107等導電特徵形成在介電層109中。在範例實施例中,導電特徵可包括擴散阻擋層和導電材料(例如擴散阻擋層上方的銅或含銅材料)。擴散阻擋層可以包括鈦、氮化鈦、鉭、氮化鉭等,且可以透過化學氣相沉積(chemical vapor deposition;CVD)、物理氣相沉積(Physical Vapor Deposition;PVD)、原子層沉積(Atomic Layer Deposition;ALD)等形成。在形成擴散阻擋層之後,在擴散阻擋層上方形成導電材料。導電特徵的形成可以包括單鑲嵌製程、雙鑲嵌製程等。
接下來,在內連線結構106上方形成鈍化層111,且在鈍化層111中形成複數個金屬-絕緣體-金屬(metal-insulator-metal;MIM)電容器113。鈍化層111可以包括複數個子層(例如參見第1B圖中的111A至111E),且可由一或多種適合的介電材料形成,例如氧化矽、氮化矽、低介電常數介電質(例如碳摻雜氧化物)、極低介電常數介電質(例如多孔摻雜碳的二氧化矽、前述的組合等。鈍化層111可以透過例如化學氣相沉積(CVD)、可流動式化學氣相沉積(FCVD)的製程來形成,但是也可以使用任何適合的製程。
金屬-絕緣體-金屬電容器113形成在鈍化層111中。第1B圖繪示第1A圖中區域102的放大圖,以顯示金屬-絕緣體-金屬電容器113的細節。如第1B圖所示,每個金屬-絕緣體-金屬電容器圖113包括兩個金屬層113M(例如銅層)和位於金屬層113M之間的介電層113I(例如高介電常數介電層)。 金屬-絕緣體-金屬電容器113的每一層(例如113M、113I和113M)形成在相應的鈍化層(例如111B、111C或111D)中。金屬-絕緣體-金屬電容器113的上金屬層113M和下金屬層113M可以分別連接到上層通孔119V和下層通孔108,其中上層通孔119V和下層通孔108分別形成在鈍化層111E和111A中,作為範例。作為另一範例,金屬-絕緣體-金屬電容器113的上金屬層113M和下金屬層113M可以分別連接到第一上層通孔119V1和第二上層通孔119V2。在第1B圖的範例中,第二上層通孔119V2延伸穿過鈍化層111D和介電層113I以與下金屬層113M連接。應注意的是,第二上層通孔119V2延伸穿過金屬-絕緣體-金屬電容器的上金屬層113M中的開口,因此會透過鈍化層111D的部分與金屬-絕緣體-金屬電容器的上金屬層113M分隔開(例如不接觸)。
再次參照第1A圖,金屬-絕緣體-金屬電容器113的下金屬層可以電耦合到內連線結構106的導電特徵,例如透過從金屬-絕緣體-金屬電容器113的下金屬層延伸到內連線結構106的導電特徵。此外,複數個金屬-絕緣體-金屬電容器113可並聯電耦合以提供大電容值。舉例而言,金屬-絕緣體-金屬電容器113的上金屬層可以電耦合在一起,且金屬-絕緣體-金屬電容器113的下金屬層可以電耦合在一起。在一些實施例中,金屬-絕緣體-金屬電容器113則被省略。
接下來參照第2圖,在鈍化層111中形成開口112。一些開口112延伸穿過鈍化層111以暴露內連線結構106的導電特徵。在一些實施例中,一些開口112延伸且部分地穿過鈍化層111以暴露金屬-絕緣體-金屬電容器113的上金屬層。開口112可以在一或多個蝕刻製程(例如非等向性蝕刻製程)中形成。
在形成開口112之後,在鈍化層111的上表面上方且沿著開口112的側壁和底部共形地形成阻擋層115。阻擋層115可以具有多層結構且可以包括擴散阻擋層(例如TiN層)和形成在擴散阻擋層上方的種子層(例如銅種子層)。阻擋層115可以使用任何適合的形成方法形成,例如化學氣相沉積、物理氣相沉積、原子層沉積、前述的組合等。
接下來,在第3圖中,在阻擋層115上形成光阻層 137。將光阻層137圖案化(例如使用微影技術)以在將要形成導電墊119(參見第4圖)的位置處形成開口138。開口138暴露例如阻擋層115的種子層。在形成開口138之後,進行除渣製程110以清除光阻層137的圖案化製程所留下的殘留物。除渣製程110可以是例如使用包含氧氣的製程氣體來進行的電漿製程。
接下來,在第4圖中,在阻擋層115上方的開口138中形成導電墊119(例如119A和119B)。導電墊119可以包括導電材料,例如銅或銅合金 (例如銅-銀合金、銅-鈷合金等),且可以使用適合的形成方法(例如電鍍、化學鍍等)來形成。在形成導電墊119之後,透過適合的移除製程(例如灰化)來移除光阻層137。接下來,進行蝕刻製程以移除阻擋層115上未形成導電墊119的部分。如第4圖所示,部分導電材料填充鈍化層111中的開口112(見第3圖)以形成通孔119V,通孔119V將導電墊119電耦合到內連線結構106的下方導電特徵及/或金屬-絕緣體-金屬電容器113。應注意的是,在本揭露的說明中,開口112中的阻擋層115被認為是通孔119V的一部分,且在鈍化層111的上表面上的阻擋層115被認為是導電墊119的一部分。儘管在第4圖中未顯示,但在形成導電墊119的相同製程步驟期間,也可在鈍化層111(例如參見第12圖中的 118)的上表面上形成導電線(例如銅線)。導電墊119和導電線可以統稱為重分佈層(redistribution layer;RDL),通孔119V可被稱為重分佈層通孔。舉例而言,導電墊119的截面形狀可以是圓頂形(例如具有彎曲的上表面)、凹形、多邊形或矩形(或正方形)形。舉例而言,重分佈層通孔119V的面積可介於約0.9x0.9µm
2和約3.5x3.5µm
2之間。
應注意的是,在第4圖中,一些導電墊119(例如119A)比其他導電墊119(例如119B)更大(例如具有在相對側壁之間測量的更大寬度)。在一些實施例中,可控塌陷晶片連接凸塊(C4 bumps)形成在較大的導電墊119A上,而微凸塊(μ-bumps)形成在較小的導電墊119B上。導電墊119的數量可以是任何適合的數量,且可以任何順序排列,如本揭露所屬技術領域中具有通常知識者所能理解的。此外,雖然在第4圖中在每一導電墊119下方繪示了一個重分佈層通孔119V,但在每一導電墊119下方的重分佈層通孔119V的數量可以是任何適合的數量,例如一個、兩個、三個或更多。此外,每個導電墊119下方的重分佈層通孔119V可以位於導電墊119的中心處,或者可以偏離導電墊119的中心。
接下來,在第5圖中,鈍化層121共形地形成在導電墊119上方和鈍化層111上方。在一些實施例中,鈍化層121具有多層結構且包括氧化物層(例如氧化矽)和位於氧化層上方的氮化物層(例如氮化矽)。在其他實施例中,鈍化層121具有單層結構,例如具有單一氮化物層。可以使用例如化學氣相沉積、物理氣相沉積、原子層沉積、前述的組合等來形成鈍化層121。
接下來,在第6圖中,透過例如旋塗在鈍化層121上形成光阻層135。接著透過例如微影技術將光阻層135圖案化以在將形成導電凸塊的位置處形成開口136。接下來,進行蝕刻製程以移除鈍化層121被開口136暴露的部分。在一些實施例中,蝕刻製程是使用包括CF
4、CHF
3、N
2和Ar的混合物的製程氣體的乾式蝕刻製程(例如電漿蝕刻製程)。也可以使用其他製程氣體,舉例而言,可以使用O
2代替CF
4。在蝕刻製程之後,暴露導電墊119。接下來,透過適當的移除製程(例如灰化)來移除光阻層135。應注意的是,為簡單起見,在第6圖中僅在較大的導電墊119A上繪示一個開口136,用於形成導電凸塊125(參見第8A圖),而在其他導電墊(例如119B)上沒有形成開口。當然,這僅僅是一個非限制性範例。本揭露所屬技術領域中具有通常知識者將容易理解可進行相同或相似的製程步驟,以在其他導電墊(例如119B)上形成導電凸塊。
接下來,在第7圖中,在鈍化層121上方、導電墊119上方和鈍化層111上方形成介電層131。在介電層131中形成開口132以暴露下方的導電墊119。介電層131可由例如聚合物、聚醯亞胺(polyimide;PI)、苯並環丁烯(benzocyclobutene;BCB)、氧化物(例如氧化矽)或氮化物(例如氮化矽)形成。作為非限制性範例,介電層131在第7圖中被繪示為單層。介電層131可以具有包括由不同介電材料形成的多個子層的多層結構。
在一些實施例中,介電層131為光敏材料,例如光敏聚合物材料,且開口132透過微影技術形成。舉例而言,光敏材料可透過例如光罩暴露於圖案化的能量源(例如光)。能量的影響在光敏材料受圖案化能量源影響的那些部分中引起化學反應,進而改變光敏材料的曝光部分的物理性質,使得光敏材料的曝光部分的物理性質改變而不同於光敏材料的未曝光部分的物理性質。隨後可以用顯影劑將光敏材料顯影以移除光敏材料的曝光部分或光敏材料的未曝光部分,取決於例如使用負光敏材料還是正光敏材料。光敏材料的剩餘部分可以被固化以形成圖案化的介電層131。在第7圖中,在開口132處的介電層131的頂角被繪示為尖銳的(例如包括兩條相交的線)以作為非限制性範例。介電層131在開口132處的頂角可以是例如圓角。
在第7圖中,由開口132暴露的介電層131的相對側壁131S之間的第一距離小於第6圖中由開口136暴露的鈍化層121的相對側壁121S之間的第二距離。換言之,介電層131的開口132比保護層121的開口136窄,使得保護層121的上表面121U和側壁121S完全被介電層131覆蓋。由於介電層131從鈍化層121的側壁121S被拉入,因此第7圖中的開口132稱為拉入式開口。在第7圖中作為非限制性範例,介電層131的側壁131S被繪示為具有線性輪廓(例如斜線或相對於基底101的主上表面傾斜的平坦側壁)。側壁131S可以是直線(例如垂直於基底101的主上表面)或曲線。開口132的寬度(例如在相對的側壁131S之間測量的距離)可以是固定的,或者可沿著開口132的深度方向連續地變化(例如逐漸地而非階梯式變化)。
與拉出式開口相比,拉入式開口132提高了裝置可靠性和產量。在拉出式開口中,介電層131的側壁131S會從開口132被拉出至圖7中虛線130所指示的位置。換言之,如果開口132被形成為拉出式開口時,開口132的寬度將大於第6圖中開口136的寬度。當形成拉出式開口時,在靠近虛線130(例如介電層131在導電墊119上方的部分與鈍化層121在導電墊119上方的部分之間)處的區域中介電層131與鈍化層121之間的界面處的機械應力遠高於裝置的其他區域。增加的應力可能導致高應力區域中的材料層分層,進而導致裝置故障且降低生產良率。此外,在形成用於形成導電凸塊125的種子層126(參見第8A圖)的後續製程中,拉出式開口對於沿拉出式開口的側壁和底部來形成共形且連續的種子層126可能更具挑戰性,因為拉出式開口具有更多的階梯形狀要被共形種子層126覆蓋。這被稱為凸塊種子層階梯覆蓋問題。凸塊種子層階梯覆蓋問題可能導致種子層126中的不連續性(例如孔洞),進而可能導致上方形成的導電凸塊125中的缺陷。本揭露透過形成用於形成導電凸塊125的拉入式開口,避免或減少了上述問題,進而提高了裝置可靠性和生產良率。應注意的是,除了拉入式開口之外,對齊式開口(參照例如第10圖中的對齊式開口136及相關說明)提供與拉入式開口相同或相似的優點。在一些實施例中,用於形成導電凸塊125的開口(例如132、136)為拉入式開口及/或對齊式開口,且未形成用於形成導電凸塊125的拉出式開口。
接下來,在第8A圖中,導電凸塊125形成在導電墊119上,且焊料區129形成在導電凸塊125上。導電凸塊125的寬度可介於約5μm和約90μm之間。導電凸塊125可以是微凸塊或可控塌陷晶片連接凸塊。舉例而言,具有介於例如約5μm和約30μm之間的寬度(例如在相對的側壁之間測量)的微凸塊可以形成在導電墊119B上方,且具有介於約20μm和約90μm之間的寬度的可控塌陷晶片連接凸塊可以形成在導電墊119A上方。在範例實施例中,微凸塊和可控塌陷晶片連接凸塊中的每一者形成在拉入式開口132(參見第7圖)中,開口132形成在相應的導電墊119上方。
可透過在介電層131上方且沿著開口132的側壁和底部形成種子層126;在種子層126上形成圖案化光阻層,其中圖案化光阻層的開口形成於要形成導電凸塊125的位置;在開口中的種子層126上方形成(例如電鍍)導電材料(例如銅);移除圖案化光阻層;且移除種子層126上未形成導電凸塊125的部分來形成導電凸塊125。應注意的是,導電材料的部分填充開口132以形成凸塊通孔125V,凸塊通孔125V將導電凸塊125電耦合到下方的導電墊119。應注意的是,在本揭露的說明中,開口132中的種子層126 (參照第7圖)被認為是凸塊通孔125V的一部分,且在介電層131的上表面上方的種子層126被認為是導電凸塊125的一部分。第8A圖繪示種子層126和導電凸塊125的導電材料(例如銅)之間的界面,以作為範例。在一些實施例中,種子層126和導電凸塊125的導電材料由相同的材料形成,因此種子層126和導電凸塊125的導電材料之間可不具有界面。
在第8A圖中,每個導電凸塊125下方(例如正下方)的凸塊通孔125V的數量為一個。當然,這僅僅是一個非限制性範例。各個導電凸塊125下方的凸塊通孔125V的數量可以是任何適合的數量,例如一個、兩個、三個或更多。此外,每個導電凸塊125下方的一或多個凸塊通孔125V可位於導電凸塊125的中心處,或者可偏離導電凸塊125的中心。
在第8A圖中,凸塊通孔125V的側壁接觸(例如物理接觸)介電層131的側壁且沿著介電層131的側壁延伸。凸塊通孔125V的寬度可以是固定的(例如具有垂直於基底101的主上表面的側壁)或可以隨著凸塊通孔125V向基底101延伸而連續地變化(例如逐漸地而非階梯式變化,或沒有不連續的變化)。在第8A圖的範例中,凸塊通孔125V的側壁具有線性輪廓(例如傾斜的直線),且凸塊通孔125V的寬度隨著凸塊通孔125V向基底101延伸而連續地縮小。凸塊通孔125V的側壁可以具有彎曲輪廓(例如曲線),例如當介電層131的側壁131S被開口132(見第7圖)暴露時其具有彎曲輪廓。應注意的是,凸塊通孔125V的側壁與鈍化層121的相應側壁之間存在間隙,介電層131填充此間隙且接觸導電墊119A的上表面。換言之,凸塊通孔125V透過介電層131橫向設置在凸塊通孔125V和鈍化層121之間的一部分來與鈍化層121分隔開(例如分離)。
在第8A圖的範例中,設置在導電墊119上的鈍化層121上方的介電層131的一部分的厚度A介於約1μm和約20μm之間。相鄰的較小導電墊119B(例如上方形成有微凸塊)之間的間距S大於約1.5μm,且相鄰的較大導電墊119A(例如上方形成有可控塌陷晶片連接凸塊)之間的間距S大於約4μm。第8A圖亦繪示鈍化層121的側壁部分(例如沿第16A圖中的導電墊119的側壁或沿導電線118的側壁的部分)的厚度T,以及鈍化層121的上部(例如沿著導電墊119的上表面或沿著導電線118的上表面的部分)的厚度G,其中厚度G介於約0.5μm和約5μm之間,且T和G之間的比率(例如T/G,稱為鈍化層121的階梯覆蓋率)介於約20%和約95%之間。在一些實施例中,相鄰導電凸塊125之間的間距P介於約5μm和約140μm之間。
第8B圖繪示包括導電凸塊125的第8A圖的半導體裝置100的一部分的放大圖。導電凸塊125及其周圍結構的尺寸將在下方說明。
如第8B圖所示,導電凸塊125(例如可控塌陷晶片連接凸塊或微凸塊)的寬度W介於約5μm和約100μm之間。介電層131中的開口132頂部的寬度B對於微凸塊而言介於約5μm和約25μm之間,對於可控塌陷晶片連接凸塊而言介於約5μm和約78μm之間。應注意的是,第8B圖中的寬度W是沿著第8B圖的水平方向測量的,開口132具有沿著垂直於第8B圖的截面的方向測量的另一寬度W2(例如從紙中出來且沿著第16B圖中導電線118的縱軸方向),其中寬度W2對於微凸塊而言介於約5μm和約36μm之間,對於可控塌陷晶片連接凸塊而言介於約20μm和約40μm之間。介電層131中的開口132底部的寬度E對於微凸塊而言介於約5μm和約22μm之間,對於可控塌陷晶片連接凸塊而言介於約5μm和約78μm之間。凸塊通孔125V的高度D大於介電層131的厚度A(參見第8A圖),且大於鈍化層121的厚度G(參見第8A圖)。
仍請參照第8B圖,如果導電墊是較大的導電墊119A(例如上方形成有可控塌陷晶片連接凸塊),則導電墊119的寬度L介於約5μm和約45μm之間,或者如果導電墊是較小的導電墊119B(例如上方形成微凸塊),則寬度L介於約1.5μm和約10μm之間。導電墊119的寬度L與間距S(見第8A圖)之間的比例等於或大於一。導電墊119(或第16A圖中的導電線118)的高度J介於約2μm和約6μm之間。第8B圖進一步繪示介電層131的側壁與導電墊119的上表面之間的夾角F',以及鈍化層121的側壁與導電墊119的上表面之間的夾角F,其中夾角F可介於10度和90度之間(例如10º<F<90º),且夾角F'可介於10度和90度之間(例如10º< F'<90º)。如果形成導電凸塊125的開口(例如第10圖中的136)是對齊式開口,則對應的夾角F和夾角F'相等。否則,夾角F可能與夾角F'不同。
第8C圖繪示第8B圖的半導體裝置100的平面圖,且第8B圖對應於沿第8C圖的截面A-A的剖視圖。應注意的是,為簡單起見,第8C圖中並未繪示所有特徵。作為非限制性範例,第8C圖中的導電墊119被繪示為具有八邊形形狀。其他形狀例如圓形、橢圓形、矩形、其他多邊形等也是可能的,且完全意圖包含在本揭露的範圍內。導電凸塊125被繪示為具有與第8C圖的範例中的導電墊119相似的幾何形狀。在其他實施例中,導電凸塊125和導電墊119具有不同的形狀(例如非幾何相似的形狀)。第8C圖進一步繪示連接到導電墊119的導電線120。導電線120沿著介電層131的上表面延伸,且與導電墊119形成重分佈層的一部分。
第9圖至第11圖繪示根據另一些實施例之在製造的各個階段的半導體裝置100B的剖視圖。半導體裝置100B類似於第8A圖的半導體裝置100,但具有對齊式開口136(參見第10圖),用於暴露導電墊119A且用於形成導電凸塊125。第9圖的製程在第1A圖、第1B圖和第2圖至第5圖的製程之後。換言之,第1A圖、第1B圖、第2圖至第5圖和第9圖至第11圖繪示形成半導體裝置100B的製程步驟。
在第9圖中,在形成鈍化層121之後,在鈍化層121上方形成介電層131,且在介電層131中形成開口132以暴露出鈍化層121。介電層131和開口132的形成可使用與上方參照第7圖說明的相同或相似的製程,因此不再重複細節。應注意的是,直到此製程階段,在導電墊119上方的鈍化層121中並未形成開口。因此,導電墊119的上表面被鈍化層121覆蓋。
接下來,在第10圖中,在介電層131上方形成圖案化光阻層133。圖案化光阻層133的開口136位於介電層131的相應開口132(參見第9圖)上方。在一些實施例中,在介電層131的上表面所測得的開口136的寬度與在介電層131的上表面所測得的開口132的寬度相同。在其他實施例中,在介電層131的上表面所測得的開口136的寬度大於在介電層131的上表面所測得的開口132的寬度。接下來,將圖案化的光阻層133作為蝕刻遮罩以進行後續的蝕刻製程,其後續蝕刻製程可與第6圖中的蝕刻製程相同或相似,以暴露導電墊119A。如第10圖所示,在蝕刻製程之後,開口136向下延伸穿過鈍化層121,且暴露出導電墊119A。
仍請參照第10圖,開口136形成為對齊式開口。對於每個對齊的開口136而言,開口136暴露的介電層131的側壁131S和開口136暴露的鈍化層121的相應側壁121S沿著同一線(例如垂直於基底101的主上表面、相對於基底101的主上表面傾斜的線或曲線)。換言之,開口136的相對側壁之間的距離沿著開口136的深度方向連續地變化(例如逐漸地而非階梯變化)。在形成對齊式開口136之後,例如透過灰化製程移除光阻層133。
接下來,在第11圖中,在與第8A圖相同或相似的製程之後,在導電墊119上方形成導電凸塊125,以下將不再重複細節。在第11圖的範例中,凸塊通孔125V的上側壁(例如側壁的上部)接觸且沿著介電層131的側壁131S延伸,凸塊通孔125V的下側壁(例如側壁的下部)接觸且沿鈍化層121的側壁121S延伸。在一些實施例中,凸塊通孔125V具有固定的(例如具有筆直的側壁)或隨著凸塊通孔125V向基底101延伸而連續地變化(例如逐漸地而非階梯變化)的寬度(例如在凸塊通孔125V的相對側壁之間測量)。
第12圖至第15圖、第16A圖和第16B圖繪示根據又一些實施例之在製造的各個階段的半導體裝置100C的剖視圖。半導體裝置100C類似於第11圖的半導體裝置100B,但是導電凸塊125形成在導電線118上而非導電墊119上。第12圖的製程在第1A圖、第1B圖和第2圖的製程之後。換言之,第1A圖、第1B圖、第2圖、第12圖至第15圖、第16A圖和第16B圖繪示形成半導體裝置100C的製程步驟。應注意的是,雖然半導體裝置100、100B和100C被描述為不同的實施例,但是半導體裝置100、100B和100C(例如100和100C,或100B和100C)的任意組合可以形成在同一基底101上,例如形成在同一基底101的不同區域中。
在第12圖中,在鈍化層111上形成多條導電線118,使用與第3圖中所示類似的製程。在一些實施例中,為了形成導電線118,圖案化的光阻層137(例如參見第3圖)形成於阻擋層115上方,其中圖案化光阻層137的圖案(例如開口)的位置對應於後續形成的導電線118的位置。接下來,進行除渣製程110。接著,在阻擋層115上方的圖案化光阻層137的圖案中形成導電材料(例如銅)。接下來,移除圖案化光阻層137,且進行蝕刻製程以移除阻擋層115上未形成導電材料的部分。
接下來,在第13圖中,鈍化層121共形地形成在導電線118上方和鈍化層111上方。鈍化層121的形成與上方參照第5圖所述的製程相同或相似,故不再贅述。
接下來,在第14圖中,在鈍化層121上方形成介電層131,且在介電層131中形成開口132,以暴露設置在導電線118的上表面上方的鈍化層121。介電層131和開口132的形成與以上參照第7圖所述的製程相同或相似,因此將不再贅述。應注意的是,直到此製程階段,在鈍化層121中並未形成開口以暴露導電線118。
接下來,在第15圖中,在介電層131上方形成光阻層133,且在開口132(參見第14圖)上方的光阻層133中形成開口136。接著,以圖案化光阻層133作為蝕刻遮罩進行蝕刻製程(例如非等向性蝕刻製程),以使開口136向下延伸,使得開口136延伸穿過保護層121以暴露出導電線118。此蝕刻製程可以與以上參照第6圖6所述的蝕刻製程相同或相似,因此不再贅述。應注意的是,由於例如使用非等向性蝕刻製程來形成開口136,開口136是對齊式開口。
接下來,在第16A圖中,在與第8A圖相同或相似的製程之後,在導電線118上方形成導電凸塊125,以下將不再重複細節。在第16A圖的範例中,兩個凸塊通孔125V形成在導電凸塊125下方,且將導電凸塊125電耦合到兩條下方的導電線118。換言之,每個凸塊通孔125V延伸到介電層131中,穿過鈍化層121,且接觸(例如物理接觸)下方的導電線118,進而將導電凸塊125與下方的導電線118電耦合。在第16A圖中所示每個導電凸塊125下方的凸塊通孔125V的數量和電耦合到的上方導電凸塊125的導電線118的數量僅是一個非限制性範例,可在每個導電凸塊125下方形成任何適合數量的凸塊通孔125V和導電線118。
如第16A圖所示,凸塊通孔125V的上側壁 (例如側壁的上部)接觸且沿介電層131的側壁131S延伸,凸塊通孔125V的下側壁(例如側壁的下部)接觸且沿鈍化層121的側壁121S延伸。在一些實施例中,凸塊通孔125V具有固定(例如具有筆直的側壁)或隨著凸塊通孔125V向基底101延伸而連續變化(例如逐漸地而非階梯變化)的寬度(例如在凸塊通孔125V的相對側壁之間測量)。
第16B圖繪示第16A圖的半導體裝置100C的一部分的平面圖,且第16A圖對應於沿第16B圖的截面B-B的剖視圖。應注意的是,為簡單起見,第16B圖中並未繪示所有特徵。作為非限制性範例,第16B圖中的導電凸塊128被繪示為八邊形的形狀。其他形狀例如圓形、橢圓形、矩形、其他多邊形等也是可能的,且完全意圖包含在本揭露的範圍內。
對所揭露的實施例的變化或修改是可能的,且完全意圖被包括在本揭露的範圍內。舉例而言,雖然不同的實施例100、100B和100C被說明為不同的半導體裝置,但是在實施例100、100B和100C中所揭露的導電凸塊125的不同結構/形狀可以形成在同一半導體裝置的不同區域中。換言之,半導體裝置可以在相同半導體裝置的不同區域中形成有第9A圖、第11圖和第16A圖中所揭露的不同導電凸塊結構。
本揭露的實施例實現了一些有利特徵。舉例而言,透過形成拉入式開口(參見例如第7圖中的132)或對齊式開口(參見例如第10圖中的136),介電層131和鈍化層121之間的附著性得到改善,且裝置中靠近介電層131和鈍化層121之間的界面(例如在介電層131的面向開口的下角落處)的機械應力降低。改善的附著性和降低的應力有助於減少或避免介電層131和鈍化層121之間的界面處的分層,進而提高裝置性能、裝置可靠性和生產良率。作為另一範例,介電層131的形成消除了與形成導電凸塊125相關的部份段,且提高了裝置可靠性和製造良率。回想為了形成導電凸塊125,首先要形成種子層126,隨後在種子層126上方形成(例如電鍍)導電材料。在不具有介電層131的情況下,就必須在導電墊119及/或導電線118上共形地形成種子層126。在先進的半導體製造中,導電墊119之間或導電線118之間的小間隙可能具有高縱深比,且可能難以在這些小間隙中形成種子層126,這可能導致無法適當地形成導電凸塊125。此外,在形成導電凸塊125之後,需要移除種子層126上未形成導電凸塊125的部分。如果種子層126的這些部分在小間隙中,則可能難以移除種子層126,這可能導致導電凸塊125之間的電短路。反之,在形成介電層131的情況下,種子層126形成於介電層131上方及開口132或136中,其中開口132/136具有更小的縱深比,因此,種子層126可容易地形成於開口中且容易地從開口中移除,進而避免上述的問題。
第17圖繪示根據一些實施例之製造半導體結構的方法1000的流程圖。應理解的是,第17圖所示的實施例方法僅僅是許多可能的實施例方法的範例。本揭露所屬技術領域中具有通常知識者將可認知到許多變化、替代和修改。舉例而言,可以添加、移除、替換、重新排列或重複如第17圖所示的各種步驟。
參照第17圖,在區塊1010,在基底上方形成內連線結構。在區塊1020,在內連線結構上方形成第一鈍化層。在區塊1030,第一導電特徵形成在第一鈍化層上方且電耦合到內連線結構。在區塊1040,在第一導電特徵和第一鈍化層上方共形地形成第二鈍化層。在區塊1050,在第二鈍化層上方形成介電層。在區塊1060,在第一導電特徵上方形成第一凸塊通孔和第一導電凸塊,且第一凸塊通孔和第一導電凸塊電耦合到第一導電特徵,其中第一凸塊通孔位在第一導電凸塊和第一導電特徵之間,第一凸塊通孔穿過第二鈍化層,接觸第一導電特徵,且延伸到介電層中。第一導電凸塊位於介電層上方且電耦合到第一凸塊通孔。
根據本揭露的實施例,一種形成半導體裝置的方法包括:在基底上方形成內連線結構;在內連線結構上方形成第一鈍化層;在第一鈍化層上方形成第一導電特徵且電耦合到內連線結構;在第一導電特徵和第一鈍化層上方共形地形成第二鈍化層;在第二鈍化層上方形成介電層;以及在第一導電特徵上方形成第一凸塊通孔和第一導電凸塊並電耦合到第一導電特徵,其中第一凸塊通孔位於第一導電凸塊和第一導電特徵之間,其中第一凸塊通孔延伸到介電層中,穿過第二鈍化層,且接觸第一導電特徵,其中第一導電凸塊位在介電層上方且電耦合到第一凸塊通孔。
在一些實施例中,介電層圍繞第一導電特徵,且介電層的遠離基底的上表面比第一導電特徵從基底延伸得更遠。
在一些實施例中,形成第一凸塊通孔和第一導電凸塊包括:在形成第二鈍化層之後且在形成介電層之前,在第二鈍化層中形成第一開口以暴露第一導電特徵的上表面;在形成介電層之後,在介電層中形成第二開口,以暴露出第一導電特徵的上表面,其中在形成第二開口之後,第二鈍化層面向第二開口的側壁被介電層覆蓋;以及形成填充第二開口且在介電層遠離基底的上表面上方延伸的導電材料。
在一些實施例中,第二開口中的導電材料的第一部分形成第一凸塊通孔,且介電層的上表面上方的導電材料的第二部分形成第一導電凸塊。
在一些實施例中,在第二開口的相對側壁之間所測得的第二開口的第二寬度小於在第一開口的相對側壁之間所測得的第一開口的第一寬度。
在一些實施例中,第二開口的第二寬度沿著第二開口的深度方向連續地變化。
在一些實施例中,形成第一凸塊通孔和第一導電凸塊包括: 在形成介電層之後,在介電層中形成延伸至介電層中的第一開口,以暴露出第二鈍化層遠離基底的上表面,其中暴露於第一開口底部的第二鈍化層沿著第一導電特徵的上表面延伸且覆蓋第一導電特徵的上表面; 在形成第一開口之後,在介電層上方形成圖案化遮罩層,其中圖案化遮罩層中的第二開口位於第一開口上方;以及使用圖案化遮罩層作為蝕刻遮罩來進行非等向性蝕刻製程,其中非等向性蝕刻製程將第二開口延伸穿過第二鈍化層以暴露第一導電特徵的上表面。
在一些實施例中,在非等向性蝕刻製程之後,介電層面向第二開口的側壁沿著與第二鈍化層面向第二開口的相應側壁對齊於同一線。
在一些實施例中,此方法更包括在非等向性蝕刻製程之後,在第一導電特徵的上表面上方形成導電材料,其中介電層中的導電材料的第一部分形成第一凸塊通孔,且在介電層的上表面上方的導電材料的第二部分形成第一導電凸塊。
在一些實施例中,第一導電特徵是第一導電線。
在一些實施例中,此方法更包括:在鄰近第一導電線的第一鈍化層上方形成第二導電線,其中第二鈍化層共形地形成在第二導電線上方;以及在第一導電凸塊和第二導電線之間形成第二凸塊通孔,其中第二凸塊通孔延伸到介電層中,穿過第二鈍化層且接觸第二導電線,其中第一導電凸塊電耦合到第一凸塊通孔和第二凸塊通孔。
在一些實施例中,此方法更包括在第一鈍化層中形成金屬-絕緣體-金屬(MIM)電容器,其中第一導電特徵形成為電耦合到金屬-絕緣體-金屬電容器。
根據本揭露的實施例,一種形成半導體裝置的方法包括:在內連線結構上方形成第一鈍化層,其中內連線結構位在形成於基底中的電子元件上方且電耦合到形成在基底中的電子元件;在第一鈍化層上方形成導電特徵,其中導電特徵電耦合到內連線結構;在導電特徵和第一鈍化層上方形成第二鈍化層,其中第二鈍化層是共形的且沿著導電特徵的外表面延伸;在第二鈍化層上方形成介電層,其中介電層遠離基底的上表面比導電特徵遠離基底的上表面從基底延伸得更遠;形成從介電層的上表面延伸至導電特徵的上表面的凸塊通孔,其中凸塊通孔的寬度隨著凸塊通孔向導電特徵的延伸而連續變化;以及在凸塊通孔上形成導電凸塊。
在一些實施例中,凸塊通孔的上側壁接觸且沿介電層面向凸塊通孔的第一側壁延伸,凸塊通孔的下側壁接觸且沿第二鈍化層面向凸塊通孔的第二側壁延伸。
在一些實施例中,介電層的第一側壁與第二鈍化層的第二側壁沿同一線對齊。
在一些實施例中,凸塊通孔與第二鈍化層被橫向設置在凸塊通孔和第二鈍化層之間的介電層的一部分隔開。
在一些實施例中,此方法更包括在第一鈍化層中形成金屬-絕緣體-金屬(MIM)電容器,其中導電特徵形成為電耦合到金屬-絕緣體-金屬電容器。
根據本揭露的實施例,一種半導體裝置包括:基底,包括裝置區域;內連線結構,位在基底上方且電耦合到裝置區域;第一鈍化層,位於內連線結構上方;導電特徵,位於第一鈍化層上方且電耦合到內連線結構;第二鈍化層,位在導電特徵和第一鈍化層上方,其中第二鈍化層是共形的且沿著導電特徵的外表面延伸;介電層,位在第二鈍化層上方,其中介電層比導電特徵從基底延伸得更遠;凸塊通孔,位於介電層中,其中凸塊通孔從介電層遠離基底的上表面延伸至導電特徵,其中凸塊通孔的寬度隨著凸塊通孔向導電特徵延伸而連續地變化;以及導電凸塊,位於凸塊通孔上。
在一些實施例中,凸塊通孔的上側壁接觸並沿介電層面向凸塊通孔的第一側壁延伸,凸塊通孔的下側壁接觸並沿第二鈍化層面向凸塊通孔的第二側壁延伸,其中第一側壁與第二側壁沿同一線對齊。
在一些實施例中,介電層的一部分橫向地設置在第二鈍化層和凸塊通孔之間,使得凸塊通孔與第二鈍化層分隔開。
以上概述了許多實施例的特徵,使本揭露所屬技術領域中具有通常知識者可以更加理解本揭露的各實施例。本揭露所屬技術領域中具有通常知識者應可理解,可以本揭露實施例為基礎輕易地設計或改變其他製程及結構,以實現與在此介紹的實施例相同的目的及/或達到與在此介紹的實施例相同的優點。本揭露所屬技術領域中具有通常知識者也應了解,這些相等的結構並未背離本揭露的精神與範圍。在不背離後附申請專利範圍的精神與範圍之前提下,可對本揭露實施例進行各種改變、置換及變動。
100,100B,100C:半導體裝置
101:半導體基底(基底)
102:區域
103:電子元件
105:導電線
106:內連線結構
107:通孔
108:下層通孔
109:介電層
110:除渣製程
111:鈍化層
111A,111B,111C,111D,111E:子層
112:開口
113:金屬-絕緣體-金屬電容器
113M:金屬層
113I:絕緣層
115:阻擋層
118:導電線
119,119A,119B:導電墊
119V,119V1,119V2:通孔(上層通孔)
120:導電線
121:鈍化層
121U:上表面
121S:側壁
125:導電凸塊
125V:凸塊通孔
126:種子層
129:焊料區
130:虛線
131:介電層
131S:側壁
132:開口(拉入式開口)
136:開口(對齊式開口)
137:圖案化光阻層(光阻層)
138:開口
1000:方法
1010,1020,1030,1040,1050,1060:區塊
A:厚度
B:寬度
D:高度
E:寬度
F,F’:夾角
G:厚度
L:寬度
J:高度
S:間距
T:厚度
W:寬度
A-A,B-B:截面
根據以下的詳細說明並配合所附圖式以更好地了解本揭露實施例的概念。應注意的是,根據本產業的標準慣例,圖式中的各種特徵未必按照比例繪製。事實上,可能任意地放大或縮小各種特徵的尺寸,以做清楚的說明。在通篇說明書及圖式中以相似的標號標示相似的特徵。
第1A圖、第1B圖、第2圖至第7圖和第8A圖至第8C圖繪示根據一些實施例之在製造的各個階段的半導體裝置的剖視圖。
第9圖至第11圖繪示根據另一些實施例之在製造的各個階段的半導體裝置的剖視圖。
第12圖至第15圖、第16A圖和第16B圖繪示根據又一些實施例之在製造的各個階段的半導體裝置的剖視圖。
第17圖繪示根據一些實施例之形成半導體裝置的方法的流程圖。
1000:方法
1010,1020,1030,1040,1050,1060:區塊
Claims (20)
- 一種半導體裝置的製造方法,包括: 在一基底上方形成一內連線結構; 在該內連線結構上方形成一第一鈍化層; 在該第一鈍化層上方形成一第一導電特徵,且該第一導電特徵電耦合到該內連線結構; 在該第一導電特徵和該第一鈍化層上方共形地形成一第二鈍化層; 在該第二鈍化層上方形成一介電層;以及 在該第一導電特徵上方形成一第一凸塊通孔和第一導電凸塊,且該第一凸塊通孔和該第一導電凸塊電耦合到該第一導電特徵,其中該第一凸塊通孔位於該第一導電凸塊和該第一導電特徵之間,該第一凸塊通孔延伸到該介電層中,通過該第二鈍化層,且接觸該第一導電特徵,其中該第一導電凸塊位於該介電層上方且電耦合到該第一凸塊通孔。
- 如請求項1之半導體裝置的製造方法,其中該介電層圍繞該第一導電特徵,且該介電層遠離該基底的一上表面比該第一導電特徵從該基底延伸得更遠。
- 如請求項1之半導體裝置的製造方法,其中形成該第一凸塊通孔和該第一導電凸塊包括: 在形成該第二鈍化層之後且在形成該介電層之前,在該第二鈍化層中形成一第一開口以暴露該第一導電特徵的一上表面; 在形成該介電層之後,在該介電層中形成一第二開口,以暴露出該第一導電特徵的該上表面,其中在形成該第二開口後,該第二鈍化層面向該第二開口的複數個側壁被該介電層覆蓋;及 形成填充該第二開口且在該介電層遠離該基底的一上表面上方延伸的一導電材料。
- 如請求項3之半導體裝置的製造方法,其中在該第二開口中的該導電材料的一第一部分形成該第一凸塊通孔,且該介電層的該上表面上方的該導電材料的一第二部分形成該第一導電凸塊。
- 如請求項3之半導體裝置的製造方法,其中在該第二開口的相對側壁之間所測得的該第二開口的一第二寬度小於在該第一開口的相對側壁之間所測得的該第一開口的一第一寬度。
- 如請求項5之半導體裝置的製造方法,其中該第二開口的該第二寬度沿著該第二開口的一深度方向連續地變化。
- 如請求項1之半導體裝置的製造方法,其中形成該第一凸塊通孔和該第一導電凸塊包括: 在形成該介電層之後,在該介電層中形成延伸至該介電層中的一第一開口,以暴露出該第二鈍化層遠離該基底的一上表面,其中暴露於該第一開口的一底部的該第二鈍化層沿著該第一導電特徵的一上表面延伸且覆蓋該上表面; 在形成該第一開口之後,在該介電層上方形成一圖案化遮罩層,其中該圖案化遮罩層中的一第二開口位於該第一開口上方;以及 使用該圖案化遮罩層作為一蝕刻遮罩來進行一非等向性蝕刻製程,其中該非等向性蝕刻製程將該第二開口延伸穿過該第二鈍化層以暴露該第一導電特徵的該上表面。
- 如請求項7之半導體裝置的製造方法,其中在該非等向性蝕刻製程之後,該介電層面向該第二開口的一側壁與該第二鈍化層面向該第二開口的一相應側壁對齊於同一線上。
- 如請求項7之半導體裝置的製造方法,更包括在該非等向性蝕刻製程之後,在該第一導電特徵的該上表面上方形成一導電材料,其中該介電層中的該導電材料的一第一部分形成該第一凸塊通孔,以及在該介電層的一上表面上方的該導電材料的一第二部分形成該第一導電凸塊。
- 如請求項7之半導體裝置的製造方法,其中該第一導電特徵是一第一導電線。
- 如請求項10之半導體裝置的製造方法,更包括: 在鄰近該第一導電線的該第一鈍化層上方形成一第二導電線,其中該第二鈍化層共形地形成在該第二導電線上方;以及 在該第一導電凸塊和該第二導電線之間形成一第二凸塊通孔,其中該第二凸塊通孔穿過該第二鈍化層延伸到該介電層中,且接觸該第二導電線,其中該第一導電凸塊電耦合到該第一凸塊通孔和該第二凸塊通孔。
- 如請求項1之半導體裝置的製造方法,更包括在該第一鈍化層中形成一金屬-絕緣體-金屬(MIM)電容器,其中該第一導電特徵形成為電耦合到該金屬-絕緣體-金屬電容器。
- 一種半導體裝置的製造方法,包括: 在一內連線結構上方形成一第一鈍化層,其中該內連線結構是位於形成在一基底中的複數個電子元件上方且電耦合到該等電子元件; 在該第一鈍化層上方形成一導電特徵,其中該導電特徵電耦合到該內連線結構; 在該導電特徵和該第一鈍化層上方形成一第二鈍化層,其中該第二鈍化層是共形的且沿著該導電特徵的複數個外表面延伸; 在該第二鈍化層上方形成一介電層,其中該介電層遠離該基底的一上表面比遠離該基底的該導電特徵的一上表面從該基底延伸得更遠; 形成一凸塊通孔,從該介電層的該上表面延伸至該導電特徵的該上表面,其中該凸塊通孔的一寬度隨著該凸塊通孔向該導電特徵延伸而連續地變化;以及 在該凸塊通孔上形成一導電凸塊。
- 如請求項13之半導體裝置的製造方法,其中該凸塊通孔的一上側壁接觸且沿該介電層面向該凸塊通孔的一第一側壁延伸,且該凸塊通孔的一下側壁接觸且沿該第二鈍化層面向該凸塊通孔的一第二側壁延伸。
- 如請求項14之半導體裝置的製造方法,其中該介電層的該第一側壁與該第二鈍化層的該第二側壁沿同一線對齊。
- 如請求項13之半導體裝置的製造方法,其中該凸塊通孔與該第二鈍化層被橫向設置在該凸塊通孔和該第二鈍化層之間的該介電層的一部分分隔開。
- 如請求項13之半導體裝置的製造方法,更包括在該第一鈍化層中形成一金屬-絕緣體-金屬(MIM)電容器,其中該導電特徵形成為電耦合到該金屬-絕緣體-金屬電容器。
- 一種半導體裝置,包括: 一基底,包括一裝置區域; 一內連線結構,位於該基底上方且電耦合到該裝置區域; 一第一鈍化層,位於該內連線結構上方; 一導電特徵,位於該第一鈍化層上方且電耦合到該內連線結構; 一第二鈍化層,位於該導電特徵和該第一鈍化層上方,其中該第二鈍化層是共形的且沿著該導電特徵的複數個外表面延伸; 一介電層,位於該第二鈍化層上方,其中該介電層比該導電特徵從該基底延伸得更遠; 一凸塊通孔,位於該介電層中,其中該凸塊通孔從遠離該基底的該介電層的一上表面延伸至該導電特徵,其中該凸塊通孔的一寬度隨著該凸塊通孔向該導電特徵延伸而連續地變化;以及 一導電凸塊,位於該凸塊通孔上。
- 如請求項18之半導體裝置,其中該凸塊通孔的一上側壁接觸且沿該介電層面向該凸塊通孔的一第一側壁延伸,且該凸塊通孔的一下側壁接觸且沿該第二鈍化層面向該凸塊通孔的一第二側壁延伸,其中該第一側壁與該第二側壁沿同一線對齊。
- 如請求項18之半導體裝置,其中該介電層的一部分橫向地設置在該第二鈍化層和該凸塊通孔之間,使得該凸塊通孔與該第二鈍化層分隔開。
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