TW202236144A - 半導體、電路結構及其相關方法 - Google Patents

半導體、電路結構及其相關方法 Download PDF

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TW202236144A
TW202236144A TW110132506A TW110132506A TW202236144A TW 202236144 A TW202236144 A TW 202236144A TW 110132506 A TW110132506 A TW 110132506A TW 110132506 A TW110132506 A TW 110132506A TW 202236144 A TW202236144 A TW 202236144A
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Taiwan
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die
transistor
circuit
gate
inter
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TW110132506A
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English (en)
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胡長芬
李紹宇
陳國基
林智鵬
王垂堂
陳卿芳
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台灣積體電路製造股份有限公司
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Publication of TW202236144A publication Critical patent/TW202236144A/zh

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Abstract

提供一種電路結構。該電路結構可包含：一第一晶粒區域，其包含一輸出閘；一第二晶粒區域，其包含一電路及一輸入閘；及一晶粒間互連件。該輸入閘可包含一電晶體。該電路可連接在該晶粒間互連件與該電晶體之一閘極區之間。該電路可包含一PMOS電晶體及一NMOS電晶體。該PMOS電晶體之一第一源極/汲極區可連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。

Description

半導體、電路結構及其相關方法
本發明實施例係有關半導體、電路結構及其相關方法。
隨著科技進步，可在一積體電路(IC)中製造之電路元件之最小大小不斷減小。因此，對於增加相同或更小大小之一IC中之電路元件之數目之需求不斷增加。
先前技術章節中論述之標的不應僅由於其在先前技術章節中提及而被假定為先前技術。類似地，先前技術章節中提及或與先前技術章節之標的相關聯之一問題不應被假定為先前已在先前技術中辨識。先前技術章節中之標的僅表示不同方法。
本發明的一實施例係關於一種電路結構，其包括：一第一晶粒區域，其包括一輸出邏輯閘；一第二晶粒區域，其包括一電路及一輸入邏輯閘；及一晶粒間互連件；其中該輸入邏輯閘包括一電晶體，其中該電路連接在該晶粒間互連件與該電晶體之一閘極區之間；其中該電路包括一PMOS電晶體及一NMOS電晶體，其中該PMOS電晶體之一第一源極/汲極區連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。
本發明的一實施例係關於一種方法，其包括：提供一第一晶粒，其包括一輸出邏輯閘；提供一第二晶粒，其包括包括一通過電路及一輸入邏輯閘的一複合電路，其中該輸入邏輯閘包括一電晶體，其中該通過電路包括一PMOS電晶體及一NMOS電晶體且連接至該電晶體之一閘極區；及至少部分經由一晶粒間互連件連接該第一晶粒及該第二晶粒，使得該第一晶粒之該輸出邏輯閘連接至該第二晶粒之該複合電路之該通過電路，其中該PMOS電晶體之一第一源極/汲極區連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。
本發明的一實施例係關於一種半導體結構，其包括：一第一晶粒；一第二晶粒，其包括一第一電晶體；一晶粒間互連件，其電耦合該第一晶粒及該第二晶粒；及一半導電路徑，其介於該晶粒間互連件與該第一電晶體之一閘極區之間，其中一有效p-n接面電連接在該半導電路徑與一參考電壓之間，其中該半導電路徑經組態以回應於存在大於一臨限電壓之一控制電壓而導電，且經組態以回應於不存在大於該臨限電壓之該控制電壓而不導電。
以下揭露提供用於實施所提供之標的之不同構件之許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露。當然，此等僅為實例且非意欲限制。另外，本揭露可在各個實例中重複元件符號及/或字母。此重複出於簡化及清楚之目的且本身不指示所論述之各項實施例及/或組態之間之一關係。
此外，為便於描述，諸如「在…下面」、「在…下方」、「下」、「在…上方」、「上」及類似者之空間相對術語可在本文中用於描述一個元件或構件與另一(些)元件或構件之關係，如圖中繪示。空間相對術語意欲涵蓋除在圖中描繪之定向以外之使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或按其他定向)且因此可同樣解釋本文中所使用之空間相對描述符。
在本揭露中，除非另外描述，否則片語「A、B及C之一者」意謂「A、B及/或C」 (A、B、C、A及B、A及C、B及C、或A、B及C)，且不意謂來自A之一個元件、來自B之一個元件及來自C之一個元件。
在本揭露中，在一值之前之諸如「約」及「大約」之表述指示該值與描述完全相同或在如描述之值之一特定範圍內，同時考量設計誤差/裕度、製造誤差/裕度、量測誤差等。一般技術者應可辨識此一描述。
可關於在特定應用積體電路(ASIC)之設計中使用標準單元(standard cell)來論述實施例，但實施例不限於此。一標準單元表示將一低階VLSI (超大規模整合)佈局囊封為一抽象邏輯表示(例如，一NAND閘或其他邏輯閘)之設計抽象。基於標準單元之設計允許一個設計者專注於數位設計之邏輯或功能態樣，而另一設計者專注於設計之實施態樣，且對於促成每一事物從簡單單功能IC至複雜數百萬閘極系統單晶片(SoC)裝置之高效設計至關重要。
在本揭露中，圖式中未描繪一單元或一佈局之每一層。一般技術者應瞭解，單元或佈局可包含有更多層來實施單元之功能性且僅為方便描述省略此等層。
在現代科技中，在一半導體晶圓(或基板)上製成積體電路(IC)，其中矽係一常見材料。一半導體製造商在一晶圓上製作眾多IC。接著，可將晶圓切割成許多晶片或晶粒。接著，晶片或晶粒經封裝且測試，且接著遞送至客戶。一IC封裝可含有一單個晶片或多個晶片。
一單晶片封裝包含一個晶粒，該晶粒可附接、接合且囊封至一封裝本體中。針對一單晶片封裝設計之一晶粒可包含用於在晶粒與封裝外部之電路之間傳達信號的專用輸入/輸出(I/O)電路區塊。
針對一單晶片封裝設計之晶粒中之專用I/O電路區塊可具有數個功能，諸如驅動晶片外之大電容及保護晶粒使之免受非預期靜電放電之影響。專用I/O電路區塊之大小可取決於晶粒經設計以驅動之晶片外電容量及/或靜電放電保護量之規格。
一多晶片封裝(有時被稱為多晶片模組(MCM))包含組裝於相同封裝中之複數個晶粒。多晶片封裝之優點包含較高整合密度及較低封裝成本。其他優點包含可歸因於彼此通信之晶粒之一較接近定位及導致之較短晶粒間互連之經改良系統效能。
多晶片封裝之另一優點可為：由於至少一些晶粒不再必須驅動晶片外之大電容，故可減小此等晶粒之I/O電路之所需驅動強度，從而導致(例如)一較小輸出單元及/或一較低功率消耗。甚至可在一多晶片封裝中之一些晶粒中消除對於專用I/O電路區塊之需求；在此等晶粒中，一個晶粒中之標準邏輯單元可經由一晶粒間互連件將信號直接驅動至另一晶粒。例示性晶粒間互連件包含一貫穿矽通路(TSV)、一貫穿介電質通路(TDV)及一混合接合。
在設計一多晶片封裝中之晶片時通常考量之一個因素係所謂的「天線效應」，有時被稱為電漿誘發損壞(PID)或電漿誘發閘極氧化物損壞。
為理解天線效應，考量藉由一晶粒間互連件(諸如一TSV)彼此連接之兩個晶粒。晶粒間互連件連接在第一晶粒之一輸出邏輯閘之一電晶體與第二晶粒之一輸入邏輯閘之一電晶體之間。第一晶粒之輸出邏輯閘及第二晶粒之輸入邏輯閘可分別被稱為一「發射器」及一「接收器」，此係因為電信號可被視為從第一晶粒之輸出邏輯閘傳輸至第二晶粒之輸入邏輯閘。在一些情況中，第一晶粒可包含比一個別邏輯閘更複雜的一輸出電路且第二晶粒可包含比一個別邏輯閘更複雜的一輸入電路。在此等情況中，晶粒間互連件可連接在第一晶粒之輸出電路之一電晶體與第二晶粒之輸入電路之一電晶體之間。在此等情況中，第一晶粒之輸出電路及第二晶粒之輸入電路可分別被稱為「發射器」及「接收器」，而不失清晰，此係因為電信號可被視為在此等兩個電路之間進行傳輸。
電信號從第一晶粒之一邏輯閘傳輸至第二晶粒之另一邏輯閘並不少見。在將一信號饋送至一邏輯閘時，將該信號饋送至該邏輯閘之一輸入電晶體之閘極端子並不少見。因此，晶粒間互連件(其係導電的且可由金屬材料製成)直接連接至第二晶粒之輸入邏輯閘之一電晶體之閘極端子並不少見。
一些IC製程(諸如基於電漿之蝕刻)可引起電荷累積於已經受此等製程之區域中。因此，導電之晶粒間互連件可在製造期間累積電荷。
一電晶體之閘極端子通常包含一介電層，諸如二氧化矽。介電層可為薄的，且因此可在直接連接至一大電位之情況下擊穿。可累積大量電荷之晶粒間互連件直接連接至閘極介電質並不少見；因此，閘極介電質可能冒被此等電荷擊穿之風險。因此，保護直接連接至晶粒間互連件之閘極介電質使之免受此等電荷或PID之影響係有利的。
提供此PID保護之一種方式係將一天線二極體引入至晶粒間互連件與第二晶粒之輸入電晶體之閘極端子(「接收器」)之間之電路節點。
添加天線二極體(儘管可用於向閘極介電質提供PID保護)可能並非最佳，此係因為天線二極體可能佔用大量面積，此增加製造成本。面積增加亦可能對諸如時序及功率消耗之其他效能度量造成不利影響。此外，由於一晶粒中之各I/O接腳將需要其自身天線二極體，故隨著更多I/O接腳放置於晶粒中，次優性可能迅速加劇。
因此，向直接連接至晶粒間互連件之閘極介電質提供PID保護之一經改良方式將係有利的。
圖2A繪示一例示性半導體配置(或半導體結構) 2a，其包含一第一晶粒20、一第二晶粒21及將晶粒20之一發射器201連接至晶粒21之一接收器211的一晶粒間互連件22。發射器201可為一簡單邏輯閘或包含兩個或更多個邏輯閘之一輸出電路。發射器201可為一標準單元之一部分，且本身可為一標準單元。接收器211可為一簡單邏輯閘或包含兩個或更多個邏輯閘之一輸入電路。接收器211可為一標準單元之一部分，且本身可為一標準單元。
晶粒21中之接收器211包含一電晶體203；為了清楚起見，接收器211可能具有之其他電晶體被省略且在圖2A中被指示為垂直橢圓。
為保護電晶體230之閘極230g使之免受天線效應(電漿誘發損壞)，可在節點214與電晶體230g之間提供不包含一直接導電路徑之一區215。那樣，累積於晶粒間互連件22上之電荷(若產生)將不會湧向閘極230g，藉此保護閘極介電質使之免受PID影響。
區215可包含允許電信號傳遞至電晶體230之其他電路元件。舉例而言，區215可包含介於晶粒間互連件22與電晶體230之閘極230g之間之一半導電路徑。區215中之半導電路徑可提供一更受控路徑，其可允許電信號而非在晶粒間互連件22上產生之大量電漿誘發電荷通過。
在一些實施例中，區215中之半導電路徑可經組態以回應於存在大於一臨限電壓之一控制電壓而導電；且區215中之半導電路徑可經組態以回應於不存在大於臨限電壓之控制電壓而不導電。
在半導體配置2a之構成組件(諸如晶粒20、晶粒21、晶粒間互連件22及其任何部分)之製造期間，未有意施加電信號。因此，區215中之半導電路徑可在半導體配置2a之製造期間保持不導電。因此，當完成製作晶粒間互連件22與接收器211之間之電連接(諸如將導電互連件沉積於(例如)晶粒21之BEOL部分中)時，電漿誘發電荷(即使在晶粒間互連件22上產生)不會突然自由地釋放至閘極230g。在完成製造半導體配置2a之後且在半導體配置2a之操作期間，可將電信號(諸如先前段落中提及之控制電壓)施加至區215以使其中之半導電路徑變得導電，藉此允許經由晶粒間互連件22在晶粒20之發射器201與晶粒21之接收器211之間傳達電信號。
圖2B係根據本揭露之一些實施例之一例示性半導體配置2b之一俯視圖。半導體配置2b包含一晶粒間互連件22及作為一接收器(諸如圖2A中之晶粒21之接收器211)之一部分之一電晶體240。
晶粒間互連件22未直接連接至電晶體240之閘極240g。即，節點214未直接連接至閘極240g。代替地，晶粒間互連件22經由一導電(例如，金屬)路徑214a、電晶體241之汲極241d、電晶體241之通道(在閘極241g下方)、電晶體241之源極241s及一導電(例如，金屬)路徑250連接至閘極240g。形成於導電路徑214a與250之間之路徑係半導電的，此係因為其由半導體材料製成。在一些實施例中，在半導體配置2b之製作期間，未將電壓有意施加至閘極241g。因此，電晶體241之通道可在製作期間保持不導電。此可在導電路徑214a與導電路徑250之間提供電隔離。此電隔離可在製作期間保護閘極240g之介電材料(諸如氧化物)使之免受在晶粒間互連件22或經由一導電路徑連接至其之其他電路結構上產生之電荷(諸如電漿誘發電荷)之影響。在完成半導體配置2b之製作之後，可藉由將適當電信號施加至閘極241g而導通閘極241g下面之半導電路徑。
此項技術中應瞭解，一電晶體之源極及汲極可被稱為該電晶體之兩個源極/汲極區，此係因為可藉由施加至該兩個源極/汲極區之電壓差判定哪一區係源極且哪一區係汲極。
圖3A係根據本揭露之一些實施例之一例示性晶粒31a之一剖面圖。晶粒31a包含可為一接收器(諸如圖2A中之晶粒21之接收器211)之一部分之一電晶體330。一晶粒間互連件32 (諸如一TSV)可將晶粒31a連接至另一晶粒。
晶粒31a包含一前段製程(FEOL)部分31a1及一後段製程(BEOL)部分31a2。FEOL部分31a1可包含電晶體，諸如電晶體330。BEOL部分31a2可包含導電互連件，諸如金屬線321、322及通路323。
晶粒31a包含電晶體330及331，該兩者具有其等各自閘極330g及331g、汲極330d及331d以及源極330s及331s。一閘極介電質包含於閘極330g及331g中。汲極330d、331d及源極330s、331s可形成於電晶體330及331之各自阱330w、331w中。阱330w、331w可形成或包含電晶體330及331之本體。如此項技術中已知，若將適當電壓施加至閘極330g、331g，則一通道可形成在閘極330g、331g下面。儘管圖3A中未明確繪示，然本體接點可將電晶體330、331之本體連接至一參考電壓(諸如接地)。
在一些實施例中，汲極330d、331d及源極330s、331s係n摻雜；且阱係p摻雜。然而，其他類型之摻雜亦可行。
電晶體331之汲極331d經由金屬連接341、342及導電通路343連接至電晶體330之閘極330g。然而，晶粒間互連件32未直接連接至電晶體330之閘極330g，此係因為至少電晶體331之閘極331g下面之通道係半導電的。因此，電晶體331可據稱為電晶體330之閘極330g提供PID保護。可認為在晶粒31a之製作期間，特定言之在晶粒間互連件32與閘極330g之間之結構連接(諸如晶粒間互連件32本身、金屬線321、322、通路323、金屬連接341、342及導電通路343)之製作期間提供用於閘極330g之PID保護，此係因為晶粒間互連件32與閘極330g之間將不存在導電路徑。在完成製作之後，可將大於電晶體331之臨限電壓之一電壓施加至閘極331g以允許電信號在晶粒間互連件32與閘極330g之間傳達。
電晶體330、331可被視為形成用於晶粒31a之一複合輸入電路33。
圖3B繪示可提供給電晶體330之閘極介電質之PID保護能力之另一態樣。
電晶體331之源極331s (以及汲極331d)可經摻雜具有與阱331w經摻雜具有之極性不同之一極性。因此，電晶體331可被視為在源極331s與阱331w之間提供一有效p-n接面35。有效p-n接面35可被視為具有一第一端部351及一第二端部352。由於阱331w可經由一本體接點(未明確繪示)連接至一參考電壓，故有效p-n接面35亦可被視為提供從源極331s至參考電壓之一放電路徑。
有效p-n接面35亦可被視為與存在於通路323與343之間之半導電路徑並聯連接且由源極331s、閘極331g下面之通道及電晶體331之汲極331d形成。若一大電位產生在晶粒間互連件32上(例如，藉由基於電漿之處理誘發)，則有效p-n接面35可提供一放電路徑，藉此有助於避免大電位命中電晶體330之閘極介電質(其原本可能擊穿閘極介電質)。
簡而言之，電晶體331及其組態可藉由在晶粒間互連件32與閘極330g之間提供一半導電路徑(此防止大量電荷經由一(例如)金屬路徑不受阻礙地流動至閘極介電質)且提供有效p-n接面35 (此提供一放電路徑)而幫助保護電晶體330之閘極介電質免於擊穿。
另一優點係可運用現代製程以一小大小製作電晶體。因此，相較於天線二極體(基於適用設計規則，其大小可為大的)，電晶體331在提供PID保護方面可能更有利。
圖3C類似於圖2B，其中不同之處在於明確繪示一有效p-n接面35。可藉由導電路徑314a與350之間之半導電路徑(鑑於閘極331g處不存在大於電晶體331之臨限電壓之一電壓，其可在半導體配置3c之製作期間保持不導電)，以及藉由可幫助針對可在製作期間透過導電路徑314a來自晶粒間互連件32之電荷產生一放電路徑的有效p-n接面35來保護電晶體330之閘極330g之閘極介電質。
在一實施例中，晶粒31a可額外地包含具有其自身閘極區、第一源極/汲極區及第二源極/汲極區之另一電晶體，其中該另一電晶體連接在晶粒間互連件32與閘極端子330g之間。在此一實施例中，電晶體331及該另一電晶體之一者係PMOS，而另一者係NMOS，藉此兩個電晶體形成一CMOS傳輸閘。
在一實施例中，無導電路徑將晶粒間互連件32直接連接至電晶體330之閘極區330g。
圖4A繪示根據本揭露之一些實施例之一例示性半導體配置(或半導體結構) 4。
半導體配置4包含一第一晶粒40、一第二晶粒41及將晶粒40之一發射器401連接至晶粒41之一接收器411的一晶粒間互連件42。發射器401可包含一輸出邏輯閘。接收器411可包含一輸入電晶體430。接收器411可包含包含一輸入電晶體430之一輸入邏輯閘。
晶粒41包含具有一第一端子431及一第二端子432之一電路412。電路412可藉由在晶粒間互連件42與電晶體430之閘極之間提供一半導電路徑而向電晶體430提供PID保護。電路412亦可提供用於釋放累積於晶粒間互連件42上之電荷之有效p-n接面。
圖4B繪示可實施電路412之數項例示性實施例。
在圖4B中，部分(a)繪示藉由一p型電晶體451及一n型電晶體452形成之一傳輸閘。傳輸閘在電路412之端子431與432之間提供一可控半導電路徑。端子431與432之間之路徑可在不存在施加至電晶體451及452之閘極端子之足夠電壓之情況下(諸如在半導體配置4之製作期間)保持不導電；該路徑可藉由導通電晶體451及452而變得導電。此等電晶體之源極/汲極區亦可結合電晶體之本體區提供有效p-n接面。部分(b)繪示藉由一p型電晶體461及一n型電晶體462形成之一傳輸閘，其中電晶體之一個源極/汲極區直接連接至另一源極/汲極區。
在圖4B中，部分(c)繪示包含串聯連接之兩個傳輸閘(包含電晶體471、472、473及474)之一實施例。
在圖4B中，部分(d)繪示一實施例，其中PMOS電晶體481、483與NMOS電晶體482、484並聯連接，其中PMOS電晶體之一個源極/汲極區未連接至NMOS電晶體之源極/汲極區。部分(e)與部分(d)之不同之處在於PMOS及NMOS分支可各包含兩個以上電晶體。
可藉由其他邏輯控制圖4B中展示之電路之電晶體之閘極端子以提供對此等電晶體之靈活或可程式化控制。此等電晶體之閘極端子可(例如)在製作之後及在電路操作期間亦連接至參考電壓，諸如接地、正電源供應器及負電源供應器。
PID保護能力亦可整合於一接收器之電路之設計中，如圖5A之實施例中展示，圖5A繪示根據本揭露之一些實施例之一例示性半導體配置(或半導體結構) 5。
類似於圖4A中之半導體配置4，圖5A中之半導體配置5包含一第一晶粒50、一第二晶粒51及將晶粒50之一發射器501連接至晶粒51之一接收器511的一晶粒間互連件52。
不同於圖4A中之半導體配置4，PID保護能力整合於晶粒51之接收器511之設計中，其中參考圖5B說明更多細節，圖5B繪示接收器511之數項實施例。
以圖5B之部分(a)為例。如此實施之接收器511可包含一邏輯閘530a及一通過電路540a。通過電路540a提供從晶粒間互連件至邏輯閘530a之閘極介電質之一半導電路徑，而不提供至此等閘極介電質之一導電(或金屬)路徑。不存在至此等閘極介電質之導電路徑可在半導體配置5之製作期間保護其等使之免受PID之影響。通過電路540a中之電晶體亦可提供連接至節點514之有效p-n接面。
圖5B中之部分(b)、(c)、(d)、(e)及(f)繪示邏輯閘530b、530c、530d、530e及530f及通過電路540b、540c、540d、540e及540f之其他實例。
圖6A至圖6C係根據本揭露之一些實施例之例示性半導體配置6a、6b、6c之剖面圖。
參考圖6A。半導體配置6a包含一第一晶粒60a、一第二晶粒61a及將晶粒60a及61a彼此連接的晶粒間互連件62a。晶粒60a、61a之各者包含各自前段製程(FEOL)部分60a1、61a1及各自後段製程(BEOL)部分60a2、61a2。FEOL部分60a1、61a1可包含電晶體。BEOL部分60a2、61a2可包含導電路徑，諸如一導電互連件64a。
晶粒61a包含一複合接收器63a，其可以類似於圖5B中展示之接收器511及其各項實施例之一方式包含一邏輯閘及一通過電路。在(例如)半導體配置6a之製作期間在晶粒間互連件62a中產生一大電位之情況下，通過電路可幫助向邏輯閘之輸入電晶體之閘極介電質提供PID保護。
在晶粒61a之製作期間，可在BEOL部分61a2之前製作FEOL部分61a1。因此，可在BEOL部分61a2中之晶粒間互連件62a及導電互連件64a之前製作複合接收器63a (其可包含電晶體)。因此，若在晶粒間互連件62a及/或導電互連件64a之製作期間產生電荷，則複合接收器63a中之通過電路可向複合接收器63a中之邏輯閘之輸入電晶體之閘極介電質提供PID保護。
可在一基板(諸如一半導體基板)上製作FEOL部分61a1。垂直於基板之一方向上之晶粒間互連件62a與複合接收器63a之間之一距離D a大於或等於約0.1微米且小於或等於約100微米。
圖6B中之半導體配置6b類似於圖6A中之半導體配置6a。不同之處在於複合接收器63b不但經由晶粒間互連件62b而且經由一TSV 62b1連接至晶粒61b。鑑於複合接收器63b中之通過電路，在TSB 62b1之製作期間產生之電漿誘發電荷可不太可能擊穿複合接收器63b中之輸入邏輯閘之電晶體之閘極介電質。垂直於基板之一方向上之TSV 62b1與複合接收器63b之間之一距離D b大於或等於約0.1微米且小於或等於約100微米。
參考圖6C，圖6C繪示具有組裝於相同封裝中之一晶粒60c及一晶粒61c之一例示性半導體配置6c。晶粒60c、61c附接至一封裝基板67且藉由囊封材料66囊封。垂直於基板之一方向上之晶粒間互連件62c與複合接收器63c之間之一距離D c大於或等於約0.1微米且小於或等於約100微米。
圖7A至圖7D係根據本揭露之一些實施例之例示性半導體封裝之剖面圖。
圖7A繪示包含兩個晶粒70a、71a之一基板上覆晶圓上覆晶片(CoWoS)封裝。晶粒71a包含一複合接收器73a，其可以可類似於圖5B中展示之接收器511及其各項實施例之一方式包含一邏輯閘及一通過電路。
複合接收器73a經由一晶粒間互連件72a連接至晶粒70a。在圖7A之實施例中，晶粒間互連件72a包含凸塊、晶粒70a、71a正下方之中介層基板中之水平及垂直線、及中介層基板下方之封裝基板中之導電線。複合接收器73a包含一通過電路，該通過電路可在晶粒間互連件72a中產生一大電位之情況下幫助保護複合接收器73a之輸入邏輯閘之閘極介電質使之免受PID損壞。
圖7B繪示類似於圖7A中展示之CoWoS封裝之一CoWoS封裝。不同之處在於晶粒71b可為包含數個組件晶粒(圖7B之實施例中繪示三個組件晶粒)之一系統整合晶片(SoIC)。除晶粒外部之佈線(如圖7A中展示)以外，複合接收器73b亦可經由一TSV 72b及一晶粒中導電線74b連接至晶粒70b。
圖7C繪示包含兩個晶粒70c、71c之一積體扇出(InFO)封裝。晶粒71c中之複合接收器73c經由可包含凸塊、支援晶粒70c、71c之封裝基板中之水平及垂直線及連接至晶粒70c之接合線的一晶粒間互連件72c連接至晶粒70c。
圖7D繪示類似於圖7C中展示之InFO封裝之一InFO封裝。不同之處在於晶粒71d可為以可類似於圖7B中之晶粒71b之組態之一方式包含數個組件晶粒(圖7D之實施例中繪示三個組件晶粒)之一系統整合晶片 (SoIC)。
圖8A繪示根據一比較實施例之一晶粒之一部分之佈局區域。圖8B繪示根據本揭露之一些實施例之一晶粒之一部分之佈局區域。
明確言之，晶粒區域8a包含表示一接收器(例如，輸入邏輯閘)之一部分801及表示用於向接收器部分801提供PID保護之天線二極體之一部分802。在圖8A之比較實施例中，晶粒間互連件可直接連接至輸入電晶體之閘極氧化物；在此一比較實施例中，具有滿足相關聯設計規則之一面積之天線二極體可用於提供PID保護。
相比之下，晶粒區域8b包含表示一複合接收器(例如，一通過電路及一輸入邏輯閘)之一部分801'，其亦可以類似於圖3A至圖5B之實施例之一方式向輸入邏輯閘提供PID保護而不使用天線二極體。圖8B展示與使用天線二極體之比較實施例相比，使用一複合接收器之實施例可提供之面積縮減之益處。
圖8C繪示與本揭露之一些實施例有關之例示性效能度量。
在圖8C中，「實施例A」係指天線二極體實施例，而「實施例B」係指複合接收器實施例。圖8C中之表展示複合接收器實施例之面積縮減、時序效能、節能及速度之優點。
圖9A至圖9C展示根據本揭露之至少一項實施例之用於製造一半導體配置之例示性方法流程圖。
參考圖9A。在步驟901，提供一第一晶粒。可藉由其他方法(諸如從第三方購買)實體上製作或獲取第一晶粒。第一晶粒可包含一輸出邏輯閘。第一晶粒可包含類似於圖6A中展示之晶粒60a之一FEOL部分及一BEOL部分。第一晶粒之輸出邏輯閘可駐留於FEOL部分中。
在步驟903，提供一第二晶粒區域。可藉由其他方法(諸如從第三方購買)實體上製作或獲取第二晶粒。第二晶粒可包含一輸入邏輯閘。第二晶粒可包含類似於圖6A中展示之晶粒61a之一FEOL部分及一BEOL部分。第二晶粒之輸入邏輯閘可駐留於FEOL部分中。將參考圖9B論述關於步驟903之更多細節。
在步驟905，連接第一晶粒及第二晶粒。可經由一晶粒間互連件製成連接。第一晶粒及第二晶粒可形成一多晶片封裝。將參考圖9C論述關於步驟905之更多細節。
應注意，圖9A中展示之序列係例示性且非限制性的。舉例而言，可在第一晶粒之前提供第二晶粒。
參考圖9B。在步驟931，可在第二晶粒中形成一FEOL部分。FEOL部分可包含類似於圖6A中展示之複合接收器63a之一複合電路。複合電路可包含一通過電路及一輸入邏輯閘。輸入邏輯閘可包含一電晶體。通過電路可包含一PMOS電晶體及一NMOS電晶體。通過電路可連接至電晶體之一閘極區。通過電路在其形成之後可保護輸入邏輯閘使之免受可與後續製作步驟(諸如步驟905中描述之第一晶粒及第二晶粒之連接)相關聯之電漿誘發損壞。保護機制可類似於參考圖2A至圖5B論述之實施例。
在步驟933，可在第二晶粒中形成一BEOL部分。BEOL部分可包含類似於圖6A中展示之導電互連件64a之一導電互連件。導電互連件可將FEOL部分中之複合電路連接至第二晶粒外部之電路，諸如第一晶粒。可在導電互連件及其至複合電路之連接之製作期間產生電漿誘發電荷，但複合電路中之通過電路可保護輸入邏輯閘使之免受此等電漿誘發電荷之未經控制釋放之影響。
在步驟935，可在第二晶粒中形成一貫穿矽通路(TSV)。TSV可以圖6B中例示性展示之一方式存在於FEOL部分及BEOL部分之一部分中。可在TSV及其至複合電路之連接之製作期間產生電漿誘發電荷，但複合電路中之通過電路可保護輸入邏輯閘使之免受此等電漿誘發電荷之未經控制釋放之影響。
應注意，圖9B中展示之序列係例示性且非限制性的。舉例而言，TSV之一第一部分可在FEOL之形成期間形成，且TSV之一第二部分可在BEOL之形成期間形成，且該兩個部分可接著經組合以形成TSV。亦應注意，TSV之形成可係選用的。
參考圖9C。在步驟951，可使用晶粒間互連件將第一晶粒連接至第二晶粒。已在圖6A至圖7D中展示各種實例。
在步驟953，可將第一晶粒及第二晶粒附接至一封裝基板。已在圖6A至圖7D中展示各種實例。
在步驟955，可至少部分囊封第一晶粒及第二晶粒。圖6C中可見一實例。
應注意，圖9C中展示之序列係例示性且非限制性的。
一積體電路(IC)之設計及製造係一集體努力。作為一IC製造系統100及一相關聯製造流程之一方塊圖之圖1展示如何配置此集體努力之一實例。系統100可用來基於一佈局圖製造一或多個光罩或一IC之一層中之至少一個組件或該兩者之一組合。
系統100包含在與一IC裝置160之製造有關之設計、開發及製造循環期間彼此互動且通信之實體。此等實體可包含一設計公司120、一遮罩室130及一IC製造商/製作者(「晶圓廠」) 150。複數個此等實體可由一單個公司擁有，或可共存於具有共用資源之一共同設施中。
設計公司(或設計團隊) 120產生包含IC裝置160之各種幾何圖案之一IC設計佈局圖122。此等圖案可對應於不同材料(諸如金屬、氧化物及半導體)之圖案且在IC裝置160之不同層中，該等層之圖案可組合以形成各種構件，諸如主動區、(閘極)電極、源極/汲極、金屬線、通路、用於接墊之開口及光學裝置。
IC設計佈局圖122以具有關於圖案之資訊之資料檔案(諸如GDSII或DFII檔案格式)呈現，且可符合適於後續遮罩及晶圓製作之各種特性。
遮罩室130至少部分基於佈局圖122執行遮罩資料製備132及遮罩製作144以產生(若干)遮罩145。
晶圓廠150包含晶圓製作152，其產生將成為IC裝置160之晶圓153，且為此可具有各種製造設施。舉例而言，可採用不同此等設施來製成FEOL及BEOL區段。晶圓廠150在製成IC裝置160時直接使用(若干)遮罩145且因此至少間接使用佈局圖122。
一IC裝置160可為並非不同於參考圖9A至圖9C之製作流程圖中提及之第一晶粒及第二晶粒之一個別晶粒。然而，此並非一限制，因為晶圓廠150亦可產生一多晶片封裝作為IC裝置160。多晶片封裝可包含參考圖2A至圖6C論述之半導體配置及參考圖7A至圖7D論述之半導體封裝。
製作步驟之一者係將圖案(光微影)轉印至晶圓153。圖案可處於奈米級，故必須在電路設計階段期間仔細定義其等在層之各者中之位置。再者，仔細控制製程以確保圖案放置之準確性。
本揭露中提供用於向經由一晶粒件互連件連接至另一晶粒之一晶粒之一輸入電晶體之閘極介電質提供PID保護的設備及方法。藉由替換晶粒間互連件與輸入電晶體之閘極介電質之間之一導電路徑，可防止來自晶粒間互連件之非所要放電擊穿閘極介電質。此外，利用小型半導體裝置(諸如電晶體)之固有或有效p-n接面亦可幫助改良PID偵測之提供且減小面積耗用。
本文中描述之實施例之任一者可單獨使用或以任何組合一起使用。涵蓋於本說明書內之一或多個實施方案亦可包含在發明內容中或在摘要中僅部分提及或暗示或完全未提及或暗示之實施例。儘管各項實施例可能已藉由可在說明書中之一或多個位置論述或暗示之先前技術中之各種缺陷激發，然實施例不一定解決此等缺陷之任一者。換言之，不同實施例可解決可在說明書中論述之不同缺陷。一些實施例可僅部分解決可在說明書中論述之一些缺陷或僅一個缺陷，且一些實施例可能不解決此等缺陷之任一者。
將瞭解，本文中不一定論述全部優點，並非全部實施例或實例需要特定優點，且其他實施例或實例可提供不同優點。
根據本揭露之一態樣，提供一種電路結構。該電路結構可包含：一第一晶粒區域，其包含一輸出邏輯閘；一第二晶粒區域，其包含一電路及一輸入邏輯閘；及一晶粒間互連件。該輸入邏輯閘可包含一電晶體。該電路可連接在該晶粒間互連件與該電晶體之一閘極區之間。該電路可包含一PMOS電晶體及一NMOS電晶體。該PMOS電晶體之一第一源極/汲極區可連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。
根據本揭露之一態樣，提供一種方法。該方法可包含：提供一第一晶粒，其包含一輸出邏輯閘；提供一第二晶粒，其包含可包含一通過電路及一輸入邏輯閘的一複合電路；及至少部分經由一晶粒間互連件連接該第一晶粒及該第二晶粒，使得該第一晶粒之該輸出邏輯閘連接至該第二晶粒之該複合電路之該通過電路。該輸入邏輯閘可包含一電晶體。該通過電路可包含一PMOS電晶體及一NMOS電晶體且可連接至該電晶體之一閘極區。該PMOS電晶體之一第一源極/汲極區可連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。
根據本揭露之一態樣，提供一種半導體結構。該半導體結構可包含：一第一晶粒；一第二晶粒，其包含一第一電晶體；一晶粒間互連件，其電耦合該第一晶粒及該第二晶粒；及一半導電路徑，其介於該晶粒間互連件與該第一電晶體之一閘極區之間。一有效p-n接面可電連接在該半導電路徑與一參考電壓之間。該半導電路徑可經組態以回應於存在大於一臨限電壓之一控制電壓而導電。該半導電路徑可經組態以回應於不存在大於該臨限電壓之該控制電壓而不導電。
前述內容略述數項實施例之特徵，使得熟習此項技術者可更佳地理解本揭露之態樣。熟習此項技術者應瞭解，其等可容易使用本揭露作為用於設計或修改其他製程及結構之一基礎以實行相同目的及/或達成本文中所介紹之實施例之相同優點。熟習此項技術者亦應瞭解，此等等效構造不背離本揭露之精神及範疇，且其等可在不背離本揭露之精神及範疇之情況下在本文中進行各種改變、置換及更改。
2a:半導體配置/半導體結構 2b:半導體配置 3c:半導體配置 4:半導體配置/半導體結構 5:半導體配置/半導體結構 6a:半導體配置 6b:半導體配置 6c:半導體配置 8a:晶粒區域 8b:晶粒區域 20:第一晶粒 21:第二晶粒 22:晶粒間互連件 31a:晶粒 31a1:前段製程(FEOL)部分 31a2:後段製程(BEOL)部分 32:晶粒間互連件 33:複合輸入電路 35:有效p-n接面 40:第一晶粒 41:第二晶粒 42:晶粒間互連件 50:第一晶粒 51:第二晶粒 52:晶粒間互連件 60a:第一晶粒 60a1:前段製程(FEOL)部分 60a2:後段製程(BEOL)部分 60c:晶粒 61a:第二晶粒 61a1:前段製程(FEOL)部分 61a2:後段製程(BEOL)部分 61b:晶粒 61c:晶粒 62a:晶粒間互連件 62b:晶粒間互連件 62b1:貫穿矽通路(TSV) 62c:晶粒間互連件 63a:複合接收器 63b:複合接收器 63c:複合接收器 64a:導電互連件 66:囊封材料 67:封裝基板 70a:晶粒 70b:晶粒 70c:晶粒 71a:晶粒 71b:晶粒 71c:晶粒 71d:晶粒 72a:晶粒間互連件 72b:貫穿矽通路(TSV) 72c:晶粒間互連件 73a:複合接收器 73b:複合接收器 73c:複合接收器 74b:晶粒中導電線 100:積體電路(IC)製造系統 120:設計公司 122:積體電路(IC)設計佈局圖 130:遮罩室 132:遮罩資料製備 144:遮罩製作 145:遮罩 150:晶圓廠 152:晶圓製作 153:晶圓 160:積體電路(IC)裝置 201:發射器 211:接收器 214:節點 214a:導電路徑 215:區 230:電晶體 230g:閘極 240:電晶體 240g:閘極 241:電晶體 241d:汲極 241g:閘極 241s:源極 250:導電路徑 314a:導電路徑 321:金屬線 322:金屬線 323:通路 330:電晶體 330d:汲極 330g:閘極 330s:源極 330w:阱 331:電晶體 331d:汲極 331g:閘極 331s:源極 331w:阱 341:金屬連接 342:金屬連接 343:導電通路 350:導電路徑 351:第一端部 352:第二端部 401:發射器 411:接收器 412:電路 430:輸入電晶體 431:第一端子 432:第二端子 451:p型電晶體 452:n型電晶體 461:p型電晶體 462:n型電晶體 471:電晶體 472:電晶體 473:電晶體 474:電晶體 481:PMOS電晶體 482:NMOS電晶體 483:PMOS電晶體 484:NMOS電晶體 501:發射器 511:接收器 514:節點 530a:邏輯閘 530b:邏輯閘 530c:邏輯閘 530d:邏輯閘 530e:邏輯閘 530f:邏輯閘 540a:通過電路 540b:通過電路 540c:通過電路 540d:通過電路 540e:通過電路 540f:通過電路 801:接收器部分 801':部分 802:部分 901:步驟 903:步驟 905:步驟 931:步驟 933:步驟 935:步驟 951:步驟 953:步驟
當結合附圖閱讀時，從以下詳細描述最佳理解本揭露之態樣。應強調，根據產業中之標準實踐，各種構件未按比例繪製。事實上，為了清楚論述可任意增大或減小各種構件之尺寸。
圖1展示根據一些實施例之一IC製造系統及一相關聯製造流程之一方塊圖。
圖2A係根據本揭露之一些實施例之半導體配置之一示意圖。
圖2B係根據本揭露之一些實施例之一例示性半導體配置之一俯視圖。
圖3A係根據本揭露之一些實施例之一例示性晶粒之一剖面圖。
圖3B係根據本揭露之一些實施例之一例示性晶粒之一剖面圖。
圖3C係根據本揭露之一些實施例之一例示性半導體配置之一俯視圖。
圖4A係根據本揭露之一些實施例之半導體配置之一示意圖。
圖4B繪示根據本揭露之一些實施例之數個電路。
圖5A係根據本揭露之一些實施例之半導體配置之一示意圖。
圖5B繪示根據本揭露之一些實施例之數個電路。
圖6A至圖6C係根據本揭露之一些實施例之例示性半導體配置之剖面圖。
圖7A至圖7D係根據本揭露之一些實施例之例示性半導體封裝之剖面圖。
圖8A繪示根據一比較實施例之一晶粒之一部分之佈局區域。
圖8B繪示根據本揭露之一些實施例之一晶粒之一部分之佈局區域。
圖8C繪示與本揭露之一些實施例有關之例示性效能度量。
圖9A至圖9C展示根據本揭露之至少一項實施例之例示性方法流程圖。
4:半導體配置/半導體結構
40:第一晶粒
41:第二晶粒
42:晶粒間互連件
401:發射器
411:接收器
412:電路
430:輸入電晶體
431:第一端子
432:第二端子

Claims (10)

  1. 一種電路結構，其包括： 一第一晶粒區域，其包括一輸出邏輯閘； 一第二晶粒區域，其包括一電路及一輸入邏輯閘；及 一晶粒間互連件； 其中該輸入邏輯閘包括一電晶體，其中該電路連接在該晶粒間互連件與該電晶體之一閘極區之間； 其中該電路包括一PMOS電晶體及一NMOS電晶體， 其中該PMOS電晶體之一第一源極/汲極區連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。
  2. 如請求項1之電路結構，其中該PMOS電晶體之一第二源極/汲極區連接至該NMOS電晶體之一第二源極/汲極區及該電晶體之該閘極區。
  3. 如請求項1之電路結構，其中該PMOS電晶體係一第一PMOS電晶體且該NMOS電晶體係一第一NMOS電晶體， 其中該電路包括一第二PMOS電晶體及一第二NMOS電晶體， 其中該第二PMOS電晶體之一第一源極/汲極區連接至該第二NMOS電晶體之一第一源極/汲極區及該電晶體之該閘極區。
  4. 如請求項1之電路結構，其中該晶粒間互連件僅經由該電路電連接至該電晶體之該閘極區。
  5. 如請求項1之電路結構，其中該第一晶粒區域包括包括該輸出邏輯閘之一第一標準單元。
  6. 一種方法，其包括： 提供一第一晶粒，其包括一輸出邏輯閘； 提供一第二晶粒，其包括包括一通過電路及一輸入邏輯閘的一複合電路，其中該輸入邏輯閘包括一電晶體，其中該通過電路包括一PMOS電晶體及一NMOS電晶體且連接至該電晶體之一閘極區；及 至少部分經由一晶粒間互連件連接該第一晶粒及該第二晶粒，使得該第一晶粒之該輸出邏輯閘連接至該第二晶粒之該複合電路之該通過電路， 其中該PMOS電晶體之一第一源極/汲極區連接至該NMOS電晶體之一第一源極/汲極區及該晶粒間互連件。
  7. 如請求項6之方法，其中提供該第二晶粒包括： 形成包括該複合電路之一前段製程(FEOL)部分。
  8. 如請求項6之方法，其中提供該第二晶粒包括： 形成包括一導電互連件之一後段製程(BEOL)部分，其中該導電互連件經組態以電連接在該複合電路與該等晶粒間互連件之間。
  9. 一種半導體結構，其包括： 一第一晶粒； 一第二晶粒，其包括一第一電晶體； 一晶粒間互連件，其電耦合該第一晶粒及該第二晶粒；及 一半導電路徑，其介於該晶粒間互連件與該第一電晶體之一閘極區之間， 其中一有效p-n接面電連接在該半導電路徑與一參考電壓之間， 其中該半導電路徑經組態以回應於存在大於一臨限電壓之一控制電壓而導電，且經組態以回應於不存在大於該臨限電壓之該控制電壓而不導電。
  10. 如請求項9之半導體結構，其中該第二晶粒包括： 一第二電晶體，其包括一閘極區、一第一源極/汲極區及一第二源極/汲極區，其中該第二電晶體連接在該晶粒間互連件與該第一電晶體之閘極端子之間。
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