TW202232581A - 用於增強裝置效能的三維金屬線之設計方法 - Google Patents

用於增強裝置效能的三維金屬線之設計方法 Download PDF

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TW202232581A
TW202232581A TW110140013A TW110140013A TW202232581A TW 202232581 A TW202232581 A TW 202232581A TW 110140013 A TW110140013 A TW 110140013A TW 110140013 A TW110140013 A TW 110140013A TW 202232581 A TW202232581 A TW 202232581A
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馬克 Ｉ 加德納
Ｈ 吉姆 富爾福德
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日商東京威力科創股份有限公司
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

基板處理方法包括在基板上形成第一層堆疊，該第一層堆疊包括在該第一層堆疊中交替的複數導電層及複數介電質層。在該第一層堆疊中形成開口，該開口延伸通過該第一層堆疊中的該等導電層的各者，使得該等導電層各者的側壁係暴露於該開口內。在該開口內形成第二層堆疊，該第二層堆疊包括位於該第二層堆疊中的半導體材料的複數通道層，使得各通道層接觸該第一層堆疊的相應導電層的暴露側壁。從該第二堆疊的該等通道層形成電晶體通道，使得各電晶體通道在該開口內相應導電層的暴露側壁之間延伸。

Description

用於增強裝置效能的三維金屬線之設計方法
本揭露係關於包括半導體裝置、電晶體、及積體電路的微電子裝置，包括微製造方法。 [相關申請案的交互參照]
本申請案係主張2020年10月30日提交的美國臨時申請案第63/107,768號、以及2021年6月30日提交的美國非臨時申請案第17/364,077號之優先權。上述申請案的整體內容係作為參考文獻而引入本文中。
此處所提供的先前技術描述，其目的係為了大致呈現本揭露之背景。本案列名發明人的工作成果、至此先前技術段落所描述的範圍、以及申請時可能不適格作為先前技術的實施態樣，均不明示或暗示承認為對抗本揭露內容的先前技術。
半導體技術持續進展至14奈米以下的較小特徵部尺寸。從先前元件所進行製造的持續縮減特徵部尺寸係對於形成所述特徵部所使用的技術帶來越來越高的要求。在半導體裝置(尤其是微觀尺寸)的製造期間係執行各種製造處理，例如膜-形成沉積、蝕刻遮罩產生、圖案化、材料蝕刻及移除、以及摻雜處理。這些處理係重複執行以在基板上形成所欲的半導體裝置元件。歷史上，已利用微製造在一平面中形成電晶體伴隨著形成在主動裝置平面上方的佈線/金屬化，而因此其特徵為二維(2D)電路或2D製造。微縮化的成果已大幅增加2D電路中每單位面積的電晶體數量，隨著微縮化進入個位數奈米的半導體裝置製造節點，再來的微縮化成果已面臨到更大挑戰。半導體裝置製造商已表示對於三維(3D)半導體電路的需求，其中在該3D半導體電路中電晶體係堆疊在彼此頂部。
因此，本揭露的其中一目標在於提供設計三維金屬線以增強裝置效能的方法及系統。
本揭露的態樣為對三維金屬線進行設計，以藉由結合3D介電質堆疊的不同層內的3D金屬層以產生水平奈米片的增強3D堆疊，而增強裝置性能的方法及結構。
態樣（1）包括基板處理方法，該方法包括在基板上形成第一層堆疊，該第一層堆疊包括在該第一層堆疊中交替的複數導電層及複數介電質層；在該第一層堆疊中形成開口，該開口延伸通過該第一層堆疊中的該等導電層的各者，使得該等導電層各者的側壁係暴露於該開口內；在該開口內形成第二層堆疊，該第二層堆疊包括位於該第二層堆疊中的半導體材料的複數通道層，使得各通道層接觸該第一層堆疊的相應導電層的暴露側壁；以及從該第二層堆疊的該等通道層形成複數電晶體通道，使得各電晶體通道在該開口內相應導電層的暴露側壁之間延伸。
態樣（2）包括如請求項1之基板處理方法，其中該形成第一層堆疊包括沉積複數金屬層以作為該等導電層。
態樣（3）包括如請求項2之基板處理方法，其中該沉積金屬包括為該等金屬層各者沉積不同金屬材料。
態樣（4）包括如請求項2之基板處理方法，其中該沉積金屬包括為該等金屬層各者沉積相同金屬材料。
態樣（5）包括如請求項1之基板處理方法，其中：該形成開口包括暴露該基板的半導體表面，以及該形成第二堆疊包括磊晶生長半導體材料的複數犧牲層，半導體材料的該等犧牲層係與該第二堆疊中的半導體材料的該等通道層交替。
態樣（6）包括如請求項5之基板處理方法，其中該形成第二堆疊包括磊晶生長SiGe材料的複數犧牲層，SiGe材料的該等犧牲層提供相對於該等通道層的蝕刻選擇性。
態樣（7）包括如請求項1之基板處理方法，其中該形成第二層堆疊包括在與對應導電層相同的平面中形成該等通道層的各者，使得該等通道層的端部係與該對應導電層的側壁對準。
態樣（8）包括如請求項1之基板處理方法，其中該形成第二層堆疊包括藉由在該第二堆疊中蝕刻出將該第二堆疊分割成複數第二堆疊的開口，以在該開口內形成複數第二層堆疊。
態樣（9）包括如請求項1之基板處理方法，其中：該形成開口包括在該第一層堆疊中形成複數開口，該形成第二層堆疊包括分別在該等開口內形成複數第二堆疊，以及從各第二層堆疊的該等通道層形成複數電晶體通道。
態樣（10）包括如請求項1之基板處理方法，其中該形成電晶體通道包括形成圍繞各通道層的全環繞閘極(GAA)結構。
態樣（11）包括如請求項1之基板處理方法，其中該全環繞閘極GAA結構包括：選擇性沉積圍繞著該通道層的高k介電質層；以及在該高k介電質層上選擇性沉積閘極金屬。
態樣（12）包括基板處理方法，該方法包括：在基板上形成第一層堆疊，該第一層堆疊包括在該第一層堆疊中交替的複數金屬層及複數介電質層；在該第一層堆疊中形成複數開口，並且在該第一層堆疊中未經覆蓋的該等開口中沉積第一半導體層，使該第一半導體層位於該基板上方；藉由磊晶生長在該第一半導體層上方的該等開口內形成第二層堆疊，該第二層堆疊包括在該第二層堆疊中交替且與該第一層堆疊的對應層對準的複數第二半導體層及複數磊晶層；以及在與該第一層堆疊的該等金屬層相同的平面中從該第二層堆疊的該等磊晶層形成複數電晶體通道，使得該等電晶體通道在該等金屬層與該等開口內的該等磊晶層之間延伸。
態樣（13）包括如請求項12之基板處理方法，更包括：藉由下列步驟在該第一層堆疊中形成該等開口：在封蓋層的至少一部分上方沉積第一遮罩層，該封蓋層係沉積在該第一層堆疊的頂部上；以及執行第一蝕刻，該第一蝕刻將該第一層堆疊未被該第一遮罩層覆蓋的部分進行蝕刻以在該第一層堆疊中形成該等開口，其中該第一層堆疊中的該等開口的長度係等於預定距離。
態樣（14）包括如請求項13之基板處理方法，其中該第一遮罩層包括光阻（PR）遮罩層。
態樣（15）包括如請求項12之基板處理方法，其中該第一層堆疊中的該等開口包括第一開口及第二開口，且其中該第一開口及該第二開口具有由該基板層所形成的基部。
態樣（16）包括如請求項15之基板處理方法，更包括：在該第一開口及該第二開口各者內形成第二層堆疊；以及在該第一開口及該第二開口內所形成的該第二層堆疊各者上方沉積另一封蓋層。
態樣（17）包括如請求項16之基板處理方法，更包括：在該第二層堆疊的該另一封蓋層上方沉積第二遮罩層，使得該第二遮罩層在該另一封蓋層上方延伸以與該封蓋層的一部份重疊，其中該第二遮罩層的寬度係等於第二預定距離。
態樣（18）包括如請求項17之基板處理方法，更包括：對該第二層堆疊執行第二蝕刻，該第二蝕刻對該第二層堆疊未被該第二遮罩層覆蓋的第一組部分進行蝕刻，以在該第二層堆疊中形成複數開口。
態樣（19）包括如請求項18之基板處理方法，其中被覆蓋在該第二遮罩層下方的該第二層堆疊的第二組部分係基於該第二蝕刻而形成第三層堆疊，其中該第三層堆疊的寬度等於該第二預定距離。
態樣（20）包括如請求項19之基板處理方法，其中被覆蓋在該第二遮罩層下方的該第二層堆疊、且形成該第三層堆疊的該第二部分組包括該等第二半導體層的一部分及該等磊晶層的一部分。
在本文中所描述的不同步驟的討論順序係為清楚的目的而呈現。一般而言，這些步驟得以任何合適順序執行。另外，雖然本文中不同特徵、技術、配置的各者可能在本揭露的不同處進行討論，但其用意在於所述概念的各者可彼此獨立、或是彼此結合而執行。因此，本發明得以許多不同方式而加以實施及檢視。
應注意的是，此發明內容章節並未指明本揭露或所請發明的所有實施例及/或漸進的新穎態樣。反而，此發明內容僅提供對不同實施例的初步討論，以及對於傳統技術的相應新穎重點。關於本發明及實施例的額外細節及/或可行觀點，將讀者導向如進一步敘述於下的本揭露的實施方式章節及相應圖式。
3D整合(即，複數裝置的垂直堆疊)的目標在於藉由在體積中而非在面積中提高電晶體密度而克服平面裝置所經歷的微縮限制。雖然裝置堆疊已由快閃記憶體產業透過採用3DNANO而成功展示及實施，但應用至隨機邏輯設計係困難得多。目前正在追求邏輯晶片(中央處理單元(CPU)、圖像處理單元(GPU)、場域可編程閘極陣列(FPGA)、單晶片系統(SoC))的3D整合。
本文中的技術能夠在減低成本下製造較高密度的電路。實施例包括具有全環繞閘極(GAA)架構邏輯設計的3D水平奈米片。利用本文中的技術可訂製N+S/D及P+S/D金屬堆疊。
本文中的技術包括GAA電晶體結構的形成方法。技術包括形成第一層堆疊，該第一層堆疊包括與介電質層交替的金屬層。在第一層堆疊內形成開口透過磊晶生長而生長第二層堆疊。第二層堆疊包括交替的半導體材料層，其中該半導體材料可對於其他半導體材料而被選擇性蝕刻。電晶體通道係從與金屬層成平面的半導體層的一部分形成。該電晶體通道的結構係在給定平面中從金屬線延伸至金屬線。已連接至電晶體結構的金屬線可作為局部內連件，其可促進對於橫向GAA電晶體的垂直堆疊的連接。
當然，本文所述的不同步驟的討論順序已為清晰目的而呈現。一般而言，這些步驟得以任何合適順序加以執行。另外，雖然本文中的不同特徵、技術、配置等各者可在本揭露的不同處進行討論，但其用意在於所述概念的各者可彼此獨立執行或彼此結合執行。因此，本發明得以許多不同方式而實施及檢視。
在圖式中，類似的元件符號係指複數圖式各處的相同或相應部分。此外，本文所使用的字詞「一」等用語通常帶有「一或更多」的意義，除非另有指明。一般而言，圖式係按照比例繪示，除非另有指明、或是繪示為示意性結構、或是流程圖。
另外，術語「大約」、「約為」及類似術語通常係指落在邊界的20%、10%或較佳為5%內的已知數值、以及介於其之間的任何數值的範圍。
本文中的技術提供在三維(3D)裝置中形成金屬線的先進處理。實施例包括將交替金屬層及介電質層的3D堆疊與水平奈米片裝置的3D堆疊結合以增強電晶體性能。利用本文中的方法可訂製N+S/D(源極/汲極)及P+S/D金屬堆疊。實施例能夠改善裝置性能ldsat(飽和汲極電流)，而這是由於自對準S/D區域能夠實現非常高的電子及電洞濃度而達成。本文中的佈線布局對準可在奈米片形成之前執行，以作為更有效電路布局的選項。技術能夠使水平奈米片/導線具有GAA架構邏輯設計。其他實施例包括互補式場效電晶體(CFET)、電晶體的並排垂直堆疊、及許多3D裝置結構。
現在將參照隨附圖式而描述本文中的技術。圖1-圖21描述示例性處理流程。該示例處理係並排使用高性能CMOS裝置所用的金屬層及介電質層的3D層堆疊而提供3DGAA水平奈米片裝置的堆疊。
在圖1中，層堆疊係沉積在基板上。繪示出橫截面的基板部分。該層堆疊包括介電質材料及金屬(導電材料)的交替層。圖1-圖21的示例實施例將包括三個具有GAA水平奈米片的電晶體。雖然在此發明示例中顯示三個電晶體層，但可使用更多層(N層)以進行本文中的3D裝置形成。
如圖1所示，第一層堆疊101係沉積在基板102上，其中第一封蓋層104係沉積在第一層堆疊101的頂部上。圖1繪示基板102的橫截面部分。第一層堆疊101包括與導電層108、112及116交替的介電質層106、110、114及118。
層106、110、114及118的介電質材料可包括低K介電質材料，例如奈米多孔二氧化矽、氫倍半矽氧烷(HSQ)、鐵氟龍-AF(聚四氟乙烯或PTFE)、及/或矽氧氟化物(FSG)，但可使用任何其他合適類型的介電質材料。此外，介電質層106、110、114及118可由相同的介電質材料或不同的介電質材料所製成。
導電層108、112及116可為任何導電材料(例如，金屬)並且可包括鋰、鈦、鈦氮化物層(TiN)、鎢、及/或金屬亞硝酸鹽，但亦可包括任何其他類型的導電材料。此外，層108、112及116可由相同導電材料或不同導電材料所製成。
用以形成導電層108、112及116的材料類型可為電晶體(導電層將與其連接)類型專屬訂制。作為示例，NMOS電晶體類型可使用第一類型的金屬(稱為「金屬1」)，而PMOS電晶體類型可使用第二類型的金屬(稱為「金屬2」)。在圖1-圖21的示例實施例中，層108係由與NMOS裝置連接的金屬1所製成，而層112及116係由與PMOS裝置連接的金屬2所製成。金屬類型通常取決於將決定NMOS或PMOS裝置的Vt(即，閾值電壓)的電路需求。此外，高k閘極介電質的厚度及高K材料的類型亦將作為此金屬選擇及高K閘極介電質材料的厚度的因素。此外，金屬堆疊可用於進一步微調此Vt。某些金屬示例係包括釕(Ru)、鉭氮化物(TaN)、鈦氮化物(TiN)、及鎢、TiC、Ga、Gd、TiON、W、TaSiN、TiSiN、Mo、WN、Al、Cu及其組合的群組。在替代實施例中，導電層108、112、及116皆可由相同材料所製成，或是皆可由彼此不同的材料所製成。
基板102更包括位於基板102中、主動裝置下方的埋入式動力軌條120。在另一實施例中，可不將動力軌條埋置在基板102中，反而動力軌條可位於基板102外部，例如位於主動裝置上方。
圖2及圖3繪示在交替介電質層及導電層的第一堆疊101中的開口形成。如圖2所示，遮罩層126係沉積在第一封蓋層104上方。遮罩層126可為光阻(PR)。遮罩層126係經圖案化，使得在遮罩層126中存在第一預定長度L1及L2的開口間隔128。雖然圖2顯示L1及L2為相等長度，但長度L1及L2可彼此不相等。雖然遮罩層126係被繪示為具有二個開口間隔128，但在該遮罩層126中可形成任何數量的開口間隔。
現在請參照圖3，使用遮罩層1262對第一層堆疊101進行蝕刻而敞開未來的3D奈米片區域。換言之，利用位於適當位置的蝕刻遮罩層126，可將第一層堆疊101指向性地蝕刻穿該層堆疊中的所有層、或是至少蝕穿金屬層。形成於其中的開口可界定此示例性三電晶體堆疊的裝置的L尺寸。在圖3的實施例中，在未被遮罩層126覆蓋的區域中，第一開口132-1及第二開口132-2係蝕刻穿所有的層106、108、110、112、114、116、118、及104以暴露下方基板102。暴露下方基板准許開口132-1及132-2內的半導體層的磊晶生長，如將敘述於下。第一開口132-1及第二開口132-2的長度係分別等於與遮罩開口尺寸相應的L1及L2。應注意到，L1及L2可具有不同尺寸、或是可為由遮罩層126所界定的相同尺寸。
在對第一層堆疊101進行蝕刻後，將蝕刻遮罩移除，隨後在第一層堆疊101中所形成的開口中生長第二堆疊。層的第一堆疊101亦稱作第一層堆疊101。第二堆疊可包括半導體材料的交替層。舉例而言，第二堆疊的交替層可包括(從底部向上)SiGe2、SiGex、磊晶通道1、SiGex、磊晶通道2、SiGex、磊晶通道3、及SiGex。應注意到，取決於3D電路布局需求，可形成一或更多堆疊。圖1-圖21的示例處理流程繪示一實施例，其包括堆疊的上方及下方位置(合適用於NMOS裝置的金屬2)中的二NMOS裝置，伴隨著位於中央(合適/選擇用於PMOS裝置的金屬1)的一PMOS裝置。圖4繪示此示例。圖4顯示將圖3的遮罩層126移除，在開口132-1及132-2中分別沉積第二堆疊133-1及133-2。第二堆疊133-1及133-2各自包括由(從底部向上)SiGe2層134、SiGex層136、磊晶通道1層138、SiGex層140、磊晶通道2層142、SiGex層144、磊晶通道3層146、及SiGex層148所製成的交替層。磊晶通道1材料、磊晶通道2材料、及磊晶通道3材料可為不同材料或相同材料。磊晶通道1材料、磊晶通道2材料及磊晶通道3材料可包括任何單晶半導體或化合物半導體。一些示例包括Si、SixGe1-x、Ge、SixC1-x、GexSny。通道還可為本質性的、或是取決於電路需求而摻雜N+或P+以作為其他選項(SiB、GeAs、SiP、SiAs為一些摻雜示例)。此外，SiGex層136、140及144可為允許對磊晶通道層138、142及146具有選擇性的任何合適組成物。圖5為圖4的俯視圖。電晶體的未來通道區域將位於SiGex層148下方，而金屬S/D區域將位於封蓋層104下方，如將進一步敘述於下。
如圖6及圖7所顯示，第二封蓋層166係在基板上沉積及平坦化。這實質上係在磊晶堆疊上方添加封蓋層。具體而言，圖6繪示沉積在由SiGex材料所製成的層148上方的第二封蓋層166。在圖1-圖21的示例實施例中，第二封蓋層166與第一封蓋層104係不同材料，使得封蓋層166對於封蓋層104具有選擇性。
圖7繪示圖6的俯視圖，其中第二封蓋層166的區域係被第一封蓋層104所圍繞。在一些實施例中，層166及第二堆疊133-1、133-2具有與各堆疊內的最終GAA電晶體的通道區域對應的尺寸。舉例而言，在圖7的俯視圖中，第二堆疊133-1及133-2可提供該堆疊內的各GAA電晶體的通道的長度及寬度尺寸二者。然而，在圖1-圖21的示例處理流程中，第二堆疊133-1及133-2係進一步劃分成界定電晶體通道寬度的較小堆疊。
圖8-圖11顯示在遮罩層170下方形成四個第二堆疊，其中該四個第二堆疊將各自提供三個堆疊GAA電晶體，而總共為12個GAA電晶體。基板係受到遮蓋(圖8，其為俯視圖)。未來通道區域係位於SiGex下方，而金屬S/D區域係位於封蓋層下方。圖8繪示圖7的俯視圖，其中遮罩層170係沉積在第一封蓋層104及第二封蓋層166上方。遮罩層170亦稱作第二遮罩層圖案，並且可為PR遮罩層。如圖8所示，第二遮罩層170係經圖案化以提供四個PR材料區域，其各者係在第二封蓋層166上方延伸並且與第一封蓋層104的部分重疊。換言之，遮罩層170係沉積在層166上方，使得遮罩層170的遮罩區域的長度大於長度L1及L2。遮罩層170的該四個區域各者將界定磊晶生長半導體材料的相應第二堆疊。此外，該遮罩層170的該四個區域各者為其堆疊內的電晶體界定通道寬度。顯示示例寬度W1及W2。寬度W1及W2可為相同或不同的。
圖9顯示在開口內蝕刻磊晶堆疊且移除蝕刻遮罩過後的俯視圖。具體而言，圖9繪示在移除遮罩層170、以及蝕刻未被遮罩層170覆蓋的堆疊層的一部分過後的圖8俯視圖。該蝕刻暴露介電質層106的區域，並且產生四個第二堆疊180-1、180-2、180-3及180-4。圖9還繪示線AA’及線BB’，其係用以繪示沿著線下方的區域的橫截面的側視圖。
圖10顯示穿過第二堆疊180-1及180-2的裁切線AA'的側視橫截面圖。堆疊180-1具有寬度W1而堆疊180-2具有寬度W2。因此，第二堆疊180-1及180-2各自包括位於封蓋層166下方的層134、136、138、140、142、144、146及148。該等層係藉由對第一堆疊101的交替層134、136、138、140、142、144、146及148(如先前在圖4所說明)進行蝕刻而形成。應注意到，由於開口184的緣故，第一堆疊101的金屬層108、112及116的相對側並未與磊晶通道層138、142及146所形成的通道區域連接。開口184內的此間隔可使用於額外的路由特徵。
圖11顯示穿過堆疊180-1及180-2的裁切線BB'的側視橫截面圖。如圖所示，堆疊180-3具有寬度W1且包括位於封蓋層166下方的層134、136、138、140、142、144、146及148。該等層係藉由對第一堆疊101的交替層134、136、138、140、142、144、146及148(如先前在圖4所說明)進行蝕刻而形成。如圖所示，第一堆疊101的層與第二堆疊180-1、180-2、180-3及180-4各者的層具有相同厚度，使得金屬層108、112及116係經垂直對準以接觸磊晶通道層138、142及146的相對端部。因此，S/D區域的金屬係連接至通道區域，且對於沿著BB'的L方向橫截面係自對準的。
圖12繪示利用介電質2 186替換SiGe2層134(磊晶堆疊的底層)過後穿過裁切線AA'，而圖13繪示穿過裁切線BB'的圖12的結構。雖然圖10將介電質材料106顯示成與堆疊底部處的SiGe2層134具有相同厚度，但本發明所屬技術領域中具有通常知識者將能理解到介電質材料106的厚度必須小於SiGe2層134的厚度，使得層134係暴露的以進行介電質2 186的選擇性蝕刻及選擇性沉積。
圖14及圖15繪示各磊晶堆疊的通道區域的釋放。圖14顯示藉由選擇性蝕刻將SiGex層從磊晶堆疊180-1及180-2移除後的側向橫截面。如圖15中的BB'橫截面所示，第二堆疊180-1及180-2係被第一堆疊101所支撐。
在釋放各堆疊的磊晶通道層138、142及146過後，全環繞閘極(GAA)結構係圍繞著圖16-圖19所示的這些層各者而形成。首先，執行選擇性高k沉積，其在未經覆蓋的磊晶通道上沉積高k材料。圖16繪示在磊晶通道層的暴露表面上沉積高k閘極材料過後的穿過圖14的裁切線AA’的側視橫截面圖。
具體而言，高k閘極層200係選擇性沉積在各堆疊的層138、142及146的暴露表面上。如圖所示，高k層200圍繞著磊晶通道層的各者。
圖17繪示在層138、142及146的暴露表面上沉積由高k閘極材料所製成的高k閘極層200過後，穿過圖15的裁切線BB'的側視橫截面圖。應注意到，在此圖式中高k層200並未覆蓋磊晶通道層138、142及146的相對側部，原因在於第一層堆疊101的金屬及介電質防止在這些表面上的沉積。
接著，可在將通道圍繞的高k層上形成金屬堆疊。這可透過進行保形沉積接著蝕刻過量材料，或是透過進行選擇性沉積而執行。圖18-圖19顯示在形成閘極堆疊並移除硬遮罩過後的側向橫截面圖。具體而言，圖18繪示穿過圖16的裁切線AA’的側視橫截面圖。如圖所示，金屬閘極層236係沉積在高k閘極層200上方。
圖19繪示在高k閘極層200上方沉積金屬閘極層236過後，穿過圖17的裁切線BB'的側視橫截面圖。閘極金屬層236的形成使堆疊180-1的電晶體通道300-1及堆疊180-2的電晶體通道300-2的形成完成。在所顯示的示例中，電晶體為無接面電晶體，其中金屬層係與電晶體的源極/汲極區域的通道層接合。對於堆疊180-3及180-4，電晶體通道亦被完成。
在圖20-圖21中，沉積介電質以將圍繞著水平通道的開口進行填充。這顯示三個電晶體的垂直堆疊。可理解到，可堆疊更多的電晶體。
圖20繪示穿過圖18的裁切線AA’的側視橫截面圖，其中填充材料264係被沉積以填充開口間隔184。圖21繪示在沉積填充材料264以填充第三堆疊183及第五堆疊183中的開口間隔過後，穿過圖19的裁切線BB'的側視橫截面圖。填充材料264可為介電質材料。
圖22繪示基板處理的非限制性示例的數據流程圖2200。在步驟2202中，第一層堆疊101係形成在基板102上，該第一層堆疊101包括在該第一層堆疊101中交替的金屬層(圖1的108、112及116)及介電質層(圖1的106、110、114及118)。
在步驟2204中，在第一層堆疊101中形成開口(圖3的132-1及132-2)，使得位於第一層堆疊101下方的半導體層102係未經覆蓋的。
在步驟2206中，第二層堆疊(圖4的133-1)係藉由磊晶生長而從半導體層102形成在開口(132-1)內，第二層堆疊(133-1)包括與該第一層堆疊101對應層對準的半導體材料交替層(圖4的134、136、138、140、142、144、146及148)。
在步驟2208中，電晶體通道(圖18的300-1及300-2)係形成自與第一堆疊101的金屬層(108、112及116)處於相同平面中的第二層堆疊(133)的半導體層，使得由磊晶通道層(138、142及146)所形成的電晶體通道在開口(132-1及132-2)內的給定金屬層(108、112及116)之間延伸。
在先前的實施方式中已闡述特定細節，例如處理系統的特定幾何形狀、以及在該處理系統中所使用的各種構件及處理的描述。然而，應當理解的是，本文中的技術可在背離這些特定細節的其他實施例中實行，且這樣的細節的用意在於說明而非限制目的。本文中所揭露的實施例已參照隨附圖式而加以說明。同樣地，為了說明目的，已闡述特定數量、材料、及配置以提供透徹的理解。然而，實施例可在不具此些特定細節的情況下實行。具有實質上相同功能構造的構件係以相同的元件符號表示，且因此可省略任何冗餘描述。
各種技術係已描述成多個分散的操作以協助理解各種實施例。敘述的順序不應被視為暗指這些操作必須與順序相關。實際上，這些操作不必以所呈現的順序執行。所描述的操作可透過與所述實施例不同的順序而執行。在額外實施例中，可執行各種額外操作及/或可省略所描述的操作。
本文中所使用之「基板」或「目標基板」通常係指根據本發明所進行處理的物件。基板可包含裝置的任何材料部分或結構，特別是半導體或其他電子裝置，且可例如係基礎基板結構（例如，半導體晶圓）、標線、或在基礎基板結構上或上方的層（例如，薄膜）。因此，基板並不限於經圖案化或未經圖案化的任何特定基礎結構、下伏層或上覆層，反而係預期包括任何這樣的層或基礎結構、以及層及/或基礎結構的任何組合。
說明內容可參照特定類型的基板，但這僅係作為說明性的目的。本發明所屬技術領域中具有通常知識者亦將理解的是，可對解釋於上的技術操作做出許多變更，而仍可達成本發明的相同目的。這些變更係意旨於被本揭露的範疇所涵蓋。因此，先前對本發明實施例的敘述並不意旨於限制。反而，對本發明實施例的任何限制係呈現在下列申請專利範圍中。
101:第一層堆疊 102:基板 104:第一封蓋層 106,110,114,118:介電質層 108,112,116:導電層 120:埋入式動力軌條 126:遮罩層 128:開口間隔 132-1:第一開口 132-2:第二開口 133-1,133-2:第二堆疊 134:SiGe2層 136:SiGex層 138:磊晶通道1層 140:SiGex層 142:磊晶通道2層 144:SiGex層 146:磊晶通道3層 148:SiGex層 166:第二封蓋層 170:遮罩層 180-1,180-2,180-3,180-4:第二堆疊 183:第三堆疊/第五堆疊 184:開口 186:介電質2 200:高k閘極層 236:金屬閘極層 264:填充材料 300-1,300-2:電晶體通道 2200:數據流程圖 2202,2204,2206,2208:步驟 AA',BB':裁切線 L1,L2:長度 W1,W2:寬度
當與隨附圖式結合考量時，從下列的實施方式將能易於獲得、同樣地能最佳理解本發明的較完整理解及其許多附帶優點，其中：
圖1根據某些實施例繪示具有介電質材料及金屬材料的交替層的第一層堆疊。
圖2根據某些實施例繪示在圖1的第一層堆疊上所沉積的第一封蓋層上方施予複數第一遮罩層。
圖3根據某些實施例繪示對圖2的第一層堆疊進行蝕刻。
圖4根據某些實施例繪示在圖3的經蝕刻區域中沉積第二層堆疊，其中該第二層堆疊具有交替的半導體層及磊晶層。
圖5根據某些實施例繪示圖4的俯視圖。
圖6根據某些實施例繪示在圖5的第二層堆疊上方沉積第二封蓋層。
圖7根據某些實施例繪示圖6的俯視圖。
圖8根據某些實施例繪示圖7的俯視圖，其中複數第二遮罩層係被施予在第二封蓋層各者上方，使其延伸而與第一封蓋層部分重疊。
圖9根據某些實施例繪示在蝕刻層第二堆疊並且標示第一層堆疊的橫截面側視圖線(AA’)及橫截面側視圖線(BB’)過後的圖8的俯視圖。
圖10根據某些實施例繪示在蝕刻第二層堆疊而形成第三層堆疊過後、沿著第一層堆疊的線(AA’)的橫截面側視圖。
圖11根據某些實施例繪示在蝕刻第二層堆疊而形成圖10中的第三層堆疊過後、沿著第一層堆疊的線(BB’)的橫截面側視圖。
圖12根據某些實施例繪示移除第三層堆疊下方的半導體(SiGe2)層並且沉積介電質層以取代經移除半導體層、沿著線(AA’)的圖10的橫截面側視圖。
圖13根據某些實施例繪示移除第三層堆疊下方的半導體(SiGe2)層並且沉積介電質層以取代經移除半導體層、沿著線(BB’)的圖11的橫截面側視圖。
圖14根據某些實施例繪示從第三層堆疊移除半導體(SiGex)層、沿著第一層堆疊的線(AA’)的圖12的橫截面側視圖。
圖15根據某些實施例繪示在從第三層堆疊移除半導體(SiGex)層後、沿著第一層堆疊的線(BB’)的圖13的橫截面側視圖。
圖16根據某些實施例繪示在第三層堆疊中沉積高k介電質層、沿著第一層堆疊的線(AA’)的圖14的橫截面側視圖。
圖17根據某些實施例繪示在第三層堆疊中沉積高k介電質層、沿著第一層堆疊的線(BB’)的圖15的橫截面側視圖。
圖18根據某些實施例繪示在蝕刻第一封蓋層及第二封蓋層且沉積金屬閘極堆疊層過後、沿著第一層堆疊的線(AA’)的圖16的橫截面側視圖。
圖19根據某些實施例繪示在蝕刻第一封蓋層及第二封蓋層且在第三層堆疊中沉積金屬閘極堆疊層過後、沿著第一層堆疊的線(BB’)的圖17的橫截面側視圖。
圖20根據某些實施例繪示在沉積介電質材料接著進行化學機械研磨過後、沿著第一層堆疊的線(AA’)的圖18的橫截面側視圖。
圖21根據某些實施例繪示在沉積介電質材料接著進行化學機械研磨過後、沿著第一層堆疊的線(BB’)的圖19的橫截面側視圖。
圖22根據某些實施例繪示出示例性基板處理方法的數據流程圖。
180-1,180-2:第二堆疊
264:填充材料
L1,L2:長度

Claims (20)

  1. 一種基板處理方法，包括： 在基板上形成第一層堆疊，該第一層堆疊包括在該第一層堆疊中交替的複數導電層及複數介電質層； 在該第一層堆疊中形成開口，該開口延伸通過該第一層堆疊中的該等導電層的各者，使得該等導電層各者的側壁係暴露於該開口內； 在該開口內形成第二層堆疊，該第二層堆疊包括位於該第二層堆疊中的半導體材料的複數通道層，使得各通道層接觸該第一層堆疊的相應導電層的暴露側壁；以及 從該第二層堆疊的該等通道層形成複數電晶體通道，使得各電晶體通道在該開口內在相應導電層的暴露側壁之間延伸。
  2. 如請求項1之基板處理方法，其中該形成該第一層堆疊包括沉積複數金屬層以作為該等導電層。
  3. 如請求項2之基板處理方法，其中該沉積該等金屬層包括為該等金屬層各者沉積不同金屬材料。
  4. 如請求項2之基板處理方法，其中該沉積該等金屬層包括為該等金屬層各者沉積相同金屬材料。
  5. 如請求項1之基板處理方法，其中： 該形成該開口包括暴露該基板的半導體表面，以及 該形成該第二層堆疊包括磊晶生長半導體材料的複數犧牲層，半導體材料的該等犧牲層係與該第二層堆疊中的半導體材料的該等通道層交替。
  6. 如請求項5之基板處理方法，其中該形成該第二層堆疊包括磊晶生長SiGe材料的複數犧牲層，SiGe材料的該等犧牲層提供相對於該等通道層的蝕刻選擇性。
  7. 如請求項1之基板處理方法，其中該形成該第二層堆疊包括在與對應導電層相同的平面中形成該等通道層的各者，使得該等通道層的端部係與該對應導電層的側壁對準。
  8. 如請求項1之基板處理方法，其中該形成該第二層堆疊包括藉由在該第二層堆疊中蝕刻出將該第二層堆疊分割成複數第二層堆疊的開口，以在該開口內形成該複數第二層堆疊。
  9. 如請求項1之基板處理方法，其中： 該形成該開口包括在該第一層堆疊中形成複數開口， 該形成該第二層堆疊包括分別在該等開口內形成複數第二層堆疊，以及 從各第二層堆疊的該等通道層形成該等電晶體通道。
  10. 如請求項1之基板處理方法，其中該形成該等電晶體通道包括形成圍繞各通道層的全環繞閘極(GAA)結構。
  11. 如請求項10之基板處理方法，其中該形成該GAA結構包括： 選擇性沉積圍繞著該通道層的高k介電質層；以及 在該高k介電質層上選擇性沉積閘極金屬。
  12. 一種基板處理方法，包括： 在基板上形成第一層堆疊，該第一層堆疊包括在該第一層堆疊中交替的複數金屬層及複數介電質層； 在該第一層堆疊中形成複數開口，並且在該第一層堆疊中未經覆蓋的該等開口中沉積第一半導體層，使該第一半導體層位於該基板上方； 藉由磊晶生長在該第一半導體層上方的該等開口內形成第二層堆疊，該第二層堆疊包括在該第二層堆疊中交替且與該第一層堆疊的對應層對準的複數第二半導體層及複數磊晶層；以及 在與該第一層堆疊的該等金屬層相同的平面中從該第二層堆疊的該等磊晶層形成複數電晶體通道，使得該等電晶體通道在該等金屬層與該等開口內的該等磊晶層之間延伸。
  13. 如請求項12之基板處理方法，更包括： 藉由下列步驟在該第一層堆疊中形成該等開口： 在封蓋層的至少一部分上方沉積第一遮罩層，該封蓋層係沉積在該第一層堆疊的頂部上；以及 執行第一蝕刻，該第一蝕刻將該第一層堆疊未被該第一遮罩層覆蓋的部分進行蝕刻以在該第一層堆疊中形成該等開口，其中該第一層堆疊中的該等開口的長度係等於預定距離。
  14. 如請求項13之基板處理方法，其中該第一遮罩層包括光阻（PR）遮罩層。
  15. 如請求項12之基板處理方法，其中該第一層堆疊中的該等開口包括第一開口及第二開口，且其中該第一開口及該第二開口具有由該基板所形成的基部。
  16. 如請求項15之基板處理方法，更包括： 在該第一開口及該第二開口各者內形成第二層堆疊；以及 在該第一開口及該第二開口內所形成的該第二層堆疊各者上方沉積另一封蓋層。
  17. 如請求項16之基板處理方法，更包括： 在該第二層堆疊的該另一封蓋層上方沉積第二遮罩層，使得該第二遮罩層在該另一封蓋層上方延伸以與該封蓋層的一部份重疊，其中該第二遮罩層的寬度係等於第二預定距離。
  18. 如請求項17之基板處理方法，更包括： 對該第二層堆疊執行第二蝕刻，該第二蝕刻對該第二層堆疊未被該第二遮罩層覆蓋的第一組部分進行蝕刻，以在該第二層堆疊中形成複數開口。
  19. 如請求項18之基板處理方法，其中被覆蓋在該第二遮罩層下方的該第二層堆疊的第二組部分係基於該第二蝕刻而形成第三層堆疊，其中該第三層堆疊的寬度等於該第二預定距離。
  20. 如請求項19之基板處理方法，其中被覆蓋在該第二遮罩層下方的該第二層堆疊、且形成該第三層堆疊的該第二部分組包括該等第二半導體層的一部分及該等磊晶層的一部分。
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