TW202230462A - 磊晶晶圓的製造方法 - Google Patents

磊晶晶圓的製造方法 Download PDF

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Publication number
TW202230462A
TW202230462A TW110145970A TW110145970A TW202230462A TW 202230462 A TW202230462 A TW 202230462A TW 110145970 A TW110145970 A TW 110145970A TW 110145970 A TW110145970 A TW 110145970A TW 202230462 A TW202230462 A TW 202230462A
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Taiwan
Prior art keywords
crystal silicon
oxygen
layer
epitaxial
atomic layer
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TW110145970A
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English (en)
Chinese (zh)
Inventor
鈴木克佳
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日商信越半導體股份有限公司
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Publication of TW202230462A publication Critical patent/TW202230462A/zh

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    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/186Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
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    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/20Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
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    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/22Sandwich processes
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    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
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    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02494Structure
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
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    • H01L21/02521Materials
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
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    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02595Microstructure polycrystalline

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
TW110145970A 2021-01-25 2021-12-09 磊晶晶圓的製造方法 TW202230462A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-009549 2021-01-25
JP2021009549 2021-01-25

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TW202230462A true TW202230462A (zh) 2022-08-01

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TW110145970A TW202230462A (zh) 2021-01-25 2021-12-09 磊晶晶圓的製造方法

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US (1) US20240063027A1 (enExample)
EP (1) EP4283024A4 (enExample)
JP (1) JP7231120B2 (enExample)
KR (1) KR20230132455A (enExample)
CN (1) CN116685723A (enExample)
TW (1) TW202230462A (enExample)
WO (1) WO2022158148A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7435516B2 (ja) * 2021-03-22 2024-02-21 信越半導体株式会社 エピタキシャルウェーハの製造方法
JP2025029932A (ja) * 2023-08-22 2025-03-07 信越半導体株式会社 エピタキシャルウェーハの製造方法
US20250239447A1 (en) * 2024-01-18 2025-07-24 Atomera Incorporated Method for making semiconductor devices including compound semiconductor materials using a superlattice separation layer

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422306A (en) 1991-12-17 1995-06-06 Matsushita Electric Industrial Co., Ltd. Method of forming semiconductor hetero interfaces
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
JP3886085B2 (ja) * 1999-05-14 2007-02-28 株式会社東芝 半導体エピタキシャル基板の製造方法
JP2003197549A (ja) 2002-09-06 2003-07-11 Sumitomo Mitsubishi Silicon Corp エピタキシャルウェーハの製造方法
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
AU2004300982B2 (en) 2003-06-26 2007-10-25 Mears Technologies, Inc. Semiconductor device including MOSFET having band-engineered superlattice
JP5168990B2 (ja) 2007-04-11 2013-03-27 信越半導体株式会社 半導体基板の製造方法
JP5205840B2 (ja) 2007-07-06 2013-06-05 信越半導体株式会社 半導体基板の製造方法
EP2770526B1 (en) * 2013-02-22 2018-10-03 IMEC vzw Oxygen monolayer on a semiconductor
JP6702268B2 (ja) 2017-06-15 2020-05-27 信越半導体株式会社 エピタキシャルウェーハの製造方法
JP7247902B2 (ja) * 2020-01-10 2023-03-29 信越半導体株式会社 エピタキシャルウェーハの製造方法

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US20240063027A1 (en) 2024-02-22
EP4283024A1 (en) 2023-11-29
JPWO2022158148A1 (enExample) 2022-07-28
EP4283024A4 (en) 2024-12-04
JP7231120B2 (ja) 2023-03-01
WO2022158148A1 (ja) 2022-07-28
KR20230132455A (ko) 2023-09-15
CN116685723A (zh) 2023-09-01

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