TW202215501A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one semiconductor element, a front-side source contact and a back-side contact metal layer. The semiconductor substrate has a through substrate hole, and includes a high-resistivity silicon carbide epitaxial layer and a gallium nitride epitaxial layer formed on a second surface of the high-resistivity silicon carbide epitaxial layer. The semiconductor element is formed on the gallium nitride epitaxial layer. The front-side source contact is formed on a surface of the gallium nitride epitaxial layer and covers the through substrate hole of the semiconductor substrate. The back-side contact metal layer is formed in the through substrate hole of the semiconductor substrate and directly contacts the front-side source contact.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Since the film formed by the epitaxy process has the advantages of high purity and good thickness control, it has been widely used in the manufacture of radio frequency (RF) components or power (power) components, in which RF components can be applied For 4G communication, 5G communication, satellite communication or 5G front-end module.

However, in the manufacturing process of radio frequency components, the original substrate thickness is usually thinned from a thickness to a thickness several levels smaller than the original thickness by processes such as grinding or polishing. The difference between the thicknesses of the substrates is too large, so it is easy to cause the variation range of the final substrate thickness to be too large. For example, the substrate thickness is thinned from about 300 μm to about 50 μm, resulting in a variation of the final substrate thickness of about ±20%. As a result, the Through Silicon Via (TSV) process is adversely affected, and problems such as device matching are likely to occur, thereby affecting the yield of RF components.

The present invention provides a semiconductor device and a manufacturing method thereof, which can solve the problems of too large variation range of substrate thickness, and the variation range of RF source impedance (RF source impedance) and RF front-to-backside capacitance (RF front-to-backside capacitance). Small.

The semiconductor device of the present invention includes a semiconductor substrate, at least one semiconductor element, a front-side source contact and a back-side contact metal layer. The semiconductor substrate has a through substrate hole, and the semiconductor substrate includes a high-resistivity silicon carbide epitaxial layer with a first surface and a second surface, and a high-resistivity silicon carbide epitaxial layer formed on the high-resistance A gallium nitride epitaxial layer on the second surface of the silicon carbide epitaxial layer, wherein the first surface is opposite to the second surface. The semiconductor element is formed on the gallium nitride epitaxial layer. The front-side source contact is formed on the surface of the gallium nitride epitaxial layer and covers the substrate through hole of the semiconductor substrate. The back contact metal layer is formed in the substrate through hole of the semiconductor substrate and is in direct contact with the front source contact.

In another embodiment of the present invention, the thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm.

In another embodiment of the present invention, the front-side source contact includes an adhesive layer, a barrier layer, and a high-conductivity layer. The adhesion layer is formed on the surface of the gallium nitride epitaxial layer. The barrier layer is formed on the surface of the adhesive layer. A highly conductive layer is formed on the surface of the barrier layer.

In another embodiment of the present invention, the above-mentioned adhesive layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm. The above-mentioned barrier layer includes Pt, Pd or Mo with a thickness between 2 nm and 200 nm. The above-mentioned highly conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 µm.

In another embodiment of the present invention, the back contact metal layer includes an adhesive layer, a barrier layer and a high conductive layer. The adhesive layer is formed on the surface of the through hole of the substrate. The barrier layer is formed on the surface of the adhesive layer. A highly conductive layer is formed on the surface of the barrier layer.

In another embodiment of the present invention, the above-mentioned adhesive layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm. The above-mentioned barrier layer includes TiW, TiN or TaN with a thickness between 2 nm and 200 nm. The above-mentioned highly conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 µm.

In another embodiment of the present invention, the included angle between the cross section of the sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 45° and 90°.

In another embodiment of the present invention, the angle between the cross section of the sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 85° and 90°.

In another embodiment of the present invention, the above-mentioned through-substrate holes are circular through-substrate holes, and have a diameter of 10 μm˜85 μm.

In another embodiment of the present invention, the above-mentioned through-substrate holes are elliptical through-substrate holes, and the length of the short-axis multiplied by the length of the long-axis of the oval-shaped through-substrate holes is 10 μm × 20 μm to 50 μm × 120 μm .

In another embodiment of the present invention, the depth of the through hole in the substrate is between 10 µm and 200 µm.

In another embodiment of the present invention, the cross-section of the substrate through hole is a stepped profile, a stepped profile plus an inclined profile, a profile with the same slope, or a profile with different slopes.

A method of manufacturing a semiconductor substrate of the present invention includes epitaxially growing a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer on a first surface of an N-type silicon carbide substrate, so as to obtain a high-resistance carbonized epitaxial layer comprising the high-resistance carbonization layer. A semiconductor epitaxial substrate of the silicon epitaxial layer and the gallium nitride epitaxial layer. A front-side source contact is formed on the surface of the gallium nitride epitaxial layer, and at least one semiconductor element is formed on the gallium nitride epitaxial layer. After forming the front-side source contact and at least one semiconductor element, a chip carrier is bonded to the surface of the gallium nitride epitaxial layer. A laser is applied from the second surface of the N-type silicon carbide substrate to form a damaged layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, wherein the second surface is opposite to the first surface of the N-type silicon carbide substrate, and then The N-type silicon carbide substrate and the semiconductor epitaxial substrate are separated from the damaged layer. Using the front-side source contact as an etch stop layer, a substrate through hole is formed by etching from the bottom of the semiconductor epitaxial substrate until part of the front-side source contact is exposed, and then a metallization process is performed to form a substrate through-hole A back-side contact metal.

In an embodiment of the present invention, the step of forming the front-side source contact includes forming an adhesive layer on the surface of the gallium nitride epitaxial layer, then forming a barrier layer on the surface of the adhesive layer, and then forming a barrier layer on the surface of the barrier layer A highly conductive layer is formed.

In an embodiment of the present invention, the step of forming the backside contact metal layer includes forming an adhesive layer on the surface of the substrate through hole, then forming a barrier layer on the surface of the adhesive layer, and then forming a highly conductive layer on the surface of the barrier layer. layer.

In an embodiment of the present invention, the first surface of the N-type silicon carbide substrate has an angle within the range of not more than 0°+/-8° with respect to the (0001) plane.

In an embodiment of the present invention, the thickness variation rate of the high-resistance silicon carbide epitaxial layer is 5%˜10%.

In an embodiment of the present invention, the method for forming the damaged layer includes applying a laser from the second surface of the N-type silicon carbide substrate into the N-type silicon carbide substrate to form the damaged layer in the N-type silicon carbide substrate.

In an embodiment of the present invention, after separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate, the method further includes removing the remaining N-type silicon carbide substrate.

In an embodiment of the present invention, the method for forming the above-mentioned damaged layer includes applying a laser from the second surface of the N-type silicon carbide substrate into the high-resistance silicon carbide epitaxial layer to form the high-resistance silicon carbide epitaxial layer damage layer.

In an embodiment of the present invention, after the backside contact metal layer is formed, the method further includes removing the wafer carrier and performing a die singulation.

Based on the above, the method of the present invention can reduce the variation range of the thickness of the substrate, and can improve the electrical connection between the front and back elements by forming the back contact metal layer in the substrate through hole that exposes part of the front source contact. In order to make components with small fluctuation range of RF source impedance and RF front and back capacitance.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Exemplary embodiments of the present invention will be fully described below with reference to the accompanying drawings, but the present invention may also be embodied in many different forms and should not be construed as limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of various regions, parts and layers may not be drawn to scale. In order to facilitate understanding, the same elements in the following description will be denoted by the same symbols.

1A to 1G are schematic cross-sectional views of the fabrication of a semiconductor device according to a first embodiment of the present invention.

1A, a high-resistance silicon carbide epitaxial layer 104 is epitaxially grown on a first surface 100a of an N-type silicon carbide substrate 100, wherein the thickness of the N-type silicon carbide substrate 100 is, for example, between 300 μm and 725 μm. , the range of the angle of the first surface 100a of the N-type silicon carbide substrate 100 relative to the (0001) plane is, for example, 0°+/-8°, preferably 0°+/-5°, more preferably 0° Within the range of °+/-3°, the optimum is 0°. The N-type silicon carbide substrate 100 has a micropipe density (MPD) of less than 1 ea/cm ² , a basal plane dislocation (BPD) of less than 3000 ea/cm ² and a threading screw dislocation (threading screw dislocation) , TSD) is less than 1000 ea/cm ² . The resistance of the N-type silicon carbide substrate 100 is approximately between 15 mohm-cm and 26 mohm-cm. In this embodiment, the N-type silicon carbide substrate 100 can be reused, thereby greatly reducing the material cost. In this embodiment, the high-resistance silicon carbide epitaxial layer 104 also has a region 102 on the side close to the N-type silicon carbide substrate 100 . The region 102 is, for example, a region with poor quality grown during the epitaxial growth of the high-resistance silicon carbide epitaxial layer 104 . In one embodiment, the region 102 serves as a buffer layer, for example, and can be retained or removed in a subsequent process (as shown in FIG. 1D ). The high-resistance silicon carbide epitaxial layer 104 is, for example, a semiconductor substrate such as semi-insulating silicon carbide (SI-SiC) suitable for radio frequency (RF) devices. The thickness of the high-resistance silicon carbide epitaxial layer 104 can be set between 20 μm and 100 μm, and the thickness variation rate of the high-resistance silicon carbide epitaxial layer 104 is approximately in the range of 5% to 10%. The surface of the high-resistance silicon carbide epitaxial layer 104 has, for example, an angle in the range of 0°+/-8°, an angle in the range of 0°+/-5°, or a range of 0°+/-3° with respect to the (0001) plane The micro-pipe density (MPD) of the high-resistance silicon carbide epitaxial layer 104 can be less than 0.5 ea/cm ² , the basal plane dislocation (BPD) can be less than 10 ea/cm ² , the penetration spiral dislocation (TSD) May be less than 300 ea/cm ² . In this embodiment, the resistance of the high-resistance silicon carbide epitaxial layer 104 is greater than 1E5 ohm-cm, for example.

Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104 to obtain a semiconductor epitaxial layer composed of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 Crystal substrate ES.

After that, a front-side source contact 108 is formed on the surface 106 a of the GaN epitaxial layer 106 . The front-side source contact 108 is formed as a single layer or multiple layers, for example. In this embodiment, the front-side source contact 108 is formed, for example, in a three-layer structure. For example, the steps of forming the front-side source contact 108 include, for example, forming an adhesive layer 108a on the surface 106a of the GaN epitaxial layer 106, then forming a barrier layer 108b on the surface of the adhesive layer 108a, and then forming a barrier layer 108b on the surface of the adhesive layer 108a. A highly conductive layer 108c is formed on the surface of the , but the present invention is not limited thereto. In this embodiment, by forming the adhesive layer 108a, the contact between the front-side source contact 108 and the dielectric layer and the semiconductor device can be improved. By forming the barrier layer 108b, the metals of the highly conductive layer 108c and the adhesion layer 108a can be prevented from mixing with each other. By forming the highly conductive layer 108c, current can be handled with low parasitic loss. The adhesive layer 108a is made of, for example, Ti, TiW, TiN, Ta or TaN with a thickness of 2 nm˜200 nm. The barrier layer 108b is made of, for example, Pt, Pd, or Mo with a thickness between 2 nm and 200 nm. The highly conductive layer 108c is made of, for example, Au, Al, Al-Cu, or Cu with a thickness of 50 nm to 10 µm. In one embodiment, the barrier layer 108b may not be formed between the adhesive layer 108a and the highly conductive layer 108c, which may be adjusted according to design requirements, which is not limited in the present invention.

Then, components such as semiconductor elements are formed in the gallium nitride epitaxial layer 106 ; for the sake of clarity, the components are omitted in FIGS. 1A to 1G .

Next, referring to FIG. 1B , after the front-side source contact 108 and the semiconductor element (not shown) are formed, a chip carrier 114 is bonded to the surface 106 a of the GaN epitaxial layer 106 , wherein the surface of the chip carrier 114 is Materials such as glass or sapphire.

Then, referring to FIG. 1C , a laser 110 is used to form a damaged layer 112 in the N-type silicon carbide substrate 100 . In the present embodiment, the method for forming the damaged layer 112 includes, for example, applying the laser 110 from the second surface 100 b of the N-type silicon carbide substrate 100 into the N-type silicon carbide substrate 100 , so as to be close to the height of the N-type silicon carbide substrate 100 . The damaged layer 112 is formed on the side of the blocking silicon carbide epitaxial layer 104 , wherein the second surface 100 b is opposite to the first surface 100 a of the N-type silicon carbide substrate 100 . By using the laser 110 to form the damaged layer 112, wafer to wafer and within wafer calculation data can be obtained.

1D , the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 112 , and a part of the N-type silicon carbide substrate 100 may remain on the surface of the high-resistance silicon carbide epitaxial layer 104 . Therefore, in one embodiment, the remaining N-type silicon carbide substrate 100 may be retained; in another embodiment, the remaining N-type silicon carbide substrate 100 may be removed, for example, by grinding or the like. In this way, the thickness of the silicon carbide substrate 100 to be ground becomes thinner, so that the variation range of the final substrate thickness becomes smaller.

Since the laser 110 is used to form the damage layer 112 for separation in the N-type silicon carbide substrate 100 after the front-side source contact 108 is formed in the process of the first embodiment, the high-resistance silicon carbide epitaxial layer 104 and the The crystallinity quality of the GaN epitaxial layer 106 . In addition, after the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 112, a sufficient thickness of the N-type silicon carbide substrate 100 can be retained, wherein the so-called sufficient thickness refers to the substrate formed on the N-type silicon carbide substrate 100 that can be supported thereon. The thickness of the film layer and components can withstand the subsequent process. In this way, the separated N-type silicon carbide substrate 100 can be reused, thereby greatly reducing the material cost. In addition, since the thickness of the substrate can be controlled more precisely, the generation of parasitic losses can be greatly reduced.

Next, referring to FIG. 1E , using the front-side source contact 108 as an etch stop layer, a through-substrate hole TSH is etched from the bottom of the semiconductor epitaxial substrate ES (eg, on the side of the region 102 ) until part of the front-side source contact is exposed. Point 108, wherein the angle θ between the cross section TSHa of the sidewall of the through-substrate hole TSH and the surface 106a of the GaN epitaxial layer 106 is, for example, between 45° and 90°, preferably between 85° and 90°. . The depth D of the through-substrate hole TSH is, for example, between 10 µm and 200 µm. The through-substrate holes TSH may be, for example, circular through-substrate holes or elliptical through-substrate holes. In one embodiment, if the through-substrate hole TSH is a circular through-substrate hole, the circular through-substrate hole has a diameter of, for example, 10 μm˜85 μm; in another embodiment, if the through-substrate hole TSH is an elliptical substrate Through holes, the length of the short axis multiplied by the length of the long axis of the oval substrate through hole is, for example, 10 µm × 20 µm to 50 µm × 120 µm. In FIG. 1E , although the cross-sections of the through-substrate holes TSH are drawn as contours with the same slope, in other embodiments, the cross-sections of the through-substrate holes TSH may also be stepped contours, stepped contours plus inclined contours, or different slopes. The contour and other contours will be described in detail later.

Then, referring to FIG. 1F , a metallization process is performed to form a back-side contact metal layer 116 in the through-substrate hole TSH. The back contact metal layer 116 is formed as a single layer or multiple layers, for example. In the present embodiment, the back contact metal layer 116 is formed, for example, in a three-layer structure. For example, the step of forming the backside contact metal layer 116 includes, for example, forming an adhesive layer 116a on the surface of the through-substrate via TSH, then forming a barrier layer 116b on the surface of the adhesive layer 116a, and then forming a barrier layer 116b on the surface of the barrier layer 116b. The conductive layer 116c, but the present invention is not limited thereto. A method of forming the back contact metal layer 116 is, for example, sputtering, electrical planting, or conformal coating. In one embodiment, if a thicker backside contact metal layer 116 is to be formed, electroplating can be used, which can further reduce the manufacturing cost. In this embodiment, by forming the adhesive layer 116a, the contact between the backside contact metal layer 116 and the side and backsides of the semiconductor element and the contact with the front-side source contact 108 can be improved. By forming the barrier layer 116b, the metals in the highly conductive layer 116c and the adhesion layer 116a can be prevented from mixing with each other. By forming the highly conductive layer 116c, current can be handled with low parasitic losses. The adhesive layer 116a is, for example, composed of Ti, TiW, TiN, Ta or TaN with a thickness of 2 nm˜200 nm. The barrier layer 116b is made of, for example, TiW, TiN, or TaN with a thickness between 2 nm and 200 nm. The highly conductive layer 116c is made of, for example, Au, Al, Al-Cu, or Cu with a thickness of 50 nm to 10 µm. In another embodiment, the barrier layer 116b may not be formed between the adhesive layer 116a and the highly conductive layer 116c, which may be adjusted according to design requirements, which is not limited in the present invention.

Then, referring to FIG. 1G , after the backside contact metal layer 116 is formed, the wafer carrier 114 may be removed. In one embodiment, if in the process shown in FIG. 1A , a plurality of semiconductor elements and other components are formed in the gallium nitride epitaxial layer 106 , in FIG. 1G , for example, a singulation process is also included, but the present invention Not limited to this.

In the process of the first embodiment, the backside contact metal layer 116 is formed in the through-substrate hole TSH after part of the front-side source contact 108 is exposed through the substrate hole TSH, so that the front-side source contact 108 can be ensured to be in contact with the backside. The metal layers 116 can be in direct contact, thereby improving the electrical connection between the front and back elements. If applied to RF components, the RF source impedance and the RF front and back capacitances can be further improved, and the variation ranges of the RF source impedance and the RF front and back capacitances can be reduced.

2A to FIG. 2G are schematic cross-sectional views of the fabrication of a semiconductor device according to a second embodiment of the present invention, wherein the same reference numerals as those in the first embodiment are used to denote the same or similar components, and the same or similar components may also be Reference is made to the relevant description of the first embodiment, which will not be repeated.

Referring first to FIG. 2A , a high-resistance silicon carbide epitaxial layer 104 having a region 102 is epitaxially grown on a first surface 100 a of an N-type silicon carbide substrate 100 . Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104 to obtain a semiconductor epitaxial layer composed of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 Crystal substrate ES. A front-side source contact 108 is formed on the surface 106a of the GaN epitaxial layer 106 . After that, components such as semiconductor elements are formed in the gallium nitride epitaxial layer 106 ; for the sake of clarity, the components are omitted in FIGS. 2A to 2G .

Next, referring to FIG. 2B , after the front-side source contact 108 and the semiconductor element (not shown) are formed, a chip carrier 114 is bonded to the surface 106 a of the GaN epitaxial layer 106 .

Then, referring to FIG. 2C , a laser 110 is used to form a damaged layer 200 in the semiconductor epitaxial substrate ES. In this embodiment, the damaged layer 200 is formed, for example, in the high-resistance silicon carbide epitaxial layer 104 and is located on one side of the region 102 opposite to the N-type silicon carbide substrate 100 . The method for forming the damaged layer 200 includes, for example, applying a laser 110 from the second surface 100b of the N-type silicon carbide substrate 100 into the high-resistance silicon carbide epitaxial layer 104 to form the damaged layer 200 in the high-resistance silicon carbide epitaxial layer 104 . By using the laser 110 to form the damaged layer 200, wafer to wafer and within wafer calculation data can be obtained.

After that, referring to FIG. 2D , the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 200 . In this embodiment, since the region 102 and the N-type silicon carbide substrate 100 have been completely removed, processes such as grinding are not required. Compared with the first embodiment, some steps can be further omitted, thereby further reducing the manufacturing cost.

Since the damaged layer 200 is formed in the high-resistance silicon carbide epitaxial layer 104 in the process of the second embodiment, after the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 200 , the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES can remain intact. Silicon carbide substrate 100 . In this way, the separated N-type silicon carbide substrate 100 can be reused, thereby greatly reducing the material cost.

Next, referring to FIG. 2E , using the front source contact 108 as an etch stop layer, a through substrate hole TSH is formed by etching from the bottom of the semiconductor epitaxial substrate ES (eg, on the side of the high-resistance silicon carbide epitaxial layer 104 ) until it is exposed. Part of the front-side source contact 108 is removed.

Then, referring to FIG. 2F , a metallization process is performed to form a back contact metal layer 116 in the through-substrate hole TSH. Then, referring to FIG. 2G , after the backside contact metal layer 116 is formed, the wafer carrier 114 may also be removed. In one embodiment, in the case where the semiconductor element is formed, for example, a singulation process may be performed subsequently, but the present invention is not limited thereto.

In the process of the second embodiment, the backside contact metal layer 116 is formed in the through substrate hole TSH after a part of the front side source contact 108 is exposed through the substrate hole TSH, so that the front side source contact 108 can be ensured to be in contact with the backside. The metal layers 116 can be in direct contact, thereby improving the electrical connection between the front and back elements. If applied to RF components, the RF source impedance and the RF front and back capacitances can be further improved, and the variation ranges of the RF source impedance and the RF front and back capacitances can be reduced.

3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

Referring to FIG. 3A , the semiconductor device 300 of this embodiment includes a semiconductor substrate 310 , at least one semiconductor element (not shown), a front-side source contact 320 , and a back-side contact metal layer 330 .

The semiconductor substrate 310 includes a high-resistance silicon carbide epitaxial layer 314 and a gallium nitride epitaxial layer 316 . In this embodiment, the semiconductor substrate 310 is a semiconductor substrate suitable for radio frequency (RF) components.

The high-resistance silicon carbide epitaxial layer 314 has a first surface 314a and a second surface 314b, wherein the first surface 314a is opposite to the second surface 314b. In this embodiment, the high-resistance silicon carbide epitaxial layer 314 further has a region 312 on the side of the first surface 314a. The region 312 is, for example, a region with poor quality grown during the epitaxial growth of the high-resistance silicon carbide epitaxial layer 314 . In one embodiment, the region 312 is, for example, a buffer layer, and the thickness t1 of the buffer layer may be less than 1.5 μm; in another embodiment, the semiconductor substrate may not have the region 312 . The high-resistance silicon carbide epitaxial layer 314 is, for example, semi-insulating silicon carbide (SI-SiC). In the present embodiment, the thickness t2 of the high-resistance silicon carbide epitaxial layer 314 is, for example, between 20 μm and 50 μm, and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 has 0°+ relative to the (0001) plane. / An angle in the range of -8°, for example in the range of 0°+/-5°, preferably in the range of 0°+/-3°. The micropipe density (MPD) of the high-resistance silicon carbide epitaxial layer 314 is less than 0.5 ea/cm ² , the basal plane dislocation (BPD) is less than 10 ea/cm ² and threading screw dislocation, TSD) is less than 500 ea/cm ² . The resistance of the high-resistance silicon carbide epitaxial layer 314 is greater than 1E5 ohm-cm. The resistance variation rate of the high-resistance silicon carbide epitaxial layer 314 is, for example, less than 50%. The so-called "resistance variation rate" refers to the result of dividing the resistance standard deviation by the average resistance value.

The gallium nitride epitaxial layer 316 is formed on the second surface 314 b of the high-resistance silicon carbide epitaxial layer 314 , and the semiconductor element (not shown) is formed on the gallium nitride epitaxial layer 316 . In this embodiment, the thickness t3 of the gallium nitride epitaxial layer 316 is less than 2 μm, and the structure shown in FIG. 3A can be fabricated by the method shown in the first embodiment or the second embodiment, and the removal height can be increased as required. The step of blocking residual structures other than the silicon carbide epitaxial layer 314 . The obtained gallium nitride epitaxial layer 316 has been tested, and its X-ray diffraction analysis (002) plane has a full width at half maximum (FWHM) of less than 100 arcsec, which proves that the grown epitaxial film is of excellent quality.

In this embodiment, the semiconductor substrate 310 has a through-substrate hole TSH1 , wherein the angle θ1 between the cross-section of the sidewall of the through-substrate hole TSH1 and the surface 316 a of the gallium nitride epitaxial layer 316 is, for example, between 45° and 90°. , preferably between 85° and 90°. For example, as shown in FIG. 3A , the angle θ1 between the cross section of the sidewall of the through-substrate hole TSH1 and the surface 316 a of the gallium nitride epitaxial layer 316 is, for example, 90°. The depth D of the through-substrate hole TSH1 is, for example, between 10 µm and 200 µm. The through substrate hole TSH1 may be, for example, a circular through substrate hole or an oval through substrate hole. In one embodiment, if the through-substrate hole TSH1 is a circular through-substrate hole, the circular through-substrate hole has a diameter of, for example, 10 μm˜85 μm; in another embodiment, if the through-substrate hole TSH1 is an oval substrate Through holes, the length of the short axis multiplied by the length of the long axis of the oval substrate through hole is, for example, 10 µm × 20 µm to 50 µm × 120 µm. In FIG. 3A , the cross-section of the through-substrate hole TSH1 is illustrated as a profile of the same slope.

The front-side source contact 320 is formed on the surface 316 a of the GaN epitaxial layer 316 and covers the through-substrate hole TSH1 of the semiconductor substrate 310 . The front-side source contact 320 includes an adhesive layer 322 , a barrier layer 324 and a high-conductivity layer 326 . The adhesive layer 322 is formed on the surface 316 a of the GaN epitaxial layer 316 . The barrier layer 324 is formed on the surface of the adhesive layer 322 . The highly conductive layer 326 is formed on the surface of the barrier layer 324 . In this embodiment, the adhesive layer 322 is, for example, composed of Ti, TiW, TiN, Ta or TaN with a thickness of 2 nm˜200 nm. The barrier layer 324 is made of, for example, Pt, Pd, or Mo with a thickness between 2 nm and 200 nm. The highly conductive layer 326 is made of, for example, Au, Al, Al-Cu or Cu with a thickness of 50 nm˜10 μm.

The backside contact metal layer 330 is formed in the through-substrate hole TSH1 of the semiconductor substrate 310 and is in direct contact with the frontside source contact 320 . The back contact metal layer 330 includes an adhesive layer 332 , a barrier layer 334 and a high conductive layer 336 . The adhesive layer 332 is formed on the surface of the substrate through hole TSH1, for example. The barrier layer 334 is formed, for example, on the surface of the adhesive layer 332 . The highly conductive layer 336 is formed, for example, on the surface of the barrier layer 334 . In the present embodiment, the adhesive layer 332 is, for example, composed of Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm. The barrier layer 334 is made of, for example, TiW, TiN, or TaN with a thickness between 2 nm and 200 nm. The highly conductive layer 336 is made of, for example, Au, Al, Al-Cu, or Cu with a thickness between 50 nm and 10 µm.

3B is a schematic cross-sectional view of another semiconductor device according to the third embodiment, in which the same or similar components are represented by the same reference numerals as in FIG. 3A , and the same or similar components can also be referred to the related description of FIG. 3A , and no longer Repeat.

In FIG. 3B , the cross-section of the through substrate hole TSH2 is illustrated as a trapezoidal profile. For example, the angle θ2 between the cross-section of the sidewall of the through-substrate hole TSH2 and the surface 316a of the GaN epitaxial layer 316 is, for example, 45°, and the cross-section of the sidewall of the through-substrate hole TSH2 has the same slope.

3C is a schematic cross-sectional view of another semiconductor device according to the third embodiment, in which the same or similar components are represented by the same reference numerals as in FIG. 3A , and the same or similar components can also be referred to the relevant description of FIG. 3A , and no longer Repeat.

In FIG. 3C, the cross-section of the through substrate hole TSH3 is illustrated as a stepped profile. For example, the angle θ3 between the cross section of the sidewall of the through substrate hole TSH3 in the GaN epitaxial layer 316 and the surface 316a of the GaN epitaxial layer 316 is, for example, 90°; The angle θ3 ′ between the cross section of the sidewall of the through substrate hole TSH3 in the layer 314 and the second surface 314 b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 90°. The maximum width L1 of the cross-section of the through-substrate hole TSH3 in the gallium nitride epitaxial layer 316 is, for example, smaller than the maximum width L2 of the cross-section of the through-substrate hole TSH3 in the high-resistance silicon carbide epitaxial layer 314 .

3D is a schematic cross-sectional view of another semiconductor device according to the third embodiment, in which the same or similar components are represented by the same reference numerals as in FIG. 3A , and the same or similar components can also be referred to the relevant description of FIG. 3A , and no longer Repeat.

In FIG. 3D, the cross-section of the through substrate hole TSH4 is illustrated as a stepped profile plus a sloped profile. For example, the angle θ4 between the cross section of the sidewall of the through-substrate hole TSH4 located in the GaN epitaxial layer 316 and the surface 316a of the GaN epitaxial layer 316 is, for example, 60°; The angle θ4 ′ between the cross section of the sidewall of the through substrate hole TSH4 in the layer 314 and the second surface 314 b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 60°. The maximum width L3 of the cross-section of the through-substrate hole TSH4 in the gallium nitride epitaxial layer 316 is, for example, smaller than the maximum width L4 of the cross-section of the through-substrate hole TSH4 in the high-resistance silicon carbide epitaxial layer 314 .

3E is a schematic cross-sectional view of another semiconductor device according to the third embodiment, in which the same or similar components are represented by the same reference numerals as in FIG. 3A , and the same or similar components can also be referred to the related description of FIG. 3A , and no longer Repeat.

In FIG. 3E , the cross-sections of the through substrate holes TSH5 are illustrated as profiles with different slopes. For example, the angle θ5 between the cross section of the sidewall of the through substrate hole TSH5 in the GaN epitaxial layer 316 and the surface 316a of the GaN epitaxial layer 316 is, for example, 45°; The included angle θ5 ′ between the cross section of the sidewall of the through-substrate hole TSH5 in the layer 314 and the second surface 314 b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 60°. The maximum width L5 of the cross-section of the through-substrate hole TSH5 in the GaN epitaxial layer 316 is, for example, smaller than the maximum width L6 of the cross-section of the through-substrate hole TSH5 in the high-resistance silicon carbide epitaxial layer 314 .

To sum up, by forming the damaged layer in the N-type silicon carbide substrate or the high-resistance silicon carbide epitaxial layer in the present invention, not only can the gallium nitride with good crystallinity quality be grown, but also due to the existence of the damaged layer, a large amount of gallium nitride can be retained. Part of the N-type silicon carbide substrate can be reused, thereby reducing the cost of the substrate. In addition, the present invention can improve the electrical connection between the front and back elements, and also improve the RF source impedance and RF front and back capacitance, and make the variation range of RF source impedance and RF front and back capacitance smaller.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100:N-type silicon carbide substrate 100a, 314a: first surface 100b, 314b: second surface 102, 312: Area 104, 314: High resistance silicon carbide epitaxial layer 106, 316: GaN epitaxial layer 106a, 316a: Surface 108, 320: front source contact 108a, 116a, 322, 332: Adhesive layer 108b, 116b, 324, 334: barrier layers 108c, 116c, 326, 336: Highly conductive layers 110: Laser 112, 200: Damage layer 114: Wafer Carrier 116, 330: backside contact metal layer 300: Semiconductor Devices 310: Semiconductor substrate D: depth ES: Semiconductor epitaxial substrate L1～L6: Maximum width t1, t2, t3: thickness TSH, TSH1 to TSH5: through-substrate vias TSHa: Section θ, θ1～θ5, θ3’～θ5’: included angle

1A to 1G are schematic cross-sectional views of the fabrication of a semiconductor device according to a first embodiment of the present invention. 2A to 2G are schematic cross-sectional views illustrating the fabrication of a semiconductor device according to a second embodiment of the present invention. 3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. 3B is a schematic cross-sectional view of another semiconductor device according to the third embodiment. 3C is a schematic cross-sectional view of still another semiconductor device according to the third embodiment. 3D is a schematic cross-sectional view of still another semiconductor device according to the third embodiment. 3E is a schematic cross-sectional view of still another semiconductor device according to the third embodiment.

102: Area

104: High resistance silicon carbide epitaxial layer

106: GaN epitaxial layer

106a: Surface

108: Front source contact

108a, 116a: Adhesive layer

108b, 116b: barrier layer

108c, 116c: high conductive layer

116: backside contact metal layer

ES: Semiconductor epitaxial substrate

TSH: Through Substrate Via

θ: included angle

Claims (21)

A semiconductor device, comprising: A semiconductor substrate having a through substrate hole, the semiconductor substrate comprising: a high-resistivity silicon carbide epitaxial layer, having a first surface and a second surface, the first surface being opposite to the second surface; and a gallium nitride epitaxial layer formed on the second surface of the high-resistance silicon carbide epitaxial layer; at least one semiconductor element formed on the gallium nitride epitaxial layer; a front-side source contact formed on the surface of the GaN epitaxial layer and covering the through-substrate hole of the semiconductor substrate; and A back contact metal layer is formed in the substrate through hole of the semiconductor substrate and is in direct contact with the front source contact. The semiconductor device according to claim 1, wherein the thickness of the high-resistance silicon carbide epitaxial layer is between 20 µm and 50 µm. The semiconductor device of claim 1, wherein the front-side source contact comprises: an adhesive layer formed on the surface of the gallium nitride epitaxial layer; a barrier layer formed on the surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer. The semiconductor device according to claim 3, wherein the adhesive layer comprises Ti, TiW, TiN, Ta or TaN with a thickness of 2 nm to 200 nm; the barrier layer comprises a thickness of 2 nm to 200 nm of Pt, Pd or Mo; the highly conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 µm. The semiconductor device of claim 1, wherein the backside contact metal layer comprises: an adhesive layer formed on the surface of the through hole of the substrate; a barrier layer formed on the surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer. The semiconductor device of claim 5, wherein the adhesive layer comprises Ti, TiW, TiN, Ta or TaN with a thickness of 2 nm to 200 nm; the barrier layer comprises a thickness of 2 nm to 200 nm of TiW, TiN or TaN; the highly conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 µm. The semiconductor device according to claim 1, wherein the included angle between the cross section of the sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 45° and 90°. The semiconductor device according to claim 7, wherein the included angle between the cross section of the sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 85° and 90°. The semiconductor device of claim 1, wherein the through-substrate vias are circular through-substrate vias and have a diameter of 10 µm to 85 µm. The semiconductor device of claim 1, wherein the through-substrate hole is an elliptical through-substrate hole, and the length of the short axis multiplied by the length of the long axis of the elliptical through-substrate hole is 10 µm × 20 µm to 50 µm × 120 µm. The semiconductor device according to claim 1, wherein the depth of the substrate through hole is between 10 µm and 200 µm. The semiconductor device of claim 1, wherein the cross-section of the through-substrate via is a stepped profile, a stepped profile plus an inclined profile, a profile with the same slope, or a profile with different slopes. A method of manufacturing a semiconductor device, comprising: A high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer are epitaxially grown on the first surface of an N-type silicon carbide substrate to obtain the high-resistance silicon carbide epitaxial layer and the gallium nitride epitaxial layer a semiconductor epitaxial substrate of the crystal layer; forming a front-side source contact on the surface of the gallium nitride epitaxial layer; forming at least one semiconductor element on the gallium nitride epitaxial layer; bonding a chip carrier to the surface of the gallium nitride epitaxial layer after forming the front-side source contact and the at least one semiconductor element; A laser is applied from the second surface of the N-type silicon carbide substrate to form a damaged layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, wherein the second surface is opposite to the N-type silicon carbide substrate the first surface of the silicon substrate; separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate from the damaged layer; Using the front-side source contact as an etch stop layer, etching a substrate through hole from the bottom of the semiconductor epitaxial substrate until a part of the front-side source contact is exposed; and A metallization process is performed to form a back-side contact metal layer in the substrate through hole. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the front-side source contact comprises: forming an adhesive layer on the surface of the gallium nitride epitaxial layer; forming a barrier layer on the surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer. The method for manufacturing a semiconductor device according to claim 13, wherein the step of forming the backside contact metal layer comprises: forming an adhesive layer on the surface of the substrate through hole; forming a barrier layer on the surface of the adhesive layer; and A highly conductive layer is formed on the surface of the barrier layer. The method for manufacturing a semiconductor device according to claim 13, wherein the first surface of the N-type silicon carbide substrate has an angle within a range of not more than 0°+/-8° with respect to the (0001) plane. The method for manufacturing a semiconductor device according to claim 13, wherein the thickness variation rate of the high-resistance silicon carbide epitaxial layer is 5% to 10%. The method of manufacturing a semiconductor device according to claim 13, wherein the method of forming the damaged layer comprises: applying the laser to the N-type silicon carbide substrate from the second surface of the N-type silicon carbide substrate to form the damaged layer in the N-type silicon carbide substrate. The method for manufacturing a semiconductor device according to claim 18, wherein after separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate, further comprising: removing the remaining N-type silicon carbide substrate. The method for manufacturing a semiconductor device according to claim 13, wherein the method for forming the damaged layer comprises: applying the laser from the second surface of the N-type silicon carbide substrate to the high-resistance silicon carbide epitaxy The damaged layer is formed in the high-resistance silicon carbide epitaxial layer. The method for manufacturing a semiconductor device according to claim 13, wherein after forming the back contact metal layer, the method further comprises: removing the wafer carrier; and performing a singulation process.

Images