TWI821604B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one semiconductor element, a front-side source contact and a back-side contact metal layer. The semiconductor substrate has a through substrate hole, and includes a high-resistivity silicon carbide epitaxial layer and a gallium nitride epitaxial layer formed on a second surface of the high-resistivity silicon carbide epitaxial layer. The semiconductor element is formed on the gallium nitride epitaxial layer. The front-side source contact is formed on a surface of the gallium nitride epitaxial layer and covers the through substrate hole of the semiconductor substrate. The back-side contact metal layer is formed in the through substrate hole of the semiconductor substrate and directly contacts the front-side source contact.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor manufacturing technology, and in particular, to a semiconductor device and a manufacturing method thereof.

Since the film layer formed by the epitaxy process has the advantages of high purity and good thickness control, it has been widely used in the manufacturing of radio frequency (RF) components or power (power) components, among which RF components can be used In 4G communications, 5G communications, satellite communications or 5G front-end modules.

However, in the manufacturing process of radio frequency components, the original substrate thickness is usually thinned from one thickness to a thickness several levels smaller than the original thickness through processes such as grinding or polishing. The difference in substrate thickness is too large, which easily leads to an excessive range of variation in the final substrate thickness. For example, the substrate thickness is thinned from about 300 μm to about 50 μm, so that the final substrate thickness varies within a range of about ±20%. As a result, it will have a negative impact on the through silicon via (TSV) process and easily cause problems such as device matching, thus affecting the yield of radio frequency components.

The present invention provides a semiconductor device and a manufacturing method thereof, which can solve the problem that the variation range of substrate thickness is too large, and the variation range of RF source impedance (RF source impedance) and RF front-to-backside capacitance (RF front-to-backside capacitance) Small.

The semiconductor device of the present invention includes a semiconductor substrate, at least one semiconductor element, a front source contact and a back contact metal layer. The semiconductor substrate has a through substrate hole, and the semiconductor substrate includes a high-resistivity silicon carbide epitaxial layer having a first surface and a second surface and a high-resistivity silicon carbide epitaxial layer formed on the and a gallium nitride epitaxial layer on a second surface of the silicon carbide epitaxial layer, wherein the first surface is opposite the second surface. Semiconductor elements are formed in gallium nitride epitaxial layers. The front source contact is formed on the surface of the gallium nitride epitaxial layer and covers the substrate through hole of the semiconductor substrate. The back contact metal layer is formed in the substrate through hole of the semiconductor substrate and is in direct contact with the front source contact.

In another embodiment of the present invention, the thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm.

In another embodiment of the invention, the front source contact includes an adhesive layer, a barrier layer and a highly conductive layer. An adhesion layer is formed on the surface of the gallium nitride epitaxial layer. The barrier layer is formed on the surface of the adhesive layer. A highly conductive layer is formed on the surface of the barrier layer.

In another embodiment of the present invention, the above-mentioned adhesive layer includes a thickness of 2 Ti, TiW, TiN, Ta or TaN between nm~200nm. The above-mentioned barrier layer includes Pt, Pd or Mo with a thickness between 2nm and 200nm. The above-mentioned high conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm.

In another embodiment of the present invention, the back contact metal layer includes an adhesive layer, a barrier layer and a highly conductive layer. An adhesive layer is formed on the surface of the substrate through hole. The barrier layer is formed on the surface of the adhesive layer. A highly conductive layer is formed on the surface of the barrier layer.

In another embodiment of the present invention, the above-mentioned adhesive layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm. The above-mentioned barrier layer includes TiW, TiN or TaN with a thickness between 2nm and 200nm. The above-mentioned high conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm.

In another embodiment of the present invention, the angle between the cross section of the side wall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 45° and 90°.

In another embodiment of the present invention, the angle between the cross section of the side wall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 85° and 90°.

In another embodiment of the present invention, the above-mentioned substrate through hole is a circular substrate through hole and has a diameter of 10 μm ~ 85 μm.

In another embodiment of the present invention, the above-mentioned substrate through hole is an elliptical substrate through hole, and the minor axis length multiplied by the major axis length of the elliptical substrate through hole is 10 μm×20 μm to 50 μm×120 μm.

In another embodiment of the present invention, the depth of the substrate through hole is between 10 μm and 200 μm.

In another embodiment of the present invention, the cross-section of the above-mentioned substrate through hole is a step formula profile, stepped profile plus sloping profile, profile with the same slope or profile with different slopes.

A method for manufacturing a semiconductor device of the present invention includes epitaxially growing a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer on a first surface of an N-type silicon carbide substrate to obtain the high-resistance carbonized epitaxial layer. A semiconductor epitaxial substrate including a silicon epitaxial layer and the gallium nitride epitaxial layer. A front-side source contact is formed on the surface of the gallium nitride epitaxial layer, and at least one semiconductor element is formed on the gallium nitride epitaxial layer. After forming the front source contact and at least one semiconductor component, a wafer carrier is bonded to the surface of the gallium nitride epitaxial layer. Apply a laser from the second surface of the N-type silicon carbide substrate to form a damage layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, wherein the second surface is relative to the first surface of the N-type silicon carbide substrate, and then The N-type silicon carbide substrate and the semiconductor epitaxial substrate are separated from the damaged layer. Using the front source contact as the etching stop layer, a substrate through hole is etched from the bottom of the semiconductor epitaxial substrate until part of the front source contact is exposed, and then a metallization process is performed to form a substrate through hole in the substrate through hole. A back-side contact metal layer.

In one embodiment of the present invention, the step of forming the front source contact includes forming an adhesive layer on the surface of the gallium nitride epitaxial layer, then forming a barrier layer on the surface of the adhesive layer, and then forming a barrier layer on the surface of the barrier layer. Form a highly conductive layer.

In one embodiment of the present invention, the step of forming the back contact metal layer includes forming an adhesive layer on the surface of the substrate through hole, then forming a barrier layer on the surface of the adhesive layer, and then forming a highly conductive layer on the surface of the barrier layer. layer.

In an embodiment of the present invention, the first surface of the N-type silicon carbide substrate The face has an angle within the range of no more than 0° +/-8° relative to the (0001) face.

In an embodiment of the present invention, the thickness variation rate of the high-resistance silicon carbide epitaxial layer is between 5% and 10%.

In one embodiment of the present invention, the method of forming the damage layer includes applying a laser from the second surface of the N-type silicon carbide substrate into the N-type silicon carbide substrate to form a damage layer in the N-type silicon carbide substrate.

In an embodiment of the present invention, after separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate, the method further includes removing the remaining N-type silicon carbide substrate.

In one embodiment of the present invention, the method of forming the above-mentioned damage layer includes applying a laser from the second surface of the N-type silicon carbide substrate into the high-resistance silicon carbide epitaxial layer to form the high-resistance silicon carbide epitaxial layer. damage layer.

In an embodiment of the present invention, after forming the back contact metal layer, the method further includes removing the wafer carrier and performing a die singulation process.

Based on the above, the method of the present invention can reduce the variation range of the substrate thickness, and can improve the electrical connection between the front and back components by forming a back contact metal layer in the substrate through hole that exposes part of the front source contact. In order to produce components with a small variation range of RF source impedance and RF front and back capacitance.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100:N-type silicon carbide substrate

100a, 314a: first surface

100b, 314b: Second surface

102, 312: Area

104, 314: High resistance silicon carbide epitaxial layer

106, 316: Gallium nitride epitaxial layer

106a, 316a: surface

108, 320: Front source contact

108a, 116a, 322, 332: Adhesion layer

108b, 116b, 324, 334: barrier layer

108c, 116c, 326, 336: Highly conductive layer

110:Laser

112, 200: Damage layer

114:Chip carrier

116, 330: Back contact metal layer

300:Semiconductor device

310:Semiconductor substrate

D: Depth

ES: Semiconductor epitaxial substrate

L1~L6: maximum width

t1, t2, t3: thickness

TSH, TSH1~TSH5: substrate through holes

TSHa: cross section

θ, θ1~θ5, θ3’~θ5’: included angle

1A to 1G are schematic cross-sectional views of a semiconductor device according to the first embodiment of the present invention.

2A to 2G are schematic cross-sectional views of a semiconductor device according to a second embodiment of the present invention.

FIG. 3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 3B is a schematic cross-sectional view of another semiconductor device according to the third embodiment.

FIG. 3C is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment.

FIG. 3D is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment.

3E is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment.

Exemplary embodiments of the present invention will be fully described below with reference to the accompanying drawings, although the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the sizes and thicknesses of various regions, locations and layers are not drawn to actual scale for clarity. To facilitate understanding, the same components in the following description will be labeled with the same symbols.

1A to 1G are schematic cross-sectional views of a semiconductor device according to the first embodiment of the present invention.

Please refer to FIG. 1A. A high-resistance silicon carbide epitaxial layer 104 is epitaxially grown on the first surface 100a of an N-type silicon carbide substrate 100. The thickness of the N-type silicon carbide substrate 100 is, for example, between 300 μm and 725 μm. N The angle range of the first surface 100a of the silicon carbide substrate 100 relative to the (0001) plane is, for example, 0°+/-8°, preferably 0°+/-5°, and more preferably 0°+ Within the range of /-3°, the best is 0°. The N-type silicon carbide substrate 100 has a micropipe density (MPD) less than 1ea/cm ² , a basal plane dislocation (BPD) less than 3000ea/cm ² , and a threading screw dislocation (TSD). ) is less than 1000ea/cm ² . The resistance value of the N-type silicon carbide substrate 100 is approximately between 15mohm-cm and 26mohm-cm. In this embodiment, the N-type silicon carbide substrate 100 can be reused, thereby significantly reducing material costs. In this embodiment, the high-resistance silicon carbide epitaxial layer 104 also has a region 102 on the side close to the N-type silicon carbide substrate 100 . The region 102 is, for example, a region of poor quality grown during the epitaxial growth of the high-resistance silicon carbide epitaxial layer 104 . In one embodiment, the region 102 serves as a buffer layer, for example, and can be retained or removed in subsequent processes (as shown in FIG. 1D ). The high-resistance silicon carbide epitaxial layer 104 is, for example, a semiconductor substrate suitable for radio frequency (RF) components such as semi-insulating silicon carbide (SI-SiC). The thickness of the high-resistance silicon carbide epitaxial layer 104 can be set between 20 μm and 100 μm, and the thickness variation rate of the high-resistance silicon epitaxial carbide layer 104 is approximately within the range of 5% to 10%. The surface of the high-resistance silicon carbide epitaxial layer 104 has, for example, an angle in the range of 0°+/-8°, an angle in the range of 0°+/-5°, or a range of 0°+/-3° relative to the (0001) plane. At an internal angle, the microtube density (MPD) of the high-resistance carbonized silicon epitaxial layer 104 can be less than 0.5ea/cm ² , the base plane dislocation (BPD) can be less than 10ea/cm ² , and the through-type spiral disarrangement (TSD) can be Less than 300ea/cm ² . In this embodiment, the resistance value of the high-resistance silicon carbide epitaxial layer 104 is, for example, greater than 1E5 ohm-cm.

Then, gallium nitride epitaxial growth is performed on the high-resistance silicon carbide epitaxial layer 104. The semiconductor epitaxial substrate ES composed of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 is obtained.

Afterwards, a front-side source contact 108 is formed on the surface 106a of the gallium nitride epitaxial layer 106. The front source contact 108 is formed in a single layer or multiple layers, for example. In this embodiment, the front source contact 108 is formed in a three-layer structure, for example. For example, the step of forming the front source contact 108 includes forming an adhesive layer 108a on the surface 106a of the gallium nitride epitaxial layer 106, then forming a barrier layer 108b on the surface of the adhesive layer 108a, and then forming a barrier layer 108b on the barrier layer 108b. A highly conductive layer 108c is formed on the surface, but the invention is not limited thereto. In this embodiment, by forming the adhesion layer 108a, the contact between the front source contact 108 and the dielectric layer and the semiconductor device can be improved. By forming the barrier layer 108b, the metals of the highly conductive layer 108c and the adhesive layer 108a can be prevented from mixing with each other. By forming the highly conductive layer 108c, current can be handled with low parasitic loss. The adhesive layer 108a is composed of Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm, for example. The barrier layer 108b is composed of, for example, Pt, Pd or Mo with a thickness between 2 nm and 200 nm. The high conductive layer 108c is composed of Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm, for example. In one embodiment, the barrier layer 108b does not need to be formed between the adhesive layer 108a and the highly conductive layer 108c, and can be adjusted according to design requirements, which is not limited in the present invention.

Then, components such as semiconductor elements are formed in the gallium nitride epitaxial layer 106; for clarity, the components are omitted in FIGS. 1A to 1G.

Next, referring to FIG. 1B , the front source contact 108 and the semiconductor After the device (not shown) is installed, a wafer carrier 114 is bonded to the surface 106a of the gallium nitride epitaxial layer 106, where the material of the wafer carrier 114 is, for example, glass or sapphire.

Then, referring to FIG. 1C , a laser 110 is used to form a damage layer 112 in the N-type silicon carbide substrate 100 . In this embodiment, the method of forming the damage layer 112 includes, for example, applying the laser 110 from the second surface 100 b of the N-type silicon carbide substrate 100 into the N-type silicon carbide substrate 100 to close to the high A damage layer 112 is formed on the side of the carbon-resistant silicon epitaxial layer 104 , where the second surface 100 b is opposite to the first surface 100 a of the N-type silicon carbide substrate 100 . By using the laser 110 to form the damage layer 112, wafer to wafer and within wafer calculation data can be obtained.

1D, the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damage layer 112, and part of the N-type silicon carbide substrate 100 may remain on the surface of the high-resistance silicon carbide epitaxial layer 104. Therefore, in one embodiment, the remaining N-type silicon carbide substrate 100 can be retained; in another embodiment, the remaining N-type silicon carbide substrate 100 can be removed, for example, by grinding. In this way, the thickness of the silicon carbide substrate 100 to be ground becomes thinner, so that the variation range of the final substrate thickness becomes smaller.

Since the process of the first embodiment uses the laser 110 to form the damage layer 112 for separation in the N-type silicon carbide substrate 100 after the front source contact 108 is formed, it is possible to ensure that the high-resistance silicon carbide epitaxial layer 104 and The crystalline quality of the gallium nitride epitaxial layer 106 . In addition, after the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 112, a sufficient thickness of the N-type silicon carbide substrate can still be retained. 100, where the so-called sufficient thickness refers to the thickness that can bear the film layers and components formed on it and withstand subsequent processes. In this way, the separated N-type silicon carbide substrate 100 can be reused, thereby significantly reducing material costs. In addition, since the substrate thickness can be controlled more accurately, the occurrence of parasitic losses can be significantly reduced.

Next, please refer to FIG. 1E , using the front source contact 108 as an etching stop layer, a substrate through hole TSH is etched from the bottom of the semiconductor epitaxial substrate ES (for example, located on the area 102 side) until part of the front source contact is exposed. Point 108, where the angle θ between the cross section TSHa of the sidewall of the substrate through hole TSH and the surface 106a of the gallium nitride epitaxial layer 106 is, for example, between 45° and 90°, preferably between 85° and 90°. . The depth D of the substrate through hole TSH is, for example, between 10 μm and 200 μm. The substrate through hole TSH may be, for example, a circular substrate through hole or an elliptical substrate through hole. In one embodiment, if the substrate through hole TSH is a circular substrate through hole, the circular substrate through hole has a diameter of, for example, 10 μm ~ 85 μm; in another embodiment, if the substrate through hole TSH is an elliptical substrate through hole , then the short axis length multiplied by the long axis length of the elliptical substrate through hole is, for example, 10 μm × 20 μm to 50 μm × 120 μm. In FIG. 1E , although the cross-section of the substrate through-hole TSH is drawn as a profile with the same slope, in other embodiments, the cross-section of the substrate through-hole TSH can also be a stepped profile, a stepped profile plus an inclined profile, or different slopes. The contours and other contours will be explained in detail later.

Then, referring to FIG. 1F, a metallization process is performed to form a back-side contact metal layer 116 in the substrate through hole TSH. The back contact metal layer 116 is formed as a single layer or multiple layers, for example. In this embodiment, the back contact metal layer 116 is formed into a three-layer structure, for example. For example, forming a back contact metal The steps of layer 116 include, for example, forming an adhesive layer 116a on the surface of the substrate through hole TSH, then forming a barrier layer 116b on the surface of the adhesive layer 116a, and then forming a highly conductive layer 116c on the surface of the barrier layer 116b. However, the present invention does not Limited to this. Methods for forming the back contact metal layer 116 include sputtering, electrical planting, conformal coating, etc. In one embodiment, electroplating can be used to form a thicker back contact metal layer 116, which can further reduce manufacturing costs. In this embodiment, by forming the adhesion layer 116a, the contact between the back contact metal layer 116 and the side and back surfaces of the semiconductor device, and the contact with the front source contact 108 can be improved. By forming the barrier layer 116b, the highly conductive layer 116c and the metal in the adhesive layer 116a can be prevented from mixing with each other. By forming the highly conductive layer 116c, current can be handled with low parasitic losses. The adhesive layer 116a is composed of Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm, for example. The barrier layer 116b is composed of, for example, TiW, TiN or TaN with a thickness between 2 nm and 200 nm. The high conductive layer 116c is composed of Au, Al, Al-Cu or Cu with a thickness of 50 nm to 10 μm, for example. In another embodiment, the barrier layer 116b may not be formed between the adhesive layer 116a and the highly conductive layer 116c. The barrier layer 116b may be adjusted according to the design requirements and is not limited in the present invention.

Afterwards, referring to FIG. 1G , after the back contact metal layer 116 is formed, the wafer carrier 114 can also be removed. In one embodiment, if a plurality of semiconductor elements and other components are formed in the gallium nitride epitaxial layer 106 in the process shown in FIG. 1A , then a singulation process is also included in FIG. 1G , but the present invention Not limited to this.

Since the process of the first embodiment is to expose part of the through hole TSH on the substrate, After the surface source contact 108, the back contact metal layer 116 is formed in the substrate through hole TSH, so it can ensure direct contact between the front source contact 108 and the back contact metal layer 116, thereby improving the relationship between the front and back components. electrical connection. If applied to RF components, the RF source impedance and RF front and back capacitances can be further improved, and the variation ranges of the RF source impedance and RF front and back capacitances can be narrowed.

2A to 2G are schematic cross-sectional views of a semiconductor device according to a second embodiment of the present invention, in which the same element symbols as in the first embodiment are used to represent the same or similar components, and the same or similar components can also be Reference is made to the relevant description of the first embodiment, which will not be described again.

Please refer to FIG. 2A. A high-resistance silicon carbide epitaxial layer 104 having a region 102 is epitaxially grown on the first surface 100a of an N-type silicon carbide substrate 100. Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104 to obtain a semiconductor epitaxial layer composed of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 . Crystal substrate ES. A front source contact 108 is formed on the surface 106a of the gallium nitride epitaxial layer 106. Afterwards, components such as semiconductor elements are formed in the gallium nitride epitaxial layer 106; for clarity, the components are omitted in FIGS. 2A to 2G.

Next, referring to FIG. 2B , after forming the front source contact 108 and the semiconductor device (not shown), a chip carrier 114 is bonded to the surface 106 a of the gallium nitride epitaxial layer 106 .

Then, please refer to FIG. 2C , using the laser 110 to form a damage layer 200 in the semiconductor epitaxial substrate ES. In this embodiment, the damage layer 200 is formed, for example, in the high-resistance silicon carbide epitaxial layer 104 and is located in an area relative to the N-type silicon carbide substrate 100 102 side. The method of forming the damage layer 200 includes, for example, applying the laser 110 from the second surface 100b of the N-type silicon carbide substrate 100 into the high-resistance silicon carbide epitaxial layer 104 to form the damage layer 200 in the high-resistance silicon carbide epitaxial layer 104 . By using the laser 110 to form the damage layer 200, wafer to wafer and within wafer calculation data can be obtained.

Afterwards, referring to FIG. 2D , the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 200 . In this embodiment, since the region 102 and the N-type silicon carbide substrate 100 have been completely removed, there is no need to perform processes such as grinding. Compared with the first embodiment, some steps can be further omitted, thereby further reducing the manufacturing cost.

Since the damage layer 200 is formed in the high-resistance silicon carbide epitaxial layer 104 during the process of the second embodiment, after the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damage layer 200, the complete N-type can be retained. Silicon carbide substrate 100. In this way, the separated N-type silicon carbide substrate 100 can be reused, thereby significantly reducing material costs.

Next, please refer to FIG. 2E , using the front source contact 108 as the etching stop layer, a substrate through hole TSH is etched from the bottom of the semiconductor epitaxial substrate ES (for example, on the side of the high-resistance silicon carbide epitaxial layer 104 ) until it is exposed. Out part of the front source contact 108.

Then, referring to FIG. 2F, a metallization process is performed to form a back contact metal layer 116 in the substrate through hole TSH. Afterwards, referring to FIG. 2G , after the back contact metal layer 116 is formed, the wafer carrier 114 can also be removed. In one embodiment, when a semiconductor element is formed, a singulation process may be performed subsequently, but the invention is not limited thereto.

Since the process of the second embodiment is to form the back contact metal layer 116 in the substrate through hole TSH after the substrate through hole TSH exposes part of the front source contact 108, it can ensure that the front source contact 108 is in contact with the back surface The metal layers 116 can be in direct contact, thereby improving the electrical connection between the front and back components. If applied to RF components, the RF source impedance and RF front and back capacitances can be further improved, and the variation ranges of the RF source impedance and RF front and back capacitances can be narrowed.

FIG. 3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

Referring to FIG. 3A , the semiconductor device 300 of this embodiment includes a semiconductor substrate 310, at least one semiconductor element (not shown), a front source contact 320, and a back contact metal layer 330.

The semiconductor substrate 310 includes a high-resistance silicon carbide epitaxial layer 314 and a gallium nitride epitaxial layer 316 . In this embodiment, the semiconductor substrate 310 is a semiconductor substrate suitable for radio frequency (RF) components.

The high-resistance silicon carbide epitaxial layer 314 has a first surface 314a and a second surface 314b, where the first surface 314a is opposite to the second surface 314b. In this embodiment, the high-resistance silicon carbide epitaxial layer 314 also has a region 312 on the first surface 314a side. The region 312 is, for example, a region of poor quality grown during the epitaxial growth of the high-resistance silicon carbide epitaxial layer 314 . In one embodiment, the region 312 is, for example, a buffer layer, and the thickness t1 of the buffer layer may be less than 1.5 μm; in another embodiment, the semiconductor substrate may not have the region 312 . The high-resistance silicon carbide epitaxial layer 314 is, for example, semi-insulating silicon carbide (SI-SiC). In this embodiment, the thickness t2 of the high-resistance silicon epitaxial carbide layer 314 is, for example, between 20 μm and 50 μm. The second surface 314b of the high-resistance silicon epitaxial carbide layer 314 has an angle of 0°+/ relative to the (0001) surface. The angle is within the range of -8°, for example, within the range of 0°+/-5°, preferably within the range of 0°+/-3°. The micropipe density (MPD) of the high-resistance carbonized silicon epitaxial layer 314 is less than 0.5ea/cm ² , the basal plane dislocation (BPD) is less than 10ea/cm ² and the threading screw is dislocation (TSD) is less than 500ea/cm ² . The resistance value of the high-resistance silicon carbide epitaxial layer 314 is greater than 1E5 ohm-cm. The resistance variation rate of the high-resistance silicon carbide epitaxial layer 314 is, for example, less than 50%. The so-called "resistance variation rate" refers to the result of dividing the standard deviation of the resistance by the average resistance value.

The gallium nitride epitaxial layer 316 is formed on the second surface 314b of the high-resistance silicon carbide epitaxial layer 314, and a semiconductor device (not shown) is formed on the gallium nitride epitaxial layer 316. In this embodiment, the thickness t3 of the gallium nitride epitaxial layer 316 is less than 2 μm, and the structure of FIG. 3A can be manufactured using the method shown in the first embodiment or the second embodiment, and the high resistance can be removed as needed. The step of carbonizing the remaining structure other than the silicon epitaxial layer 314 . The obtained gallium nitride epitaxial layer 316 has been tested and its X-ray diffraction analysis shows that the half-maximum width (FWHM) of the (002) plane is less than 100 arcsec, verifying that the grown epitaxial film is of excellent quality.

In this embodiment, the semiconductor substrate 310 has a substrate through hole TSH1, wherein the angle θ1 between the cross section of the sidewall of the substrate through hole TSH1 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, between 45° and 90°. , preferably between 85° and 90°. For example, as shown in FIG. 3A , the angle θ1 between the cross section of the side wall of the substrate through hole TSH1 and the surface 316 a of the gallium nitride epitaxial layer 316 is, for example, 90°. Substrate through hole The depth D of TSH1 is, for example, between 10 μm and 200 μm. The substrate through hole TSH1 may be, for example, a circular substrate through hole or an elliptical substrate through hole. In one embodiment, if the substrate through hole TSH1 is a circular substrate through hole, the circular substrate through hole has a diameter of, for example, 10 μm ~ 85 μm; in another embodiment, if the substrate through hole TSH1 is an elliptical substrate through hole , then the short axis length multiplied by the long axis length of the elliptical substrate through hole is, for example, 10 μm × 20 μm to 50 μm × 120 μm. In FIG. 3A , the cross-section of the substrate through hole TSH1 is illustrated as a profile with the same slope.

The front source contact 320 is formed on the surface 316 a of the gallium nitride epitaxial layer 316 and covers the through-substrate hole TSH1 of the semiconductor substrate 310 . The front source contact 320 includes an adhesive layer 322, a barrier layer 324, and a highly conductive layer 326. The adhesion layer 322 is formed on the surface 316a of the gallium nitride epitaxial layer 316. The barrier layer 324 is formed on the surface of the adhesive layer 322 . The highly conductive layer 326 is formed on the surface of the barrier layer 324 . In this embodiment, the adhesive layer 322 is composed of Ti, TiW, TiN, Ta or TaN with a thickness between 2 nm and 200 nm, for example. The barrier layer 324 is made of Pt, Pd or Mo with a thickness between 2 nm and 200 nm, for example. The high conductive layer 326 is composed of, for example, Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm.

The back contact metal layer 330 is formed in the substrate through hole TSH1 of the semiconductor substrate 310 and is in direct contact with the front source contact 320 . The back contact metal layer 330 includes an adhesive layer 332, a barrier layer 334 and a highly conductive layer 336. The adhesive layer 332 is formed, for example, on the surface of the substrate through hole TSH1. The barrier layer 334 is formed on the surface of the adhesive layer 332, for example. The highly conductive layer 336 is formed on the surface of the barrier layer 334, for example. In this embodiment, the adhesive layer 332 is made of, for example, Ti, TiW, or Ti with a thickness between 2 nm and 200 nm. Composed of TiN, Ta or TaN. The barrier layer 334 is composed of TiW, TiN or TaN with a thickness between 2 nm and 200 nm, for example. The high conductive layer 336 is composed of, for example, Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm.

FIG. 3B is a schematic cross-sectional view of another semiconductor device according to the third embodiment, in which the same element symbols as in FIG. 3A are used to represent the same or similar components, and the same or similar components can also refer to the relevant description of FIG. 3A , which will no longer be used. Repeat.

In FIG. 3B , the cross-section of the substrate through hole TSH2 is illustrated as a trapezoidal outline. For example, the angle θ2 between the cross section of the side wall of the substrate through hole TSH2 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 45°, and the cross section of the side wall of the substrate through hole TSH2 has the same slope.

FIG. 3C is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment, in which the same element symbols as those in FIG. 3A are used to represent the same or similar components, and the same or similar components can also be referred to the relevant description of FIG. 3A , which will no longer be used. Repeat.

In FIG. 3C , the cross-section of the substrate through hole TSH3 is illustrated as a stepped profile. For example, the angle θ3 between the cross section of the sidewall of the substrate through hole TSH3 located in the gallium nitride epitaxial layer 316 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 90°; The angle θ3′ between the cross section of the side wall of the substrate through hole TSH3 in the layer 314 and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 90°. The maximum width L1 of the cross-section of the substrate through-hole TSH3 located in the gallium nitride epitaxial layer 316 is, for example, smaller than the maximum width L2 of the cross-section of the substrate through-hole TSH3 located in the high-resistance silicon carbide epitaxial layer 314 .

FIG. 3D is a cross-sectional view of another semiconductor device according to the third embodiment. 3A uses the same element symbols to represent the same or similar components, and the same or similar components can also refer to the relevant description of FIG. 3A and will not be described again.

In FIG. 3D , the cross-section of the substrate through hole TSH4 is illustrated as a stepped profile plus an inclined profile. For example, the angle θ4 between the cross section of the sidewall of the substrate through hole TSH4 located in the gallium nitride epitaxial layer 316 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 60°; The angle θ4′ between the cross section of the side wall of the substrate through hole TSH4 in the layer 314 and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 60°. The maximum width L3 of the cross-section of the substrate through-hole TSH4 located in the gallium nitride epitaxial layer 316 is, for example, smaller than the maximum width L4 of the cross-section of the substrate through-hole TSH4 located in the high-resistance silicon carbide epitaxial layer 314 .

FIG. 3E is a schematic cross-sectional view of yet another semiconductor device according to the third embodiment, in which the same element symbols as in FIG. 3A are used to represent the same or similar components, and the same or similar components can also be referred to the relevant description of FIG. 3A , which will not be repeated. Repeat.

In FIG. 3E , the cross-section of the substrate through hole TSH5 is illustrated as profiles with different slopes. For example, the angle θ5 between the cross section of the sidewall of the substrate through hole TSH5 located in the gallium nitride epitaxial layer 316 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 45°; The angle θ5′ between the cross section of the side wall of the substrate through hole TSH5 in the layer 314 and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 60°. The maximum width L5 of the cross-section of the substrate through-hole TSH5 located in the gallium nitride epitaxial layer 316 is, for example, smaller than the maximum width L6 of the cross-section of the substrate through-hole TSH5 located in the high-resistance silicon carbide epitaxial layer 314 .

To sum up, the present invention uses an N-type silicon carbide substrate or a high-resistance silicon carbide The formation of a damaged layer in the epitaxial layer not only allows the growth of gallium nitride with good crystalline quality, but also allows most of the N-type silicon carbide substrate to be retained due to the existence of the damaged layer, allowing it to be reused, thereby reducing the cost of the substrate. Moreover, the present invention can improve the electrical connection between the front and back components by forming the front source contact covering the substrate through hole of the semiconductor substrate, and then forming the back contact metal layer in the substrate through hole, and can also improve the radio frequency. source impedance and RF front and back capacitance, and make the variation range of RF source impedance and RF front and back capacitance smaller.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

102:Area

104: High resistance silicon carbide epitaxial layer

106:GaN epitaxial layer

106a: Surface

108: Front source contact

108a, 116a: Adhesion layer

108b, 116b: barrier layer

108c, 116c: Highly conductive layer

116: Back contact metal layer

ES: Semiconductor epitaxial substrate

TSH: through substrate hole

θ: included angle

Claims (21)

A semiconductor device includes: a semiconductor substrate having a through substrate hole; the semiconductor substrate includes: a high-resistivity silicon carbide epitaxial layer having a first surface and a second surface, the first surface is relative to the second surface, wherein the micropipe density (MPD) of the high-resistance silicon carbide epitaxial layer is less than 0.5ea/cm ² and the base plane dislocation (BPD) Less than 10ea/cm ² and through-spiral dislocation (TSD) less than 300ea/cm ² ; and a gallium nitride epitaxial layer formed on the second surface of the high-resistance silicon carbide epitaxial layer; at least one semiconductor A component formed on the gallium nitride epitaxial layer; a front source contact formed on the surface of the gallium nitride epitaxial layer and covering the substrate through hole of the semiconductor substrate; and a back contact metal A layer is formed within the substrate through hole of the semiconductor substrate and is in direct contact with the front source contact. The semiconductor device according to claim 1, wherein the front source contact includes: an adhesive layer formed on the surface of the gallium nitride epitaxial layer; a barrier layer formed on the adhesive layer surface; and a highly conductive layer formed on the surface of the barrier layer. The semiconductor device according to claim 2, wherein the adhesive layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2nm~200nm; the barrier layer includes Pt, Pd with a thickness between 2nm~200nm. Or Mo; the highly conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm. The semiconductor device according to claim 1, wherein the back contact metal layer includes: an adhesive layer formed on the surface of the substrate through hole; a barrier layer formed on the surface of the adhesive layer; and a highly conductive layer layer is formed on the surface of the barrier layer. The semiconductor device according to claim 4, wherein the adhesive layer includes Ti, TiW, TiN, Ta or TaN with a thickness between 2nm~200nm; the barrier layer includes TiW, TiN with a thickness between 2nm~200nm. or TaN; the highly conductive layer includes Au, Al, Al-Cu or Cu with a thickness between 50 nm and 10 μm. The semiconductor device according to claim 1, wherein the angle between the cross section of the sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 45° and 90°. The semiconductor device according to claim 6, wherein the angle between the cross section of the sidewall of the substrate through hole and the surface of the gallium nitride epitaxial layer is between 85° and 90°. The semiconductor device according to claim 1, wherein the substrate through hole is a circular substrate through hole and has a diameter of 10 μm ~ 85 μm. The semiconductor device according to claim 1, wherein the substrate through hole is an elliptical substrate through hole, and the minor axis length times the major axis length of the elliptical substrate through hole is 10 μm×20 μm to 50 μm×120 μm. The semiconductor device according to claim 1, wherein the depth of the substrate through hole is between 10 μm and 200 μm. The semiconductor device according to claim 1, wherein the cross-section of the substrate through hole is a stepped profile, a stepped profile plus a sloped profile, a profile with the same slope, or a profile with different slopes. The semiconductor device according to claim 1, wherein the thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm. A method of manufacturing a semiconductor device, including: epitaxially growing a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer on a first surface of an N-type silicon carbide substrate to obtain the high-resistance silicon carbide epitaxial layer. A semiconductor epitaxial substrate with a crystal layer and the gallium nitride epitaxial layer; forming a front-side source contact on the surface of the gallium nitride epitaxial layer; The epitaxial layer forms at least one semiconductor element; after forming the front source contact and the at least one semiconductor element, a wafer carrier is bonded to the surface of the gallium nitride epitaxial layer; from the N-type A laser is applied to the second surface of the silicon carbide substrate to form a damage layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, wherein the second surface is relative to the N-type silicon carbide substrate. first surface; Separate the N-type silicon carbide substrate and the semiconductor epitaxial substrate from the damaged layer; use the front source contact as an etching stop layer, and form a substrate through hole by etching from the bottom of the semiconductor epitaxial substrate, Until part of the front source contact is exposed; and a metallization process is performed to form a back-side contact metal layer in the substrate through hole. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the front source contact includes: forming an adhesive layer on the surface of the gallium nitride epitaxial layer; A barrier layer is formed on the surface; and a highly conductive layer is formed on the surface of the barrier layer. The manufacturing method of a semiconductor device according to claim 13, wherein the step of forming the back contact metal layer includes: forming an adhesive layer on the surface of the substrate through hole; forming a barrier layer on the surface of the adhesive layer; and forming a highly conductive layer on the surface of the barrier layer. The method of manufacturing a semiconductor device according to claim 13, wherein the first surface of the N-type silicon carbide substrate has an angle with respect to the (0001) plane of no more than 0° +/-8°. The manufacturing method of a semiconductor device as claimed in claim 13, wherein the thickness variation rate of the high-resistance silicon carbide epitaxial layer is between 5% and 10%. The method of manufacturing a semiconductor device according to claim 13, wherein the method of forming the damage layer includes applying the laser to the N-type silicon carbide substrate from the second surface of the N-type silicon carbide substrate. to form the damage layer in the N-type silicon carbide substrate. The method of manufacturing a semiconductor device according to claim 18, further comprising: removing the remaining N-type silicon carbide substrate after separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate. The manufacturing method of a semiconductor device according to claim 13, wherein the method of forming the damage layer includes: applying the laser from the second surface of the N-type silicon carbide substrate to the high-resistance silicon carbide In the crystal layer, the damage layer is formed in the high-resistance silicon carbide epitaxial layer. The manufacturing method of a semiconductor device according to claim 13, wherein after forming the back contact metal layer, it further includes: removing the wafer carrier; and performing a singulation process.

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