IE83621B1 - A planar schottky diode and manufacturing method - Google Patents

Description

A Planar Schottky Diode and Manufacturing Method INTRODUCTION Field of the Invention The invention relates to planar Schottky diodes.

Prior Art Discussion Schottky diodes are the preferred active device for use at frequencies from 300 GHz to 3 THz and above. A favoured configuration is planar where it is necessary to incorporate an airbridged connection to the Schottky anode from the anode pad.

This is necessary to reduce parasitic capacitance which will limit the upper operating frequency, whilst preserving the planar nature of the device. It is also necessary to isolate the active area of the device.

Planar Schottky diodes evolved from whisker contacted diodes where a sharpened metal whisker was brought into Contact with the device anode. Whisker devices have very low parasitic losses but the whisker Contact is problematic, difficult to assemble, and has reliability issues. Planar Schottky diodes are an improvement over such approaches, and the paper "Schottky contact with dimensions less than 0.5um2" by N.S. Peev, Microelectronic Engineering 43-44 (1998) 599-603 describes one such diode. It appears that this approach would provide a diode having either a high resistance or having poor diode performance.

US 4,665,413 describes another Schottky diode, and also a manufacturing process.

A mesa has an exposed edge at a generally vertical side.

The invention is directed towards providing an improved Schottky barrier diode and method of producing same.

Statements of Invention According to the invention, there is provided a method of producing a Schottky diode comprising the steps of: (a) fabricating an active mesa on a substrate, (b) growing a doped epilayer on a side wall of the mesa, (c) fabricating a cathode ohmic contact on the active mesa, and (d) after fabricating the cathode ohmic contact, fabricating a Schottky contact on the epilayer, and fabricating an anode Contact pad on the substrate.

In one embodiment, the method comprises the further step of annealing after fabricating the cathode ohmic contact and before fabricating the anode.

In another embodiment, the method comprises the further step of fabricating an insulating layer over the active mesa with an overhang over said side wall, and growing the epilayer under the overhang.

In a further embodiment, the epilayer is grown by preferential lateral MOVPE growth.

In one embodiment, the mesa comprises highly doped N+ GaAs and the epilayer comprises less doped GaAs material.

In another embodiment, the method comprises the further steps of forming an oxide on the active mesa, etching the oxide to expose part of the active mesa, and the cathode ohmic contact and the epilayer are located on opposed sides of remaining oxide.

In a further embodiment, the step (b) comprises the sub—steps of: dry etching to expose horizontal AlGaAs layer surfaces and a side wall of the active mesa, the active mesa being of GaAs composition; oxidising the exposed horizontal A1GaAs layer surfaces; preferentially wet etching the GaAs active mesa side wall; and epitaxially growing GaAs on the wet etched surface of the side wall.

In one embodiment, the overhang insulating material is of A1GaAs, SiO2, or silicon nitride composition.

In another embodiment, the step (c) comprises the sub-steps of:- applying an insulator layer over horizontal surfaces; etching the insulator layer to define a top cathode area over the mesa; and depositing ohmic metal on the exposed top cathode area.

In a further embodiment, the insulator layer is applied by sputtering.

In one embodiment, the step (c) comprises the further sub—steps of:~ etching the insulator layer from the substrate adjoining the mesa; and depositing an ohmic metal on the exposed substrate so that it is integral with the cathode ohmic metal on top of the active mesa.

In another embodiment, cathode ohmic metal thickness is such that the cathode has a stepped configuration.

In a further embodiment, the step (d) comprises electroplating the Schottky Contact to the epilayer.

In another aspect, the invention provides a Schottky diode comprising: a substrate; an active mesa on the substrate; an epilayer on a vertical side wall of the active mesa; an insulator above the epilayer; a cathode on the active mesa and isolated from the epilayer by the insulator; an anode contact pad on the substrate and contacting a Schottky contact on the epilayer.

In one embodiment, the epilayer is epitaxially grown n-doped GaAs, and the active mesa is more highly doped n—doped GaAs.

In another embodiment, the insulator is an oxide.

In a further embodiment, the Schottky Contact has an area in the range of 100 um2 to 0.0025 umz.

In one embodiment, the range is 40 um2 to 0.05 um2.

In another embodiment, the anode is of elongate shape, having a rectangular cross- section, and contacting the epilayer centrally on the substrate as viewed in plan.

Detailed Description of the Invention The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:- Fig. I is a perspective view of a Schottky diode of the invention; Fig.2 is a series of diagrams showing a manufacturing process for the diode; Fig. 3 is a series of diagrams showing an alternative manufacturing process; Fig. 4 is a diagram showing a device incorporating two Schottky diodes of the invention.

Referring to Fig. l a Schottky barrier diode l of the invention is shown. A mesa 3 of highly conductive N‘ GaAs is fabricated on a semi-insulating ("S.l.") substrate 2 of AlGaAs/GaAs/AlGaAs composition. A thin epilayer 4 of less conductive N type GaAs is grown on the vertical sidewall of this mesa by preferential lateral MOVPE growth. A cathode ohmic contact 9 is formed to the GaAs mesa 3. A thin section 6 of SiO2 is used to passivate this from the lateral grown epilayer 4. A Schottky contact 10 is formed between an anode Contact pad "finger" 7 and the laterally grown sidewall 4. The finger 7 is contiguous with a contact pad 8.

The diode may be referred to as a "transverse diode". Because there is no airbridge, fabrication is simple and there is excellent reliability. Also, the nature of the diode is such that the fabrication of the Schottky Contact and anode finger are self—aligning.

This removes the need for difficult alignment during patterning of the anode and finger. Regarding anode definition, the junction area of the device is the product of the width of the contacting finger and the height of the GaAs mesa. Therefore, exceedingly small anode areas are possible, leading to very low junction capacitances. Because the mesa height is defined by well controlled etch processes, and line widths down to 0.5 pm are readily achievable for the anode contact without having to resort to electron beam lithography, means that an anode area of 0.1 pm2 (0.5 x 0.2 um) or less can be fabricated by conventional lithography. The same anode area of 0.1 umz for a circular Schottky anode of a conventional planar diode needs a diameter of 0.36 um for which E beam lithography is required. Table 1 below illustrates this. Even smaller anode areas are achievable using E beam lithography to write a 250 nm or 100 nm line for the anode Contact (*).

Anode area (um?) Dimensions of Equivalent Transverse diode diameter of Prior anode (um) Art anode (um) .1 0.5x0.2 0.36 .05 0.5 x 0.1 0. *0.025 0.25 x 0.1 0.18 *0.0l 0.1 x 0.1 0.11 Table 1 Regarding package parasitics, the lack of an airbridge minimises the parasitic capacitance so that the shunt capacitance of the package compares favourably with other types of planar diode as shown in Table 2. The figure for the transverse diode is calculated from probable package dimensions for a similar diode. By simple modelling of the structure, especially the mesa shape, the parasitics can be optimised reducing the shunt capacitance and package resistance.

Type of diode Shunt capacitance (fF) Surface channel 13-15 Quasi—vertical 4-5 Transverse 3-4 Whisker contacted ~l Table 2 The transverse diode can take advantage of membrane technology by fabricating on GaAs membranes. This may be used to integrate the diode with other elements on the membrane or substrate. For example it is possible to thin the diode substrate to obtain a membrane of at least 3 microns, in order to minimise radiofrequency losses.

It is very difficult to integrate prior planar diodes with other circuit elements reliably on membranes. However this would be relatively easy with the transverse diode of the invention as there are no complications caused by an airbridge. Because of the true planar nature of the transverse diode, reliable standard microelectronic processing techniques can be used for the integration of the transverse diode with other circuit elements on a membrane.

It will be appreciated that electron flow through the device is truly planar in one direction only, unlike airbridged planar diodes.

Referring to Figs. 2(a) to 2(h) a manufacturing process for the diode 1 is illustrated.

In general terms, in this process after the mesa is formed on the substrate an insulating layer is formed on top of the mesa with an overhang. The epilayer is grown under the overhang on the exposed side wall. The cathode ohmic contact is formed, and is connected to provide a very low resistance interface between the cathode and the mesa. The Schottky contact 10 is then formed by plating part of the epilayer with Pt/Au, and forming the anode finger 7 on the substrate, in contact with the Pt/Au 10. Because the Schottky contact 10 is formed towards the end of the process, the annealing of the cathode ohmic contact does not have any adverse impact on quality of the Schottky contact.

The starting material is a substrate 20 of semi-insulating GaAs on which is grown 0.5 mm of AlGaAs as an etch stop layer 21, 3.0 pm of undoped GaAs to form a membrane 22, 0.5 um AlGaAs 23, 1.0 mm of highly doped N" GaAs 24, and 0.5 pm of AlGaAs 25. All thicknesses are typical and will vary depending on diode application.

Fabrication starts with lithographically patterning the diode mesa with photo-resist 26 and dry etching through the top AlGaAs 25 and highly doped GaAs layer 24, to leave the mesa (Fig. 2(b)). Buffer areas are defined to the sides of the mesa and the middle AlGaAs layer 23 is etched to expose the underlying GaAs 22. The exposed AlGaAs 23 and 25(a) is then oxidised in a furnace with water vapour. This passivates the AlGaAs to inhibit overgrowth on the oxidised areas and makes the layer an electrical insulator.

The buffer areas also ensure that the GaAs overgrowth will not grow on the oxidised AlGaAs. A shallow recess is wet etched in the sidewall of the GaAs 24(a) using a preferential etchant, the depth is typically 0.15 mm for a mixer diode but will be wider for a varactor type diode. N type GaAs 27 is then epitaxially grown on the recessed GaAs 24(a) sidewalls and buffer areas by Metal Organic Vapour Phase Epitaxy (MOVPE) or Molecular Beam Epitaxy (MBE). The doping of this overgrowth is typically lEl7 cm3 for a mixer diode but will vary depending on the desired diode characteristics.

A thin layer 30 of silicon dioxide is then sputter deposited over the entire surface for further passivation during subsequent metal depositions. The cathode ohmic contact area on the mesa is defined in resist and the exposed SiO2 30 and oxidised AlGaAs layers 25(a) are dry etched. Ohmic metals such as gold, germanium, nickel are deposited by evaporation and lift-off, the wafer is annealed in a reducing atmosphere at typically 425°C to form a low resistance ohmic Contact area 35 to the N" GaAs 24(a). The cathode Contact pad 36 and ohmic Contact area 35 is defined in resist and gold deposited by evaporation and lift-off. This pad can then be gold plated to increase the thickness to ensure low electrical resistance.

An anode finger 41 and Contact pad is defined in resist and the exposed SiO2 is dry etched to expose the very small area of the vertical mesa sidewall where the Pt/ Au Schottky anode contact 40 will be formed as well as the finger and pad outline. Any SiO2 residues are removed from the Schottky anode site by a quick wet etch in buffered oxide etch. The Schottky anode (contact) 40 is then formed by electroplating platinum and then gold on to the very small exposed area of the vertical mesa sidewall. A gold seed layer is deposited by evaporation and lift-off to form the anode finger and contact pad 41. This is then plated with gold to minimise electrical resistance.

At this stage the diodes can be diced for separation into individual chips, or the substrate can be thinned to reduce losses due to parasitics. The device can be flip- chip mounted into a circuit and the GaAs substrate completely removed to the lower AlGaAs etch stop layer to leave the active device on a thin AlGaAs/GaAs/ AlGaAs membrane. When diced, the parts of the diode have the configuration as shown in Fig. l, the same reference numerals being used.

Referring to Fig. 3, another method uses conventional fabrication process steps and only four levels of lithography. The structure of the epi starting material would consist of a thin etch stop layer of AlGaAs on a semi insulating (SI) GaAs substrate.

For membrane applications a layer of SI GaAs of required thickness for the membrane and a further thin layer of AlGaAs overlying this would be necessary. The final layer is N* GaAs for the diode mesa, this can be thinned to the required thickness before mesa formation depending on diode requirements.

Silicon dioxide is deposited onto the substrate, coated with photoresist and the mesa pattern defined. The oxide and GaAs mesa are then dry etched and oxide deposited on the horizontal substrate surfaces. This can be done by sputtering which gives preferential oxide deposition normal to the substrate surface and then removing any residues on the side walls using a brief wet etch. The purpose of the oxide is to inhibit MOVPE growth. The Schottky GaAs epilayer is then laterally grown on the vertical side walls of the mesa.

Level 2 consists of patterning the ohmic Contact and cathode pad in resist, depositing the ohmic metals by metal evaporation and standard lift-off, and finally annealing to create an ohmic contact. The whole substrate is then passivated with silicon dioxide and the anode contact finger and pad lithography performed for level 3, which also defines the width of the anode. There is no critical alignment with this step as it is self—aligning, the anode finger pattern can overlap the mesa with no detrimental effects on the fabrication. In fact a degree of overlap is necessary as the anode junction will be located where the anode finger pattern intersects the mesa side wall.

This can be understood by reference to Fig. 3, in which the ‘Pattern for anode formation’ drawing shows a degree of misalignment in that the edge of the resist pattern is not aligned to the vertical epilayer. Alignment in the other direction is not an issue. The anode finger pattern is dry etched through the oxide to the substrate, exposing the anode area on the side wall; a brief wet oxide etch removes any residues and creates a lip for the anode finger metal lift—of‘f. Platinum is then electroplated to form the Schottky contact followed by a gold Contact layer. Gold is deposited by metal evaporation to form the anode finger and Contact pad using the underlying oxide to assist with lift-off. An option exists here to plate more gold if necessary to ensure good contact between the finger and the plated Schottky contact.

Finally the cathode pad is defined in level 4 and exposed by a wet oxide etch. The devices would then be thinned on the backside and separated using standard processing techniques. If the devices are required on membranes the backside would be thinned using mechanical chemical thinning and the final substrate removed by a chemical etch to the underlying AlGaAs etch stop layer.

An advantage of the diode is that any RIE plasma damage to the anode area is minimised during etching of the anode window. Plasma damage can cause traps and increase diode noise. Exposure to the RIE plasma flux of the anode area is minimal because the anode surface is vertical. In conventional planar and whisker diodes the anode area is normal to the plasma flux during any RIE etching of the anode, although the anode may have some protection by thin oxide.

The device can be easily integrated with other circuit elements on a thin membrane such as a filter by depositing the filter and or probe metallisations at the same time as the cathode and anode gold seed layers. The complete circuit with diode(s) is then defined in resist and the AlGaAs/GaAs/ AlGaAs layers wet etched through to the GaAs substrate. The structure is then thinned on the back side to typically 100 um thickness by mounting the front side using wax to a temporary substrate, and employing chemical mechanical polishing or rapid etching. The remaining GaAs substrate is then removed using a preferential wet etch to the lower AlGaAs etch stop layer. After mounting the membrane circuit in place the temporary substrate can be removed. Such an arrangement is shown in Fig. 4, in which the following are the items:- : Two diodes in anti—parallel configuration : Filter : Probe or contact pad : Membrane It will be appreciated that in the diode of the invention the anode area is very small because the sidewall is vertical giving less Contact area than an angled sidewall.

Using E beam lithography a Schottky anode of 0.1 mm width can be formed on a 0.1 pm vertical sidewall mesa, giving a Schottky anode of 0.01 umz. Also, the series resistance of the diode is very low as the ohmic metal is annealed after formation in the diode to achieve a low electrical resistance. Also, the diode is easily integrated into circuits with other elements such as filters, which can all be suspended on a thin membrane. This produces a circuit with low losses at THz frequencies. Also, the diode fabrication process is much simpler than prior processes.

The invention is not limited to the embodiments described but may be varied in construction and detail. For example the barrier diode may be produced as part of a process for manufacturing a MESFET or HEMT type device. Also, the epilayer may be grown by other suitable methods such as MBE or gas phase epitaxy.

Claims (10)

Claims

1.A method of producing a Schottky diode comprising the steps of: (a) fabricating an active mesa on a substrate, (b) growing a doped epilayer on a side wall of the mesa, fabricating a cathode ohmic contact on the active mesa, and (C) (d) after fabricating the cathode ohmic contact, fabricating a Schottky Contact on the epilayer, and fabricating an anode Contact pad on the substrate.

2.A method as claimed in claim 1, comprising the further step of annealing after fabricating the cathode ohmic Contact and before fabricating the anode.

3.A method as claimed in claims l or 2, comprising the further step of fabricating an insulating layer over the active mesa with an overhang over said side wall, and growing the epilayer under the overhang.

4.A method as claimed in any preceding claim, wherein the epilayer is grown by preferential lateral MOVPE growth.

5.A method as claimed in any preceding claim, wherein the mesa comprises highly doped Nl GaAs and the epilayer comprises less doped GaAs material.

6.A method as claimed in any preceding claim, comprising the further steps of forming an oxide on the active mesa, etching the oxide to expose part of the active mesa, and the cathode ohmic contact and the epilayer are located on opposed sides of remaining oxide.

7. A method as claimed in any preceding claim, wherein the step (b) comprises the sub—steps of: dry etching to expose horizontal AlGaAs layer surfaces and a side wall of the active mesa, the active mesa being of GaAs composition; oxidising the exposed horizontal AlGaAs layer surfaces; preferentially wet etching the GaAs active mesa side wall; and epitaxially growing GaAs on the wet etched surface of the side wall.

8. A method as claimed in any of claims 3 to 7, wherein the overhang insulating material is of AlGaAs, SiO2, or silicon nitride composition.

9. A method as claimed in any preceding claim, wherein the step (C) comprises the sub—steps of:— applying an insulator layer over horizontal surfaces; etching the insulator layer to define a top cathode area over the mesa; and depositing ohmic metal on the exposed top cathode area.

10. A method as claimed in claim 9, wherein the insulator layer is applied by sputtering. A method as claimed in claim 9 or 10, wherein the step (c) comprises the further sub-steps of:- etching the insulator layer from the substrate adjoining the mesa; and depositing an ohmic metal on the exposed substrate so that it is integral with the cathode ohmic metal on top of the active mesa. A method as claimed in claim 11, wherein cathode ohmic metal thickness is such that the cathode has a stepped configuration. A method as claimed in any preceding claim wherein the step (d) comprises electroplating the Schottky contact to the epilayer. A method of producing a Schottky barrier diode substantially as described with reference to