CN114300431A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN114300431A CN114300431A CN202110977082.5A CN202110977082A CN114300431A CN 114300431 A CN114300431 A CN 114300431A CN 202110977082 A CN202110977082 A CN 202110977082A CN 114300431 A CN114300431 A CN 114300431A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 42
- 239000000758 substrate Substances 0.000 claims abstract description 206
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 121
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 121
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 49
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 283
- 230000004888 barrier function Effects 0.000 claims description 40
- 239000012790 adhesive layer Substances 0.000 claims description 25
- 230000008569 process Effects 0.000 claims description 19
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910018182 Al—Cu Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 102100029223 Teashirt homolog 1 Human genes 0.000 description 11
- 101710201303 Threonine synthase-like 1 Proteins 0.000 description 11
- 101000633632 Homo sapiens Teashirt homolog 3 Proteins 0.000 description 5
- 102100029222 Teashirt homolog 3 Human genes 0.000 description 5
- 238000000227 grinding Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 102100029218 Teashirt homolog 2 Human genes 0.000 description 3
- 101710201302 Threonine synthase-like 2 Proteins 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a semiconductor substrate, at least one semiconductor device, a front source contact and a back contact metal layer. The semiconductor substrate is provided with a substrate through hole and comprises a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer formed on the second surface of the high-resistance silicon carbide epitaxial layer. The semiconductor device is formed on the gallium nitride epitaxial layer. The front source contact is formed on the surface of the gallium nitride epitaxial layer and covers the substrate through hole of the semiconductor substrate. The back contact metal layer is formed in the substrate via of the semiconductor substrate and is in direct contact with the front source contact.
Description
Technical Field
The present invention relates to semiconductor manufacturing technologies, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
Since the film formed by epitaxial (epitaxiy) process has the advantages of high purity and good thickness controllability, it has been widely used in the manufacture of Radio Frequency (RF) devices or power (power) devices, wherein the RF devices can be applied to 4G communication, 5G communication, satellite communication or 5G front-end module (front-end module).
However, in the manufacturing process of the rf device, the original substrate thickness is usually thinned from one thickness to a thickness smaller than the original thickness by grinding (grinding) or polishing (polishing) and the like, and the variation (variation) range of the final substrate thickness is easily too large because the difference between the thicknesses of the substrates to be removed is too large. For example, the substrate thickness is thinned from about 300 μm to about 50 μm, such that the final substrate thickness varies by about ± 20%. Therefore, adverse effects are generated on a Through Silicon Via (TSV) process, and device matching (device matching) is easily generated, thereby affecting the yield of the rf device.
Disclosure of Invention
The present invention is directed to a semiconductor device and a method for manufacturing the same, which can solve the problem of a large variation range of a substrate thickness, and which has a small variation range of a radio frequency source impedance (RF source impedance) and a radio frequency front-to-back side capacitance (RF front-to-back side capacitance).
According to an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, at least one semiconductor device, a front side source contact, and a back side contact metal layer. The semiconductor substrate has a through substrate via (through substrate), and the semiconductor substrate includes a high-resistance silicon carbide epitaxial layer (high-resistance silicon carbide epitaxial layer) having a first surface and a second surface, and a gallium nitride epitaxial layer formed on the second surface of the high-resistance silicon carbide epitaxial layer, wherein the first surface is opposite to the second surface. The semiconductor device is formed on the gallium nitride epitaxial layer. The front source contact is formed on the surface of the gallium nitride epitaxial layer and covers the substrate through hole of the semiconductor substrate. The back contact metal layer is formed in the substrate via of the semiconductor substrate and is in direct contact with the front source contact.
In the semiconductor device according to the embodiment of the present invention, the thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm.
In the semiconductor device according to an embodiment of the present invention, the front side source contact includes an adhesive layer, a barrier layer, and a highly conductive layer. The adhesion layer is formed on the surface of the gallium nitride epitaxial layer. The barrier layer is formed on the surface of the adhesion layer. The high-conductivity layer is formed on the surface of the barrier layer.
In the semiconductor device according to an embodiment of the present invention, the adhesion layer includes Ti, TiW, TiN, Ta, or TaN having a thickness of between 2nm and 200 nm. The barrier layer comprises Pt, Pd or Mo with the thickness of 2 nm-200 nm. The high conductive layer comprises Au, Al-Cu or Cu with the thickness of 50 nm-10 mu m.
In the semiconductor device according to an embodiment of the present invention, the back contact metal layer includes an adhesive layer, a barrier layer, and a highly conductive layer. The adhesion layer is formed on the surface of the substrate through hole. The barrier layer is formed on the surface of the adhesion layer. The high-conductivity layer is formed on the surface of the barrier layer.
In the semiconductor device according to an embodiment of the present invention, the adhesion layer includes Ti, TiW, TiN, Ta, or TaN having a thickness of between 2nm and 200 nm. The barrier layer comprises TiW, TiN or TaN with the thickness of 2 nm-200 nm. The high conductive layer comprises Au, Al-Cu or Cu with the thickness of 50 nm-10 mu m.
In the semiconductor device according to the embodiment of the present invention, an angle between a cross section of the sidewall of the substrate through-hole and the surface of the gallium nitride epitaxial layer is between 45 ° and 90 °.
In the semiconductor device according to the embodiment of the present invention, an angle between a cross section of the sidewall of the substrate through-hole and the surface of the gallium nitride epitaxial layer is between 85 ° and 90 °.
In the semiconductor device according to an embodiment of the present invention, the substrate through-hole is a circular substrate through-hole and has a diameter of 10 μm to 85 μm.
In the semiconductor device according to the embodiment of the present invention, the substrate through-hole is an elliptical substrate through-hole, and the length of the minor axis multiplied by the length of the major axis of the elliptical substrate through-hole is 10 μm × 20 μm to 50 μm × 120 μm.
In the semiconductor device according to an embodiment of the present invention, the substrate through-hole has a depth of 10 μm to 200 μm.
In the semiconductor device according to an embodiment of the present invention, the cross section of the substrate via hole is a stepped profile, a stepped profile plus an upper inclined profile, a profile of the same slope, or a profile of different slopes.
According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes epitaxially growing a high-resistivity epitaxial silicon carbide layer and an epitaxial gallium nitride layer on a first surface of an N-type silicon carbide substrate to obtain a semiconductor epitaxial substrate including the high-resistivity epitaxial silicon carbide layer and the epitaxial gallium nitride layer. A front-side source contact is formed on the surface of the GaN epitaxial layer, and at least one semiconductor device is formed on the GaN epitaxial layer. After the front-side source contact and the at least one semiconductor device are formed, a wafer carrier is bonded to the surface of the gallium nitride epitaxial layer. Applying a laser from a second surface of the N-type silicon carbide substrate opposite to the first surface of the N-type silicon carbide substrate to form a damaged layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate, and then separating the N-type silicon carbide substrate from the damaged layer. And etching a substrate through hole from the bottom of the semiconductor epitaxial substrate by using the front-side source contact as an etching stop layer until part of the front-side source contact is exposed, and then performing a metallization process to form a back-side contact metal layer in the substrate through hole.
In another embodiment of the present invention, the step of forming the front-side source contact includes forming an adhesive layer on the surface of the gan epitaxial layer, forming a barrier layer on the surface of the adhesive layer, and forming a highly conductive layer on the surface of the barrier layer.
In another embodiment of the present invention, the step of forming the back contact metal layer includes forming an adhesive layer on the surface of the through hole of the substrate, forming a barrier layer on the surface of the adhesive layer, and forming a high-conductivity layer on the surface of the barrier layer.
In the manufacturing method according to another embodiment of the present invention, the first surface of the above-described N-type silicon carbide substrate has an angle in a range of not more than 0 ° +/-8 ° with respect to the (0001) plane.
In a manufacturing method according to another embodiment of the present invention, the thickness variation rate of the high-resistance silicon carbide epitaxial layer is 5% to 10%.
In a manufacturing method according to another embodiment of the present invention, the method of forming the damaged layer described above includes applying a laser into the N-type silicon carbide substrate from the second surface of the N-type silicon carbide substrate to form the damaged layer within the N-type silicon carbide substrate.
In the manufacturing method according to another embodiment of the present invention, after separating the N-type silicon carbide substrate from the semiconductor epitaxial substrate, further includes removing the remaining N-type silicon carbide substrate.
In a manufacturing method according to another embodiment of the present invention, the method of forming the above-described damaged layer includes applying laser light into the high-resistance silicon carbide epitaxial layer from the second surface of the N-type silicon carbide substrate to form the damaged layer within the high-resistance silicon carbide epitaxial layer.
In the manufacturing method according to another embodiment of the present invention, after forming the back contact metal layer, further comprising removing the wafer carrier and performing a singulation process (die singulation).
Based on the above, the method of the present invention can reduce the variation range of the substrate thickness, and can improve the electrical connection between the front and back devices by forming the back contact metal layer in the substrate via hole exposing part of the front source contact, so as to manufacture the device with small variation range of the radio frequency source impedance and the radio frequency front and back capacitance.
Drawings
FIGS. 1A to 1G are schematic cross-sectional views illustrating the fabrication of a semiconductor device according to a first embodiment of the present invention;
FIGS. 2A to 2G are schematic cross-sectional views illustrating the fabrication of a semiconductor device according to a second embodiment of the present invention;
FIG. 3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention;
fig. 3B is a schematic cross-sectional view of another semiconductor device according to a third embodiment;
FIG. 3C is a schematic cross-sectional view of still another semiconductor device according to a third embodiment;
FIG. 3D is a schematic sectional view of still another semiconductor device according to a third embodiment;
fig. 3E is a schematic cross-sectional view of another semiconductor device according to the third embodiment.
Description of the reference numerals
100: n-type silicon carbide substrate
100a, 314 a: first surface
100b, 314 b: second surface
102. 312: region(s)
104. 314: high resistivity silicon carbide epitaxial layer
106. 316: epitaxial layer of gallium nitride
106a, 316 a: surface of
108. 320, and (3) respectively: front side source contact
108a, 116a, 322, 332: adhesive layer
108b, 116b, 324, 334: barrier layer
108c, 116c, 326, 336: high conductive layer
110: laser
112. 200: damaged layer
114: wafer carrier
116. 330: back contact metal layer
300: semiconductor device with a plurality of semiconductor chips
310: semiconductor substrate
D: depth of field
ES: semiconductor epitaxial substrate
L1-L6: maximum width
t1, t2, t 3: thickness of
TSH, TSH 1-TSH 5: substrate through-hole
TSHa: cross section of
θ, θ 1 to θ 5, θ 3 'to θ 5': included angle
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, but the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and thickness of regions, regions and layers may not be drawn to scale for clarity. For ease of understanding, like components will be described with like reference numerals in the following description.
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a semiconductor device according to a first embodiment of the present invention.
Referring to fig. 1A, a high resistivity silicon carbide epitaxial layer 104 is epitaxially grown on a first surface 100a of an N-type silicon carbide substrate 100, wherein the thickness of the N-type silicon carbide substrate 100 is, for example, 300 μm to 725 μm, and the angle of the first surface 100a of the N-type silicon carbide substrate 100 relative to the (0001) plane is, for example, in the range of 0 ° +/-8 °, preferably in the range of 0 ° +/-5 °, more preferably in the range of 0 ° +/-3 °, and most preferably 0 °. The N-type silicon carbide substrate 100 has a micropipe density (MPD) of less than 1ea/cm2Basal Plane Dislocation (BPD) less than 3000ea/cm2And threading dislocation (TSD) less than 1000ea/cm2. The resistance of the N-type silicon carbide substrate 100 is approximately between 15mohm-cm and 26 mohm-cm. In the present embodiment, the N-type silicon carbide substrate 100 can be reused, thereby greatly reducing the material cost. In the present embodiment, the high-resistivity silicon carbide epitaxial layer 104 further has a region 102 on the side close to the N-type silicon carbide substrate 100. The region 102 is, for example, a region of poor quality grown when epitaxially growing a high-resistivity silicon carbide epitaxial layer 104. In one embodiment, the region 102 may be used as a buffer layer, for example, and may be retained or removed in a subsequent process (as shown in FIG. 1D). The high-resistance silicon carbide epitaxial layer 104 is a semiconductor substrate suitable for Radio Frequency (RF) devices, such as semi-insulating silicon carbide (SI-SiC). The thickness of the high-resistance silicon carbide epitaxial layer 104 can be set between 20 μm and 100 μm,and the thickness change rate of the high-resistance silicon carbide epitaxial layer 104 is approximately in the range of 5% -10%. The surface of the high resistivity silicon carbide epitaxial layer 104 may have an angle in the range of 0 ° +/-8 °, 0 ° +/-5 °, or 0 ° +/-3 °, for example, with respect to the (0001) plane, and the micropipe density (MPD) of the high resistivity silicon carbide epitaxial layer 104 may be less than 0.5ea/cm2Basal Plane Dislocations (BPD) may be less than 10ea/cm2The Threading Screw Dislocation (TSD) can be less than 300ea/cm2. In the present embodiment, the high resistance silicon carbide epitaxial layer 104 has a resistance value of, for example, greater than 1E5 ohm-cm.
Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104, and a semiconductor epitaxial substrate ES composed of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 is obtained.
Then, a front-side source contact 108 is formed on the surface 106a of the gan epitaxial layer 106. The front side source contact 108 is formed, for example, as a single layer or multiple layers. In the present embodiment, the front source contact 108 is formed in a three-layer structure, for example. For example, the step of forming the front side source contact 108 includes forming an adhesive layer 108a on the surface 106a of the gan epitaxial layer 106, then forming a barrier layer 108b on the surface of the adhesive layer 108a, and then forming a highly conductive layer 108c on the surface of the barrier layer 108b, but the invention is not limited thereto. In the present embodiment, by forming the adhesion layer 108a, the contact between the front side source contact 108 and the dielectric layer and the semiconductor device can be improved. By forming the barrier layer 108b, the metals of the highly conductive layer 108c and the adhesion layer 108a can be prevented from intermixing. By forming the highly conductive layer 108c, current can be handled with low parasitic loss. The adhesive layer 108a is made of, for example, Ti, TiW, TiN, Ta, or TaN with a thickness of 2nm to 200 nm. The barrier layer 108b is made of, for example, Pt, Pd, or Mo with a thickness of 2nm to 200 nm. The highly conductive layer 108c is made of, for example, Au, Al-Cu or Cu with a thickness of 50nm to 10 μm. In an embodiment, the blocking layer 108b may not be formed between the adhesive layer 108a and the highly conductive layer 108c, and may be adjusted according to design requirements, which is not limited in the present invention.
Then, a semiconductor device or the like is formed in the gallium nitride epitaxial layer 106; for clarity, the components are omitted from fig. 1A to 1G.
Next, referring to fig. 1B, after forming the front-side source contact 108 and the semiconductor device (not shown), a wafer carrier (carrier)114 is bonded to the surface 106a of the gan epitaxial layer 106, wherein the material of the wafer carrier 114 is, for example, glass or sapphire.
Then, referring to fig. 1C, a laser 110 is used to form a damaged layer 112 in the N-type silicon carbide substrate 100. In the present embodiment, the method of forming the damaged layer 112 includes, for example, applying a laser 110 from the second surface 100b of the N-type silicon carbide substrate 100 into the N-type silicon carbide substrate 100 to form the damaged layer 112 in the N-type silicon carbide substrate 100 near the high resistance silicon carbide epitaxial layer 104 side, wherein the second surface 100b is opposite to the first surface 100a of the N-type silicon carbide substrate 100. Wafer to wafer and with wafer calculation data may be obtained by using laser 110 to form damage layer 112.
Thereafter, referring to fig. 1D, the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 112, and a portion of the N-type silicon carbide substrate 100 may remain on the surface of the high-resistance silicon carbide epitaxial layer 104. Thus, in one embodiment, the remaining N-type silicon carbide substrate 100 may remain; in another embodiment, the remaining N-type silicon carbide substrate 100 may be removed, for example, by grinding or the like. As a result, the thickness of the silicon carbide substrate 100 to be ground becomes thin, and the variation range of the final substrate thickness becomes small.
In the process of the first embodiment, the damaged layer 112 for separation is formed in the N-type silicon carbide substrate 100 by the laser 110 after the front source contact 108 is formed, so that the crystalline quality of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 can be ensured. In addition, after the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 112, a sufficient thickness of the N-type silicon carbide substrate 100 can be maintained, wherein the sufficient thickness is a thickness capable of supporting the film layer and the member formed thereon and withstanding the subsequent processes. Thus, the separated N-type silicon carbide substrate 100 can be reused, and the material cost is greatly reduced. In addition, the thickness of the substrate can be controlled more precisely, so that the generation of parasitic loss can be greatly reduced.
Next, referring to fig. 1E, a substrate via hole TSH is formed by etching from the bottom (e.g., on the side of the region 102) of the semiconductor epitaxial substrate ES by using the front side source contact 108 as an etching stop layer until a portion of the front side source contact 108 is exposed, wherein an included angle θ between a cross section TSHa of a sidewall of the substrate via hole TSH and the surface 106a of the gan epitaxial layer 106 is, for example, 45 ° to 90 °, and preferably 85 ° to 90 °. The depth D of the substrate through hole TSH is, for example, 10 μm to 200 μm. The substrate via TSH may be, for example, a circular substrate via or an oval substrate via. In one embodiment, if the substrate via TSH is a circular substrate via, the circular substrate via has a diameter of, for example, 10 μm to 85 μm; in another embodiment, if the substrate via TSH is an elliptical substrate via, the length of the minor axis multiplied by the length of the major axis of the elliptical substrate via is, for example, 10 μm × 20 μm to 50 μm × 120 μm. In fig. 1E, the cross section of the substrate through hole TSH is drawn as a profile with the same slope, but in other embodiments, the cross section of the substrate through hole TSH may be a profile such as a stepped profile, a stepped profile plus an inclined profile, or a profile with different slopes, which will be described in detail later.
Then, referring to fig. 1F, a metallization process is performed to form a back-side contact metal (back-side contact metal)116 in the substrate via TSH. The back contact metal layer 116 is formed in a single layer or a plurality of layers, for example. In the present embodiment, the back contact metal layer 116 is formed in a three-layer structure, for example. For example, the step of forming the back contact metal layer 116 includes forming an adhesive layer 116a on the surface of the substrate via TSH, forming a barrier layer 116b on the surface of the adhesive layer 116a, and forming a highly conductive layer 116c on the surface of the barrier layer 116b, but the invention is not limited thereto. The back contact metal layer 116 may be formed by sputtering, electroplating, or conformal coating. In one embodiment, electroplating may be used to form a thicker back contact metal layer 116, thereby further reducing manufacturing costs. In the present embodiment, by forming the adhesive layer 116a, the contact between the back contact metal layer 116 and the side and back surfaces of the semiconductor device and the contact between the front source contact 108 can be improved. By forming the barrier layer 116b, the metal in the highly conductive layer 116c and the adhesion layer 116a can be prevented from intermixing. By forming the highly conductive layer 116c, current can be handled with low parasitic loss. The adhesive layer 116a is made of, for example, Ti, TiW, TiN, Ta, or TaN with a thickness of 2nm to 200 nm. The barrier layer 116b is made of, for example, TiW, TiN, or TaN having a thickness of 2nm to 200 nm. The highly conductive layer 116c is made of, for example, Au, Al-Cu or Cu with a thickness of 50nm to 10 μm. In another embodiment, the barrier layer 116b may not be formed between the adhesive layer 116a and the high conductive layer 116c, and may be adjusted according to design requirements, which is not limited in the present invention.
Thereafter, referring to fig. 1G, after the back contact metal layer 116 is formed, the wafer carrier 114 may be removed. In one embodiment, if a plurality of semiconductor devices and other components are formed in the gan epitaxial layer 106 in the process shown in fig. 1A, a single process is also included in fig. 1G, but the invention is not limited thereto.
Since the process of the first embodiment is to form the back contact metal layer 116 in the substrate through hole TSH after the substrate through hole TSH exposes a portion of the front source contact 108, direct contact between the front source contact 108 and the back contact metal layer 116 can be ensured, thereby improving electrical connection between front and back devices. If the method is applied to a radio frequency device, the radio frequency source impedance and the radio frequency front and back surface capacitance can be further improved, and the variation range of the radio frequency source impedance and the radio frequency front and back surface capacitance can be reduced.
Fig. 2A to fig. 2G are schematic cross-sectional views illustrating the manufacture of a semiconductor device according to a second embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to denote the same or similar components, and the same or similar components can refer to the related description of the first embodiment, which is not repeated herein.
Referring to fig. 2A, a high-resistivity silicon carbide epitaxial layer 104 having a region 102 is epitaxially grown on a first surface 100a of an N-type silicon carbide substrate 100. Then, a gallium nitride epitaxial layer 106 is epitaxially grown on the high-resistance silicon carbide epitaxial layer 104, and a semiconductor epitaxial substrate ES composed of the high-resistance silicon carbide epitaxial layer 104 and the gallium nitride epitaxial layer 106 is obtained. A front side source contact 108 is formed on the surface 106a of the gan epitaxial layer 106. Thereafter, a semiconductor device or the like is formed in the gallium nitride epitaxial layer 106; for clarity, the components are omitted from fig. 2A to 2G.
Next, referring to fig. 2B, after the front-side source contact 108 and the semiconductor device (not shown) are formed, a wafer carrier 114 is bonded to the surface 106a of the gan epitaxial layer 106.
Then, referring to fig. 2C, a damaged layer 200 is formed in the semiconductor epitaxial substrate ES by using the laser 110. In the present embodiment, the damaged layer 200 is formed in the high-resistance silicon carbide epitaxial layer 104, for example, and is located on the side opposite to the region 102 of the N-type silicon carbide substrate 100. The method of forming the damaged layer 200 includes, for example, applying a laser 110 from the second surface 100b of the N-type silicon carbide substrate 100 into the high resistance silicon carbide epitaxial layer 104 to form the damaged layer 200 within the high resistance silicon carbide epitaxial layer 104. By using laser 110 to form damage layer 200, wafer to wafer and with wafer calculation data may be obtained.
Thereafter, referring to fig. 2D, the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 200. In the present embodiment, since the region 102 and the N-type silicon carbide substrate 100 are completely removed, a process such as grinding may not be required, and a part of the steps may be further omitted compared to the first embodiment, thereby further reducing the manufacturing cost.
Since the damaged layer 200 is formed within the high-resistance silicon carbide epitaxial layer 104 in the process of the second embodiment, the N-type silicon carbide substrate 100 can be left intact after the N-type silicon carbide substrate 100 and the semiconductor epitaxial substrate ES are separated from the damaged layer 200. Thus, the separated N-type silicon carbide substrate 100 can be reused, and the material cost is greatly reduced.
Next, referring to fig. 2E, a substrate via hole TSH is etched from the bottom of the semiconductor epitaxial substrate ES (e.g., on the side of the high-resistance silicon carbide epitaxial layer 104) by using the front-side source contact 108 as an etch stop layer until a portion of the front-side source contact 108 is exposed.
Then, referring to fig. 2F, a metallization process is performed to form a back contact metal layer 116 in the substrate via TSH. Thereafter, referring to fig. 2G, after the back contact metal layer 116 is formed, the wafer carrier 114 may be removed. In an embodiment, in the case of forming a semiconductor device, a subsequent process such as a singulation process may also be performed, but the present invention is not limited thereto.
Since the process of the second embodiment is to form the back contact metal layer 116 in the substrate through hole TSH after the substrate through hole TSH exposes a portion of the front source contact 108, direct contact between the front source contact 108 and the back contact metal layer 116 can be ensured, thereby improving electrical connection between front and back devices. If the method is applied to a radio frequency device, the radio frequency source impedance and the radio frequency front and back surface capacitance can be further improved, and the variation range of the radio frequency source impedance and the radio frequency front and back surface capacitance can be reduced.
Fig. 3A is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the invention.
Referring to fig. 3A, the semiconductor device 300 of the present embodiment includes a semiconductor substrate 310, at least one semiconductor device (not shown), a front side source contact 320, and a back side contact metal layer 330.
The semiconductor substrate 310 includes a high resistivity silicon carbide epitaxial layer 314 and a gallium nitride epitaxial layer 316. In the present embodiment, the semiconductor substrate 310 is a semiconductor substrate suitable for a Radio Frequency (RF) device.
The high-resistivity silicon carbide epitaxial layer 314 has a first surface 314a and a second surface 314b, wherein the first surface 314a is opposite to the second surface 314 b. In the present embodiment, the high-resistance silicon carbide epitaxial layer 314 further has a region 312 on the first surface 314a side. The region 312 is, for example, a region of poor quality grown during epitaxial growth of the high-resistance silicon carbide epitaxial layer 314. In one embodiment, the region 312 is, for example, a buffer layer, and the thickness t1 of the buffer layer may be less than 1.5 μm; in another embodimentThe semiconductor substrate may not have the region 312. The high resistance silicon carbide epitaxial layer 314 is, for example, semi-insulating silicon carbide (SI-SiC). In the present embodiment, the thickness t2 of the high-resistivity silicon carbide epitaxial layer 314 is, for example, between 20 μm and 50 μm, and the second surface 314b of the high-resistivity silicon carbide epitaxial layer 314 has an angle in the range of 0 ° +/-8 °, for example, in the range of 0 ° +/-5 °, preferably in the range of 0 ° +/-3 °, with respect to the (0001) plane. The micro-pipe density (MPD) of the high-resistance silicon carbide epitaxial layer 314 is less than 0.5ea/cm2Basal Plane Dislocation (BPD) less than 10ea/cm2And threading dislocation (TSD) less than 500ea/cm2. The high resistance silicon carbide epitaxial layer 314 has a resistance greater than 1E5 ohm-cm. The resistance change rate of the high-resistance silicon carbide epitaxial layer 314 is, for example, less than 50%, and the "resistance change rate" is a result of dividing the standard deviation of resistance by the average value of resistance.
A gallium nitride epitaxial layer 316 is formed on the second surface 314b of the high-resistance silicon carbide epitaxial layer 314, and a semiconductor device (not shown) is formed on the gallium nitride epitaxial layer 316. In the present embodiment, the thickness t3 of the gan epitaxial layer 316 is less than 2 μm, and the structure of fig. 3A can be fabricated by the method shown in the first embodiment or the second embodiment, and steps for removing the residual structure except the high-resistance sic epitaxial layer 314 can be added as required. The resulting gan epitaxial layer 316 was tested to have a full width at half maximum (FWHM) of the (002) plane of less than 100arcsec by X-ray diffraction analysis, confirming that an epitaxial film of excellent quality was grown.
In the present embodiment, the semiconductor substrate 310 has a substrate through hole TSH1, wherein an included angle θ 1 between a cross section of a sidewall of the substrate through hole TSH1 and the surface 316a of the gan epitaxial layer 316 is, for example, 45 ° to 90 °, and preferably 85 ° to 90 °. For example, as shown in fig. 3A, the angle θ 1 between the cross section of the sidewall of the substrate via TSH1 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 90 °. The depth D of the substrate via TSH1 is, for example, 10 μm to 200 μm. The substrate via TSH1 may be, for example, a circular substrate via or an oval substrate via. In one embodiment, if the substrate via TSH1 is a circular substrate via, the circular substrate via has a diameter of, for example, 10 μm to 85 μm; in another embodiment, if the substrate via TSH1 is an oval substrate via, the length of the minor axis multiplied by the length of the major axis of the oval substrate via is, for example, 10 μm 20 μm to 50 μm 120 μm. In fig. 3A, a cross-section of the substrate via TSH1 is illustrated as a profile of the same slope.
The front side source contact 320 is formed on the surface 316a of the gan epitaxial layer 316 and covers the substrate via TSH1 of the semiconductor substrate 310. The front side source contact 320 includes an adhesive layer 322, a barrier layer 324, and a highly conductive layer 326. An adhesive layer 322 is formed on the surface 316a of the gan epitaxial layer 316. The barrier layer 324 is formed on the surface of the adhesive layer 322. A highly conductive layer 326 is formed on the surface of the barrier layer 324. In the present embodiment, the adhesion layer 322 is made of, for example, Ti, TiW, TiN, Ta or TaN with a thickness of 2nm to 200 nm. The barrier layer 324 is made of, for example, Pt, Pd, or Mo with a thickness of between 2nm and 200 nm. The highly conductive layer 326 is made of, for example, Au, Al-Cu or Cu with a thickness of 50nm to 10 μm.
The back contact metal layer 330 is formed in the substrate via TSH1 of the semiconductor substrate 310 and is in direct contact with the front source contact 320. The back contact metal layer 330 includes an adhesive layer 332, a barrier layer 334 and a highly conductive layer 336. The adhesive layer 332 is formed on the surface of the substrate via TSH1, for example. The barrier layer 334 is formed on the surface of the adhesive layer 332, for example. The highly conductive layer 336 is formed on the surface of the barrier layer 334, for example. In the present embodiment, the adhesive layer 332 is made of, for example, Ti, TiW, TiN, Ta, or TaN with a thickness of 2nm to 200 nm. The barrier layer 334 is made of, for example, TiW, TiN, or TaN having a thickness of 2nm to 200 nm. The highly conductive layer 336 is made of, for example, Au, Al-Cu or Cu with a thickness of 50nm to 10 μm.
Fig. 3B is a cross-sectional view of another semiconductor device according to a third embodiment, wherein the same device symbols as those in fig. 3A are used to represent the same or similar components, and the same or similar components can also refer to the related description in fig. 3A, which is not repeated herein.
In fig. 3B, the cross-section of the substrate via TSH2 is illustrated as a trapezoidal profile. For example, the angle θ 2 between the cross section of the sidewall of the substrate via TSH2 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 45 °, and the cross section of the sidewall of the substrate via TSH2 has the same slope.
Fig. 3C is a cross-sectional view of another semiconductor device according to a third embodiment, wherein the same reference numerals as in fig. 3A are used to denote the same or similar components, and the same or similar components may also be referred to the related description of fig. 3A, and are not repeated herein.
In fig. 3C, the cross-section of the substrate via TSH3 is illustrated as a stepped profile. For example, the included angle θ 3 between the cross section of the sidewall of the substrate via TSH3 located in the gallium nitride epitaxial layer 316 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 90 °; the angle θ 3' between the cross section of the sidewall of the substrate via TSH3 located within the high-resistance silicon carbide epitaxial layer 314 and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 90 °. The maximum width L1 of the cross section of the substrate via TSH3 located within the gallium nitride epitaxial layer 316 is, for example, less than the maximum width L2 of the cross section of the substrate via TSH3 located within the high resistance silicon carbide epitaxial layer 314.
Fig. 3D is a cross-sectional view of another semiconductor device according to a third embodiment, wherein the same device symbols as those in fig. 3A are used to represent the same or similar components, and the same or similar components can also refer to the related description in fig. 3A, which is not repeated herein.
In fig. 3D, the cross-section of the substrate via TSH4 is illustrated as a stepped profile plus an inclined ramp profile. For example, the included angle θ 4 between the cross section of the sidewall of the substrate via TSH4 located in the gallium nitride epitaxial layer 316 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 60 °; the angle θ 4' between the cross section of the sidewall of the substrate via TSH4 located within the high-resistance silicon carbide epitaxial layer 314 and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 60 °. The maximum width L3 of the cross section of the substrate via TSH4 located within the gallium nitride epitaxial layer 316 is, for example, less than the maximum width L4 of the cross section of the substrate via TSH4 located within the high resistance silicon carbide epitaxial layer 314.
Fig. 3E is a cross-sectional view of another semiconductor device according to a third embodiment, wherein the same device symbols as those in fig. 3A are used to represent the same or similar components, and the same or similar components can also refer to the related description in fig. 3A, which is not repeated herein.
In fig. 3E, a cross-section of the substrate via TSH5 is illustrated as a profile of different slopes. For example, an angle θ 5 between a cross section of a sidewall of the substrate via TSH5 located in the gallium nitride epitaxial layer 316 and the surface 316a of the gallium nitride epitaxial layer 316 is, for example, 45 °; the angle θ 5' between the cross section of the sidewall of the substrate via TSH5 located within the high-resistance silicon carbide epitaxial layer 314 and the second surface 314b of the high-resistance silicon carbide epitaxial layer 314 is, for example, 60 °. The maximum width L5 of the cross section of the substrate via TSH5 located within the gallium nitride epitaxial layer 316 is, for example, less than the maximum width L6 of the cross section of the substrate via TSH5 located within the high resistance silicon carbide epitaxial layer 314.
In summary, the damaged layer is formed in the N-type silicon carbide substrate or the high-resistance silicon carbide epitaxial layer, so that gallium nitride with good crystallization quality can be grown, most of the N-type silicon carbide substrate can be retained due to the damaged layer, and can be reused, thereby reducing the substrate cost. In addition, the invention forms the back contact metal layer in the substrate through hole after forming the front source contact which covers the substrate through hole of the semiconductor substrate, thereby improving the electrical connection between the front device and the back device, improving the radio frequency source impedance and the radio frequency front-back capacitance, and reducing the variation range of the radio frequency source impedance and the radio frequency front-back capacitance.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (21)
1. A semiconductor device, comprising:
a semiconductor substrate having a substrate via, the semiconductor substrate comprising:
the high-resistance silicon carbide epitaxial layer is provided with a first surface and a second surface, and the first surface is opposite to the second surface; and
the gallium nitride epitaxial layer is formed on the second surface of the high-resistance silicon carbide epitaxial layer;
at least one semiconductor device formed on the gallium nitride epitaxial layer;
a front source contact formed on the surface of the gallium nitride epitaxial layer and covering the substrate through hole of the semiconductor substrate; and
and the back contact metal layer is formed in the substrate through hole of the semiconductor substrate and is directly contacted with the front source contact.
2. The semiconductor device according to claim 1, wherein the thickness of the high-resistance silicon carbide epitaxial layer is between 20 μm and 50 μm.
3. The semiconductor device of claim 1, wherein the front side source contact comprises:
an adhesive layer formed on the surface of the gallium nitride epitaxial layer;
the barrier layer is formed on the surface of the adhesion layer; and
and the high conductive layer is formed on the surface of the barrier layer.
4. The semiconductor device according to claim 3, wherein the adhesion layer comprises Ti, TiW, TiN, Ta, or TaN with a thickness of between 2nm and 200 nm; the barrier layer comprises Pt, Pd or Mo with the thickness of 2 nm-200 nm; the high conductive layer comprises Au, Al-Cu or Cu with the thickness of 50 nm-10 mu m.
5. The semiconductor device of claim 1, wherein the back contact metal layer comprises:
the adhesion layer is formed on the surface of the substrate through hole;
the barrier layer is formed on the surface of the adhesion layer; and
and the high conductive layer is formed on the surface of the barrier layer.
6. The semiconductor device according to claim 5, wherein the adhesion layer comprises Ti, TiW, TiN, Ta, or TaN with a thickness of between 2nm and 200 nm; the barrier layer comprises TiW, TiN or TaN with the thickness of 2 nm-200 nm; the high conductive layer comprises Au, Al-Cu or Cu with the thickness of 50 nm-10 mu m.
7. The semiconductor device according to claim 1, wherein an angle between a cross section of a sidewall of the substrate via hole and the surface of the gallium nitride epitaxial layer is between 45 ° and 90 °.
8. The semiconductor device according to claim 7, wherein an angle between a cross section of a sidewall of the substrate via hole and the surface of the gallium nitride epitaxial layer is between 85 ° and 90 °.
9. The semiconductor device according to claim 1, wherein the substrate via hole is a circular substrate via hole and has a diameter of 10 μm to 85 μm.
10. The semiconductor device according to claim 1, wherein the substrate via is an elliptical substrate via, and a length of a minor axis multiplied by a length of a major axis of the elliptical substrate via is 10 μ ι η x 20 μ ι η to 50 μ ι η x 120 μ ι η.
11. The semiconductor device according to claim 1, wherein a depth of the substrate via is between 10 μm and 200 μm.
12. The semiconductor device according to claim 1, wherein a cross section of the substrate via is a stepped profile, a stepped profile plus an inclined profile, a profile of the same slope, or a profile of different slopes.
13. A method for manufacturing a semiconductor device, comprising:
epitaxially growing a high-resistance silicon carbide epitaxial layer and a gallium nitride epitaxial layer on the first surface of the N-type silicon carbide substrate to obtain a semiconductor epitaxial substrate containing the high-resistance silicon carbide epitaxial layer and the gallium nitride epitaxial layer;
forming a front source contact on the surface of the gallium nitride epitaxial layer;
forming at least one semiconductor device on the gallium nitride epitaxial layer;
bonding a wafer carrier to the surface of the gallium nitride epitaxial layer after forming the front side source contact and the at least one semiconductor device;
applying a laser from a second surface of the N-type silicon carbide substrate opposite the first surface of the N-type silicon carbide substrate to form a damaged layer on the N-type silicon carbide substrate or the semiconductor epitaxial substrate;
separating the N-type silicon carbide substrate and the semiconductor epitaxial substrate from the damaged layer;
etching from the bottom of the semiconductor epitaxial substrate to form a substrate through hole by taking the front source contact as an etching stop layer until part of the front source contact is exposed; and
and carrying out a metallization process to form a back contact metal layer in the substrate through hole.
14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the front-side source contact comprises:
forming an adhesive layer on the surface of the gallium nitride epitaxial layer;
forming a barrier layer on the surface of the adhesion layer; and
and forming a high-conductivity layer on the surface of the barrier layer.
15. The method according to claim 13, wherein the step of forming the back contact metal layer comprises:
forming an adhesion layer on the surface of the substrate through hole;
forming a barrier layer on the surface of the adhesion layer; and
and forming a high-conductivity layer on the surface of the barrier layer.
16. The method for manufacturing a semiconductor device according to claim 13, wherein the first surface of the N-type silicon carbide substrate has an angle in a range of not more than 0 ° +/-8 ° with respect to a (0001) plane.
17. The method for manufacturing a semiconductor device according to claim 13, wherein a thickness change rate of the high-resistance silicon carbide epitaxial layer is 5% to 10%.
18. The method for manufacturing a semiconductor device according to claim 13, wherein the method for forming the damaged layer comprises: applying the laser into the N-type silicon carbide substrate from the second surface of the N-type silicon carbide substrate to form the damaged layer within the N-type silicon carbide substrate.
19. The method according to claim 18, further comprising, after separating the N-type silicon carbide substrate from the semiconductor epitaxial substrate: and removing the residual N-type silicon carbide substrate.
20. The method for manufacturing a semiconductor device according to claim 13, wherein the method for forming the damaged layer comprises: applying the laser light into the high-resistance silicon carbide epitaxial layer from the second surface of the N-type silicon carbide substrate to form the damaged layer within the high-resistance silicon carbide epitaxial layer.
21. The method for manufacturing a semiconductor device according to claim 13, further comprising, after the forming of the back contact metal layer: removing the wafer carrier; and performing a singulation process.
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| WO2013159083A1 (en) * | 2012-04-20 | 2013-10-24 | Ii-Vi Incorporated | LARGE DIAMETER, HIGH QUALITY SiC SINGLE CRYSTALS, METHOD AND APPARATUS |
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