TWI758562B - Semiconductor on insulator substrate and method for manufacturing the same - Google Patents

Abstract

The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

Description

Semiconductor substrate on insulating layer and method of forming the same

Embodiments of the present invention relate to a semiconductor-on-insulator substrate and a method for forming the same, and more particularly, to a single-crystal active layer that is substantially free of dislocation defects in the semiconductor-on-insulator substrate and a method for forming the same.

Integrated circuits are formed on semiconductor substrates, and after packaging, chips or microchips are formed. Conventional integrated circuits are formed on a base semiconductor substrate, and the substrate is composed of a semiconductor material such as silicon. In recent years, semiconductor-on-insulator substrates have been used as an alternative. The semiconductor-on-insulator substrate has a thin layer of active semiconductor material (eg, silicon), which is spaced from the underlying processing substrate by a layer of insulating material. The insulating material layer can electrically isolate the thin layer of active semiconductor material from the processing substrate to reduce device leakage current formed in the thin layer of active semiconductor material. Thin layers of active semiconductor materials may also provide other advantages, such as faster switching times, lower operating voltages, and smaller packaging.

An embodiment of the present invention provides a method for forming a semiconductor substrate on an insulating layer, comprising: epitaxially forming a silicon germanium layer on a sacrificial substrate; epitaxially forming a first active layer on the silicon germanium layer, and the first active layers have different compositions on the composition of the silicon germanium layer; bonding the first active layer to the dielectric layer on the first substrate; removing the sacrificial substrate and the silicon germanium layer; etching the first active layer to expose the outer side of the upper surface of the dielectric layer and epitaxially forming a second active layer on the first active layer to form a connected active layer, wherein the first active layer and the second active layer have substantially the same composition.

An embodiment of the present invention provides a method for forming a semiconductor substrate on an insulating layer, comprising: epitaxially forming a silicon germanium layer on a sacrificial substrate. A first active layer with a first thickness is epitaxially formed on the upper surface of the silicon germanium layer, and the first active layer includes a semiconductor material. The sacrificial substrate is turned over and the first active layer is bonded to the dielectric layer on the first substrate. Parts of the sacrificial substrate and the SiGe layer are removed, and the remaining part of the SiGe layer is left to cover the upper surface of the first active layer. The remaining portion of the SiGe layer and the upper portion of the first active layer are removed. A second active layer is formed on the first active layer, the first active layer and the second active layer have a combined second thickness, and the second thickness is greater than the first thickness.

An embodiment of the present invention provides a semiconductor-on-insulator substrate, comprising: a dielectric layer on the first substrate, wherein the outer edge of the dielectric layer is aligned with the outer edge of the first substrate. The active layer covers the first annular portion of the dielectric layer. and a second annular portion of the upper surface of the dielectric layer surrounding the first annular portion and extending to the outer edge of the dielectric layer. The active layer does not cover the second annular portion.

thk, thk ₁ , thk ₂ , 206, 302: thickness

100: Semiconductor substrate on insulating layer

102: The first substrate

104: Dielectric layer

104s, 106s, 108s, 202s, 204s: Upper surface

106: Active Layer

108: The first active layer

110: Second active layer

114: maximum width

116: Outside edge width

118: The first ring part

120: The second ring part

122: Lower part

124: Upper part

126: Crystal face shape

200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100: Cutaway view

202: SiGe layer

204: Sacrificial Substrate

304: Chart

602: Upper part

604: Residual SiGe layer

702: Thin Layer

802: Mask Layer

1002: Semiconductor Devices

1004: Interconnect structure

1006: Metal interconnect layer

1008: Interlayer Dielectric Structure

1102: Die

1104: Cutting Line

1200: Method

1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216: Steps

FIGS. 1A to 1C are cross-sectional views of a semiconductor substrate on an insulating layer in some embodiments of the present invention.

FIGS. 2, 3A-3B, and 4-11 are cross-sectional views of a method of forming a semiconductor-on-insulator substrate in some embodiments of the present invention.

FIG. 12 shows the formation of a semiconductor-on-insulator substrate in some embodiments of the present invention. flow chart of the method.

Different embodiments or examples provided by the embodiments of the present invention may implement different structures of the present invention. The examples of specific components and arrangements are intended to simplify the invention and not to limit it. For example, the description of forming the first member on the second member includes the two being in direct contact, or with other additional members interposed between them rather than being in direct contact. In addition, reference numerals may be repeated in various examples of the present disclosure, but these repetitions are only used to simplify and clarify the description, and do not mean that elements with the same reference numerals in different embodiments and/or arrangements have the same corresponding relationship.

In addition, spatially relative terms such as "below," "below," "under," "above," "upper," or similar terms may be used to simplify the description of an element relative to another element in the figures relation. Spatial relative terms can be extended to elements used in other orientations and are not limited to the orientation shown. Elements can also be rotated by 90° or other angles, so the directional term is only used to describe the direction in the illustration. Furthermore, the terms "first," "second," "third," "fourth," and similar terms are used for distinction only, and the terms may be used interchangeably in various embodiments. For example, when a certain unit (eg, an opening) is referred to as a "first unit" in some embodiments, it may be referred to as a "second unit" in other embodiments.

Semiconductor-on-insulator substrates are used in many modern radio frequency devices, such as silicon-based photonics and high-precision MEMS. Devices formed in a semiconductor-on-insulator substrate may have improved performance and smaller packages compared to devices formed in a base substrate. The active semiconductor material in the semiconductor substrate on the insulating layer can ideally have a relaxed single crystal lattice without defects and dislocations. This structure in active semiconductor material promotes more efficient current flow for buried semiconductor device.

One of the methods for forming a semiconductor-on-insulator substrate includes epitaxially growing a single-crystal silicon layer on a silicon germanium layer on a sacrificial substrate. The silicon germanium layer is then bonded to the oxide layer, which is otherwise bonded to the handle substrate. Then, the sacrificial substrate and the silicon germanium layer are removed by an etching process to retain the semiconductor-on-insulator substrate. substrate.

However, it is currently known that it is difficult to form a single crystal silicon layer on the silicon germanium layer with a desired thickness (such as the thickness required for radio frequency applications, ranging from approximately 75 nm to approximately 150 nm) due to the lattice mismatch of the silicon germanium layer. stress. For example, using a low germanium concentration silicon germanium layer, a thick single crystal layer can be formed on the sacrificial substrate. However, this method has poor control over the thickness of the single crystal silicon layer because the etching selectivity of the single crystal silicon layer is low. On the other hand, using a high-concentration SiGe layer has better control over the overall thickness variation of a single-crystal Si layer because a SiGe layer with a high germanium concentration has a higher etch selectivity than silicon. But this approach also makes the single-crystal silicon layer more prone to dislocation defects along the upper surface of the layer, because of the high stress caused by the lattice mismatch of the silicon-germanium layer. For example, epitaxial growth of a single crystal silicon layer with a thickness of 70 nm to 150 nm may generate dislocations along the upper surface of the single crystal silicon layer. The etch rate of the dislocation is higher than the etch rate of the remaining single crystal silicon layer, and a divot may be formed along the upper surface of the single crystal silicon layer. Voids will negatively affect device performance in semiconductor-on-insulator substrates.

In some embodiments of the present invention, a low-cost method can be used to fabricate a semiconductor-on-insulator substrate having a single crystal active layer that is substantially free of dislocation defects. The above method includes epitaxially forming a silicon germanium layer on a sacrificial substrate. The active layer is epitaxially formed on the SiGe layer, and the composition of the active layer is different from that of the SiGe layer. flip A sacrificial substrate is attached, and the active layer is bonded to the upper surface of the dielectric layer on the first substrate. The sacrificial substrate and the SiGe layer are removed, followed by selective epitaxial growth to increase the thickness of the active layer. After the silicon germanium layer is removed, the thickness of the active layer is increased by selective epitaxial growth, and dislocation defects will not be generated in the active layer when the thickness of the active layer is increased. In addition, the SiGe layer with high germanium concentration has good etch selectivity, which can improve the overall thickness variation of the active layer.

FIG. 1A is a cross-sectional view of an on-insulator substrate having a substantially dislocation defect-free single crystal active layer in some embodiments.

The semiconductor-on-insulator substrate 100 includes a first substrate 102 covering a dielectric layer 104 . For example, the first substrate 102 can be a base silicon substrate in the form of a dish-shaped substrate. In some embodiments, the thickness of the first substrate 102 is between approximately 200 μm and approximately 1000 μm. For example, the dielectric layer 104 can be or can include silicon oxide, silicon carbide, silicon nitride, silicon-rich oxide, or the like.

The active layer 106 is directly on the dielectric layer 104 . The active layer 106 is disposed on the dielectric layer 104 . In some embodiments, the active layer 106 has a thickness thk. In some embodiments, the thickness thk of the active layer 106 is between approximately 70 nm and approximately 150 nm. In some embodiments, the thickness thk of the active layer 106 may be up to about 2000 nm. The active layer 106 has a relaxed single crystal lattice and is substantially free of dislocation defects. In some embodiments, the active layer 106 may comprise single crystal silicon. In other embodiments, the active layer 106 may comprise different semiconductor materials. In some embodiments, the active layer 106 may also be a semiconductor compound composed of two or more different elements. For example, these elements may form binary alloys (eg, gallium arsenide), ternary alloys (eg, indium gallium arsenide or aluminum gallium arsenide), or quaternary alloys (eg, aluminum indium gallium phosphide).

The active layer 106 has a maximum width 114 defined by the sidewalls, and a lateral outer edge width 116 is spaced between the sidewalls and the outer edge of the dielectric layer 104 . Since there is a lateral distance between the dielectric layer 104 and the active layer 106 , the upper surface of the dielectric layer 104 is exposed. In some embodiments, the outer edge width 116 may be between approximately 1 mm and approximately 2 mm.

FIG. 1B shows a top view of the semiconductor-on-insulator substrate 100 of FIG. 1A. As shown in FIG. 1B , the active layer 106 covers the first annular portion 118 of the upper surface 104s of the dielectric layer 104 . The outermost edge of the sidewall of the active layer 106 defines the inner boundary of the second annular portion of the upper surface of the dielectric layer 104 . The second annular portion 120 surrounds the first annular portion 118 and extends laterally across the outer edge width 116 to the outermost edges of the dielectric layer 104 and the first substrate 102 . The active layer 106 does not cover the second annular portion 120 , and the second annular portion 120 is exposed on the upper surface 104s of the dielectric layer 104 .

As shown in FIG. 1C , the sidewall of the active layer 106 (in cross-sectional view) includes a lower portion 122 and an upper portion 124 . The underside portion 122 has a substantially linear profile extending vertically upward from the dielectric layer 104 . The upper portion 124 has a bevel profile, and its crystal plane shape 126 slopes inward toward the upper surface 106s of the active layer 106 . The width of the upper surface 106 s of the active layer 106 is smaller than the maximum width 114 of the active layer 106 . In some embodiments, the epitaxial growth of the active layer 106 can make the sidewall of the active layer 106 and the upper portion 124 thereof have the crystal plane shape 126 . In some embodiments, the crystallographic structure of crystal face shape 126 may be Miller index (1,1,1). In other embodiments, the crystallographic structures of the crystal face shapes 126 may be different Miller indices (such as (1,1,0), (0,0,1), or other values).

In this way, the semiconductor-on-insulator substrate according to the embodiment of the present invention 100 has an active layer 106, which is a contiguous active layer of semiconductor material, having a substantially relaxed lattice structure and substantially no defects, and having a thickness of up to 150 nm or more.

FIGS. 2 to 11 are cross-sectional views corresponding to a method of forming a semiconductor-on-insulator structure in some embodiments, and the semiconductor-on-insulator structure has a single crystal active layer substantially free of dislocation defects. This approach results in a good overall thickness variation for the final active layer. For example, the total thickness variation of the final active layer may be less than about 4 nm. Although FIGS. 2-11 are used to illustrate the method, it should be understood that the structures of FIGS. 2-11 are not limited to being formed in the illustrated method, but may be independent of the method.

As shown in the cross-sectional view 200 of FIG. 2 , a SiGe layer 202 is epitaxially formed on the upper surface 204s of the sacrificial substrate 204 . For example, the sacrificial substrate 204 may be a base silicon structure in the form of a dish-shaped substrate. For example, the diameter of the substrate can be 1 inch (25mm), 2 inches (51mm), 3 inches (76mm), 4 inches (100mm), 5 inches (130nm), 125mm (4.9 inches), 150mm (5.9 inches) , commonly called 6 inches), 200mm (7.9 inches, commonly called 8 inches), 300mm (11.8 inches, commonly called 12 inches), or 450mm (17.7 inches, commonly called 18 inches). In some embodiments, the sacrificial substrate 204 may have p-type doping (eg, p+ doping). In other embodiments, the sacrificial substrate 204 may have n-type doping. In some embodiments, the thickness of the sacrificial substrate 204 is between approximately 200 μm and approximately 1000 μm.

In some embodiments, the silicon germanium layer 202 can be directly formed on the sacrificial substrate 204, and the formation method can be an epitaxial growth process. In other embodiments, an additional semiconductor layer (not shown) having the same composition (eg, silicon) as the sacrificial substrate 204 may be formed on the sacrificial substrate 204 before the SiGe layer 202 is formed. In these embodiments, the additional semiconductor layer is doped (eg, p-type doped) compared to the sacrificial substrate 204 concentration is lower.

In various embodiments, the silicon germanium layer 202 may be formed by an epitaxial growth process, such as molecular beam epitaxy, chemical vapor deposition, or low pressure chemical vapor deposition. During the chemical vapor deposition process, the sacrificial substrate 204 can be exposed to one or more volatile gas precursors, which can decompose and react on the upper surface 204s of the sacrificial substrate 204 to create the SiGe layer 202 of the desired thickness 206 . In some embodiments, the thickness 206 of the silicon germanium layer 202 may be between approximately 20 nm and approximately 200 nm.

In some embodiments, the silicon germanium layer 202 may contain a substantially fixed atomic % of germanium throughout the thickness 206 . In some embodiments, the substantially fixed atomic % of germanium may be between approximately 10 atomic % and approximately 100 atomic %. In some embodiments, the substantially fixed atomic % of germanium may be between approximately 25 atomic % and approximately 35 atomic %. In other embodiments, the atomic % germanium of the silicon germanium layer 202 can vary with the thickness 206 , which can be achieved by changing the precursor gases in the deposition process of the silicon germanium layer 202 . For example, the gas precursors and process conditions selected at the beginning are favorable for the formation of high concentration of silicon and low concentration of germanium, which is conducive to the formation of a lattice mismatch between the formed silicon germanium layer 202 and the upper surface of the underlying sacrificial substrate 204 . The degree of matching is reduced, and the adhesion to the sacrificial substrate 204 is improved. During the deposition of the SiGe layer, the gas precursors and process conditions may be gradually changed to increase the concentration of germanium (eg, atomic %) near the upper surface 202s of the SiGe layer 202 . The higher germanium concentration along the upper surface 202s of the silicon germanium layer 202 is beneficial to improve the etching selectivity in the subsequent etching process. In some embodiments, the germanium concentration (relative to the silicon concentration) of the sacrificial substrate 204 may be between about 0 to 20 atomic %. In some embodiments, the germanium concentration (relative to the silicon concentration) of the upper surface 202s of the silicon germanium layer 202 may be between approximately 10 atomic % and 100 atomic %.

As shown in the cross-sectional view 300 of FIG. 3A, the first active layer is epitaxially grown 108 on the silicon germanium layer 202. The material composition of the first active layer 108 is different from that of the SiGe layer 202 . For example, the first active layer 108 may include a semiconductor material such as silicon. In some embodiments, the first active layer 108 may include a single crystal silicon layer. The first active layer 108 can also be a semiconductor compound composed of two or more different elements. For example, these elements may form binary alloys (eg, gallium arsenide), ternary alloys (eg, indium gallium arsenide or aluminum gallium arsenide), or quaternary alloys (eg, aluminum indium gallium phosphide).

In various embodiments, the epitaxial growth method of the first active layer 108 may adopt vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, or the like. In some embodiments, the vapor phase epitaxy process can deposit silicon by reacting tetrachlorosilane with hydrogen gas at an elevated temperature (eg, about 1200° C.). In other embodiments, vapor phase epitaxy may use silanes, dichlorosilanes, and/or trichlorosilanes to deposit silicon at lower temperatures (eg, about 650° C.). This process does not produce by-products such as hydrogen chloride that can etch silicon. To control the growth rate of silicon, it can reach single crystal or polycrystalline silicon structure.

The first active layer 108 can be grown to a desired thickness 302 . In some embodiments, the thickness 302 of the first active layer 108 may be between approximately 20 nm and approximately 50 nm. The thickness 302 of the first active layer 108 can be adjusted according to the atomic % of germanium in the silicon germanium layer 202 , so the first active layer 108 can have the stress exerted by the silicon germanium layer 202 without generating dislocation defects.

For example, the graph 304 shown in FIG. 3B is the critical thickness as a function of germanium content (ie, beyond this thickness, defects are formed in the first active layer of epitaxial silicon). As shown in FIG. 3B, as the germanium content increases, the thickness that the first active layer 108 can have decreases. For example, when the germanium concentration is 0.3, the thickness of the first active layer 108 is approximately 20 nm without defects. At a germanium concentration of 0.2, the thickness of the first active layer 108 can be up to approximately 200 μm without defects.

As shown in the cross-sectional view 400 of FIG. 4 , the sacrificial substrate 204 is turned over and the first active layer 108 is bonded to the upper surface 104s of the dielectric layer 104 of the first substrate 102 . In some embodiments, a direct bonding process or a fusion bonding process may be employed. The direct bonding process relies on intermolecular forces such as Van der Waals forces, hydrogen bonding, or covalent bonding to form a bond between two mating surfaces. The bonding process does not require additional or intermediate layers between the surfaces to be bonded. In some embodiments, in order to increase the bonding strength, an oxide layer (not shown) can be formed on the upper surface of the dielectric layer 104 before bonding, and then the oxide layer is bonded to the mating surface of the first active layer 108 . Direct bonding can be performed at room temperature, followed by an elevated temperature to temper the bonded structure.

In some embodiments, the first substrate 102 is used to provide the required support for the structure and thus need not be present in the device structure or the interconnect structure. In many instances, the first substrate 102 is in the form of a dish-shaped substrate. In some embodiments, the diameter of the first substrate 102 and the sacrificial substrate 204 may be the same. The first substrate 102 may include a base silicon substrate, and the thickness may be between approximately 300 nm and approximately 1000 nm.

As shown in cross-sectional view 500 of FIG. 5 , the sacrificial substrate 204 is removed after bonding to the first substrate 102 . In some embodiments, the removal method of the sacrificial substrate 204 may be an etching, mechanical polishing, and/or chemical mechanical planarization process. The etching process may include wet etching or dry etching. In some embodiments, the etching process may employ a wet etchant containing tetramethylammonium hydroxide. In other embodiments, the wet etchant may comprise a mixture of hydrofluoric acid, nitric acid, and acetic acid; potassium hydroxide; and/or a buffered oxide etchant. In some embodiments, the wet etching step includes thinning the sacrificial substrate 204 followed by chemical mechanical polishing to completely remove the sacrificial substrate 204 . In some embodiments, the thinning step includes a dry etching process.

As shown in cross-sectional view 600 of FIG. 6, the silicon germanium layer is partially removed 202. In some embodiments, the silicon germanium layer 202 may be partially removed to leave the residual silicon germanium layer 604 to cover the upper surface 108s of the first active layer 108 . In some embodiments, the wet etching process employs tetramethylammonium hydroxide or potassium hydroxide, which selectively removes the upper portion 602 of the silicon germanium layer 202 . When the etching rate of the etchant such as tetramethylammonium hydroxide to the underlying epitaxial material such as silicon is greater than the etching rate of the silicon germanium material, the wet etching process is terminated before reaching the upper surface 108s of the first active layer 108 , which would otherwise cause an undesirably high total thickness variation in the epitaxial material.

In some embodiments, the wet etching process for removing the silicon germanium layer 202 can also remove an additional semiconductor layer (not shown), and the doping concentration of the additional semiconductor layer is lower than that of the sacrificial substrate 204 . Due to the high etch selectivity of tetramethylammonium hydroxide to silicon and silicon germanium, eg, the etch rate of silicon is more than 20 times higher than that of silicon germanium, it provides good overall thickness variation when removing additional semiconductor layers .

As shown in the cross-sectional view 700 of FIG. 7, the remaining silicon germanium layer 604 is completely removed. In some embodiments, dry etching or wet etching may be employed to remove the residual silicon germanium layer. A wet etching method or a dry etching method can be selected to preferably etch the remaining silicon germanium layer 604 without etching the first active layer 108 . In some embodiments, the dry etching method may employ a hydrogen chloride etchant. In some embodiments, the temperature of the etching process is between 500°C and 700°C, preferably close to 500°C. The low temperature process can reduce crystal variation or defect generation in the first active layer 108 . In other embodiments, a wet etch process containing hydrogen chloride may be used to completely remove the remaining silicon germanium layer 604 .

In some embodiments, dry etching or wet etching may continue until the remaining silicon germanium layer 604 is completely removed to remove the strained thin layer 702 from the upper surface 108s of the first active layer 108 (eg, etching to remove the first The strained portion of the active layer 108 share). By removing the thin layer 702, the crystalline structure of the first active 108 is transformed to be substantially relaxed. In some embodiments, the thickness of the removed thin layer 702 may be between approximately 5 nm and approximately 10 nm. In some embodiments, the thickness of the first active layer 108 reduced by removing the thin layer 702 may be between approximately 10 nm and approximately 40 nm.

In some embodiments, an initial cleaning process is performed prior to removing the residual SiGe layer 604 . The initial cleaning process removes native oxide in the remaining silicon germanium layer 604 from the process that partially removed the silicon germanium layer 202 . In some embodiments, the cleaning process may include a plasma-assisted dry etch process that exposes the residual SiGe layer 604 to the plasma and by-products of hydrogen, nitrogen trifluoride, and ammonia simultaneously. In some embodiments, the temperature of the cleaning process may be less than 400° C. to reduce crystal changes and defects in the first active layer 108 .

As shown in the cross-sectional view 800 of FIG. 8 , the first active layer 108 is selectively etched to define the outermost sidewalls and expose the outer edge width 116 of the upper surface 104s of the dielectric layer 104 . In some embodiments, the mask layer 802 may be formed on the top surface 108s of the first active layer 108 on the dish-shaped first annular portion 118 thereof. The mask layer 802 may extend radially from the upper surface 108s of the first active layer 108 to cover the outer radius of the first annular portion 118 to expose the outer edge of the first active layer 108 to be etched. In some embodiments, the mask layer 802 may include organic materials (eg, photoresist, amorphous carbon, siloxane-based materials, or the like), or inorganic materials (eg, silicon oxide, silicon nitride, nitride) titanium, or the like). In some embodiments, the outer edge width 116 of the dielectric layer may be between 1 mm and about 2 mm. In some embodiments, the process of selectively etching the first active layer 108 to expose the outer edge width 116 may use an etchant including hydrogen chloride or tetramethylammonium hydroxide.

Selectively etch the first active layer 108 to expose the outer edge width The method of 116 can effectively reduce the total thickness variation of the first active layer 108 . The etching process used to remove the silicon germanium layer 202 and the thin layer 702 of the first active layer 108 may result in more erosion and thus more thickness variation at the outer edges of the first active layer 108 . Etching the outer edge of the first active layer 108 can remove locally high thickness variation material, so that the overall thickness variation of the first active layer 108 is low. The above steps also remove wafer defects along the edges of the first active layer 108 from the step of bonding the first active layer 108 to the dielectric layer 104 .

As shown in the cross-sectional view 900 of FIG. 9 , the second active layer 110 is epitaxially grown on the first active layer 108 . The crystal structure (eg, lattice) of the second active layer substantially repeats the crystal structure of the first active layer 108 . Since the first active layer 108 is a relaxed layer substantially free of dislocation defects, the second active layer 110 can be formed to a desired thickness without dislocation defects. In some embodiments, the second active layer 110 and the first active layer 108 together form the connected active layer 106 . In some embodiments, the active layer 106 includes silicon. In some embodiments, the total thickness of the active layer 106 is between about 70 nm to 150 nm. In other embodiments, the total thickness of the active layer 106 is greater than 150 nm.

The first active layer 108 or the second active layer 110 does not cover the outer edge of the upper surface 104s of the dielectric layer 104 . After the mask layer 802 is peeled off, the first active layer 108 (indicated by the dotted line) has a flat upper surface and substantially vertical sidewalls on the substrate, and the exposed outer edge width 116 of the upper surface 104s of the dielectric layer 104 will be around the first active layer 108 . The outer edge width 116 extends laterally from the outermost edge of the sidewall of the first active layer 108 to the outer edge of the dielectric layer 104 .

The formation method of the second active layer 110 may be a selective epitaxial growth process, which uses the first active layer 108 as a seed crystal for growing the second active layer 110 . In some embodiments, the first active layer 108 may comprise silicon, and the selective epitaxial growth process may epitaxially grow silicon on the exposed surface of the first active layer 108 . In some embodiments, the selective epitaxial growth process may include precursor gases including dichlorosilane with (or without) hydrogen chloride; or silane, disilane, or trisilane with (or without) hydrogen chloride. In some embodiments, a cyclic deposition-etch approach may be employed to achieve selective epitaxial growth. This process can use silane-based precursor gas, and the process temperature can be lower than 550 ℃.

In some embodiments, the epitaxially grown second active layer 110 may have the crystal plane shape 126 of the upper side portion 124 of the sidewall of the active layer 106 . In some embodiments, the crystallographic orientation of the crystal plane shape 126 may be a value defined by the Miller index, such as (1,1,1). In other embodiments, the crystallographic orientation of the crystal plane shape 126 may be other values defined by the Miller index, such as (1,1,0), (0,0,1), or other values. The selective epitaxy of the second active layer 110 is generally in an anisotropic mode, that is, the ratio between the extension in the vertical direction and the extension in the lateral direction is about 1:1. In some embodiments, the selective epitaxial growth process produces a single crystal layer of silicon, such as is known as an epitaxial lateral overgrowth layer.

The lateral growth of the second active layer 110 causes the second active layer 110 to grow on the sidewall of the first active layer 108 adjacent to the exposed outer edge width 116 of the upper surface 104s of the dielectric layer 104 . Although there are some small reductions in the exposed outer edge width 116, these reductions are on the order of nanometers, approximately equal to the grown thickness of the second active layer 110 (eg, thickness thk ₂ minus thickness thk ₁ ). The remaining exposed outer edge width 116 is substantially between about 1 mm and 2 mm.

In some embodiments, the cross-sectional profile sidewall of the active layer 106 has a lower portion 122 and an upper portion 124 . The lower side lower portion 122 has a self-dielectric layer 104 is a substantially linear profile extending vertically upwards. The upper portion 124 has a bevel profile, and its crystal plane or tapered shape slopes inwardly toward the upper surface 106s of the active layer 106 . The width of the upper surface 106 s of the active layer 106 is smaller than the maximum width 114 of the active layer 106 . In some embodiments, the orientation and cross-sectional profile of the upper sidewall portion 124 of the active layer 106 vary depending on the specific material cost and lattice properties of the first active layer and the second active layer. In some embodiments, the crystalline structure of the active layer 106 can be represented by the Miller index, which has various values including (1, 1, 1).

As shown in cross-sectional view 1000 of FIG. 10 , a plurality of semiconductor devices 1002 are formed in active layer 106 . In various embodiments, the plurality of semiconductor devices 1002 may include MOSFETs and/or other field effect transistors. Although not shown, the transistors may be other forms, such as fin field effect transistor devices, bipolar junction transistors, or other transistors.

Next, the interconnect structure 1004 can be fabricated on the upper surface 106s of the active layer 106 . The interconnect structure includes a plurality of metal interconnect layers 1006 (eg, metal lines, vias, and contacts) coupled to the plurality of semiconductor devices 1002 , and an interlayer dielectric structure 1008 surrounds the metal interconnect layers 1006 . In some embodiments, the metal interconnect layer 1006 may include copper, tungsten, aluminum, gold, titanium, or titanium nitride. In some embodiments, the interlayer dielectric structure 1008 may comprise silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a very low-k dielectric material, some other dielectric material, or any combination of the above.

As shown in the cross-sectional view 1100 of FIG. 11 , the substrate is cut from the first substrate 102 to form a plurality of individual dies 1102 . In some embodiments, the method of dicing individual dies from the first substrate 102 may cut or break along the dicing lines 1104, such as mechanical dicing using a dicing saw, laser dicing, or other feasible dicing methods Law.

FIG. 12 is a flowchart of some embodiments of a method of forming a semiconductor-on-insulator substrate.

The method 1200 described herein is described as a series of steps or events, but it should be understood that the order of the steps or events is only used to illustrate rather than limit the embodiments of the present invention. For example, some steps may be performed in a different order, and/or some steps may be performed concurrently with other steps, in a different order than described herein. Furthermore, not all steps are required for one or more of the embodiments described herein. Furthermore, one or more of the steps described herein may be performed in one or more separate steps and/or aspects.

In step 1202, a silicon germanium layer is epitaxially formed on the sacrificial substrate. The cross-sectional view 200 shown in FIG. 2 corresponds to some embodiments of step 1202 .

In step 1204, a first active layer is epitaxially formed on the silicon germanium layer, and the composition of the first active layer is different from that of the silicon germanium layer. The cross-sectional view 300 shown in FIG. 3 corresponds to some embodiments of step 1204 .

In step 1206, the sacrificial substrate is turned over and the first active layer is bonded to the upper surface of the dielectric layer on the first substrate. The cross-sectional view 400 shown in FIG. 4 corresponds to some embodiments of step 1206 .

In step 1208, the sacrificial substrate and the silicon germanium layer are removed. The cross-sectional views 500 , 600 , and 700 shown in FIGS. 5-7 correspond to some embodiments of step 1208 .

In step 1210, the first active layer is etched to define outermost sidewalls and to expose outer edges of the upper surface of the dielectric layer. The cross-sectional view 800 shown in FIG. 8 corresponds to some embodiments of step 1210 .

In step 1212, a second active layer is epitaxially formed on the first active layer, and the first active layer or the second active layer does not cover the upper surface of the dielectric layer Side edge width. The first active layer and the second active layer together form a connected active layer. The cross-sectional view 900 shown in FIG. 9 corresponds to some embodiments of step 1212 .

In step 1214, a plurality of semiconductor devices are formed in the first active layer and the second active layer, and interconnect structures are formed on the semiconductor devices. The cross-sectional view 1000 shown in FIG. 10 corresponds to some embodiments of step 1214 .

In step 1216, a dicing process is performed to form a plurality of separate dies. The cross-sectional view 1100 shown in FIG. 11 corresponds to some embodiments of step 1216 .

In conclusion, some embodiments of the present invention relate to a method for forming a semiconductor-on-insulator substrate having a single crystal active layer that is thick (greater than 75 nm) and substantially free of dislocation defects. The above method provides an active layer with good thickness variation (eg, less than 4 nm).

As mentioned above, some embodiments of the present invention provide a method of fabricating a semiconductor-on-insulator substrate, including epitaxially forming a silicon germanium layer on a sacrificial substrate. The first active layer is epitaxially formed on the silicon germanium layer, and the composition of the first active layer is different from that of the silicon germanium layer. The first active layer is bonded to the dielectric layer on the first substrate. Remove the sacrificial substrate and the SiGe layer. The first active layer is etched to expose the outer edge of the upper surface of the dielectric layer. A second active layer is epitaxially formed on the first active layer to form a connected active layer, wherein the first active layer and the second active layer have substantially the same composition.

In some embodiments, neither the first active layer nor the second active layer covers the outer edge width of the upper surface of the dielectric layer in the above method.

In some embodiments, the connected active layer in the above method comprises silicon.

In some embodiments, the thickness of the active layer connected in the above method is The degree is between approximately 70 nm to approximately 150 nm.

In some embodiments, the connected active layers in the above method include a lower portion having sidewalls extending vertically, and an upper portion having a crystal plane shape inclined inwardly toward the upper surface of the connected active layer.

In some embodiments, the crystal structure of the connected active layers in the above method includes a Miller index of (1, 1, 1).

In some embodiments, the silicon germanium layer in the above method includes a germanium concentration ranging from 10 atomic % to 100 atomic %.

In some embodiments, the silicon germanium layer in the above method includes a germanium concentration between about 25 atomic % and 35 atomic %.

In some embodiments, the step of removing the silicon germanium layer in the above method includes partially removing the silicon germanium layer, leaving a residual portion to cover the first active layer, and simultaneously exposing the residual portion to hydrogen, three Nitrogen fluoride, and ammonia plasma and by-products to clean residual parts.

In some embodiments, the above method includes removing residual portions of the silicon germanium layer with a hydrogen chloride etch process.

In some embodiments, the above method includes removing a portion of the first active layer after removing the silicon germanium layer and before epitaxially forming the second active layer.

In some embodiments, in the above method, the thickness of the first active layer is grown to be between about 20 nm to 50 nm, and the thickness of the silicon germanium layer is grown to be between about 20 nm to about 200 nm.

In addition, other embodiments of the present invention provide methods including epitaxially forming a silicon germanium layer on a sacrificial substrate. A first active layer with a first thickness is epitaxially formed on the upper surface of the silicon germanium layer, and the first active layer includes a semiconductor material. Flip the sacrificial base board, and the first active layer is bonded to the dielectric layer on the first substrate. Parts of the sacrificial substrate and the SiGe layer are removed, and the remaining part of the SiGe layer is left to cover the upper surface of the first active layer. The remaining portion of the SiGe layer and the upper portion of the first active layer are removed. A second active layer is formed on the first active layer, the first active layer and the second active layer have a combined second thickness, and the second thickness is greater than the first thickness.

In some embodiments, the above-described method of removing portions of the silicon germanium layer includes etching with tetramethylammonium hydroxide or potassium hydroxide.

In some embodiments, the above method includes etching the first active layer to define outermost sidewalls and exposing outer edges of a surface of the dielectric layer facing the first active layer.

In some embodiments, the method of removing the remaining portion of the silicon germanium layer includes etching with hydrogen chloride.

In some embodiments, the second active layer of the above method has an overall lower width along a lowermost surface of the second active layer, an upper overall width along an uppermost surface of the second active layer, and an overall lower width greater than the overall width of the upper side.

In addition, other embodiments of the present invention provide a semiconductor-on-insulator substrate including a dielectric layer on the first substrate, wherein the outer edge of the dielectric layer is aligned with the outer edge of the first substrate. The active layer covers the first annular portion of the dielectric layer. and a second annular portion of the upper surface of the dielectric layer surrounding the first annular portion and extending to the outer edge of the dielectric layer. The active layer does not cover the second annular portion.

In some embodiments, the height of the active layer of the semiconductor-on-insulator substrate is between about 70 nm and about 150 nm.

In some embodiments, the active layer of the semiconductor-on-insulator substrate includes a lower side portion having sidewalls extending vertically, and a crystal plane shape facing toward The upper part of the upper surface of the active layer which is inclined inward.

The features of the above-mentioned embodiments are helpful for those skilled in the art to understand the embodiments of the present invention. Those skilled in the art should understand that the embodiments of the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and/or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

thk ₁ , thk ₂ ‧‧‧Thickness

102‧‧‧First substrate

104‧‧‧Dielectric layer

104s, 106s‧‧‧Top surface

106‧‧‧Active Layer

108‧‧‧First Active Layer

110‧‧‧Second Active Layer

116‧‧‧Outer edge width

122‧‧‧Lower part

124‧‧‧Top part

126‧‧‧Crystal face shape

900‧‧‧Cross-sectional view

Claims (10)

A method for forming a semiconductor substrate on an insulating layer, comprising: epitaxially forming a silicon germanium layer on a sacrificial substrate; epitaxially forming a first active layer on the silicon germanium layer, and the composition of the first active layer is different from The composition of the silicon germanium layer; bonding the first active layer to a dielectric layer on a first substrate; removing the sacrificial substrate and the silicon germanium layer; etching the first active layer to expose the dielectric layer The outer edge of the upper surface; epitaxially forms a second active layer on the first active layer to form a connected active layer, the connected active layer covers an annular portion of the dielectric layer, wherein the first active layer An active layer and the second active layer have substantially the same composition; transistors are formed along a top surface of the connected active layer and directly above the annular portion; and the A plurality of interconnect layers are formed in a dielectric structure on the top surface, wherein the interconnect layers are respectively disposed over the transistors and completely disposed directly over the annular portion. The method for forming a semiconductor-on-insulator substrate according to claim 1, wherein neither the first active layer nor the second active layer covers the outer edge width of the upper surface of the dielectric layer. The method for forming a semiconductor-on-insulator substrate as described in claim 1 or 2, wherein the connected active layer comprises a lower portion with sidewalls extending vertically, and an upper surface of the connected active layer with a crystal plane shape Inwardly sloping upper part. The method for forming a semiconductor substrate on an insulating layer as described in claim 3, wherein the crystal structure of the connected active layer includes a Miller index of (1,1,1). The method for forming a semiconductor-on-insulator substrate as described in claim 1 or 2 of the claimed scope, wherein the step of removing the silicon-germanium layer comprises partially removing the silicon-germanium layer and leaving a residual part to cover The first active layer, and the residual portion is exposed to hydrogen, nitrogen trifluoride, and ammonia plasma and by-products simultaneously to clean the residual portion. A method for forming a semiconductor substrate on an insulating layer, comprising: epitaxially forming a silicon germanium layer on a sacrificial substrate; epitaxially forming a first active layer with a first thickness on the upper surface of the silicon germanium layer, and the The first active layer includes a semiconductor material; the sacrificial substrate is turned over, and the first active layer is bonded to a dielectric layer on a first substrate; the sacrificial substrate and portions of the silicon germanium layer are removed, and leaving a residual part of the silicon germanium layer to cover the upper surface of the first active layer; removing the residual part of the silicon germanium layer and the upper side part of the first active layer; forming a second active layer On the first active layer, the first active layer and the second active layer have a combined second thickness, and the second thickness is greater than the first thickness, and the first active layer and the second active layer cover an annular portion of the dielectric layer; a plurality of transistors are formed along a top surface of the second active layer and directly above the annular portion; and a dielectric on the top surface of the second active layer forming pluralities in the electrical structure An interconnection layer, wherein the interconnection layers are respectively disposed on the transistors and completely disposed directly above the annular portion. The method for forming a semiconductor substrate on an insulating layer as described in item 6 of the claimed scope, further comprising: etching the first active layer to define an outermost sidewall and exposing the dielectric layer facing the first active layer an outer edge of the surface. The method for forming a semiconductor-on-insulator substrate as described in claim 6 or 7, wherein the second active layer has a lower overall width along the lowermost surface of the second active layer, and along the second active layer The uppermost surface of the active layer has an upper total width, and the lower total width is greater than the upper total width. A semiconductor substrate on an insulating layer, comprising: a dielectric layer located on a first substrate, wherein the outer edge of the dielectric layer is aligned with the outer edge of the first substrate; an active layer covering an outer edge of the dielectric layer a first annular portion, wherein the sidewall of the active layer has a vertical lower portion and an inclined upper portion, and the lower portion contacts the upper portion, wherein the active layer has a relaxed single crystal The lattice is substantially free of defects, and the thickness of the active layer is between approximately 70 nm and approximately 150 nm; a second annular portion of the upper surface of the dielectric layer surrounds the first annular portion and extends to an outer edge of the dielectric layer, wherein the active layer does not cover the second annular portion; a plurality of transistors disposed along a top surface of the active layer just above the first annular portion; and a plurality of transistors interconnect layer, a dielectric disposed on the top surface of the active layer In the structure, the interconnect layers are respectively disposed on the transistors and completely disposed directly above the first annular portion. The semiconductor-on-insulator substrate of claim 9, wherein a distance between the first annular portion and an outer edge of the dielectric layer is between approximately 1 mm and approximately 2 mm.

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