KR102392556B1 - Method of manufacturing semiconductor devices - Google Patents

Abstract

The present invention provides the steps of forming an epitaxial layer and a ground pad on the front surface of a substrate, forming a via hole exposing the ground pad by etching the substrate and a region of the epi layer, and the rear surface of the substrate and the ground Forming a plating layer for electrically connecting the pad, wherein the forming of the plating layer includes a photoresist pattern that covers the back surface of the substrate and exposes the via hole on the inner bottom and inner wall surface of the via hole. Disclosed is a method of manufacturing a semiconductor device comprising: forming a first plating layer; and forming a second plating layer on the first plating layer and a rear surface of the substrate after removing the photoresist pattern.

Description

Method of manufacturing semiconductor devices

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a via hole in which a plating layer having a uniform thickness is formed.

High Electron Mobility Transistor (HEMT) based on AlGaN/GaN heterojunction structure has high breakdown electric field, high two-dimensional electron gas (2-DEG) concentration, high electron mobility, and high saturation. Because it has speed and excellent thermal characteristics, it is widely used in fields that require high frequency, high voltage and high power, such as radar or wireless communication fields.

In the case of manufacturing a high-frequency single integrated circuit (MMIC) using a high electron mobility transistor (HEMT), a via hole is formed on the back side of the substrate through an etching process for improved high-frequency characteristics, smooth heat dissipation, and stable grounding. should be formed and the plating process should be performed to electrically connect the rear surface of the substrate and the ground pad on the front surface of the substrate.

The present invention forms a plating layer of uniform thickness inside a via hole and on the rear surface of a substrate to enable stable electrical connection between the ground pad formed on the front surface of the substrate and the rear surface of the substrate, thereby improving the reliability of the semiconductor device. An object of the present invention is to provide a method for manufacturing

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those of ordinary skill in the art from the description below.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an epitaxial layer and a grounding pad on the entire surface of a substrate, etching the substrate and a region of the epitaxial layer to form a via hole exposing the grounding pad, and and forming a plating layer electrically connecting the back surface of the substrate and the ground pad. The forming of the plating layer includes forming a first plating layer on the inner bottom and inner wall surfaces of the via hole by using a photoresist pattern that covers the back surface of the substrate and exposes the via hole, and removing the photoresist pattern and then forming a second plating layer on the first plating layer and the rear surface of the substrate.

Through the method of manufacturing a semiconductor device according to the present invention, by maintaining a uniform thickness of the plating layer formed inside the via hole and on the rear surface of the substrate, a stable electrical connection between the ground pad formed on the front surface of the substrate and the rear surface of the substrate is possible, There is an effect that the reliability of the semiconductor device is improved.

1 to 15 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in stages.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is not limited to the embodiments disclosed below, but may be implemented in various forms and various modifications and changes may be made. However, it is provided in order to complete the disclosure of the present invention through the description of the present embodiment, and to fully inform those of ordinary skill in the art to which the present invention pertains to the scope of the invention. In the accompanying drawings, for convenience of explanation, the size is enlarged than the actual size, and the ratio of each component may be exaggerated or reduced.

The terminology used herein is for the purpose of describing the embodiment and is not intended to limit the present invention. Also, unless otherwise defined, terms used herein may be interpreted as meanings commonly known to those of ordinary skill in the art.

In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprises' and/or 'comprising' refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

When a layer is referred to herein as being 'on' another layer, it may be formed directly on top of the other layer, or a third layer may be interposed therebetween.

Although terms such as first and second are used herein to describe various regions, layers, and the like, these regions and layers should not be limited by these terms. These terms are only used to distinguish one region or layer from another. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment. The embodiments described and illustrated herein also include complementary embodiments thereof. Parts indicated with like reference numerals throughout the specification indicate like elements.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail step by step with reference to FIGS. 1 to 15 .

1 to 15 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in stages. In the semiconductor device of FIGS. 1 to 15 , a downward-facing surface is referred to as a front surface, and an upward-directed surface is referred to as a rear surface.

Referring to FIG. 1 , a first epitaxial layer 101 , a second epitaxial layer 102 , and a ground pad 103 may be sequentially formed on the front surface 100a of the substrate 100 . For example, the substrate 100 may be formed of silicon carbide (SiC). For example, the substrate 100 may have a disk shape. For example, the substrate 100 may be a wafer having a flat zone in one area. For example, the first epitaxial layer 101 may be formed of gallium nitride (GaN). For example, the second epitaxial layer 102 may be formed of aluminum gallium nitride (AlGaN). For example, the first epitaxial layer 101 and the second epitaxial layer 102 may be formed by a metal organic chemical vapor deposition (MOCVD) method. A seed layer (not shown) may be interposed between the substrate 100 and the first epitaxial layer 101 . The seed layer (not shown) may enable epitaxial growth of the first epitaxial layer 101 . The first epitaxial layer 101 and the second epitaxial layer 102 may have a heterojunction structure. For example, the first epitaxial layer 101 and the second epitaxial layer 102 may form a two-dimensional electron gas (2-DEG) layer through an AlGaN/GaN heterojunction structure. The ground pad 103 may be formed on a partial region of the front surface of the second epitaxial layer 102 . For example, the ground pad 103 may be formed of nickel (Ni) or gold (Au).

Referring to FIG. 2 , an adhesive layer (not shown) covering the second epitaxial layer 102 and the ground pad 103 may be formed. For example, the adhesive layer (not shown) may be formed of wax. The carrier wafer 104 may be adhered on an adhesive layer (not shown) to cover the second epitaxial layer 102 and the ground pad 103 . For example, the carrier wafer 104 may be formed of the same material as the substrate 100 . For example, the carrier wafer 104 may be formed of silicon carbide (SiC). The carrier wafer 104 may perform a subsequent process on the back surface 100b of the substrate 100 . After the carrier wafer 104 is adhered, a back grinding process may be performed on the back surface 100b of the substrate 100 to reduce the thickness of the substrate 100 .

Referring to FIG. 3 , the first photoresist pattern 105 may be formed on a partial region of the rear surface 100b of the substrate 100 . The first photoresist pattern 105 may be manufactured through a photolithography process. The first photoresist pattern 105 may define a region in which a via hole is to be formed.

Referring to FIG. 4 , the first base metal layer 106 may be deposited on the rear surface 100b of the substrate 100 and the rear surface of the first photoresist pattern 105 . For example, the first base metal layer 106 may be made of a material such as titanium (Ti) or gold (Au) and deposited to a thickness of 100 Å to 200 Å. For example, the first base metal layer 106 may be deposited by a sputtering method.

Referring to FIG. 5 , the metal mask layer 107 may be formed on the rear surface of the first base metal layer 106 . The metal mask layer 107 may be formed in a region where the first photoresist pattern 105 is not formed. For example, the metal mask layer 107 may be formed of nickel (Ni). For example, the metal mask layer 107 may be formed to a thickness of 5 μm to 7 μm. For example, the metal mask layer 107 may be formed by a sputtering method.

5 and 6 , the metal mask layer 107 may be used as an etch mask to remove the first photoresist pattern 105 . At this time, the first base metal layer 106 formed on the rear surface of the first photoresist pattern 105 may also be removed. The first base metal layer 106 and the first photoresist pattern 105 may be removed to expose a portion of the back surface 100b of the substrate 100 .

Referring to FIG. 7 , a portion of the substrate 100 may be etched by using the metal mask layer 107 as an etching mask. For example, when the substrate 100 is formed of silicon carbide (SiC), a portion of the substrate 100 may be etched through a dry etching process such as etching using an inductively coupled plasma (ICP). A portion of the substrate 100 may be etched to expose a portion of the rear surface of the first epitaxial layer 101 .

7 and 8 , the metal mask layer 107 and the first base metal layer 106 may be removed. For example, the metal mask layer 107 may be removed using nitric acid.

Referring to FIG. 9 , after the removal of the metal mask layer 107 is completed, a portion of the first epitaxial layer 101 and the second epitaxial layer 102 may be etched to form a via hole VH. For example, the first epitaxial layer 101 and the second epitaxial layer 102 may be etched through a dry etching process such as etching using an inductively coupled plasma (ICP). A portion of the first epitaxial layer 101 and the second epitaxial layer 102 may be etched to expose a rear surface of the ground pad 103 . In the etching process of the first epitaxial layer 101 and the second epitaxial layer 102 , the ground pad 103 may be used as an etch stop layer.

Referring to FIG. 10 , the second base metal layer 108 may be deposited to cover the rear surface of the semiconductor device on which the etching process is completed. The second base metal layer 108 may be deposited inside the via hole VH and on the rear surface 100b of the substrate 100 . The second base metal layer 108 may be deposited on the inner bottom of the via hole VH and the inner wall surface of the via hole VH. For example, the second base metal layer 108 may be made of a material such as titanium (Ti) or gold (Au) and deposited to a thickness of 1000 Å to 2000 Å. For example, the second base metal layer 108 may be deposited by a sputtering method.

Referring to FIG. 11 , the second photoresist pattern 110 may be formed on a partial region of the rear surface of the second base metal layer 108 . The second photoresist pattern 110 may be manufactured through a photolithography process. The second photoresist pattern 110 may expose the second base metal layer 108 inside the via hole VH. The second photoresist pattern 110 may have a negative optical characteristic in which the exposed region remains. When the second photoresist pattern 110 has a positive optical characteristic, in order for the second photoresist pattern 110 to remain only on the back surface 100b of the substrate 100, exposure may be required inside the via hole VH. .

Referring to FIG. 12 , a first plating layer 109a may be formed in the via hole VH. The first plating layer 109a may be formed on an inner bottom of the via hole VH and an inner wall surface of the via hole VH. The first plating layer 109a may be formed by a first thickness T1.

Referring to FIG. 13 , after the formation of the first plating layer 109a inside the via hole VH is completed, the second photoresist pattern 110 described with reference to FIG. 11 may be removed.

12 to 14 , after the removal of the second photoresist pattern 110 is completed, a second plating layer 109b may be formed. The second plating layer 109b may be formed inside the via hole VH and on the rear surface 100b of the substrate 100 . In the process of forming the second plating layer 109b, the rate at which the second plating layer 109b is formed on the rear surface 100b of the substrate 100 is higher than the rate at which the second plating layer 109b is formed inside the via hole VH. can be fast That is, the second plating layer 109b may be formed thicker on the back surface 100b of the substrate 100 than inside the via hole VH. The thickness of the first plating layer 109a and the second plating layer 109b inside the via hole VH may be the second thickness T2. The thickness of the second plating layer 109b formed on the rear surface 100b of the substrate 100 may be a third thickness T3. The second thickness T2 and the third thickness T3 may be substantially the same. The second thickness T2 and the third thickness T3 may be thicker than the first thickness T1 . By adjusting the plating time in the steps shown in FIGS. 12 and 14 , the first thickness T1 , the second thickness T2 , and the third thickness T3 may be adjusted. When the first plating layer 109a and the second plating layer 109b are formed, the ground pad 103 formed on the rear surface 100b of the substrate 100 and the front surface 100a of the substrate 100 is the plating layer 109 . and the second base metal layer 108 may be electrically connected. Since the ground pad 103 formed on the rear surface 100b of the substrate 100 and the front surface 100a of the substrate 100 is electrically connected through the plating layer 109 having a uniform thickness, stable grounding of the semiconductor device is achieved. It may be possible.

Referring to FIG. 15 , after the formation of the second plating layer 109b is completed, the carrier wafer 104 described with reference to FIG. 2 may be removed.

Those of ordinary skill in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate
101: first epi layer
102: second epi layer
103: ground pad
104: carrier wafer
105: first photoresist pattern
106: first base metal layer
107: metal mask layer
108: second base metal layer
109: plating layer
110: second photoresist pattern
VH : Via hole

Claims (10)

forming an epitaxial layer and a ground pad on the front surface of the substrate;
forming a via hole exposing the ground pad by etching one region of the substrate and the epitaxial layer;
forming a base metal layer on a rear surface of the substrate inside and outside the via hole; and
forming a plating layer electrically connecting the rear surface of the substrate and the ground pad;
The step of forming the plating layer is:
forming a first plating layer on the inner bottom and inner wall surfaces of the via holes by using a photoresist pattern covering the rear surface of the substrate and exposing the via holes; and
and forming a second plating layer on the first plating layer and the rear surface of the substrate after removing the photoresist pattern,
The thickness of the second plating layer formed on the first plating layer is smaller than the thickness of the second plating layer formed on the rear surface of the substrate,
The thickness of the first and second plating layers formed inside the via hole is substantially the same as the thickness of the second plating layer formed outside the via hole,
A method of manufacturing a semiconductor device in which a sidewall of the photoresist pattern is aligned with a sidewall of the base metal layer inside the via hole.

delete delete The method of claim 1,
The epitaxial layer includes a first epitaxial layer and a second epitaxial layer sequentially formed on the front surface of the substrate,
The first epitaxial layer is formed of gallium nitride (GaN),
The second epitaxial layer is a method of manufacturing a semiconductor device formed of aluminum gallium nitride (AlGaN).
The method of claim 1,
The epitaxial layer is formed through a chemical vapor deposition method, a method of manufacturing a semiconductor device having a heterojunction structure.
The method of claim 1,
After forming the epitaxial layer and the ground pad, before forming the via hole:
forming an adhesive layer covering the epitaxial layer and the ground pad;
adhering a carrier wafer onto the adhesive layer;
backgrinding the back surface of the substrate after the carrier wafer is adhered; and
and forming a metal mask layer defining a region in which the via hole is to be formed on the rear surface of the substrate.
The method of claim 1,
Etching one region of the substrate and the epitaxial layer is performed using an inductively coupled plasma (ICP),
A method of manufacturing a semiconductor device using the ground pad as an etch stop layer.
delete The method of claim 1,
The base metal layer is formed of titanium (Ti) or gold (Au), and is deposited to a thickness of 1000 Å to 2000 Å.
The method of claim 1,
The plating layer and the substrate are electrically connected to each other with the base metal layer therebetween.

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