CN108428669B - Three-dimensional heterogeneous integrated system and manufacturing method thereof - Google Patents
Three-dimensional heterogeneous integrated system and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
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Abstract
The invention relates to a three-dimensional heterogeneous integrated system and a manufacturing method thereof, wherein the method comprises the following steps: preparing a silicon carbide substrate layer and a silicon carbide epitaxial layer; respectively manufacturing back through holes on the silicon carbide substrate layer and the silicon carbide epitaxial layer, growing at least one passive device on the silicon carbide epitaxial layer, and preparing an active device; bonding at least one active device on the silicon carbide-based substrate layer using a benzocyclobutene polymer; bonding and connecting the silicon carbide substrate layer and the silicon carbide epitaxial layer; a bond connection between the active device and the passive device. The embodiment of the invention ensures the reliability of the device process and improves the manufacturing efficiency of the device.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a three-dimensional heterogeneous integrated system and a manufacturing method thereof.
Background
With the development and progress of science and technology, the utilization degree of electromagnetic waves by human beings is higher and higher, and at present, how to utilize electromagnetic waves and how to manufacture more complete devices to utilize electromagnetic waves become a technical problem which is more and more emphasized in the fields of microelectronics and the like.
Silicon (Si) is a leading material in the semiconductor technology center, and has significant advantages mainly in terms of complexity of integration, maturity, yield, cost, and the like. Integrated silicon (CMOS and BiCMOS) radio frequency technology has made significant advances in power in recent years, with frequencies extending to around 100 GHz. However, silicon materials have certain limitations, and many functional applications can be realized only by using compound semiconductor technologies such as indium phosphide (InP) and gallium nitride (GaN) in combination with silicon materials. For indium phosphide, a transistor with a maximum frequency of 1 thz can be manufactured, and has very high gain and power. The gallium nitride material device has the characteristics of large bandwidth, high breakdown voltage, high output frequency and the like, and the output frequency can reach 100 GHz. Each semiconductor device needs to be grown on a substrate during manufacturing, but only one processing mode can be performed on one substrate, devices on different substrates cannot be integrated on the same substrate, so that for a system requiring multiple devices, the occupied area of the substrate is larger than that of the device, and gaps and distances exist among different substrates in one system, so that the volume of the system is further increased. Therefore, in order to reduce the system size and improve the flexibility of the system function, Heterogeneous semiconductors need to be integrated, that is, Heterogeneous integration (Heterogeneous integration) is required.
Then, the multilayer multi-chip integration technology is widely used for laterally integrating different kinds of semiconductor devices on a single substrate, and also for passive elements (including filters and antennas). By this technique, the passive element can realize a high Q value and miniaturization.
As frequencies increase, interconnect block and inline losses between integrated circuits increase rapidly. Therefore, there is a need to overcome parasitic effects therein. This requires three-dimensional monolithic or wafer-level heterogeneous integration of different semiconductors. With this technique, high frequency and high performance can be achieved via compound semiconductor materials (mainly including indium phosphide and gallium nitride), while also taking advantage of various advantages of silicon materials. Moreover, scaling has become an inevitable choice and trend in the semiconductor industry, enabling increased density of functional units within a given area of a semiconductor chip.
There is also a need to improve the quality of device production. The precision of the process can be improved by Micro-Electro-Mechanical systems (MEMS) processing. The device realizes the high-progress and high-consistency production and the integration of multifunctional devices.
Heterogeneous integration technologies include hybrid integration technologies and monolithic integration technologies. The hybrid integration technology mainly refers to the integration of chips of different substrates through bonding. The monolithic integration technology is to integrate devices with different functions, such as an indium phosphide device with high frequency or a gallium nitride device with high bandwidth and high power, on a single chip. Although the monolithic integration technology does not require packaging of the chip, the process manufacturing difficulty is relatively large.
In conventional systems, chips of different substrate materials are used to achieve desired performance through hybrid integration techniques. However, this method does not integrate chips with different substrates on the same chip, which not only has a larger volume, but also increases the loss of the microstrip line with the increase of frequency. Then, the impact of these parasitic effects on system performance is significant.
In summary, the methods for manufacturing heterogeneous integrated systems in the prior art mainly have the following problems:
the chips are integrated in a bonding mode, and under the condition of high frequency, the bonding can generate a large parasitic effect, the influence on the overall performance of the system is large, the efficiency of the whole system is reduced, the overall output power of the system is influenced, and the heterogeneous integrated system loses the research significance at high frequency.
In addition, the traditional method cannot effectively reduce the area of the chip and cannot well improve the integration level of the device. In the era of rapid development of semiconductor technology, this method is inevitably eliminated by the era.
The silicon is used as a substrate material, so that the silicon has very obvious advantages, and has very good performance no matter the cost or the performance; however, when the power is high or the integration is high, the heat dissipation performance of silicon becomes a very important obstacle to the technology development. Also, silicon is brittle and easily damaged or scratched. A more suitable substrate material is needed to improve the overall performance of the system.
Disclosure of Invention
In view of the above, the present invention provides a three-dimensional heterogeneous integrated system and a manufacturing method thereof, which solve the problems of low integration level and low efficiency existing in the conventional technology and the conventional material.
The invention provides a method for manufacturing a three-dimensional heterogeneous integrated system based on the above purpose, which comprises the following steps:
preparing a silicon carbide substrate layer and a silicon carbide epitaxial layer;
respectively manufacturing back through holes on the silicon carbide substrate layer and the silicon carbide epitaxial layer, growing at least one passive device on the silicon carbide epitaxial layer, and preparing an active device;
bonding at least one active device on the silicon carbide-based substrate layer using a benzocyclobutene polymer;
bonding and connecting the silicon carbide substrate layer and the silicon carbide epitaxial layer;
a bond connection between the active device and the passive device.
Optionally, the step of respectively manufacturing back through holes on the silicon carbide-based substrate layer and the silicon carbide-based epitaxial layer includes:
thinning the silicon carbide substrate layer and the silicon carbide epitaxial layer;
and etching the silicon carbide substrate layer and the silicon carbide epitaxial layer, and respectively forming back through holes on the silicon carbide substrate layer and the silicon carbide epitaxial layer.
Optionally, the step of etching the target coating and the silicon carbide-based substrate layer to form a through hole specifically includes:
respectively sputtering Ti/Au metal layers on the surface of the silicon carbide-based substrate layer and the surface of the silicon carbide-based epitaxial layer, and respectively coating photoresist with the model of RZJ-304 to form a target coating;
photoetching a set pattern on the target coating in a contact photoetching mode;
and etching the target coating and the silicon carbide substrate layer by an inductive coupling plasma etching mode to form a back through hole, wherein the etching depth is 50-200 mu m.
Optionally, the step of thinning the silicon carbide-based substrate layer and the silicon carbide-based epitaxial layer includes:
respectively coating paraffin on the silicon carbide substrate layer and the silicon carbide epitaxial layer;
and respectively polishing the silicon carbide substrate layer and the silicon carbide epitaxial layer to set thicknesses by using a grinding disc and diamond powder.
Optionally, the step of forming an electrical connection between the active device and the passive device specifically includes:
and penetrating the bonding gold wire through the back through hole, and bonding the active device and the passive device.
Optionally, when the active device is provided with more than one active device, the step of forming an electrical connection between the active device and the passive device specifically includes:
and bonding the passive device by using the bonding alloy wire.
Optionally, when there is more than one passive device, the step of forming an electrical connection between the active device and the passive device specifically includes:
the active devices are bonded with a bonding alloy wire.
Meanwhile, the invention also provides a three-dimensional heterogeneous integrated system, which comprises a substrate layer and an epitaxial layer arranged on one side of the substrate layer; at least one active device is arranged between the substrate layer and the epitaxial layer, and the active device is adhered to the substrate layer through benzocyclobutene polymer and is positioned in a groove correspondingly arranged on the epitaxial layer; at least one passive device grows on one side of the epitaxial layer, which is far away from the substrate layer;
back through holes are formed in the substrate layer and the epitaxial layer;
the substrate layer and the epitaxial layer are bonded through a bonding metal wire penetrating through the back through hole; the active device and the passive device are bonded by a bond wire through a back via.
Optionally, when more than one active device is arranged, the active devices are bonded by using a bonding gold wire; when more than one passive device is arranged, the passive devices are bonded by using a bonding gold wire.
Optionally, the substrate layer is a silicon carbide-based substrate; the epitaxial layer is a silicon carbide-based epitaxial layer; the active devices include gallium nitride devices and indium phosphide devices.
The invention has the following advantages:
the devices are manufactured respectively through layering, and the processing is relatively independent, so that the reliability of the device process is ensured, and the manufacturing efficiency of the devices is improved;
the SiC material is introduced as the substrate, although the cost is increased, the method is very important for the integration level and the high efficiency of the chip and has reference significance for the development of the semiconductor integration in the future;
the BCB is used for bonding the device and the substrate, so that the devices grown under different substrates can be integrated on the same substrate, the size of a chip is reduced, and the complexity of the process is greatly reduced.
The device is integrated in three dimensions, so that the area of an integrated chip is greatly reduced, the length of a lead is reduced, parasitic parameters are successfully reduced, the performance of the device under high frequency is ensured, and the overall performance of a system is also improved.
Drawings
FIG. 1 is a method for manufacturing a heterogeneous integrated system according to an embodiment of the present invention;
fig. 2 is a heterogeneous integrated system structure according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The embodiment of the invention firstly provides a manufacturing method of a three-dimensional heterogeneous integrated system, as shown in fig. 1, comprising the following steps:
step 101: preparing a silicon carbide substrate layer and a silicon carbide epitaxial layer;
step 102: respectively manufacturing back through holes on the silicon carbide substrate layer and the silicon carbide epitaxial layer, growing at least one passive device on the silicon carbide epitaxial layer, and preparing an active device;
step 103: bonding at least one active device on the silicon carbide-based substrate layer using a benzocyclobutene polymer;
step 104: bonding and connecting the silicon carbide substrate layer and the silicon carbide epitaxial layer;
step 105: a bond connection between the active device and the passive device.
In step 102 above, the active devices include gallium nitride devices and indium phosphide devices.
And then removing the substrate from the GaN device and the InP device through a thinning process, connecting the devices to the silicon carbide-based substrate layer through BCB, and connecting the silicon carbide-based substrate layer and the silicon carbide-based epitaxial layer through a gold bonding wire.
And then the silicon carbide substrate layer and the silicon carbide epitaxial layer are mutually connected from bottom to top through a gold bonding wire.
In a specific embodiment, when the silicon carbide substrate layer and the silicon carbide epitaxial layer are manufactured, the surfaces of the silicon carbide substrate layer and the silicon carbide epitaxial layer are subjected to process treatment. The preparation process of the silicon carbide substrate layer comprises the steps of selecting 2 SiC substrates, sputtering a Ti layer on the surface of the SiC substrate, then sputtering an Au layer, and then performing photoresist whirl coating; and carrying out contact photoetching on the surface spun by the glue, and developing to form a required pattern. And then the thickness of Au is thickened through electroplating to reach the required thickness, and a silicon carbide substrate layer is formed. Specifically, in one embodiment, Ti/Au is sputtered on the surface of 2 SiC substrates, RZJ-304 photoresist is coated on the surfaces, spin coating is performed at the rotation speed of 1000-2000r/min (preferably 1500r/min), 20-40s (preferably 30s), the thickness is about 2-6 μm, the thickness is preferably 5 μm, contact type photoetching is performed according to different functions, exposure is performed for 20-40s (preferably 30s), and development is performed for 1-5min (preferably 1.5min) to form the required pattern. The two SiC substrates are divided into a silicon carbide substrate layer and a silicon carbide epitaxial layer. Then electroplating the surface of the substrate to reach the required thickness.
After the silicon carbide substrate layer and the silicon carbide epitaxial layer are prepared, the back surfaces of the silicon carbide substrate layer and the silicon carbide epitaxial layer are thinned, Ni sputtering and photoetching are carried out on the back surfaces, and through hole etching is carried out through ICP (inductively Coupled plasma emission Spectrometer) to form a back through hole. And photoetching the surface of the silicon carbide-based epitaxial layer, forming a required passive device by electroplating and PECVD (plasma enhanced chemical vapor deposition), and removing unnecessary metal by corrosion of potassium iodide.
In one embodiment, the thinning process is as follows:
and adhering the silicon carbide substrate layer and the front surface of the silicon carbide epitaxial layer on the quartz substrate through low-temperature paraffin. The melting point of paraffin is about 90 ℃, a quartz plate is placed on a hot plate, excessive paraffin is coated on the surface of the quartz plate, after the paraffin is melted, a silicon carbide substrate is placed on the paraffin, the middle of a tweezers is used for slightly extruding towards two sides, the excessive paraffin is extruded out, each part is guaranteed to be provided with the paraffin, and then the pressing block and a heavy object are used for carrying out static pressure, so that the smoothness of the pasting process is guaranteed. Then thinning the back of the SiC-based substrate layer by diamond powder;
preparing thinning liquid, and mixing diamond particles with the diameter of 5um and distilled water according to a proportion. The mixing ratio was 100g diamond powder plus 900mL water. Firstly, the grinding disc is corrected, an iron cylinder with the diameter of 20cm is used for correcting the grinding disc, the position is 15cm away from the center of the circle, the position is not changed, the position can ensure that the friction force born by the left side and the right side of the substrate in the mask process is uniform, and a good thinning effect can be achieved. If the grinding disc is closer to the center of the grinding disc, the thinning effect is poorer and is about 1 um/min. If the polishing disc is closer to the periphery of the polishing disc, the flatness is poorer, and the difference between the circle center of the substrate and the flatness of the periphery of the substrate is about 15 mu m. The thinning is carried out at the position of 15cm of the circle center, the thinning speed is about 2um/min, and the uniformity is kept within 5 um. The rotational speed of the abrasive is 50 revolutions per minute, the rotational speed of the grinding disc is 45 revolutions per minute, and the rotational speeds of the abrasive and the grinding disc are not changed. The grinding disc time is not more than 10min, so that the grinding disc is in a shape of protruding in the middle and recessed on two sides. The treatment can effectively avoid the shaking caused by uneven friction in the process of grinding the disc, and prevent the SiC substrate from cracking. When the silicon carbide substrate is thinned, the autorotation speed of the wafer is about 80 r/min, and the thickness of the substrate is measured every 15 minutes of grinding. And the grinding disc needs to be corrected once every 60um grinding to ensure the stability of the process.
And 3 SiC substrates are thinned to 100um, and then the back is polished by polishing solution, so that the roughness of the surface is ensured. Roughness affects the adhesion of the metal after the sputtering process. And then carrying out Ni sputtering on the back, carrying out photoetching and developing on the Ni surface through RZJ-304 photoresist to form a pupil pattern, and carrying out through hole etching through ICP to form a through hole of 100 um. After the SiC substrate is separated from the quartz plate by the heating stage, paraffin can be removed by acetone or isopropyl alcohol.
When a gallium nitride device is prepared, an AlN nucleating layer, a GaN buffer layer, an AlN inserting layer, an AlGaN barrier layer, a first layer of SiN and a second layer of SiN are sequentially grown on a SiC substrate, a source electrode and a grid electrode which are in ohmic contact are respectively arranged at two ends of the GaN buffer layer, and T-shaped grids are arranged on the second layer of SiN and the first layer of SiN. After the AlN nucleation layer is grown on the SiC substrate, since the thermal expansion coefficient and the lattice constant between the SiC substrate and the GaN thin film are mismatched, the AlN nucleation layer is required to solve the problems caused by the lattice mismatch and the thermal mismatch, and the AlN nucleation layer is required to be larger than the strain critical thickness of the GaN on the substrate. During the process of manufacturing the gallium nitride device, atoms are difficult to be uniformly distributed on the surface of the substrate. Therefore, the GaN buffer layer needs to grow at a lower temperature, so that the movement of atoms can be greatly reduced; and then continuously growing the GaN buffer layer at high temperature to reach the required thickness. The GaN portion formed at a low temperature and the GaN portion formed at a high temperature are integrally formed as a GaN buffer layer.
An AlN insert layer is added between the GaN and the AlGaN, so that the stress is obviously adjusted, the dislocation of the AlGaN film is reduced, and the material quality is improved. When the thickness is proper, the two-dimensional electron gas reaches the peak value, and the electrical property of the device is improved.
The thickness of the growth of the AlGaN barrier layer determines the final performance of the device. And growing a first layer of SiN by PECVD (plasma enhanced Chemical Vapor Deposition), so as to reduce the current collapse of the device. And then growing a T-shaped gate by Ni/Au evaporation. And after the Schottky contact of the grid is completed, a second layer of SiN is grown again to protect the grid.
Two-dimensional electron gas of a source electrode and a drain electrode is mainly led out through ohmic contact, so that the electrical property of the device is improved, and the material is generally Ti, Al, Ni or Au. And generating a source electrode ohmic contact and a drain electrode ohmic contact.
The two-dimensional electron gas between adjacent devices is completely depleted by mesa isolation. And reserving the place where the device is needed, and carrying out ICP (plasma etching) on the place where the device is not needed. The devices are not connected.
After the device is manufactured, back pupil etching and back gold etching are required to be carried out on the device. And (3) drilling holes on the source electrode through photoetching, and sputtering a layer of gold on the hole wall and the hole bottom through sputtering to improve the performance of the whole device.
The same process is used for manufacturing InP-based InP devices.
And after the active device is manufactured, throwing a layer of photoresist on the surfaces of the manufactured GaN device and the InP device to protect the surface structure of the device. And then the front side is bonded with a quartz plate by paraffin, the back side is thinned, the influence of the substrate on the device is reduced as much as possible, about 5-15 um remains, and then residual substances of the substrate are removed by wet etching, so that the device is completely removed from the substrate. After the substrate is removed, each device is separated independently by a dicing saw. The device is connected to the silicon carbide substrate layer through benzocyclobutene BCB, the silicon carbide substrate layer is connected with the silicon carbide epitaxial layer through a substrate punching technology, active and passive devices on the two layers are connected in the through hole of the silicon carbide epitaxial layer through a bonding gold wire, the electrical performance of the two layers of devices is realized, the area of a chip is reduced, and the integration level of the system is improved. And the bonding gold wire penetrates through the back through hole, so that the length of the wire is greatly reduced, and the influence of parasitic parameters on a system is reduced. Because the silicon carbide-based epitaxial layer is thinned, the connection between the active device and the passive device can be realized directly through a bonding machine, the complexity of the process is reduced, and the process efficiency is improved.
And finally, the silicon carbide substrate layer and the silicon carbide epitaxial layer are mutually connected from bottom to top through a gold bonding wire, so that the manufacture of a three-dimensional heterogeneous integrated system is realized, and the three-dimensional heterogeneous integrated system has the performances of high efficiency, high power and high frequency.
In a specific embodiment of the present invention, the step of forming a back via hole in the silicon carbide-based substrate layer includes:
respectively carrying out pattern photoetching on the front surface of the silicon carbide-based substrate and the front surface of the silicon carbide-based epitaxial layer; the front surface is one surface of the silicon carbide substrate layer or the silicon carbide epitaxial layer;
thinning the back of the silicon carbide substrate layer and the back of the silicon carbide epitaxial layer; the back surface is the other surface of the silicon carbide-based substrate or the silicon carbide-based epitaxial layer;
and etching the silicon carbide substrate layer and the silicon carbide epitaxial layer to form a back through hole.
In the embodiment, when the back surface of the substrate layer is thinned, the back surface of the substrate layer and the quartz plate need to be bonded through paraffin, and the RZJ-304 type photoresist can form a target coating with a larger thickness, so that the structure of the active device cannot be damaged in the process of bonding the front surface of the active device and the quartz plate through paraffin; and the structure of the active device is not changed in the process of thinning the substrate.
Fig. 2 is a schematic structural diagram of a three-dimensional heterogeneous integrated system according to an embodiment of the present invention, including: the device comprises a silicon carbide substrate layer 1, a back through hole 2, a silicon carbide epitaxial layer 3, an active device, benzocyclobutene 6 and a passive device 7. Wherein the active devices include a gallium nitride device 4 and an indium phosphide device 5. Wherein the gallium nitride device 4 has the characteristics of high power and high efficiency millimeter wave. The indium phosphide device 5 has a high-frequency characteristic. Grooves matched with the shapes of the active devices are formed in the silicon carbide-based epitaxial layer 3, and the gallium nitride device 4 and the indium phosphide device 5 are adhered to the silicon carbide-based substrate layer 1 through BCB (benzocyclobutene polymer). The passive devices 7 are grown directly on the side of the silicon carbide-based epitaxial layer 3 remote from the recess. The silicon carbide substrate layer 1 and the silicon carbide epitaxial layer 3 are bonded by a bonding gold wire penetrating through the back through hole 2; and the gallium nitride device 4 and the indium phosphide device 5 are bonded through a bonding gold wire. When more than one passive device 7 is arranged, the passive devices are bonded through the bonding gold wire.
The three-dimensional heterogeneous integration system provided by the embodiment of the invention changes the traditional plane structure, adopts a three-dimensional structure mode and improves the integration level of the whole system. The silicon carbide substrate layer and the silicon carbide epitaxial layer both use silicon carbide as substrate materials, and a back through hole process is completed on the silicon carbide substrate layer and the silicon carbide epitaxial layer, so that the heat dissipation capacity of the system is improved, the better integration level is favorably achieved, and the back through hole plays an important role in connection between devices later.
The active device is respectively pasted on the silicon carbide substrate layer through benzocyclobutene BCB, so that the reliability of the device is improved, and the device can stably work on the silicon carbide substrate. The passive device is grown on the silicon carbide-based epitaxial layer by means of material growth. The two substrates are grounded through a back through hole, and the silicon carbide substrate layer and the silicon carbide epitaxial layer are electrically connected through the bonding alloy wire. And the passive device and the active device are electrically connected through the bonding alloy wire. And the bonding gold wire can penetrate through the silicon carbide substrate layer and the back through hole on the silicon carbide epitaxial layer, so that the length of the wire is reduced, and the influence of parasitic parameters on the system performance is reduced.
It is to be understood that the various embodiments described herein are for purposes of illustration and explanation only and are not intended to be limiting. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A manufacturing method of a three-dimensional heterogeneous integrated system is characterized by comprising the following steps:
preparing a silicon carbide substrate layer and a silicon carbide epitaxial layer;
etching the silicon carbide substrate layer and the silicon carbide epitaxial layer, respectively manufacturing back through holes on the silicon carbide substrate layer and the silicon carbide epitaxial layer, growing at least one passive device on the silicon carbide epitaxial layer, and preparing an active device, wherein the active device comprises a gallium nitride device and an indium phosphide device;
bonding at least one active device on the silicon carbide-based substrate layer using a benzocyclobutene polymer;
bonding and connecting the silicon carbide substrate layer and the silicon carbide epitaxial layer through the back through hole;
and bonding and connecting the active device and the passive device through the back through hole.
2. The method of claim 1, wherein the step of forming back vias in the silicon carbide-based substrate layer and the silicon carbide-based epitaxial layer respectively comprises:
thinning the silicon carbide substrate layer and the silicon carbide epitaxial layer;
and etching the silicon carbide substrate layer and the silicon carbide epitaxial layer, and respectively forming back through holes on the silicon carbide substrate layer and the silicon carbide epitaxial layer.
3. The method for manufacturing a three-dimensional heterogeneous integrated system according to claim 2, wherein the step of etching the silicon carbide-based epitaxial layer and the silicon carbide-based substrate layer to form a back via hole specifically comprises:
respectively coating photoresist with the model number of RZJ-304 on the surface of the silicon carbide-based substrate layer and the surface of the silicon carbide-based epitaxial layer to form a target coating;
photoetching a set pattern on the target coating in a contact photoetching mode;
and etching the target coating and the silicon carbide substrate layer by an inductive coupling plasma etching mode to form a back through hole, wherein the etching depth is 50-200 mu m.
4. The method of claim 2, wherein the step of thinning the silicon carbide-based substrate layer and the silicon carbide-based epitaxial layer comprises:
respectively coating paraffin on the silicon carbide substrate layer and the silicon carbide epitaxial layer;
and respectively polishing the silicon carbide substrate layer and the silicon carbide epitaxial layer to set thicknesses by using a grinding disc and diamond powder.
5. The method of claim 4, wherein the step of forming a bonding connection between the active device and the passive device comprises:
and penetrating the bonding gold wire through the back through hole, and bonding the active device and the passive device.
6. The method of claim 1, wherein when the active device is provided with more than one active device, the step of forming a bonding connection between the active device and the passive device comprises:
the active devices are bonded with a bonding alloy wire.
7. The method according to claim 1, wherein when the passive device is provided with more than one passive device, the step of forming the bonding connection between the active device and the passive device comprises:
and bonding the passive device by using the bonding alloy wire.
8. A three-dimensional heterogeneous integrated system is characterized by comprising a silicon carbide substrate layer and a silicon carbide epitaxial layer arranged on one side of the silicon carbide substrate layer; at least one active device is arranged between the silicon carbide substrate layer and the silicon carbide epitaxial layer, the active device is adhered to the silicon carbide substrate layer through benzocyclobutene polymer and is positioned in a groove correspondingly arranged on the silicon carbide epitaxial layer, and the active device comprises a gallium nitride device and an indium phosphide device; at least one passive device grows on one side of the silicon carbide-based epitaxial layer, which is far away from the silicon carbide-based substrate layer;
back through holes are formed in the silicon carbide substrate layer and the silicon carbide epitaxial layer through an etching process;
the silicon carbide substrate layer and the silicon carbide epitaxial layer are bonded through a bonding gold wire penetrating through the back through hole; the active device and the passive device are bonded by a bond wire through a back via.
9. The three-dimensional heterogeneous integrated system according to claim 8, wherein when more than one active devices are arranged, the active devices are bonded with each other by using a gold bonding wire; when more than one passive device is arranged, the passive devices are bonded by using a bonding gold wire.
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