KR20220155353A - Methods of forming group III-nitride single crystal piezoelectric thin films - Google Patents

Abstract

A method of forming a piezoelectric thin film may include depositing a material on a first surface of a Si substrate to provide a stress neutral template layer. A piezoelectric thin film comprising a Group III element and nitrogen may be sputtered onto the stress-neutral template layer, and Si opposite the first surface to remove the Si substrate and the stress-neutral template layer to provide the remainder of the piezoelectric thin film. A second surface of the substrate may be treated. A piezoelectric resonator may be formed on the remaining portion of the piezoelectric thin film.

Description

Methods of forming group III-nitride single crystal piezoelectric thin films

Cross-references to related applications and claims of priority

This application was filed with the USPTO on January 14, 2020 and is entitled "Methods of Forming Group III Piezoelectric Thin Films through Removal of Portions of First Sputtered Material (METHODS OF FORMING GROUP III PIEZOELECTRIC THIN FILMS VIA REMOVAL US Patent Application Serial No. 16/742,202 (Attorney Docket No. 170964-00020), entitled "Of PORTIONS OF FIRST SPUTTERED MATERIAL", which claims priority to and is a continuation-in-part portion thereof, filed with the USPTO on August 15, 2019 and US Provisional Patent Application No. 62 entitled "METHODS OF FORMING GROUP III PIEZOELECTRIC THIN FILMS VIA REMOVAL OF PORTIONS OF FIRST SPUTTERED MATERIAL" /887,126 (SL reference number 181246-00013), filed with the USPTO on October 16, 2017, and entitled "Piezoelectric ACOUSTIC RESONATOR MANUFACTURED WITH Continuation-in-part of U.S. Patent Application Serial No. 15/784,919 (Attorney Docket No. A969RO-0007US2), "PIEZOELECTRIC THIN FILM TRANSFER PROCESS" (currently U.S. Patent No. 10,355,659, issued July 16, 2019), July 2019 US Patent Application Serial No. 16/513,143 (SL reference number) filed with the USPTO on the 16th and entitled "METHODS OF FORMING GROUP Ⅲ PIEZOELECTRIC THIN FILMS VIA SPUTTERING" 181246-00010), and this application was filed with the USPTO on December 12, 2019 16/ 709,813 , entitled Method And Structure For Single Crystal Acoustic Resonator Devices Using Thermal Recrystallization , entitled Method And Structure For Single Crystal Acoustic Resonator Devices Using Thermal Recrystallization. The disclosure is incorporated herein by reference in its entirety.

This application also incorporates by reference the entirety of the following commonly owned disclosures: Single Crystal Piezoelectric Using Low-Vapor Pressure Metal- Organic Precursors in a CVD System, filed with the USPTO on February 7, 2020 and entitled Apparatus For Forming Single Crystal Piezoelectric Layers Using Low-Vapor Pressure Metalorganic Precursors In CVD Systems And Methods Of Forming Single Crystal Piezoelectric Layers Using The Same U.S. Provisional Patent Application Serial No. 16/784,843 (Attorney Docket No. 181246-00022), filed March 11, 2016 and entitled " Method Of Manufacture For Single Crystal Resonator Devices Using Micro-vias " Crystal Acoustic Resonator Devices Using Micro - Vias ), a continuation-in-part of U.S. Patent Application Serial No. 15/068,510, filed on July 27, 2016 and entitled " Method of Manufacturing Single- Crystal Elastic Resonator Devices Using Micro - Vias " Of Manufacture For Single Crystal Acoustic Resonator Devices Using Micro - Vias ," US Patent Application Serial No. 15/221,358. This application is also incorporated by reference for all purposes to the following co-pending patent applications, all of which are co-owned: Filed on Jun. 2, 2014 and entitled " Resonant Circuit with Monocrystal Capacitor Dielectric Material " ( Resonance Circuit With A Single Crystal Capacitor Dielectric Material ), U.S. Patent Application Serial No. 14/298,057 (Attorney Docket No. A969RO-000100US), filed on June 2, 2014, entitled "Single Crystal Capacitor for Resonant Circuit " US Patent Application Serial No. 14/298,076 (Attorney Docket No. A969RO-000200US), "Method Of Manufacture For Single Crystal Capacitor Dielectric For A Resonance Circuit ", filed on June 2, 2014, entitled This " Integrated Circuit Configured With Two Or More Single Crystal Acoustic Resonator Devices " , US Patent Application Serial No. 14/298,100 (Attorney Docket No. A969RO -000300US), July 25, 2014 US Patent Application Serial No. 14/341,314 (Attorney Docket No. A969RO-000400US), filed on July 31, 2014, entitled "WAFER SCALE PACKAGING", filed on July 31, 2014 and entitled " U.S. Patent Application Serial No. 14/449,001 (Attorney Docket No. A969RO-000500US), "Mobile Communication Device Configured With A Single Crystal Piezo Resonator Structure ", filed August 26, 2014 become and invent US Patent Application Serial No. 14/ 469,503 entitled " Membrane Substrate Structure For Single Crystal Acoustic Resonator Device " (Attorney Docket No. A969RO -000600US).

technology field

The present invention relates generally to electronic devices. More specifically, the present invention provides techniques related to bulk acoustic wave resonator devices, single crystal bulk acoustic wave resonator devices, single crystal filter and resonator devices, and methods of manufacturing piezoelectric thin films included therein. By way of example only, the present invention may be used to form single crystal resonator devices for communication devices, mobile devices, computing devices, among others.

Embodiments according to the present invention may provide methods for forming Group III nitride single crystal piezoelectric thin films using aligned deposition and stress neutral template layers. According to these embodiments, a method of forming a piezoelectric thin film may include depositing a material on a first surface of a Si substrate to provide a stress neutral template layer. A piezoelectric thin film comprising a Group III element and nitrogen may be sputtered onto the stress-neutral template layer, and Si opposite the first surface to remove the Si substrate and the stress-neutral template layer to provide the remainder of the piezoelectric thin film. A second surface of the substrate may be treated. A piezoelectric resonator may be formed on the remaining portion of the piezoelectric thin film.

In some embodiments, a method of forming a single crystal piezoelectric thin film includes epitaxially depositing a material on a first surface of a Si substrate to provide a template layer; sputtering a single crystal piezoelectric thin film containing a Group III element and nitrogen on the template layer; treating a second surface of the Si substrate opposite the first surface to remove the Si substrate and template layer to provide a remaining portion of the single crystal piezoelectric thin film; and forming a single crystal piezoelectric resonator on the remaining portion of the single crystal piezoelectric thin film.

In some embodiments, a method of forming a piezoelectric thin film may include depositing a material on a first surface of a Si substrate to provide a template layer surface having a stress in the range of about -200 Mpa to about +200 MPa. can A single crystal piezoelectric thin film containing a Group III element and nitrogen may be sputtered on the surface of the template layer. a second portion of the Si substrate opposite the first surface to remove the Si substrate and template layer surface to provide a remainder of the single crystal piezoelectric thin film having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees, as measured at FWHM using XRD; The surface may be treated, and a single crystal piezoelectric resonator may be formed on the remainder of the single crystal piezoelectric thin film.

In some embodiments, a method of forming a piezoelectric thin film is to apply a material on a first surface of a Si substrate using MOCVD or MBE to provide a template layer surface having a stress ranging from about -200 Mpa to about +200 MPa. depositing; sputtering a single crystal piezoelectric thin film containing a Group III element and nitrogen on the surface of the template layer; a second portion of the Si substrate opposite the first surface to remove the Si substrate and template layer surface to provide a remainder of the single crystal piezoelectric thin film having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees, as measured at FWHM using XRD; treating the surface; and forming a single crystal piezoelectric resonator on the remaining portion of the single crystal piezoelectric thin film.

1A is a simplified diagram illustrating an elastic resonator device with top side interconnects according to an example of the present invention.
1B is a simplified diagram illustrating an elastic resonator device with bottom side interconnects in accordance with an example of the present invention.
1C is a simplified diagram illustrating an elastomeric resonator device with interposer/capless structure interconnects in accordance with an example of the present invention.
1D is a simplified diagram illustrating an elastomeric resonator device with interposer/capless structure interconnects with shared backside trenches in accordance with an example of the present invention.
2 and 3 are simplified diagrams showing steps for a fabrication method for an elastic resonator device according to an example of the present invention.
4A is a simplified diagram illustrating steps for a method of creating a topside micro-trench in accordance with an example of the present invention.
4B and 4C are simplified diagrams illustrating alternative methods for performing the method step of forming a topside micro-trench as described in FIG. 4A.
4D and 4E are simplified diagrams illustrating an alternative method for performing the method step of forming a topside micro-trench as described in FIG. 4A.
5-8 are simplified diagrams illustrating steps for a method of fabricating an elastic resonator device according to an example of the present invention.
9A is a simplified diagram illustrating method steps for forming backside trenches in accordance with an example of the present invention.
9B and 9C are simplified diagrams illustrating an alternative method for performing the method steps of forming backside trenches and simultaneously singulating a seed substrate as described in FIG. 9A in accordance with an embodiment of the present invention.
10 is a simplified diagram illustrating method steps for forming backside metallization and electrical interconnections between the top and bottom sides of a resonator in accordance with an example of the present invention.
11A and 11B are simplified diagrams illustrating alternative steps for a manufacturing method for an elastic resonator device according to an example of the present invention.
12A-12E are simplified diagrams illustrating steps for a manufacturing method for an elastic resonator device using a blind via interposer according to an example of the present invention.
13 is a simplified diagram showing steps for a manufacturing method for an elastic resonator device according to an example of the present invention.
14A-14G are simplified diagrams illustrating method steps for a cap wafer process for an elastic resonator device according to an example of the present invention.
15A-15E are simplifications showing method steps for fabricating an elastomeric resonator device with a shared backside trench that can be implemented in both an interposer/cap version and a no-interposer version, according to examples of the present invention. drawings that have been
16A-16C, through 31A-31C are simplified cross-sectional views showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to examples of the present invention. they are drawings
32A-32C and 46A-46C are simplified diagrams illustrating various cross-sectional views of single crystal elastic resonator devices and method steps for a cavity bond transfer process for single crystal elastic resonator devices according to examples of the present invention.
47A-47C and 59A-59C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device, and a rigidly mounted transfer process for single crystal elastic resonator devices according to examples of the present invention. admit.
60 illustrates forming a single crystal piezoelectric thin film by epitaxial growth of a stress neutral template layer on a substrate in some embodiments according to the present invention, sputtering the single crystal piezoelectric thin film on the stress neutral template layer, A substrate and a stress-neutral template are prepared such that a portion of the single crystal piezoelectric thin film remains to be included in the devices shown, for example, in FIGS. 8-9A, 22-23, 39-40, and 52-53. It is a flow chart showing the methods of removal.
61 is a cross-sectional view illustrating a stress neutral template layer formed on a substrate according to FIG. 60 in some embodiments according to the present invention.
62 is a cross-sectional view illustrating a single crystal piezoelectric thin film formed on the stress-neutral template layer of FIG. 61 formed according to FIG. 60 in some embodiments according to the present invention.
63 and 64 are graphs illustrating experimental XRD measurements for wafers formed according to FIG. 60 in some embodiments according to the present invention.
65 and 66 show the presence of abnormally oriented grains and abnormally oriented grains (AOG) in piezoelectric layers formed on AlN and AlGaN templates, respectively, in some embodiments according to the present invention. These are experimental SEM images showing the relative absence of
67 is a Si <111> substrate with single crystal AlN piezoelectric thin films sputtered using various bias power levels onto AlGaN stress neutral template layers with 20% Ga formed using MOCVD in some embodiments in accordance with the present invention. Table of experimental data including XRD measurements for

In accordance with the present invention, techniques are provided generally relating to electronic devices. More specifically, the present invention provides techniques relating to fabrication methods and structures for bulk acoustic wave resonator devices, single crystal resonator devices, single crystal filter and resonator devices, and the like. By way of example only, the present invention has been applied to single crystal resonator devices for communication devices, mobile devices, computing devices, among others.

As recognized by the present inventors, high quality single crystal piezoelectric thin films (or layers) can be fabricated by epitaxially forming a material on a substrate such as Si<111> to provide a template layer of high crystallinity. Next, a piezoelectric material can be sputtered over the template layer so that the piezoelectric material can be formed as a single crystal piezoelectric material despite the use of sputtering to form the piezoelectric material. As further appreciated by the inventors, epitaxially formed templates can be made substantially stress neutral by controlling the composition of the template layer. A substantially stress-neutral template layer may allow the sputtered piezoelectric material to have a relatively low stress compared to cases where the underlying material is not substantially stress-neutral. Providing the sputtered piezoelectric material at a relatively neutral stress can increase the reliability of the subsequently sputtered high quality single crystal piezoelectric thin film after the template is removed, even though the sputtered high quality single crystal piezoelectric thin film is relatively thin.

Accordingly, embodiments according to the present invention can achieve a high-quality single crystal piezoelectric thin film by forming a high-order template layer to provide a surface that is substantially free of abnormally oriented particles (AOG) and is relatively stress-neutral. Since the piezoelectric material can be sputtered onto the template surface, the sputtered piezoelectric material can become a single crystal piezoelectric thin film structure (due to the substantially AOG-free surface), while the relatively stress-neutral template surface used to form the piezoelectric material Due to the effect of , it is resistant to cracking once removed from the substrate.

1A is a simplified diagram illustrating an elastic resonator device 101 with top side interconnects according to an example of the present invention. As shown, device 101 includes a thinned seed substrate 112 having a single crystal piezoelectric thin film 120 overlying with micro-vias 129 . The micro-via 129 may include a top micro-trench 121 , a top-side metal plug 146 , a back-side trench 114 , and a back-side metal plug 147 . Although device 101 is shown with a single micro-via 129, device 101 may have multiple micro-vias. The upper side metal electrode 130 is formed to lie on the piezoelectric thin film 120 . The upper cap structure is bonded to the piezoelectric thin film 120 . This top cap structure has one or more top bond pads 143, one or more bond pads 144, and one or more through vias 151 connected to a top side metal 145 with a top side metal plug 146. A poser substrate 119 is included. Solder balls 170 are electrically coupled to one or more top bond pads 143 .

The thinned substrate 112 has first and second backside trenches 113 and 114 . The back side metal electrode 131 is formed under a portion of the thinned seed substrate 112 , the first back side trench 113 , and the top side metal electrode 130 . The backside metal plug 147 is formed under a portion of the thinned seed substrate 112 , the second backside trench 114 and the top side metal 145 . The rear-side metal plug 147 is electrically coupled to the upper-side metal plug 146 and the rear-side metal electrode 131 . The backside cap structure 161 is bonded to the thinned seed substrate 112 under the first and second backside trenches 113 and 114 . Further details regarding the manufacturing method of such a device will be discussed starting with FIG. 2 .

1B is a simplified diagram illustrating an elastic resonator device 102 with backside interconnects according to an example of the present invention. As shown, device 101 includes a thinned seed substrate 112 having a piezoelectric thin film 120 overlying with micro-vias 129 . The micro-via 129 may include a top micro-trench 121 , a top-side metal plug 146 , a back-side trench 114 , and a back-side metal plug 147 . Although device 102 is shown with a single micro-via 129, device 102 may have multiple micro-vias. The upper side metal electrode 130 is formed to lie on the piezoelectric thin film 120 . The upper cap structure is bonded to the piezoelectric thin film 120 . The upper cap structure 119 includes one or more bond pads 144 on the piezoelectric thin film 120 and bond pads connected to the top metal 145 . Topside metal 145 includes topside metal plug 146 .

The thinned substrate 112 has first and second backside trenches 113 and 114 . The back side metal electrode 131 is formed under a portion of the thinned seed substrate 112 , the first back side trench 113 , and the top side metal electrode 130 . The backside metal plug 147 is formed under a portion of the thinned seed substrate 112 , the second backside trench 114 , and the top side metal plug 146 . The rear-side metal plug 147 is electrically coupled to the top-side metal plug 146 . The backside cap structure 162 is bonded to the thinned seed substrate 112 below the first and second backside trenches. One or more backside bond pads 171 , 172 , 173 are formed within one or more portions of the backside cap structure 162 . Solder balls 170 are electrically coupled to one or more backside bond pads 171-173. Further details regarding the manufacturing method of such a device will be discussed starting with FIG. 14A.

1C is a simplified diagram illustrating an elastic resonator device with interposer/cap-free structure interconnections in accordance with an example of the present invention. As shown, device 103 includes a thinned seed substrate 112 having a single crystal piezoelectric thin film 120 overlying with micro-vias 129 . The micro-via 129 may include a top micro-trench 121 , a top-side metal plug 146 , a back-side trench 114 , and a back-side metal plug 147 . Although device 103 is shown with a single micro-via 129, device 103 may have multiple micro-vias. The upper side metal electrode 130 is formed to lie on the piezoelectric thin film 120 . The thinned substrate 112 has first and second backside trenches 113 and 114 . The back side metal electrode 131 is formed under a portion of the thinned seed substrate 112 , the first back side trench 113 , and the top side metal electrode 130 . The backside metal plug 147 is formed under a portion of the thinned seed substrate 112 , the second backside trench 114 and the top side metal 145 . The rear-side metal plug 147 is electrically coupled to the upper-side metal plug 146 and the rear-side metal electrode 131 . Further details regarding the manufacturing method of such a device will be discussed starting with FIG. 2 .

1D is a simplified diagram illustrating an elastic resonator device with interposer/capless structure interconnects with a shared backside trench in accordance with an example of the present invention. As shown, device 104 includes a thinned seed substrate 112 having a single crystal piezoelectric thin film 120 overlying with micro-vias 129 . The micro-via 129 may include a top-side micro-trench 121 , a top-side metal plug 146 , and a back-side metal plug 147 . Although device 104 is shown with a single micro-via 129, device 104 may have multiple micro-vias. The upper side metal electrode 130 is formed to lie on the piezoelectric thin film 120 . The thinned substrate 112 has a first back side trench 113 . The back side metal electrode 131 is formed under a portion of the thinned seed substrate 112 , the first back side trench 113 , and the top side metal electrode 130 . The backside metal 147 is formed under a portion of the thinned seed substrate 112 , the second backside trench 114 and the topside metal 145 . The rear-side metal 147 is electrically coupled to the upper-side metal plug 146 and the rear-side metal electrode 131 . Further details regarding the manufacturing method of such a device will be discussed starting with FIG. 2 .

2 and 3 are simplified diagrams illustrating steps for a method of fabricating an elastic resonator device according to an example of the present invention. This method illustrates a process for fabricating an elastic resonator device similar to that shown in FIG. 1A. 2 may represent method steps for providing a partially processed piezoelectric substrate. As shown, the device 200 includes a seed (or growth) substrate 110 having a piezoelectric thin film 120 formed thereon. In certain examples, the seed substrate may include silicon, silicon carbide, aluminum oxide, or monocrystalline aluminum gallium nitride material, or the like. The piezoelectric thin film 120 may include a piezoelectric single crystal layer or a thin piezoelectric single crystal layer. In some embodiments according to the present invention, as used herein, “single crystal piezoelectric layer” includes piezoelectric layers having a crystalline quality of less than about 0.5 degrees to about 0.4 degrees as measured at FWHM using XRD. In some embodiments according to the present invention, a "single crystal piezoelectric layer" includes piezoelectric layers having a crystalline quality of less than about 1.0 degrees to about 0.4 degrees measured at FWHM using XRD. In some embodiments according to the present invention, a “single crystal piezoelectric layer” includes piezoelectric layers having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees as measured at FWHM using XRD. Processes for forming the single crystal piezoelectric layer, such as those related to the formation of single crystal piezoelectric resonators and/or filters as shown in FIGS. 1-15, 16-31, 32-46, 47-59 It will be further appreciated that it can be applied to all embodiments described herein.

60 illustrates forming a single-crystal piezoelectric thin film by epitaxial growth of a stress-neutral template layer on a substrate in some embodiments according to the present invention, and sputtering the single-crystal piezoelectric thin film on the stress-neutral template layer. Methods of removing the substrate and stress-neutral template (6000 ) is a flowchart showing.

According to FIG. 60, a substrate 100 is loaded into a processing chamber (block 6005). It will be appreciated that the processing chamber can be any processing chamber that supports relatively highly ordered formation of material layers on a substrate. For example, the processing chamber may be a device that allows, for example, CVD processing (such as a metal organic CVD or MOCVD processing chamber), molecular beam epitaxy (MBE) processing, ALD processing, or the like. can Other types of processes may be used whereby a layer may be formed with a relatively high quality crystallinity on a substrate such that the layer is relatively free of abnormally oriented grains at the top surface of the layer, for example. 63 shows an exemplary MOCVD processing chamber that can be used to epitaxially deposit material on a substrate. As used herein, the term “ordered” will be understood to include processes that provide for epitaxial formation of layers on a substrate as opposed to less ordered formation methods such as sputtering. The substrate may be a silicon substrate, although other types of substrates may be used. The silicon substrate may have a specific crystal orientation, such as silicon <111>. Silicon substrates with other crystal orientations may also be used.

As further shown in FIG. 60, a nitride material comprising at least one Group III element, such as AlGaN, is placed on top of the substrate 100 to form the stress-neutral template layer 6101 as shown in FIG. It is deposited on the surface (block 6110). As recognized by the present inventors, the stress-neutral template layer 6101 is a relatively ordered deposition process, for example filed with the USPTO on Feb. 7, 2020, Attorney Docket No. 181246-00022 and entitled Low-vapor pressure metalorganic in CVD systems Apparatus For Forming Single Crystal Piezoelectric Layers Using Low-Vapor Pressure Metalorganic Precursors In CVD Systems And Methods Of Forming Single Crystal Piezoelectric Layers Using The Same , and may be formed using the MOCVD system shown in commonly assigned US Provisional Patent Application Serial No. 16/784,843, the entire contents of which are incorporated herein by reference. This approach can form the template layer to have a relatively high crystallinity quality, and in particular, the top surface of the stress-neutral template layer 6101 can be relatively free of abnormally oriented particles.

It will be appreciated that the stress neutral template layer 6101 may begin with a nucleation layer 6102 such as aluminum nitride (AlN) incorporating an increasing amount of gallium (Ga) as deposition progresses. . Thus, the stress neutral template layer 6101 can have a relatively high concentration of Ga at the top surface 6103. In some embodiments, the stress-neutral template layer 6101 may start as a nucleation layer 6102 of AlN and gradually increase the content of Ga, thereby a top surface of the stress-neutral template layer 6101. becomes close to GaN. Thus, the composition of the stress neutral template layer 6101 may be deposited according to the formula Al _x Ga _(1-x) N, in some embodiments according to the present invention, where the amount of Ga is from about 20% to about 80%. It will be appreciated that it can be in the range of In some embodiments, the ratio of Ga to the total amount of group-III material at the surface of the stress-neutral template layer 6101 (“1-x”) may range from about 0.5 to 1.0. In some embodiments according to the present invention, the Ga content can be kept constant as the deposition progresses. In some embodiments according to the present invention, the Ga content may be about 100% at the surface of the stress neutral template layer 6101 .

As recognized by the present inventors, increasing the Ga content as deposition of the stress-neutral template layer 6101 progresses can reduce the tension in the template material, thereby reducing the stress-neutral template layer 6101. will provide a stress in the range of about +200 MPa to about -200 MPa at the silver surface 6103. The stress in the template layer can also be configured by controlling the thickness T of the template layer 6101 with the profile used to control the composition. Thus, changing the composition (rate and target composition) during deposition and selecting a particular thickness T at which the template layer is grown can enable the desired stress neutrality of the template layer for the subsequent sputtering process. In some embodiments, the thickness T of the stress-neutral template layer from the surface of the Si substrate to the surface of the stress-neutral template layer 6101 ranges from about 400 nm to about 600 nm.

Still referring to FIG. 60 , a piezoelectric material may be sputtered onto the top surface 6103 of the stress neutral template layer 6101 (block 6015). Sputtering is filed with the USPTO on July 16, 2019, and the attorney document number is 181246-00010, and the name of the invention is methods of forming group Ⅲ piezoelectric thin films through sputtering ( METHODS OF FORMING GROUP Ⅲ PIEZOELECTRIC THIN FILMS VIA SPUTTERING ) Commonly assigned United States Patent Application Serial No. 16/513,143, the entire contents of which are incorporated herein by reference, and filed with the USPTO on January 14, 2020, Attorney Docket No. 181246-00020, entitled 1 METHODS OF FORMING GROUP Ⅲ PIEZOELECTRIC THIN FILMS VIA REMOVAL OF PORTIONS OF FIRST SPUTTERED MATERIAL , the entire contents of which are incorporated herein by reference , can be performed using the system described in commonly assigned US patent application Ser. No. 16/742,202. In some embodiments, the sputtering system and the MOCVD system referenced in block 6010 are different systems. In some embodiments, the piezoelectric material is selected from Group III elements including Al, Sc and Ga. Other materials such as Hf, Mg (HfMgAlN), Zr, (ZrMgAlN), and Cr (AlCrN) may also be included. For example, in some embodiments, a piezoelectric material may be sputtered AlScN onto the AlGaN or GaN stress neutral template layer 6101 to have an Sc concentration ranging from about 9% to about 20%.

As recognized by the present inventors, sputtering on a stress-neutral template layer 6101 of high crystalline qualities provides a single crystal piezoelectric thin film 120 with relatively low stress once the underlying template layer is removed for subsequent processing. can do. In particular, highly ordered formation of stress-neutral templates can provide high-quality crystalline structures such that the sputtered piezoelectric material can be of single-crystal quality without further processing. For example, in some embodiments according to the present invention, no thermal annealing is performed on the single crystal piezoelectric thin film. In contrast, some conventional processes discuss forming a high quality piezoelectric layer by first sputtering the polycrystalline piezoelectric layer and then annealing the polycrystalline piezoelectric layer to recrystallize it into a high quality piezoelectric layer.

In some embodiments according to the present invention, the single crystal piezoelectric thin film 120 may have a crystalline quality of less than about 1.0 degrees to about 0.4 degrees measured at FWHM using XRD. In some embodiments in accordance with the present invention, single crystal piezoelectric thin film 120 may have a crystalline quality of less than about 0.44 degrees to about 0.25 degrees as measured at FWHM using XRD.

In addition, the stress-neutral nature of the template layer may allow the sputtered piezoelectric material to have relatively low stress after removal of the template layer, whereby the single crystal piezoelectric thin film 120 may be incorporated into a single crystal piezoelectric resonator or filter. do. In contrast, if piezoelectric material is sputtered onto a structure that is not stress neutral, the resulting piezoelectric material may delaminate or otherwise deform when incorporated into a resonator or filter.

63 and 64 are graphs illustrating experimental XRD measurements for wafers formed according to FIG. 60 in some embodiments according to the present invention. According to FIG. 63, an AlGaN stress neutral template layer 6101 was formed with a Ga concentration of about 20% on a Si <111> substrate in some embodiments. FWHM using XRD of both sputtered AlScN (with 20% concentration of Sc) and AlGaN stress-neutral template layer 6101 (with about 20% concentration of Ga) as the piezoelectric thin film material, as shown in FIG. Measurements ranged from about 0.44 degrees to about 0.34 degrees. Experimental data is shown for four different wafers with the materials formed thereon as described above. 64 shows experimental data for measurements of materials used to form the wafers.

65 and 66 are experimental data showing the presence and relative absence of Anomalously Oriented Particles (AOG) in piezoelectric layers formed on AlN and AlGaN templates, respectively, in some embodiments according to the present invention. These are SEM images. According to FIG. 65 , the experimental SEM image shows the presence of AOG as lighter parts 6705 of the piezoelectric layer 6710 . In contrast, in FIG. 66 , the experimental SEM image shows that the single crystal piezoelectric layer 6810 is relatively free of AOG.

Referring back to FIG. 60, the single crystal piezoelectric thin film 120 is, for example, the piezoelectric thin film 120, 1620 shown in FIGS. 8 to 9A, 22 to 23, 39 to 40, and 52 to 53, respectively. , 3220, and 4720). Accordingly, the single crystal piezoelectric thin film 120 is bonded (block 6020) to, for example, a bond substrate (see 2210 in FIG. 22B). The substrate (substrate on which the stress-neutral template layer 6101 is formed—e.g., a growth substrate) and the stress-neutral template layer 6101 are removed as further described herein, thus the single crystal piezoelectric thin film ( 120) remains (ie, the remaining portion of single crystal piezoelectric thin film 120) (block 6025). Next, the rest of the single crystal piezoelectric thin film 120 is shown in, for example, FIGS. 8 to 9A, 22 to 23, 39 to 40, and 52 to 53 in some embodiments according to the present invention. used to complete the formation of a resonator or filter device as described herein as part of the described processes.

67 shows Si < 111> Table of experimental data including XRD measurements on the substrate. 67 shows the deposition conditions and results for four sputtered AlN films of 7500 Å on various substrates/templates. According to FIG. 67, Wafer 1 included the formation of sputtered AlN piezoelectric thin films directly on the bare substrate, which showed an XRD measurement of 1.29 degree FWHM, which also resulted in Wafer 1 cracking. In contrast, wafers 2-4 were formed as described above using power levels of 14.4W, 20W and 25W, respectively. The table in FIG. 67 shows that wafers 2-4 all exhibit XRD measurements from about 0.811 degrees to about 0.805 degrees FWHM.

3 may represent method steps for forming the top side metallization or top resonator metal electrode 130 . In certain instances, the topside metal electrode 130 may include molybdenum, aluminum, ruthenium, or titanium materials, or the like, and combinations thereof. This layer may be deposited and patterned on top of the piezoelectric layer by a lift-off process, wet etch process, dry etch process, metal printing process, metal laminating process, or the like. The lift-off process may include a sequential process of lithographic patterning, metal deposition, and lift-off steps to create the topside metal layer. Wet/dry etching processes may include sequential processes of metal deposition, lithographic patterning, metal deposition, and metal etching steps to create the topside metal layer. Those skilled in the art will recognize other variations, modifications and alternatives.

4A is a simplified diagram showing steps for a manufacturing method for an elastic resonator device 401 according to an example of the present invention. This figure may represent method steps for forming one or more topside micro-trenches 121 within a portion of a piezoelectric thin film 120 . This topside micro-trench 121 may serve as the primary interconnection junction between the topside and bottomside of an acoustic membrane to be developed in later method steps. In the example, the topside micro-trench 121 extends through the entirety of the piezoelectric thin film 120 and stops at the seed substrate 110 . These topside micro-trenches 121 may be formed through a dry etching process, a laser drilling process, or the like. 4b and 4c describe these options in more detail.

4b and 4c are simplified diagrams illustrating alternative methods for performing a method step as described in FIG. 4a. As shown, FIG. 4B shows the method steps using a laser drill that can quickly and accurately form a topside micro-trench 121 in a piezoelectric thin film 120 . In an example, a laser drill may be used to form a nominal 50 um hole, or 10 um to 500 um diameter holes, through the piezoelectric thin film 120 and stop at the seed substrate 110 below the interface between the layers 120 and 110. The protective layer 122 may be formed to cross over the piezoelectric thin film 120 and the upper metal electrode 130 . This protective layer 122 may serve to protect the device from laser debris and provide a mask for etching of the topside micro-vias 121 . In a specific example, the laser drill may be an 11 W high power diode pumped UV laser or the like. This mask 122 may subsequently be removed before proceeding to other steps. A mask can also be omitted from the laser drilling process, and an air stream can be used to remove the laser debris.

4C may represent method steps for using a dry etching process to form a topside micro-trench 121 in a piezoelectric thin film 120 . As shown, a lithographic masking layer 123 may be formed overlying the piezoelectric thin film 120 and the top metal electrode 130 . The topside micro-trench 121 may be formed by exposure to plasma, or the like.

4D and 4E are simplified diagrams illustrating an alternative method for performing the method steps as described in FIG. 4A. These figures may represent method steps for simultaneously fabricating a plurality of elastic resonator devices. In FIG. 4D, two devices are shown on die #1 and die #2, respectively. 4E shows the process of forming micro-vias 121 on their respective dies while also etching scribe lines 124 or dicing lines. In the example, etching of the scribe line 124 singulates the piezoelectric single crystal layer 120 and relieves its stress.

5-8 are simplified diagrams illustrating steps for a manufacturing method for an elastic resonator device according to an example of the present invention. 5 may represent method steps for forming one or more bond pads 140 and forming a topside metal 141 electrically coupled to at least one of the bond pads 140 . The top metal 141 may include a top metal plug 146 formed in the top micro-trench 121 . In a particular example, topside metal plug 146 fills topside micro-trench 121 to form the topside portion of the micro-via.

In an example, bond pads 140 and topside metal 141 may include a gold material or other interconnect metal material depending on the application of the device. These metal materials may be formed by a lift-off process, a wet etching process, a dry etching process, a screen printing process, an electroplating process, a metal printing process, or the like. In a specific example, the deposited metal materials may also serve as bond pads for a cap structure described below.

6 may represent method steps for preparing an elastic resonator device for bonding, which may be hermetic bonding. As shown, the top cap structure is placed over the partially treated elastic resonator device as described in the previous figures. The top cap structure is constructed using the interposer substrate 119 in two configurations: fully processed interposer version 601 (through glass vias) and partially processed interposer version 602 (blind via version). can be formed In the 601 version, interposer substrate 119 includes through via structures 151 extending through interposer substrate 119 and electrically coupled to lower bond pads 142 and upper bond pads 143. do. In the 602 version, the interposer substrate 119 includes blind via structures 152 that extend only through a portion of the interposer substrate 119 from the bottom side. These blind via structures 152 are also electrically coupled to lower bond pads 142 . In certain examples, the interposer substrate may include silicon, glass, smart glass, or other similar materials.

7 may represent method steps for bonding a top cap structure to a partially processed elastic resonator device. As shown, interposer substrate 119 is bonded to the piezoelectric layer by bond pads 140, 142 and topside metal 141, which are now bonded to bond pad 144 and topside metal 145. displayed This bonding process may be performed using a compression bond method or the like. 8 may represent thinning the seed substrate 110 , which may now be referred to as a thinned seed substrate 111 . This substrate thinning process may include grinding and etching processes or the like. In a particular example, this process may include a wafer back grinding process followed by stress relief, which may involve dry etching, CMP polishing or annealing processes.

9A is a simplified diagram showing steps for a manufacturing method for an elastic resonator device 901 according to an example of the present invention. 9A shows backside trenches 113 to allow access to the piezoelectric thin film 120 (or the piezoelectric layer 6120 or 6101 shown in FIGS. 62-63) from the backside of the thinned seed substrate 111. and 114). In some embodiments, the substrate thinning process described above with reference to FIG. 8 may be performed in combination with the process shown in FIG. 9A in which exposed portions of the piezoelectric layer surface are further treated to remove portions of the exposed piezoelectric layer. It will be understood that it can. For example, in some embodiments, the thinned substrate 112 is used as a mask to further remove the lowest portions of the piezoelectric thin film exposed by the thinned substrate 112, thereby reducing the amount of exposed piezoelectric layer. Removal of the initially formed portion may be performed. It will be appreciated that in some embodiments according to the present invention, the techniques described above with reference to FIG. 8 may also be used in accordance with FIG. 9A. The processes described above in connection with removing a portion of a piezoelectric thin film that is initially formed on a substrate may be other processes described herein, such as those relating to FIGS. 16-31 , 32-46 , and 47-59 . It will be further understood that the embodiments may be applied. For example, removal of an initially formed portion of a piezoelectric thin film formed using various processes may be applied to the structures and processes described with reference to FIGS. 24, 41 and 53.

In an example, the first backside trench 113 may be formed within the thinned seed substrate 111 and below the topside metal electrode 130 . The second backside trench 114 may be formed within the thinned seed substrate 111 and below the topside micro-trench 121 and the topside metal plug 146 . This substrate is now denoted as thinned substrate 112 . In a particular example, these trenches 113 and 114 may be formed using a deep reactive ion etching (DRIE) process, a Bosch process, or the like. The size, shape and number of trenches may vary depending on the design of the resonator device. In various examples, the first back-side trench may be formed in a shape of the top-side metal electrode or a trench shape similar to the shape of the back-side metal electrode. The first back-side trench may also be formed in a trench shape different from both the shapes of the top-side metal electrode and the back-side metal electrode.

9B and 9C are simplified diagrams illustrating an alternative method for performing method steps as described in FIG. 9A. Like FIGS. 4D and 4E , these figures may represent method steps for simultaneously fabricating a plurality of elastic resonator devices. In FIG. 9B, two devices with cap structures are shown on die #1 and die #2, respectively. 9C shows the process of forming backside trenches 113 and 114 on their respective die while also etching the scribe line 115 or dicing line. In the example, etching of the scribe line 115 provides an arbitrary way to singulate the backside wafer 112 .

10 is a simplified diagram showing steps for a manufacturing method for an elastic resonator device 1000 according to an example of the present invention. This figure may indicate a method step of forming the backside metal electrode 131 and the backside metal plug 147 in the backside trenches of the thinned seed substrate 112 . In an example, backside metal electrode 131 may be formed under one or more portions of thinned substrate 112 , within first backside trench 113 , and under topside metal electrode 130 . This process completes the resonator structure within the elastic resonator device. A backside metal plug 147 may be formed under one or more portions of the thinned substrate 112 , within the second backside trench 114 , and under the topside micro-trench 121 . The rear-side metal plug 147 may be electrically coupled to the upper-side metal plug 146 and the rear-side metal electrode 131 . In certain instances, the backside metal electrode 130 may include molybdenum, aluminum, ruthenium, or titanium materials or the like, and combinations thereof. The backside metal plug may include gold material, low-resistance interconnect metals, electrode metals, or the like. These layers may be deposited using the deposition methods described above.

11A and 11B are simplified diagrams illustrating alternative steps for a manufacturing method for an elastic resonator device according to an example of the present invention. These figures show methods of bonding a backside cap structure under a thinned seed substrate 112 . In FIG. 11A , the backside cap structure is a dry film cap 161 which may include a permanent photo-imageable dry film such as solder mask, polyimide or the like. Bonding of such cap structures can be cost effective and reliable, but may not create an airtight seal. In FIG. 11B, the backside cap structure is a substrate 162 that may include silicon, glass, or other similar material. Bonding of such substrates can provide a hermetic seal, but can be more expensive and require additional processes. Depending on the application, any of these backside cap structures may be bonded under the first and second backside vias.

12A-12E are simplified diagrams illustrating steps for a manufacturing method for an elastic resonator device according to an example of the present invention. More specifically, these figures describe additional steps for processing a blind via interposer ("602") version of the top cap structure. 12A shows an elastic resonator device 1201 with blind vias 152 in the top cap structure. In FIG. 12B , interposer substrate 119 is thinned, which forms a thinned interposer substrate 118 exposing blind vias 152 . This thinning process may be a combination of a grinding process and an etching process as described for thinning the seed substrate. In FIG. 12C , a redistribution layer (RDL) process and metallization process are performed to create top cap bond pads 160 formed overlying and electrically coupled to blind vias 152 . can be applied As shown in FIG. 12D , a ball grid array (BGA) process may be applied to form solder balls 170 overlying and electrically coupled to top cap bond pads 160 . This process leaves the elastic resonator device ready for wire bonding 171, as shown in FIG. 12E.

13 is a simplified diagram showing steps for a manufacturing method for an elastic resonator device according to an example of the present invention. As shown, device 1300 includes two fully processed elastic resonator devices ready to singulate to create individual devices. In an example, the die singulation process may be performed using a wafer dicing saw process, a laser cut singulation process, or other processes and combinations thereof.

14A-14G are simplified diagrams illustrating steps for a manufacturing method for an elastic resonator device according to an example of the present invention. This method illustrates a process for fabricating an elastic resonator device similar to that shown in FIG. 1B. The method for this example of an elastic resonator may follow steps similar to those described in FIGS. 1-5. Figure 14a shows where this method differs from the previously described method. Here, the top cap structure substrate 119 includes only one metallization layer with one or more bottom bond pads 142 . Compared to Fig. 6, since the interconnections will be formed on the lower side of the elastic resonator device, there is no via structure in the top cap structure.

14B-14F show method steps similar to those described in the first process flow. 14B may show method steps for bonding the top cap structure to the piezoelectric thin film 120 via bond pads 140, 142 and topside metal 141, which now have a topside metal plug 146. Represented by topside metal 145 and bond pads 144 . 14C may represent method steps for thinning the seed substrate 110, which forms a thinned seed substrate 111 similar to that described in FIG. 14D may represent method steps for forming first and second backside trenches similar to those described in FIG. 9A. 14E may represent method steps for forming a backside metal electrode 131 and a backside metal plug 147 similar to those described in FIG. 10 . 14F may represent method steps for bonding the backside cap structure 162 similar to those described in FIGS. 11A and 11B .

14G shows another step, different from the process flow described above. Here, the rear side bond pads 171 , 172 , and 173 are formed in the rear side cap structure 162 . In an example, these backside bond pads 171-173 may be formed through masking, etching and metal deposition processes similar to those used to form other metal materials. A BGA process may be applied to form solder balls 170 that contact these backside bond pads 171-173, which prepares the resonator device 1407 for wire bonding.

15A-15E are simplified diagrams illustrating steps for a manufacturing method for an elastic resonator device according to an example of the present invention. This method illustrates a process for fabricating an elastic resonator device similar to that shown in FIG. 1B. The method for this example may follow steps similar to those described in FIGS. 1-5 . Figure 15a shows where this method differs from that described above. A temporary carrier 218 with a layer of temporary adhesive 217 is attached to the substrate. In particular examples, temporary carrier 218 may include glass wafers, silicon wafers, or other wafers and the like.

15B-15F show method steps similar to those described in the first process flow. 15B may represent method steps for thinning the seed substrate 110, which forms a thinned substrate 111 similar to that described in FIG. In certain examples, thinning of the seed substrate 110 may include a backside grinding process followed by a stress relief process. The stress relieving process may include dry etching, chemical mechanical planarization (CMP) and annealing processes.

15C may represent method steps for forming a shared backside trench 113 similar to the techniques described in FIG. 9A. The main difference is that the shared backside trench is configured underneath all of the topside metal electrode 130, topside micro-trench 121 and topside metal plug 146. In an example, the shared backside trench 113 is a backside resonator cavity that can vary in size, shape (all possible geometries) and sidewall profile (tapered convex, tapered concave, or rectangular). In a particular example, formation of the shared backside trench 113 may include a litho-etching process that may include backside-to-front alignment and dry etching of the backside substrate 111 . The piezoelectric thin film 120 may serve as an etch stop layer for the formation of the shared backside trench 113 .

FIG. 15D may represent method steps for forming backside metal electrode 131 and backside metal 147 similar to those described in FIG. 10 . In an example, formation of the backside metal electrode 131 may include deposition and patterning of metal materials within the shared backside trench 113 . Here, the rear-side metal 131 serves as the electrode in the micro-via 121 and the back-side plug/connection metal 147 . The thickness, shape, and type of metal may vary as a function of the resonator/filter design. As an example, the back side electrode 131 and the via plug metal 147 may be different metals. In a specific example, these backside metals 131 and 147 may be deposited and patterned on the surface of the piezoelectric thin film 120 or rerouted to the backside of the substrate 112 . In an example, the backside metal electrode may be patterned to be configured within the boundaries of the shared backside trench such that the backside metal electrode does not contact one or more sidewalls of the seed substrate created during formation of the shared backside trench.

FIG. 15E shows bonding of a backside cap structure 162 similar to that described in FIGS. 11A and 11B after unbonding of the temporary carrier 218, and cleaning the top side of the device to remove the temporary adhesive 217. You can indicate the steps of how to do it. Those skilled in the art will recognize other variations, modifications and alternatives to the method steps described above.

As used herein, the term "substrate" can mean a bulk substrate, or an epitaxial region containing aluminum, gallium, or a ternary compound of aluminum and gallium and nitrogen, or functional regions, combinations, and the like. may include overlying growth structures.

Using the present invention, one or more advantages over existing techniques are achieved. In particular, the device can be manufactured in a relatively simple and cost effective manner using conventional materials and/or methods according to those skilled in the art. Using this method, a reliable single-crystal-based elastic resonator can be created using multiple schemes of three-dimensional stacking through a wafer-level process. These filters or resonators may be implemented as an RF filter device, RF filter system, or the like. Depending on the embodiment, one or more of these advantages may be achieved. Of course, other variations, modifications and alternatives may exist.

As 4G LTE and 5G become more popular day by day, wireless data communication requires high performance RF filters with frequencies above about 5 GHz. Bulk Acoustic Wave Resonators (BAWRs), which are widely used in these filters operating at frequencies below about 3 GHz, are prime candidates for meeting these needs. Current bulk acoustic wave resonators use polycrystalline piezoelectric AlN thin films, where the c-axis of each particle is aligned perpendicular to the surface of the film, allowing high piezoelectric performance, while the a or b-axis of the particle is randomly distributed. This unique particle distribution works well when the thickness of the piezoelectric film is greater than about 1 μm, which is the perfect thickness for bulk acoustic wave (BAW) filters operating at frequencies in the 1 to 3 GHz range. However, the quality of polycrystalline piezoelectric films degrades rapidly as the thicknesses decrease to less than about 0.5 um required for resonators and filters operating at frequencies above about 5 GHz.

Monocrystalline or epitaxial piezoelectric thin films grown on compatible crystalline substrates exhibit excellent crystalline quality and high piezoelectric performance down to a very thin thickness, for example 0.4 um. The present invention provides fabrication processes and structures of high quality bulk acoustic wave resonators with monocrystalline or epitaxial piezoelectric thin films for high frequency BAW filter applications.

BAWRs may require a piezoelectric material in crystalline form, i.e. polycrystalline or monocrystalline, for example AlN. The quality of a film is highly dependent on the chemical, crystallographic or topographical quality of the layer from which it is grown. In conventional BAWR processes (including film bulk acoustic resonator (FBAR) or solidly mounted resonator (SMR) geometries), the piezoelectric film is typically a patterned material composed of molybdenum (Mo), tungsten (W) or ruthenium (Ru). grown on the lower electrode. The surface geometry of the patterned bottom electrode has a significant effect on the crystalline orientation and crystalline quality of the piezoelectric film, requiring complex modifications of the structure.

Accordingly, the present invention uses single crystal piezoelectric films and thin film transfer processes to create a BAWR with improved ultimate quality factor and electro-mechanical coupling for RF filters. These methods and structures facilitate fabrication methods and structures of RF filters using monocrystalline or epitaxial piezoelectric films to meet the growing demands of modern data communications.

In an example, the present invention provides transfer structures and processes for elastic resonator devices that provide a flat, high quality single crystal piezoelectric film for high Q and good acoustic wave control at high frequencies. As described above, polycrystalline piezoelectric layers limit Q at high frequencies. Additionally, growing epitaxial piezoelectric layers on patterned electrodes affects the crystalline orientation of the piezoelectric layer, which limits the ability to have tight boundary control of the resulting resonators. As described further below, embodiments of the present invention may overcome these limitations and exhibit improved performance and cost effectiveness.

16A-16C,-31A-31C show a fabrication method for an elastic resonator device using a transfer structure with a sacrificial layer. In this series of figures described below, the "a" figures show simplified views showing top cross-sectional views of single crystal resonator devices according to various embodiments of the present invention. Figures "b" show simplified views showing longitudinal cross-sections of the same devices as in the "a" figures. Likewise, the "c" figures show simplified figures showing cross-sectional views in the width direction of the same devices as in the "a" figures. In some cases, certain features are omitted to emphasize other features and relationships between those features. Variations, modifications and alternatives to the examples shown in this series of figures will be recognized by those skilled in the art.

16A-16C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a piezoelectric thin film 1620 overlying a growth substrate 1610 . In an example, the growth substrate 1610 may include silicon (S), silicon carbide (SiC), sapphire, or other similar materials. The piezoelectric film 1620 may be a film containing a group III nitride such as aluminum nitride (AlN), gallium nitride (GaN), or other similar materials. Additionally, these piezoelectric substrates may be subject to a thickness trim. The piezoelectric thin film 1620 (with or without a seed layer) may be formed as described above with reference to FIGS. 60-64 in some embodiments.

17A-17C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a first electrode 1710 overlying a surface region of a piezoelectric thin film 1620 . In an example, the first electrode 1710 may include molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials. In a particular example, the first electrode 1710 may be subjected to a dry etch with a gradient. As an example, the slope may be about 60 degrees.

18A-18C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a first passivation layer 1810 overlying the first electrode 1710 and the piezoelectric thin film 1620 . In an example, the first passivation layer 1810 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a particular example, the first passivation layer 1810 can have a thickness ranging from about 50 nm to about 100 nm.

19A-19C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a sacrificial layer 1910 overlying a portion of the first electrode 1810 and a portion of the piezoelectric film 1620 . In an example, the sacrificial layer 1910 may include polycrystalline silicon (poly-Si), amorphous silicon (a-Si), or other similar materials. In a specific example, this sacrificial layer 1910 may be subjected to a graded dry etch and may be deposited to a thickness of about 1 um. Phosphorus doped SiO ₂ (PSG) can also be used as a sacrificial layer with different combinations of support layers (eg, SiNx).

20A-20C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for the single crystal elastic resonator device according to an example of the present invention. As shown, these figures show method steps for forming the sacrificial layer 1910 , the first electrode 1710 , and the support layer 2010 overlying the piezoelectric thin film 1620 . In an example, the support layer 2010 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN), or other similar materials. In a particular example, this support layer 2010 may be deposited to a thickness of about 2-3 um. As described above, in the case of the PSG sacrificial layer, other support layers (eg SiNx) may be used.

21A-21C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for polishing support layer 2010 to form polished support layer 2011 . In an example, the polishing process may include a chemical-mechanical planarization process or the like.

22A-22C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show turning the device over and physically bonding the overlying support layer 2011 over and over the bond substrate 2210 . In an example, the bond substrate 2210 is a bonding support layer 2220 overlying a substrate having silicon (Si), sapphire (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), silicon carbide (SiC), or other similar materials. ) (SiO ₂ or similar material). In certain embodiments, the bonding support layer 2220 of the bond substrate 2210 is physically bonded to the polished support layer 2011 . Additionally, the physical bonding process may include a room temperature bonding process followed by a 300° C. annealing process.

23A-23C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show the method steps of the removal of the growth substrate 1610, or otherwise the transfer of the piezoelectric thin film 1620. In an example, the removal process may include a grinding process, a blanket etch process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, or the like, and combinations thereof.

24A-24C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures form an electrode contact via 2410 in a piezoelectric film 1620 (which becomes the piezoelectric film 1621) overlying the first electrode 1710, the piezoelectric film 1620, and the sacrificial Method steps for forming one or more release holes 2420 in the first passivation layer 1810 overlying the layer 1910 are shown. Via formation processes can include various types of etching processes.

25A-25C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming the second electrode 2510 overlying the piezoelectric film 1621 . In an example, formation of the second electrode 2510 deposits molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; Next, it includes etching the second electrode 2510 to form the electrode cavity 2511 and removing the portion 2511 from the second electrode to form the top metal 2520. In addition, the upper metal 2520 is physically coupled to the first electrode 1720 through the electrode contact via 2410 .

26A-26C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures form a first contact metal 2610 overlying a portion of the second electrode 2510 and a portion of the piezoelectric film 1621, and a portion of the top metal 2520 and a portion of the piezoelectric film 1621. ) shows the method steps of forming a second contact metal 2611 overlying a portion of. In an example, the first and second contact metals include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or related alloys of these materials or other similar materials. can do.

27A-27C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a second passivation layer 2710 overlying the second electrode 2510 , the top metal 2520 , and the piezoelectric film 1621 . In an example, the second passivation layer 2710 may include silicon nitride (SiN), silicon oxide (SiOx) or other similar materials. In a particular example, the second passivation layer 2710 can have a thickness ranging from about 50 nm to about 100 nm.

28A-28C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for removing the sacrificial layer 1910 to form the air cavity 2810 . In an example, the removal process may include a poly-Si etch or an a-Si etch, or the like.

29A-29C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a sacrificial layer for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures show method steps for processing second electrode 2510 and top metal 2520 to form treated second electrode 2910 and top metal 2920 . This step may follow the formation of second electrode 2510 and top metal 2520 . In an example, processing of these two components deposits molybdenum (Mo), ruthenium (Ru), tungsten (W) or other similar materials; This material is then etched (eg, dry etched or the like) to form a treated second electrode 2910 having an electrode cavity 2912 and a treated top metal 2920. The processed top metal 2920 remains separated from the processed second electrode 2910 by the removal of portion 2911 . In a particular example, the treated second electrode 2910 is characterized by adding an energy confining structure configured on the treated second electrode 2910 to increase Q.

30A-30C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a sacrificial layer for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures show method steps for processing the first electrode 1710 to form the treated first electrode 2310 . This step may follow formation of the first electrode 1710 . In an example, processing of these two components deposits molybdenum (Mo), ruthenium (Ru), tungsten (W) or other similar materials; and then etching (eg, dry etching or the like) this material to form a treated first electrode 3010 having an electrode cavity, similar to the treated second electrode 2910. do. Air cavity 2811 shows the change in cavity shape due to the treated first electrode 3010. In a specific example, the treated first electrode 3010 is characterized by adding an energy confining structure configured on the treated second electrode 3010 to increase Q.

31A-31C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a sacrificial layer for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures process the first electrode 1710 to form a treated first electrode 2310, and process the second electrode 2510/top metal 2520 to form a treated second electrode. Method steps for forming electrode 2910/treated top metal 2920 are shown. These steps may follow the formation of each individual electrode, as described with respect to FIGS. 29A-29C and 30A-30C. Other variations, modifications and alternatives will be recognized by those skilled in the art.

32A-32C and 46A-46C show a fabrication method for an elastic resonator device using a transfer structure without a sacrificial layer. In this series of figures described below, the "a" figures show simplified views showing top cross-sectional views of single crystal resonator devices according to various embodiments of the present invention. Figures "b" show simplified views showing longitudinal cross-sections of the same devices as in the "a" figures. Likewise, the "c" figures show simplified figures showing cross-sectional views in the width direction of the same devices as in the "a" figures. In some cases, certain features are omitted to emphasize other features and relationships between those features. Variations, modifications and alternatives to the examples shown in this series of figures will be recognized by those skilled in the art.

32A-32C are simplified diagrams showing various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a piezoelectric film 3220 overlying a growth substrate 3210 . In an example, growth substrate 3210 may include silicon (S), silicon carbide (SiC), or other similar materials. The piezoelectric film 3220 may be an epitaxial film including aluminum nitride (AlN), gallium nitride (GaN), or other similar materials. Additionally, such piezoelectric substrates may be subject to thickness trimming. The piezoelectric thin film 3220 (with or without a seed layer) may be formed as described above with reference to FIGS. 16 and 60-64 in some embodiments.

33A-33C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming the first electrode 3310 overlying the surface region of the piezoelectric film 3220 . In an example, the first electrode 3310 may include molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials. In a specific example, the first electrode 3310 may be subjected to a dry etch with a gradient. As an example, the slope may be about 60 degrees.

34A-34C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a first passivation layer 3410 overlying the first electrode 3310 and the piezoelectric film 3220 . In an example, the first passivation layer 3410 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a particular example, the first passivation layer 3410 can have a thickness ranging from about 50 nm to about 100 nm.

35A-35C are simplified diagrams showing various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a support layer 3510 overlying the first electrode 3310 and the piezoelectric film 3220 . In an example, the support layer 3510 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN), or other similar materials. In a particular example, this support layer 3510 may be deposited to a thickness of about 2-3 um. As described above, in the case of the PSG sacrificial layer, other support layers (eg SiNx) may be used.

36A-36C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show optional method steps for processing support layer 3510 (to form support layer 3511) within region 3610. In an example, the process may include partial etching of the support layer 3510 to create a flat bond surface. In certain instances, processing may include a cavity region. In other examples, this step may be replaced with a polishing process such as a chemical-mechanical planarization process or the like.

37A-37C are simplified diagrams showing various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming an air cavity 3710 within a portion of support layer 3511 (to form support layer 3512). In an example, cavity formation may include an etching process stopping at the first passivation layer 3410 .

38A-38C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming one or more cavity vent holes 3810 in a portion of the piezoelectric film 3220 through the first passivation layer 3410. In an example, cavity vent 3810 is coupled to air cavity 3710 .

39A-39C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show turning the device over and physically bonding the overlying support layer 3512 over and over the bond substrate 3910 . In an example, the bond substrate 3910 is a bonding support layer 3920 overlying a substrate having silicon (Si), sapphire (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), silicon carbide (SiC), or other similar materials. ) (SiO ₂ or similar material). In certain embodiments, the bonding support layer 3920 of the bond substrate 3910 is physically bonded to the polished support layer 3512. Additionally, the physical bonding process may include a room temperature bonding process followed by a 300° C. annealing process.

40A-40C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show the method steps of the removal of the growth substrate 3210, or otherwise the transfer of the piezoelectric film 3220. In an example, the removal process may include a grinding process, a blanket etch process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, or the like, and combinations thereof.

41A-41C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming an electrode contact via 4110 in the piezoelectric film 3220 overlying the first electrode 3310 . Via formation processes can include various types of etching processes.

42A-42C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a second electrode 4210 overlying the piezoelectric film 3220 . In an example, the formation of the second electrode 4210 deposits molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; Next, it includes etching the second electrode 4210 to form the electrode cavity 4211 and removing the portion 4211 from the second electrode to form the top metal 4220. In addition, the upper metal 4220 is physically coupled to the first electrode 3310 through the electrode contact via 4110 .

43A-43C are simplified diagrams illustrating various cross-sectional views of method steps for a single crystal elastic resonator device and a transfer process for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures form a first contact metal 4310 overlying a portion of the second electrode 4210 and a portion of the piezoelectric film 3220, and a portion of the top metal 4220 and a portion of the piezoelectric film 3220. ) shows the method steps of forming a second contact metal 4311 overlying a portion of. In an example, the first and second contact metals may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or other similar materials. These figures also show method steps for forming a second passivation layer 4320 overlying the second electrode 4210 , the top metal 4220 , and the piezoelectric film 3220 . In an example, the second passivation layer 4320 may include silicon nitride (SiN), silicon oxide (SiOx) or other similar materials. In certain examples, the second passivation layer 4320 can have a thickness ranging from about 50 nm to about 100 nm.

44A-44C are simplified diagrams showing various cross-sectional views of method steps for a single crystal elastic resonator device, and a transfer process for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures show method steps for processing second electrode 4210 and top metal 4220 to form treated second electrode 4410 and top metal 4420 . This step may follow the formation of second electrode 4210 and top metal 4220 . In an example, processing of these two components deposits molybdenum (Mo), ruthenium (Ru), tungsten (W) or other similar materials; This material is then etched (eg, dry etched or the like) to form a treated second electrode 4410 having an electrode cavity 4412 and a treated top metal 4420 . The processed top metal 4420 remains separated from the processed second electrode 4410 by the removal of portion 4411 . In a particular example, the treated second electrode 4410 is characterized by adding an energy confining structure configured on the treated second electrode 4410 to increase Q.

45A-45C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a sacrificial layer for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures show method steps for processing the first electrode 3310 to form a treated first electrode 4510 . This step may follow the formation of the first electrode 3310 . In an example, processing of these two components deposits molybdenum (Mo), ruthenium (Ru), tungsten (W) or other similar materials; and then etching (eg, dry etching or the like) this material to form a treated first electrode 4510 having an electrode cavity, similar to the treated second electrode 4410. do. Air cavity 3711 shows the change in cavity shape due to the treated first electrode 4510. In a particular example, the treated first electrode 4510 is characterized by adding an energy confining structure configured on the treated second electrode 4510 to increase Q.

46A-46C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a sacrificial layer for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures process the first electrode 3310 to form a treated first electrode 4510, and process the second electrode 4210/top metal 4220 to form a treated second electrode. Method steps for forming electrode 4410/treated top metal 4420 are shown. These steps may follow formation of each individual electrode, as described with respect to FIGS. 44A-44C and 45A-45C. Other variations, modifications and alternatives will be recognized by those skilled in the art.

47A-47C and 59A-59C show a fabrication method for an elastic resonator device using a transfer structure with a multi-layer mirror structure. In this series of figures described below, the "a" figures show simplified views showing top cross-sectional views of single crystal resonator devices according to various embodiments of the present invention. Figures "b" show simplified views showing longitudinal cross-sections of the same devices as in the "a" figures. Likewise, the "c" figures show simplified figures showing cross-sectional views in the width direction of the same devices as in the "a" figures. In some cases, certain features are omitted to emphasize other features and relationships between those features. Variations, modifications and alternatives to the examples shown in this series of figures will be recognized by those skilled in the art.

47A-47C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a piezoelectric film 4720 overlying a growth substrate 4710 . In an example, the growth substrate 4710 may include silicon (S), silicon carbide (SiC), or other similar materials. The piezoelectric thin film 4720 may be an epitaxial film containing aluminum nitride (AlN), gallium nitride (GaN), or other similar materials. Additionally, such piezoelectric substrates may be subject to thickness trimming. The piezoelectric thin film 4720 (with or without a seed layer) may be formed as described above with reference to FIGS. 60-64 in some embodiments.

48A-48C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a first electrode 4810 overlying the surface region of the piezoelectric film 4720 . In an example, the first electrode 4810 may include molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials. In a particular example, the first electrode 4810 may be subjected to a dry etch with a gradient. As an example, the slope may be about 60 degrees.

49A-49C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a multilayer mirror or reflector structure. In the example, the multilayer mirror includes at least one pair of layers having a low impedance layer 4910 and a high impedance layer 4920 . 49A-49C, two pairs of low/high impedance layers are shown (low impedance 4910 and 4911; high impedance 4920 and 4921). In an example, the mirror/reflector area may be larger than the resonator area and may include the resonator area. In certain embodiments, the thickness of each layer is about 1/4 the wavelength of an acoustic wave at the target frequency. The layers can be deposited in sequence and then etched, or each layer can be deposited and etched individually. In another example, the first electrode 4810 may be patterned after the mirror structure is patterned.

50A-50C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show the method steps of forming a support layer 5010 overlying the mirror structure (layers 4910, 4911, 4920, and 4921), the first electrode 4810, and the piezoelectric film 4720. shows In an example, the support layer 5010 may include silicon dioxide (SiO ₂ ), silicon nitride (SiN), or other similar materials. In a specific example, this support layer 5010 may be deposited to a thickness of about 2-3 um. As described above, other support layers (eg SiNx) may be used.

51A-51C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for the single crystal elastic resonator device according to an example of the present invention. As shown, these figures show method steps for polishing support layer 5010 to form polished support layer 5011 . In an example, the polishing process may include a chemical-mechanical planarization process or the like.

52A-52C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show turning the device over and physically bonding the overlying support layer 5011 overlying the bond substrate 5210 . In an example, the bond substrate 5210 is a bonding support layer 5220 overlying a substrate having silicon (Si), sapphire (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), silicon carbide (SiC), or other similar materials. ) (SiO ₂ or similar material). In certain embodiments, the bonding support layer 5220 of the bond substrate 5210 is physically bonded to the polished support layer 5011 . Additionally, the physical bonding process may include a room temperature bonding process followed by a 300° C. annealing process.

53A-53C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show the method steps of the removal of the growth substrate 4710, or otherwise the transfer of the piezoelectric thin film 4720. In an example, the removal process may include a grinding process, a blanket etch process, a film transfer process, an ion implantation transfer process, a laser crack transfer process, or the like, and combinations thereof.

54A-54C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming an electrode contact via 5410 in a piezoelectric film 4720 overlying a first electrode 4810 . Via formation processes can include various types of etching processes.

55A-55C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures show method steps for forming a second electrode 5510 overlying the piezoelectric film 4720 . In an example, formation of the second electrode 5510 deposits molybdenum (Mo), ruthenium (Ru), tungsten (W), or other similar materials; Next, it includes etching the second electrode 5510 to form the electrode cavity 5511 and removing the portion 5511 from the second electrode to form the top metal 5520. In addition, the top metal 5520 is physically coupled to the first electrode 5520 through the electrode contact via 5410 .

56A-56C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device and a multilayer mirror for single crystal elastic resonator devices according to an example of the present invention. As shown, these figures form a first contact metal 5610 overlying a portion of the second electrode 5510 and a portion of the piezoelectric film 4720, and a portion of the top metal 5520 and the piezoelectric film 4720. ) shows the method steps of forming a second contact metal 5611 overlying a portion of . In an example, the first and second contact metals may include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or other similar materials. This figure also shows method steps for forming a second passivation layer 5620 overlying the second electrode 5510 , the top metal 5520 and the piezoelectric film 4720 . In an example, the second passivation layer 5620 may include silicon nitride (SiN), silicon oxide (SiOx), or other similar materials. In a particular example, the second passivation layer 5620 can have a thickness ranging from about 50 nm to about 100 nm.

57A-57C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a multilayer mirror for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures show method steps for processing second electrode 5510 and top metal 5520 to form treated second electrode 5710 and top metal 5720 . This step may follow the formation of second electrode 5710 and top metal 5720 . In an example, processing of these two components deposits molybdenum (Mo), ruthenium (Ru), tungsten (W) or other similar materials; This material is then etched (eg, dry etched or the like) to form a treated second electrode 5410 having an electrode cavity 5712 and a treated top metal 5720. The processed top metal 5720 remains separated from the processed second electrode 5710 by the removal of portion 5711 . In a particular example, this process provides a greater thickness to the second electrode and top metal while creating electrode cavity 5712 . In a specific example, the treated second electrode 5710 is characterized by adding an energy confining structure configured on the treated second electrode 5710 to increase Q.

58A-58C are simplified diagrams showing various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a multilayer mirror for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures show method steps for processing the first electrode 4810 to form a treated first electrode 5810 . This step may follow formation of the first electrode 4810 . In an example, processing of these two components deposits molybdenum (Mo), ruthenium (Ru), tungsten (W) or other similar materials; and then etching (eg, dry etching or the like) this material to form a treated first electrode 5810 having an electrode cavity, similar to the treated second electrode 5710. do. Compared to the previous two examples, there are no air cavities. In a particular example, the treated first electrode 5810 is characterized by the addition of an energy confining structure configured on the treated second electrode 5810 to increase Q.

59A-59C are simplified diagrams illustrating various cross-sectional views of method steps for a transfer process using a single crystal elastic resonator device, and a multilayer mirror for single crystal elastic resonator devices, according to another example of the present invention. As shown, these figures process the first electrode 4810 to form a treated first electrode 5810, and process the second electrode 5510/top metal 5520 to form a treated second electrode. Method steps for forming electrode 5710/treated top metal 5720 are shown. These steps may follow formation of each individual electrode, as described with respect to FIGS. 57A-57C and 58A-58C. Other variations, modifications and alternatives will be recognized by those skilled in the art.

In each of the previous examples of transfer processes, energy confining structures may be formed on the first electrode, the second electrode, or both. In an example, these energy confining structures are mass loaded areas surrounding the resonator region. The resonator region is a region where the first electrode, the piezoelectric layer, and the second electrode overlap. A larger mass load within the energy confining structure lowers the cutoff frequency of the resonator. The cutoff frequency is a lower limit or an upper limit of a frequency at which an elastic wave can propagate in a direction parallel to the surface of the piezoelectric film. Therefore, since the cutoff frequency is a resonant frequency at which a wave travels along the thickness direction, it is determined by the entire laminated structure of the resonator along the vertical direction. In piezoelectric films (eg, AlN), elastic waves of a frequency lower than the cutoff frequency can propagate in a parallel direction along the surface of the film, that is, the elastic waves exhibit high-band cutoff-type dispersion characteristics. In this case, the mass loaded region surrounding the resonator provides a barrier preventing elastic waves from propagating out of the resonator. In doing so, this property increases the quality factor of the resonator, improves the performance of the resonator, and consequently improves the performance of the filter.

Additionally, the uppermost monocrystalline piezoelectric layer may be replaced by a polycrystalline piezoelectric film. In these films, the lower part close to the interface with the substrate has poor crystalline quality with smaller grain sizes and wider piezoelectric polarization orientation distribution than the upper part of the film close to the surface. This is due to the polycrystalline growth of the piezoelectric film, i.e. nucleation and that the initial film has random crystalline orientations. Considering AlN as a piezoelectric material, the growth rate or polarization orientation along the c-axis is higher than other crystalline orientations, which increases the proportion of particles with the c-axis perpendicular to the growth surface as the film grows thicker. In a typical polycrystalline AlN film of about 1 um thickness, the upper part of the film close to the surface has better crystalline quality and better alignment in terms of piezoelectric polarization. By using the thin film transfer process contemplated in the present invention, it is possible to use the upper part of the polycrystalline film in high frequency BAW resonators with very thin piezoelectric films. This may be done by removing a portion of the piezoelectric layer during the growth substrate removal process. Of course, there may be other variations, modifications and alternatives.

While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. As an example, a packaged device may include any combination of elements described above as well as outside of this specification. Accordingly, the above description and examples are not to be regarded as limiting the scope of the present invention, which is defined by the appended claims.

Claims (25)

As a method of forming a piezoelectric thin film,
depositing a material on the first surface of the Si substrate to provide a stress neutral template layer;
sputtering a piezoelectric thin film containing a Group III element and nitrogen on the stress-neutral template layer;
treating a second surface of the Si substrate opposite the first surface to remove the Si substrate and the stress neutral template layer to provide a remainder of the piezoelectric thin film; and
Forming a piezoelectric resonator in the remaining portion of the piezoelectric thin film.
How to include. The method of claim 1 , wherein depositing a material on the first surface of the Si substrate comprises chemical vapor deposition (chemical vapor deposition) to provide the stress neutral template layer to have a stress in the range of about -200 MPa to about +200 MPa. A method comprising performing Chemical Vapor Deposition (CVD) or Molecular Bean Epitaxy (MBE). 3. The method of claim 2, wherein depositing a material on the first surface of the Si substrate comprises a metal organic chemical vapor phase to deposit layers of Al _x Ga _(1-x) N on the first surface of the Si substrate. A method comprising performing vapor deposition (MOCVD). 4. The method of claim 3, wherein the concentration of Ga is in the range of about 20% to about 80% at the surface of the stress neutral template layer. 4. The method of claim 3, wherein the thickness of the stress-neutral template layer from the first surface of the Si substrate to the surface of the stress-neutral template layer is in a range of about 400 nm to about 600 nm. The method of claim 1 , wherein depositing a material on the first surface of the Si substrate comprises metal organic chemical vapor phase to deposit layers of Al _x Ga _(1-x) N on the first surface of the Si substrate. A method comprising performing vapor deposition (MOCVD). 7. The method of claim 6 wherein performing MOCVD to deposit Al _x Ga _(1-x) N on the first surface of the Si substrate first nucleates AlN in contact with the first surface of the Si substrate. A method comprising forming a layer. 4. The method of claim 3, wherein sputtering the piezoelectric thin film comprises sputtering Al and Sc onto the surface of the stress neutral template layer to provide an AlScN piezoelectric thin film. 9. The method of claim 8, wherein the AlScN piezoelectric thin film has an Sc concentration ranging from about 9% to about 20% Sc. 7. The method of claim 6, wherein the ratio of Ga to the total amount of Group III material (&quot;1-x&quot;) at the surface of the stress-neutral template layer is in the range of about 0.5 to 1.0;
Sputtering the piezoelectric thin film comprises sputtering Al onto the surface of the stress neutral template layer to provide an AlN piezoelectric thin film having a crystalline quality of approximately less than about 0.5 degrees to about 0.4 degrees as measured at FWHM using XRD. A method comprising the steps of: 7. The method of claim 6, wherein the ratio of Ga to the total amount of Group III material (&quot;1-x&quot;) at the surface of the stress-neutral template layer is in the range of about 0.5 to 1.0;
Sputtering the piezoelectric thin film sputters Al and Sc onto the surface of the stress neutral template layer to provide an AlScN piezoelectric thin film having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees as measured at FWHM using XRD A method comprising the steps of: 11. The method of claim 10, wherein sputtering the piezoelectric thin film is performed at a power level of about 14 W to about 25 W. 3. The method of claim 2, wherein treating the second surface of the Si substrate comprises removing the Si substrate and about 500 angstroms of the stress neutral template layer. The method of claim 1 , wherein the Si substrate comprises a Si <111> substrate. 2. The method of claim 1, wherein the piezoelectric thin film sputtered on the template layer is substantially free of abnormally oriented grains. As a method of forming a single crystal piezoelectric thin film,
epitaxially depositing a material on the first surface of the Si substrate to provide a template layer;
sputtering a single crystal piezoelectric thin film containing a Group III element and nitrogen on the template layer;
treating a second surface of the Si substrate opposite the first surface to remove the Si substrate and the template layer to provide a remainder of the single crystal piezoelectric thin film; and
Forming a single crystal piezoelectric resonator in the remaining portion of the single crystal piezoelectric thin film.
How to include. 17. The method of claim 16, wherein epitaxially depositing material on the first surface of the Si substrate comprises performing chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). 17. The method of claim 16, wherein the epitaxially depositing step epitaxially deposits a material onto the first surface of the Si substrate to provide a stress neutral template layer having a stress in the range of about -200 MPa to about +200 MPa. A method comprising depositing. 17. The method of claim 16, wherein epitaxially depositing a material on the first surface of the Si substrate comprises a metal organic method to deposit layers of Al _x Ga _(1-x) N on the first surface of the Si substrate. A method comprising performing chemical vapor deposition (MOCVD). 20. The method of claim 19, wherein performing MOCVD to deposit Al _x Ga _(1-x) N on the first surface of the Si substrate first comprises a nucleation layer of AlN in contact with the first surface of the Si substrate. A method comprising the step of forming a. 20. The method of claim 19, wherein the ratio of Ga to the total amount of Group III material ("1-x") at the surface of the template layer is in the range of about 0.5 to 1;
sputtering the single crystal piezoelectric thin film comprises sputtering Al and Sc on the surface of the template layer to provide an AlScN piezoelectric thin film having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees as measured at FWHM using XRD. Including, method. 20. The method of claim 19, wherein the concentration of Ga is in the range of about 20% to about 80% at the surface of the template layer. 20. The method of claim 19, wherein the thickness of the template layer from the first surface of the Si substrate to the surface of the template layer is in a range of about 400 nm to about 600 nm. As a method of forming a piezoelectric thin film,
depositing a material on the first surface of the Si substrate to provide a template layer surface having a stress ranging from about -200 Mpa to about +200 MPa;
sputtering a single crystal piezoelectric thin film containing a Group III element and nitrogen on the surface of the template layer;
the Si opposite to the first surface to remove the Si substrate and the template layer surface to provide a remainder of the single crystal piezoelectric thin film having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees as measured at FWHM using XRD treating the second surface of the substrate; and
Forming a single crystal piezoelectric resonator in the remaining portion of the single crystal piezoelectric thin film.
How to include. As a method of forming a piezoelectric thin film,
depositing a material onto the first surface of the Si substrate using MOCVD or MBE to provide a template layer surface having a stress in the range of about -200 Mpa to about +200 MPa;
sputtering a single crystal piezoelectric thin film containing a Group III element and nitrogen on the surface of the template layer;
the Si opposite to the first surface to remove the Si substrate and the template layer surface to provide a remainder of the single crystal piezoelectric thin film having a crystalline quality of less than about 0.44 degrees to about 0.25 degrees as measured at FWHM using XRD treating the second surface of the substrate; and
Forming a single crystal piezoelectric resonator in the remaining portion of the single crystal piezoelectric thin film.
How to include.

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