TW202207314A - 具有多通道主動區之半導體元件 - Google Patents

具有多通道主動區之半導體元件 Download PDF

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TW202207314A
TW202207314A TW110116841A TW110116841A TW202207314A TW 202207314 A TW202207314 A TW 202207314A TW 110116841 A TW110116841 A TW 110116841A TW 110116841 A TW110116841 A TW 110116841A TW 202207314 A TW202207314 A TW 202207314A
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Taiwan
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pattern
insulating layer
semiconductor
source
channel
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TW110116841A
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English (en)
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金文鉉
鄭舜文
河大元
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南韓商三星電子股份有限公司
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Publication of TW202207314A publication Critical patent/TW202207314A/zh

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Abstract

本發明提供一種多通道絕緣層上半導體（SOI）電晶體，包含其上具有電絕緣層的基底及電絕緣層上的半導體主動層。亦提供內埋於半導體主動層內的間隔開的絕緣閘極電極的豎直堆疊。此豎直堆疊包含鄰近電絕緣層延伸的第一絕緣閘極電極及與半導體主動層的表面間隔開的第(N-1)絕緣閘極電極，其中N為大於二的正整數。第N絕緣閘極電極設置於半導體主動層的表面上。一對源極/汲極區設置於半導體主動層內。這些源極/汲極區鄰近間隔開的絕緣閘極電極的豎直堆疊的相對側延伸。在這些態樣中的一些中，半導體主動層在所述對源極/汲極區與電絕緣層之間延伸，而第一絕緣閘極電極接觸電絕緣層。

Description

具有多通道主動區之半導體元件以及其製造方法
[優先權申請案的引用]
此美國非臨時專利申請案根據35 U.S.C. § 119主張2020年8月4日申請的韓國專利申請案第10-2020-0097389號的優先權，所述申請案的揭露內容以引用的方式併入本文中。
本發明概念的實施例是關於半導體元件以及其形成方法，且更特定而言，是關於場效電晶體以及形成場效電晶體的方法。
半導體元件可包含積體電路，所述積體電路包含金屬氧化物半導體場效電晶體（metal-oxide-semiconductor field effect transistors；MOSFET），包含互補式金屬氧化物半導體（complementary metal-oxide-semiconductor；CMOS）場效電晶體（field effect transistors；FET）。隨著半導體元件的大小及設計規則已減小，MOSFET的佈局大小（例如，佔據面積）亦已按比例縮小。不幸的是，MOSFET的大小減小可能使半導體元件的許多操作特性劣化。因此，已開發出用於形成半導體元件的各種方法以達成極佳效能，同時克服與高整合度相關聯的許多限制。
本發明概念的實施例可提供具有改良的可靠性及電特性的半導體元件。
在一態樣中，一種半導體元件可包含支撐基底、支撐基底上的絕緣層、絕緣層上的半導體圖案（其中半導體圖案與絕緣層接觸）以及半導體圖案上的一對源極/汲極圖案。亦提供通道結構，所述通道結構安置於所述一對源極/汲極圖案之間。通道結構包含堆疊且彼此間隔開的通道圖案。亦提供閘極電極，所述閘極電極與通道結構相交且在第一方向上延伸。閘極電極可包含安置於通道結構與絕緣層之間的第一部分，且第一部分的底部表面的水平面可低於源極/汲極圖案的最底部表面的水平面。
在另一態樣中，一種半導體元件可包含支撐基底、支撐基底上的絕緣層以及半導體圖案，所述半導體圖案設置於絕緣層上且與絕緣層接觸。一對源極/汲極圖案設置於半導體圖案上，且提供通道結構，所述通道結構安置於所述一對源極/汲極圖案之間。通道結構包含至少一個通道圖案。提供閘極電極，所述閘極電極與通道結構相交且在第一方向上延伸。閘極電極可包含安置於絕緣層與通道結構的最下部分之間的一個部分，且所述一個部分可穿透半導體圖案。源極/汲極圖案的下部部分可位於半導體圖案中。源極/汲極圖案可藉由插入於其間的半導體圖案而與絕緣層間隔開。
在另一態樣中，半導體元件可包含支撐基底、支撐基底上的絕緣層以及第一半導體圖案及第二半導體圖案，所述第一半導體圖案及第二半導體圖案設置於絕緣層上且分別包含在第一方向上彼此鄰近的PMOSFET區及NMOSFET區。一對第一源極/汲極圖案設置於第一半導體圖案上，且一對第二源極/汲極圖案設置於第二半導體圖案上。第一通道結構設置於所述對第一源極/汲極圖案之間，且第二通道結構設置於所述對第二源極/汲極圖案之間。且，第一通道結構及第二通道結構中的每一者包含依序堆疊且彼此間隔開的第一通道圖案、第二通道圖案以及第三通道圖案。另外，提供第一閘極電極及第二閘極電極，所述第一閘極電極及第二閘極電極在第一方向上延伸且分別與第一通道結構及第二通道結構相交。第一閘極電極及第二閘極電極中的每一者包含絕緣層與第一通道圖案之間的第一部分、第一通道圖案與第二通道圖案之間的第二部分、第二通道圖案與第三通道圖案之間的第三部分以及第三通道圖案上的第四部分。提供第一閘極絕緣層及第二閘極絕緣層，所述第一閘極絕緣層及第二閘極絕緣層分別安置於第一通道結構與第一閘極電極之間及第二通道結構與第二閘極電極之間。第一閘極間隔件及第二閘極間隔件分別設置於第一閘極電極及第二閘極電極的側壁上。第一閘極封蓋圖案及第二閘極封蓋圖案分別設置於第一閘極電極及第二閘極電極的頂部表面上。第一層間絕緣層設置於第一閘極封蓋圖案及第二閘極封蓋圖案上。且，提供源極/汲極觸點，所述源極/汲極觸點穿透第一層間絕緣層，以便連接至第一源極/汲極圖案及第二源極/汲極圖案。另外，閘極觸點穿透第一層間絕緣層以及第一閘極封蓋圖案及第二閘極封蓋圖案，以便分別連接至第一閘極電極及第二閘極電極。第二層間絕緣層設置於第一層間絕緣層上，且第一金屬層設置於第二層間絕緣層中。第一金屬層包含電連接至源極/汲極觸點及閘極觸點的第一互連線。第一互連線在與第一方向相交的第二方向上彼此平行地延伸。第三層間絕緣層設置於第二層間絕緣層上。第二金屬層設置於第三層間絕緣層中。第二金屬層可包含電連接至第一互連線的第二互連線，且第二互連線可在第一方向上彼此平行地延伸。第一閘極電極的第一部分可穿透第一半導體圖案，且第二閘極電極的第一部分可穿透第二半導體圖案。第一源極/汲極圖案可穿透第一半導體圖案的上部部分，且第二源極/汲極圖案可穿透第二半導體圖案的上部部分。
在又另一態樣中，提供一種多通道絕緣層上半導體（semiconductor-on-insulator；SOI）電晶體，其包含其上具有電絕緣層的基底及在電絕緣層上的半導體主動層。亦提供內埋於半導體主動層內的間隔開的絕緣閘極電極的豎直堆疊。此豎直堆疊包含鄰近電絕緣層延伸的第一絕緣閘極電極及與半導體主動層的表面間隔開的第(N-1)絕緣閘極電極，其中N為大於二的正整數。第N絕緣閘極電極亦設置於半導體主動層的表面上。一對源極/汲極區設置於半導體主動層內。這些源極/汲極區鄰近間隔開的絕緣閘極電極的豎直堆疊的相對側延伸。在這些態樣中的一些中，半導體主動層在所述對源極/汲極區與電絕緣層之間延伸，而第一絕緣閘極電極接觸電絕緣層。
圖1是說明根據本發明概念的一些實施例的半導體元件的平面圖，且圖2A、圖2B、圖2C以及圖2D是分別沿圖1的線A-A'、線B-B'、線C-C'以及線D-D'截取的橫截面圖。在圖1中，省略一些組件以清楚地展示所說明的組件。
參看圖1及圖2A至圖2D，半導體元件可包含支撐基底100、支撐基底100上的絕緣層101以及絕緣層101上的第一半導體圖案102a及第二半導體圖案102b。絕緣層101的頂部表面的一部分可藉由第一半導體圖案102a及第二半導體圖案102b暴露。
支撐基底100可為包含矽的半導體基底或化合物半導體基底。舉例而言，支撐基底100可為矽基底。絕緣層可為（例如）氧化矽層。第一半導體圖案102a及第二半導體圖案102b中的每一者可為（例如）矽層。支撐基底100、絕緣層101以及第一半導體圖案102a及第二半導體圖案102b可為絕緣層上矽（silicon-on-insulator；SOI）基底的部分。絕緣層101的頂部表面可藉由第一半導體圖案102a及第二半導體圖案102b暴露。第一半導體圖案102a及第二半導體圖案102b可藉由插入於其間的絕緣層101的暴露的頂部表面而在第一方向D1上彼此間隔開。
邏輯單元LC可設置於第一半導體圖案102a、第二半導體圖案102b以及絕緣層101上。用於構成邏輯電路的邏輯電晶體可安置於邏輯單元LC中。邏輯單元LC可包含PMOSFET區PR及NMOSFET區NR。PMOSFET區PR可限定於第一半導體圖案102a上，且NMOSFET區NR可限定於第二半導體圖案102b上。
在圖2A中，第一通道結構CH1可設置於第一半導體圖案102a上。在圖2B中，第二通道結構CH2可設置於第二半導體圖案102b上。第一通道結構CH1及第二通道結構CH2中的每一者可包含依序堆疊的第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3。第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3可在豎直方向（亦即，第三方向D3）上彼此間隔開。第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3中的每一者可包含（例如）矽（Si）。
在圖2A中，多個第一凹部RS1可設置於第一半導體圖案102a的上部部分中。第一源極/汲極圖案SD1可分別設置於第一凹部RS1中。第一源極/汲極圖案SD1可為具有第一導電型（例如，p型）的摻雜劑區。第一通道結構CH1可安置於一對第一源極/汲極圖案SD1之間。第一通道結構CH1的第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3可將所述對第一源極/汲極圖案SD1彼此電連接。
在圖2B中，多個第二凹部RS2可設置於第二半導體圖案102b的上部部分中。第二源極/汲極圖案SD2可分別設置於第二凹部RS2中。第二源極/汲極圖案SD2可為具有第二導電型（例如，N型）的摻雜劑區。第二通道結構CH2可安置於一對第二源極/汲極圖案SD2之間。第二通道結構CH2的第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3可將所述對第二源極/汲極圖案SD2彼此電連接。
在一些實施例中，第一源極/汲極圖案SD1及第二源極/汲極圖案SD2中的每一者的頂部表面可安置於與第三通道圖案SP3的頂部表面實質上相同的水平面處。在某些實施例中，第一源極/汲極圖案SD1及第二源極/汲極圖案SD2中的每一者的頂部表面可高於第三通道圖案SP3的頂部表面。
第一源極/汲極圖案SD1可包含晶格常數大於第一半導體圖案102a的半導體元件的晶格常數的半導體元件（例如，SiGe）。因此，所述對第一源極/汲極圖案SD1可向其間的第一通道結構CH1提供壓縮應力，從而改良元件效能。
舉例而言，第一源極/汲極圖案SD1中的每一者可包含覆蓋第一凹部RS1的內表面的低濃度矽鍺（silicon-germanium；SiGe）層及覆蓋低濃度矽鍺（SiGe）層的高濃度矽鍺（SiGe）層。高濃度矽鍺層的體積與第一源極/汲極圖案SD1的總體積的比率可大於低濃度矽鍺層的體積與第一源極/汲極圖案SD1的總體積的比率。相反，第二源極/汲極圖案SD2可包含與第二半導體圖案102b相同的半導體元件（例如，矽）。
閘極電極GE可與第一半導體圖案102a及第二半導體圖案102b相交且可在第一方向D1上延伸。閘極電極GE可在第二方向D2上以第一間距P1配置。閘極電極GE中的每一者可與第一通道結構CH1及第二通道結構CH2豎直重疊。如所展示，閘極電極GE可包含安置於絕緣層101與第一通道圖案SP1之間的第一部分PO1、安置於第一通道圖案SP1與第二通道圖案SP2之間的第二部分PO2、安置於第二通道圖案SP2與第三通道圖案SP3之間的第三部分PO3以及第三通道圖案SP3上的第四部分PO4。第一部分PO1可安置於第一半導體圖案102a及第二半導體圖案102b中的每一者中。稍後將詳細描述第一部分PO1。
參看圖2D，閘極電極GE可設置於第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3中的每一者的頂部表面TS、底部表面BS以及兩個側壁SW上。換言之，根據本發明實施例的邏輯電晶體可為閘極全環繞型場效電晶體，其中閘極電極GE三維地包圍通道。
閘極電極GE可包含第一金屬圖案及第一金屬圖案上的第二金屬圖案。第一金屬圖案可設置於閘極絕緣層GI上且可鄰近於第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3。第一金屬圖案可包含用於調節邏輯電晶體的臨限電壓的功函數金屬。可藉由調節第一金屬圖案的厚度及組成來獲得邏輯電晶體的所要臨限電壓。
第一金屬圖案可包含金屬氮化物層。舉例而言，第一金屬圖案可包含氮（N）及由鈦（Ti）、鉭（Ta）、鋁（Al）、鎢（W）以及鉬（Mo）所構成的族群中選出的至少一種金屬。另外，第一金屬圖案可更包含碳（C）。在一些實施例中，第一金屬圖案可包含多個堆疊的功函數金屬層。且第二金屬圖案可包含具有比第一金屬圖案的電阻低的電阻的金屬。舉例而言，第二金屬圖案可包含由鎢（W）、鋁（Al）、鈦（Ti）以及鉭（Ta）所構成的族群中選出的至少一種金屬。
閘極絕緣層GI可安置於閘極電極GE與第一通道結構CH1之間及閘極電極GE與第二通道結構CH2之間。閘極絕緣層GI可覆蓋第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3中的每一者的頂部表面TS、底部表面BS以及兩個側壁SW。閘極絕緣層GI亦可安置於閘極電極GE與半導體圖案102a及半導體圖案102b之間。特定而言，閘極絕緣層GI可安置於閘極電極GE的第一部分PO1與半導體圖案102a及半導體圖案102b中的每一者之間。閘極絕緣層GI可覆蓋絕緣層101（參見圖2D）。閘極絕緣層GI可包含高k介電材料。舉例而言，高k介電材料可包含以下各者中的至少一者：氧化鉿、鉿矽氧化物、氧化鑭、氧化鋯、鋯矽氧化物、氧化鉭、氧化鈦、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、氧化鋰、氧化鋁、鉛鈧鉭氧化物或鉛鋅鈮酸。
參看圖2A及圖2B，一對閘極間隔件GS可分別安置於閘極電極GE的第四部分PO4的兩個側壁上。閘極間隔件GS可在圖1的第一方向D1上沿閘極電極GE延伸。閘極間隔件GS的頂部表面可高於閘極電極GE的頂部表面。閘極間隔件GS的頂部表面可與稍後將描述的第一層間絕緣層110的頂部表面共面。閘極間隔件GS可包含SiCN、SiCON以及SiN中的至少一者。在某些實施例中，閘極間隔件GS中的每一者可具有由SiCN、SiCON或SiN中的至少兩者形成的多層結構。
閘極封蓋圖案GP可設置於閘極電極GE上。閘極封蓋圖案GP可在第一方向D1上沿閘極電極GE延伸。閘極封蓋圖案GP可包含具有相對於稍後將描述的第一層間絕緣層110及第二層間絕緣層120的蝕刻選擇性的材料。舉例而言，閘極封蓋圖案GP可包含SiON、SiCN、SiCON或SiN中的至少一者。
參看圖2B，絕緣圖案IP可設置於NMOSFET區NR上。絕緣圖案IP可分別安置於第二源極/汲極圖案SD2與閘極電極GE的第二部分PO2及第三部分PO3之間。絕緣圖案IP可與第二源極/汲極圖案SD2直接接觸。閘極電極GE的第二部分PO2及第三部分PO3中的每一者可藉由絕緣圖案IP與第二源極/汲極圖案SD2間隔開。
在圖2C中，第一層間絕緣層110可設置於絕緣層101上。第一層間絕緣層110可覆蓋閘極間隔件GS以及第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。第一層間絕緣層110的頂部表面可與閘極封蓋圖案GP的頂部表面及閘極間隔件GS的頂部表面實質上共面。第二層間絕緣層120可安置於第一層間絕緣層110及閘極封蓋圖案GP上。舉例而言，第一層間絕緣層110及第二層間絕緣層120中的每一者可包含氧化矽層。
源極/汲極觸點AC可穿透第二層間絕緣層120及第一層間絕緣層110，以便分別電連接至第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。一對源極/汲極觸點AC可分別設置於閘極電極GE的兩側。當在平面圖中查看時，源極/汲極觸點AC可具有在第一方向D1上延伸的桿形狀。
源極/汲極觸點AC可為自對準觸點。換言之，源極/汲極觸點AC可經形成為使用閘極封蓋圖案GP及閘極間隔件GS自對準。舉例而言，源極/汲極觸點AC可覆蓋閘極間隔件GS的側壁的至少一部分。即使圖式中未展示，源極/汲極觸點AC亦可覆蓋閘極封蓋圖案GP的頂部表面的一部分。
矽化物圖案SC可分別安置於源極/汲極觸點AC與第一源極/汲極圖案SD1之間及源極/汲極觸點AC與第二源極/汲極圖案SD2之間。源極/汲極觸點AC可經由矽化物圖案SC電連接至源極/汲極圖案SD1或源極/汲極圖案SD2。矽化物圖案SC可包含金屬矽化物，且可包含例如矽化鈦、矽化鉭、矽化鎢、矽化鎳或矽化鈷中的至少一者。
閘極觸點GC可穿透第二層間絕緣層120及閘極封蓋圖案GP，以便電連接至閘極電極GE。舉例而言，如圖2B中所說明，源極/汲極觸點AC中的每一者的鄰近於閘極觸點GC的上部區可填充有上部絕緣圖案UIP。因此，有可能防止由於閘極觸點GC與鄰近於閘極觸點GC的源極/汲極觸點AC之間的接觸而引起短路的製程缺陷。
源極/汲極觸點AC及閘極觸點GC中的每一者可包含導電圖案FM及包圍導電圖案FM的障壁圖案BM。舉例而言，導電圖案FM可包含鋁、銅、鎢、鉬或鈷中的至少一種金屬。障壁圖案BM可覆蓋導電圖案FM的底部表面及側壁。障壁圖案BM可包含金屬層及/或金屬氮化物層。金屬層可包含鈦、鉭、鎢、鎳、鈷或鉑中的至少一者。金屬氮化物層可包含氮化鈦（TiN）層、氮化鉭（TaN）層、氮化鎢（WN）層、氮化鎳（NiN）層、氮化鈷（CoN）層或氮化鉑（PtN）層中的至少一者。
第一金屬層M1可設置於設置於第二層間絕緣層120上的第三層間絕緣層130中。第一金屬層M1可包含第一下部電力互連線M1_R1、第二下部電力互連線M1_R2以及下部互連線M1_I。下部互連線M1_I可安置於第一下部電力互連線M1_R1與第二下部電力互連線M1_R2之間。下部互連線M1_I中的每一者可具有在第二方向D2上延伸的線形狀或桿形狀。
第一金屬層M1可更包含下部通孔VI1。下部通孔VI1可設置於第一金屬層M1的互連線M1_R1、互連線M1_R2以及互連線M1_I下方。下部通孔VI1中的一些可分別安置於源極/汲極觸點AC與第一金屬層M1的互連線M1_R1、互連線M1_R2以及互連線M1_I中的對應者之間。下部通孔VI1中的其他者可分別安置於閘極觸點GC與第一金屬層M1的互連線M1_R1、互連線M1_R2以及互連線M1_I中的對應者之間。
第二金屬層M2可設置於設置於第三層間絕緣層130上的第四層間絕緣層140中。第二金屬層M2可包含上部互連線M2_I。參看圖2B及圖2C，第二金屬層M2的上部互連線M2_I中的每一者可具有在第一方向D1上延伸的線形狀或桿形狀。換言之，上部互連線M2_I可在第一方向D1上彼此平行地延伸。第二金屬層M2可更包含上部通孔VI2。上部通孔VI2可設置於上部互連線M2_I下方。上部通孔VI2可安置於上部互連線M2_I與第一金屬層M1的互連線M1_R1、互連線M1_R2以及互連線M1_I之間。
第一金屬層M1的互連線及第二金屬層M2的互連線可包含相同導電材料或不同導電材料。舉例而言，第一金屬層M1及第二金屬層M2的互連線中的每一者可包含由鋁、銅、鎢、鉬以及鈷所構成的族群中選出的至少一種金屬材料。儘管圖式中未展示，但堆疊金屬層（例如，M3、M4、M5等）可另外安置於第四層間絕緣層140上。堆疊金屬層中的每一者可包含佈線互連線。
圖3A是圖2A的一部分『aa』的放大圖。圖3B是圖2B的一部分『bb』的放大圖。參看圖3A及圖3B，閘極電極GE的第一部分PO1可安置於半導體圖案102a及半導體圖案102b中的每一者中。閘極電極GE的第一部分PO1可對應於閘極電極GE的最下部分。閘極電極GE的第一部分PO1可穿透半導體圖案102a及半導體圖案102b中的每一者。
參看圖3A，閘極電極GE的第一部分PO1可具有在絕緣層101與第一通道圖案SP1之間彼此相對的底部表面L1及頂部表面L2。第一部分PO1的底部表面L1的水平面可低於第一源極/汲極圖案SD1的最底部表面B1的水平面。閘極電極GE的第一部分PO1的頂部表面L2的水平面可高於第一源極/汲極圖案SD1的最底部表面B1的水平面。換言之，第一源極/汲極圖案SD1的最底部表面B1的水平面可位於第一部分PO1的底部表面L1的水平面與頂部表面L2的水平面之間。
第二源極/汲極圖案SD2的最底部表面B2的水平面亦可位於第一部分PO1的底部表面L1的水平面與頂部表面L2的水平面之間（參見圖3B）。
第一部分PO1的厚度H1可與第二部分PO2的厚度H2及第三部分PO3的厚度H3不同。第一部分PO1的厚度H1可大於第二部分PO2的厚度H2及第三部分PO3的厚度H3。第一部分PO1的厚度H1可介於第二部分PO2及第三部分PO3的厚度H2及厚度H3中的每一者的200%至300%之間的範圍內。
在圖3A中，包圍閘極電極GE的第二部分PO2及第三部分PO3的閘極絕緣層GI可與第一源極/汲極圖案SD1接觸。包圍閘極電極GE的第一部分PO1的閘極絕緣層GI可不與第一源極/汲極圖案SD1接觸。包圍第一部分PO1的閘極絕緣層GI可藉由插入於其間的第一半導體圖案102a而與第一源極/汲極圖案SD1間隔開。
在圖3B中，絕緣圖案IP可安置於第二部分PO2及第三部分PO3中的每一者與第二源極/汲極圖案SD2之間，但絕緣圖案IP可不設置於第一部分PO1與第二源極/汲極圖案SD2之間。第一部分PO1可藉由插入於其間的第二半導體圖案102b而在第二方向D2上與第二源極/汲極圖案SD2間隔開。
在圖3A及圖3B中，PMOSFET區PR的閘極電極GE的第一部分PO1在第二方向D2上的寬度可實質上等於NMOSFET區NR的閘極電極GE的第一部分PO1在第二方向D2上的寬度。相反，PMOSFET區PR的閘極電極GE的第二部分PO2在第二方向D2上的寬度可與NMOSFET區NR的閘極電極GE的第二部分PO2在第二方向D2上的寬度不同。PMOSFET區PR的閘極電極GE的第三部分PO3在第二方向D2上的寬度可與NMOSFET區NR的閘極電極GE的第三部分PO3在第二方向D2上的寬度不同。另外，在第三方向D3上絕緣層101距源極/汲極圖案SD1及源極/汲極圖案SD2中的每一者的距離可大於在第三方向D3上絕緣層101距閘極電極GE的第一部分PO1的距離。
根據本發明概念的實施例，半導體圖案102a及半導體圖案102b可不安置於對應於閘極電極GE的最下部分的第一部分PO1下方。因此，通道可不形成於第一部分PO1下方，且因此有可能防止洩漏電流在閘極電極GE下方流動（例如，防止穿通效應）。
另外，根據本發明概念的實施例，第一源極/汲極圖案SD1及第二源極/汲極圖案SD2的最底部表面B1及最底部表面B2可位於閘極電極GE的第一部分PO1的底部表面L1與頂部表面L2之間的水平面處，且因此可增加元件的可靠性。詳言之，第一源極/汲極圖案SD1及第二源極/汲極圖案SD2可藉由插入於其間的半導體圖案102a及半導體圖案102b而在第三方向D3上與絕緣層101間隔開。當源極/汲極圖案SD1及源極/汲極圖案SD2在第三方向D3上自半導體圖案102a及半導體圖案102b磊晶成長時，如稍後在圖11A至圖11C中描述，可能不會發生堆疊缺陷，且因此可改良可靠性。若自絕緣層101執行磊晶生長，則可在第一源極/汲極圖案SD1中產生堆疊缺陷，且可減小施加至第一通道結構CH1的壓縮應力。在此情況下，元件的可靠性可能降低。
圖4A是根據本發明概念的一些實施例的對應於圖2A的部分『aa』的放大圖。圖4B是根據本發明概念的一些實施例的對應於圖2B的部分『bb』的放大圖。在下文中，出於易於及方便解釋的目的，將省略對與圖3A及圖3B的實施例中相同的特徵的描述。
參看圖4A，閘極電極GE的第一部分PO1在第二方向D2上的寬度W1可隨著在第三方向D3上距絕緣層101的高度的增加而增加。包圍第一部分PO1的閘極絕緣層GI可與第一源極/汲極圖案SD1接觸。在某些實施例中，包圍第一部分PO1的閘極絕緣層GI可不與第一源極/汲極圖案SD1接觸。當在稍後在圖13A至圖13C中描述的蝕刻第一犧牲圖案200P的製程中蝕刻第一犧牲圖案200P周圍的第一半導體圖案102a的上部部分時，可達成本發明實施例中的閘極電極GE的第一部分PO1在第二方向D2上的寬度W1的增加。
參看圖4B，絕緣圖案IP可設置於閘極電極GE的第一部分PO1與第二源極/汲極圖案SD2之間。當在稍後在圖13A至圖13C中描述的製程中亦蝕刻第一犧牲圖案200P周圍的第二半導體圖案102b的上部部分時，絕緣圖案IP可安置於第二半導體圖案102b的經蝕刻上部部分中。
圖5A是根據本發明概念的一些實施例的對應於圖2A的部分『aa』的放大圖。圖5B是根據本發明概念的一些實施例的對應於圖2B的部分『bb』的放大圖。在下文中，出於易於及方便解釋的目的，將省略對與圖3A及圖3B的實施例中相同的特徵的描述。
參看圖5A及圖5B，第一部分PO1的厚度H1可小於第二部分PO2的厚度H2及第三部分PO3的厚度H3。在圖5A中，第一源極/汲極圖案SD1之間的第一部分PO1在第二方向D2上的寬度W1可大於第二部分PO2在第二方向D2上的寬度W2及第三部分PO3在第二方向D2上的寬度W3。在圖5B中，第二源極/汲極圖案SD2之間的第一部分PO1在第二方向D2上的寬度J1可大於第二部分PO2在第二方向D2上的寬度J2及第三部分PO3在第二方向D2上的寬度J3。
圖6A至圖14C是說明根據本發明概念的一些實施例的製造半導體元件的方法的橫截面圖。圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A、圖13A以及圖14A是對應於圖1的線A-A'的橫截面圖。圖10B、圖11B、圖12B、圖13B以及圖14B是對應於圖1的線B-B'的橫截面圖。圖6B、圖7B、圖8B、圖10C、圖11C以及圖12C是對應於圖1的線C-C'的橫截面圖。圖6C、圖7C、圖8C、圖9B、圖12D、圖13C以及圖14C是對應於圖1的線D-D'的橫截面圖。
參看圖6A、圖6B以及圖6C，可提供支撐基底100、絕緣層101以及半導體層102。犧牲線200L可形成於半導體層102中。犧牲線200L可包含鍺（Ge）或矽鍺（SiGe）。犧牲線200L可具有在第一方向D1上延伸的線形狀。犧牲線200L可在第二方向D2上彼此間隔開。
參看圖7A、圖7B以及圖7C，交替堆疊的主動層ACL及犧牲層SAL可形成於支撐基底100上。主動層ACL可包含矽（Si），且犧牲層SAL可包含鍺（Ge）或矽鍺（SiGe）。作為實例，說明三個主動層ACL及兩個犧牲層SAL。在某些實施例中，可不同地改變交替堆疊的主動層ACL及犧牲層SAL的數目。在圖式中，最下主動層ACL1直接形成於半導體層102上。替代地，在某些實施例中，犧牲層SAL可另外形成於半導體層102與最下主動層ACL1之間（參見圖16A及圖16B）。在此情況下，可形成三個犧牲層SAL及三個主動層ACL。
遮罩圖案MAP可形成於PMOSFET區PR及NMOSFET區NR中的每一者上。遮罩圖案MAP可具有在第二方向D2上延伸的線形狀或桿形狀。舉例而言，遮罩圖案MAP可包含氮化矽。
參看圖8A、圖8B以及圖8C，可藉由使用遮罩圖案MAP作為蝕刻遮罩來對犧牲層SAL、主動層ACL、半導體層102以及犧牲線200L執行圖案化製程。可藉由圖案化製程由半導體層102形成第一半導體圖案102a及第二半導體圖案102b。第二半導體圖案102b可與第一半導體圖案102a實質上相同，且因此省略沿圖1的線B-B'截取的橫截面圖。第一半導體圖案102a及第二半導體圖案102b可分別形成於PMOSFET區PR及NMOSFET區NR上。藉由圖案化製程，類似圖8C的第一犧牲圖案200P、主動圖案ACP以及第二犧牲圖案SAP可分別由犧牲線200L、主動層ACL以及犧牲層SAL形成。可藉由圖案化製程暴露絕緣層101的頂部表面的一部分。
參看圖9A及圖9B，與第一半導體圖案102a及第二半導體圖案102b相交的第三犧牲圖案PP可形成於絕緣層101上。第三犧牲圖案PP中的每一者可具有在第一方向D1上延伸的線形狀或桿形狀。第三犧牲圖案PP可在第二方向D2上以預定間距配置。舉例而言，第三犧牲圖案PP的形成可包含在支撐基底100的整個頂部表面上形成犧牲層，在犧牲層上形成硬遮罩圖案MP，以及使用硬遮罩圖案MP作為蝕刻遮罩來圖案化犧牲層。犧牲層可包含多晶矽。
一對閘極間隔件GS可分別形成於第三犧牲圖案PP中的每一者的兩個側壁上。閘極間隔件GS的形成可包含在支撐基底100上共形地形成閘極間隔件層及非等向性地蝕刻閘極間隔件層。舉例而言，閘極間隔件層可包含SiCN、SiCON或SiN中的至少一者。在某些實施例中，閘極間隔件層可由包含SiCN、SiCON或SiN中的至少兩者的多層形成。
參看圖10A至圖10C，第一凹部RS1可形成於第一半導體圖案102a的上部部分中。第二凹部RS2可形成於第二半導體圖案102b的上部部分中。舉例而言，可使用硬遮罩圖案MP及閘極間隔件GS作為蝕刻遮罩來蝕刻主動圖案ACP、第二犧牲圖案SAP、第一半導體圖案102a的上部部分以及第二半導體圖案102b的上部部分。第一凹部RS1可形成於一對第三犧牲圖案PP之間。第一通道結構CH1可藉由形成第一凹部RS1而由主動圖案ACP形成。
第一通道結構CH1可在第二方向D2上彼此間隔開且可分別形成於第三犧牲圖案PP下方。第一凹部RS1可不暴露絕緣層101。可執行用於形成第一凹部RS1的蝕刻製程，直至第一凹部RS1的最底部表面位於第一犧牲圖案200P的頂部表面與底部表面之間的水平面處。第二凹部RS2可藉由與上文所描述的第一凹部RS1相同的方法形成。
在圖10A及圖10B中，可不蝕刻第一犧牲圖案200P。在某些實施例中，當第一犧牲圖案200P在第二方向D2上的寬度大於第二犧牲圖案SAP在第二方向D2上的寬度時，亦可蝕刻第一犧牲圖案200P的上部部分的邊緣部分。
第二半導體圖案102b的上部部分的第二凹部RS2可藉由與上文所描述的第一凹部RS1相同的方法形成。第二通道結構CH2可藉由形成第二凹部RS2而由主動圖案ACP形成。第二通道結構CH2可在第二方向D2上彼此間隔開且可分別形成於第三犧牲圖案PP下方。
參看圖11A至圖11C，第一源極/汲極圖案SD1可分別形成於第一凹部RS1中。第二源極/汲極圖案SD2可分別形成於第二凹部RS2中。可獨立於第二源極/汲極圖案SD2的形成來執行第一源極/汲極圖案SD1的形成。第一源極/汲極圖案SD1的形成及第二源極/汲極圖案SD2的形成可藉由選擇性磊晶生長（selective epitaxial growth；SEG）製程來執行。舉例而言，SEG製程可包含化學氣相沈積（chemical vapor deposition；CVD）製程或分子束磊晶法（molecular beam epitaxy；MBE）製程。
第一源極/汲極圖案SD1的形成可包含使用第一半導體圖案102a及第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3作為晶種層來執行SEG製程。特定而言，由於在本發明概念的實施例中，第一凹部RS1並不暴露絕緣層101，因此第一半導體圖案102a可用作晶種層。因此，第一源極/汲極圖案SD1可在與第三方向D3平行的[100]方向上生長且其中晶體產生及晶體生長為有利的。當第一源極/汲極圖案SD1在[100]方向上生長時，可減少第一源極/汲極圖案SD1的堆疊缺陷。
第一源極/汲極圖案SD1可由能夠向第一通道結構CH1提供壓縮應力的材料形成。舉例而言，第一源極/汲極圖案SD1可由晶格常數大於第一半導體圖案102a的半導體元件的晶格常數的半導體元件（例如，SiGe）形成。在SEG製程中（或在SEG製程之後），第一源極/汲極圖案SD1可摻雜有P型摻雜劑。
第二源極/汲極圖案SD2的形成可包含使用第二半導體圖案102b及第二半導體圖案102b上的第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3作為晶種層來執行SEG製程。舉例而言，第二源極/汲極圖案SD2可由與第二半導體圖案102b相同的半導體元件（例如，矽）形成。在SEG製程中或在SEG製程之後，第二源極/汲極圖案SD2可摻雜有N型摻雜劑。
參看圖12A至圖12D，可形成第一層間絕緣層110以覆蓋第一源極/汲極圖案SD1及第二源極/汲極圖案SD2、硬遮罩圖案MP以及閘極間隔件GS。舉例而言，第一層間絕緣層110可包含氧化矽層。
第一層間絕緣層110可經平坦化，直至暴露第三犧牲圖案PP的頂部表面。第一層間絕緣層110的平坦化製程可使用回蝕製程或化學機械拋光（chemical mechanical polishing；CMP）製程來執行。可在平坦化製程期間完全移除硬遮罩圖案MP。因此，第一層間絕緣層110的頂部表面可與第三犧牲圖案PP的頂部表面及閘極間隔件GS的頂部表面實質上共面。接著，可選擇性地移除經暴露的第三犧牲圖案PP。可藉由移除第三犧牲圖案PP來形成暴露通道結構CH1及通道結構CH2的第一空白空間ET1、第一犧牲圖案200P以及第二犧牲圖案SAP（參見圖12D）。
參看圖13A至圖13C，可選擇性地移除經由第一空白空間ET1暴露的第一犧牲圖案200P及第二犧牲圖案SAP。可執行選擇性地蝕刻第一犧牲圖案200P及第二犧牲圖案SAP的蝕刻製程以僅移除第一犧牲圖案200P及第二犧牲圖案SAP，同時留下第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3。蝕刻製程可為濕式蝕刻製程。
相對於具有相對較高鍺濃度的矽鍺，蝕刻製程可具有較高蝕刻速率。在移除第二犧牲圖案SAP期間，第一源極/汲極圖案SD1的低濃度矽鍺層可防止蝕刻劑滲透至高濃度矽鍺層中且對其進行蝕刻。用於蝕刻製程中的蝕刻劑可快速移除具有相對較高鍺濃度的第一犧牲圖案200P及第二犧牲圖案SAP，但可不移除具有相對較低鍺濃度的第一源極/汲極圖案SD1的低濃度矽鍺層的大部分。亦可在蝕刻製程期間移除NMOSFET區NR上的第一犧牲圖案200P及第二犧牲圖案SAP。同時，第二源極/汲極圖案SD2可含有無鍺的矽（Si），且因此第二源極/汲極圖案SD2可不經移除，而是可在蝕刻製程期間保留。由於選擇性地移除第一犧牲圖案200P及第二犧牲圖案SAP，因此第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3可保留在第一半導體圖案102a及第二半導體圖案102b中的每一者上。
第二空白空間ET2及第三空白空間ET3可分別藉由移除第一犧牲圖案200P及第二犧牲圖案SAP而形成。第二空白空間ET2可限定於第一通道圖案SP1與半導體圖案102a及半導體圖案102b中的每一者的暴露的內表面之間。第三空白空間ET3可限定於第一通道圖案SP1與第二通道圖案SP2之間及第二通道圖案SP2與第三通道圖案SP3之間。
參看圖14A至圖14C，閘極絕緣層GI可共形地形成於第一空白空間ET1、第二空白空間ET2以及第三空白空間ET3中。舉例而言，介面層可形成於第一通道圖案SP1、第二通道圖案SP2以及第三通道圖案SP3的暴露表面以及第一半導體圖案102a及第二半導體圖案102b的暴露內表面上。介面層可藉由熱氧化製程形成。高k介電層可共形地形成於介面層上。高k介電層可覆蓋介面層。介面層及高k介電層可構成閘極絕緣層GI。
閘極電極GE可形成於第一空白空間ET1、第二空白空間ET2以及第三空白空間ET3中。閘極電極GE可包含填充第二空白空間ET2的第一部分PO1。閘極電極GE可包含分別填充第三空白空間ET3的第二部分PO2及第三部分PO3。閘極電極GE可更包含填充第一空白空間ET1的第四部分PO4。閘極封蓋圖案GP可形成於閘極電極GE上。
同時，在形成閘極絕緣層GI之前，絕緣圖案IP可形成於NMOSFET區NR上。絕緣圖案IP可經形成以填充第三空白空間ET3的一部分。因此，NMOSFET區NR上的閘極電極GE的第二部分PO2及第三部分PO3可藉由插入於其間的絕緣圖案IP而與第二源極/汲極圖案SD2間隔開。
再次參看圖1及圖2A至圖2D，第二層間絕緣層120可形成於第一層間絕緣層110上。第二層間絕緣層120可包含氧化矽層。源極/汲極觸點AC可形成於第二層間絕緣層120及第一層間絕緣層110中。源極/汲極觸點AC可穿透第二層間絕緣層120及第一層間絕緣層110，以便電連接至第一源極/汲極圖案SD1及第二源極/汲極圖案SD2。可形成閘極觸點GC。閘極觸點GC可穿透第二層間絕緣層120及閘極封蓋圖案GP，以便電連接至閘極電極GE。
第三層間絕緣層130可形成於源極/汲極觸點AC、閘極觸點GC以及第二層間絕緣層120上。第一金屬層M1可形成於第三層間絕緣層130中。第四層間絕緣層140可形成於第三層間絕緣層130上。第二金屬層M2可形成於第四層間絕緣層140中。
圖15A至圖15C是說明在圖6A的半導體層102中形成犧牲線200L的方法的橫截面圖。圖15A至圖15C是對應於圖1的線A-A'的橫截面圖。參看圖15A，可提供支撐基底100、支撐基底100上的絕緣層101以及絕緣層101上的半導體層102。半導體層102可為（例如）絕緣層上矽（SOI）。半導體層102的厚度T1可與上文所描述的閘極電極GE的第一部分PO1的厚度相關。
換言之，當半導體層102的厚度T1大於圖7A的犧牲層SAL中的每一者的厚度時，第一部分PO1的厚度可大於第二部分PO2及第三部分PO3的厚度（參見圖3A、圖3B、圖4A以及圖4B）。當半導體層102的厚度T1小於圖7A的犧牲層SAL中的每一者的厚度時，第一部分PO1的厚度可小於第二部分PO2及第三部分PO3的厚度（參見圖5A及圖5B）。
犧牲半導體層200可形成於半導體層102上。犧牲半導體層200可為矽鍺（SiGe）層。犧牲半導體層200的厚度T2可大於半導體層102的厚度T1。
遮罩圖案300可形成於犧牲半導體層200上。遮罩圖案300可具有在第一方向D1上延伸的線形狀。遮罩圖案300可在第二方向D2上彼此間隔開以在其間限定開口OP。遮罩圖案300可包含（例如）氮化矽。可藉由（例如）雙重圖案化製程形成遮罩圖案300。可取決於開口OP在第二方向D2上的寬度來判定閘極電極GE的第一部分PO1的寬度。
參看圖15B，可在高溫下執行的熱處理製程中經由開口OP將氧注入至犧牲半導體層200的經暴露部分中。在此製程中，半導體層102的矽可擴散至犧牲半導體層200中，且犧牲半導體層200的鍺可擴散至半導體層102中。在犧牲半導體層200中，矽可與氧反應以形成對應於開口OP的氧化矽圖案400。對應於開口OP的犧牲線200L可形成於半導體層102中。犧牲線200L可包含鍺或矽鍺。犧牲線200L中每單位體積的鍺的量可大於犧牲半導體層200中每單位體積的鍺的量（Ge冷凝）。
參看圖15C，可藉由（例如）濕式蝕刻製程選擇性地移除氧化矽圖案400。接著，可藉由（例如）溶離製程移除遮罩圖案300。再次參看圖6A，可移除犧牲半導體層200。可藉由（例如）平坦化製程（例如，CMP製程）移除犧牲半導體層200。因此，可暴露犧牲線200L的頂部表面及半導體層102的頂部表面。
圖16A及圖16B是分別沿圖1的線A-A'及線B-B'截取的橫截面圖，以說明根據本發明概念的一些實施例的半導體元件。圖17A是圖16A的一部分『cc』的放大圖。圖17B是圖16B的一部分『dd』的放大圖。在下文中，出於易於及方便解釋的目的，將省略對與圖2A至圖2D的實施例中相同的特徵的描述。
參看圖16A及圖17A，PMOSFET區PR上的閘極電極GE的第一部分PO1可更包含沿第一半導體圖案102a的頂部表面102U延伸的第一延伸部EL1。換言之，閘極電極GE的第一部分PO1可包含安置於第一半導體圖案102a中的下部部分BL及設置於第一半導體圖案102a的頂部表面102U上的第一延伸部EL1。第一延伸部EL1在第二方向D2上的寬度可大於下部部分BL在第二方向D2上的寬度。
第一延伸部EL1可安置於第一源極/汲極圖案SD1之間。覆蓋第一延伸部EL1的閘極絕緣層GI可與第一源極/汲極圖案SD1接觸。第一延伸部EL1的邊緣部分可藉由插入於其間的第一半導體圖案102a而與絕緣層101豎直間隔開。
參看圖16B及圖17B，NMOSFET區NR上的閘極電極GE的第一部分PO1可更包含自第二半導體圖案102b的頂部表面102T突出的第二延伸部EL2。換言之，閘極電極GE的第一部分PO1可包含安置於第二半導體圖案102b中的下部部分BL及自第二半導體圖案102b的頂部表面102T突出的第二延伸部EL2。第二延伸部EL2可安置於第二源極/汲極圖案SD2之間。絕緣圖案IP可安置於第二延伸部EL2與第二源極/汲極圖案SD2之間。
當在形成圖7A至圖7C中的最下主動層ACL1之前在半導體層102上另外形成犧牲層SAL時，可形成圖16A、圖16B、圖17A以及圖17B的實施例的結構。在此情況下，第二犧牲圖案SAP可直接形成於圖12A及圖12B中的第一犧牲圖案200P上，且因此可改變圖13A及圖13B中的第二空白空間ET2的形狀。
圖18A、圖18B以及圖18C是分別沿圖1的線A-A'、線B-B'以及線D-D'截取的橫截面圖，以說明根據本發明概念的一些實施例的半導體元件。在下文中，出於易於及方便解釋的目的，將省略對與圖2A至圖2D的實施例中相同的特徵的描述。
參看圖18A至圖18C，根據本發明實施例的第一通道結構及第二通道結構中的每一者可包含單通道圖案SP。通道圖案SP的厚度可大於閘極電極GE的第一部分PO1的厚度。閘極電極GE可包含安置於絕緣層101與通道圖案SP之間的第一部分PO1及通道圖案SP上的第二部分PO2。閘極電極GE可包圍單通道圖案SP的四個表面以形成閘極全環繞結構。
參看圖7A至圖7C，代替在半導體層102上交替地形成主動層ACL及犧牲層SAL，可使單個主動層ACL生長至對應於最上主動層ACL的頂部表面的水平面。後續製程可類似於上文參看圖8A至圖14C所描述的製程。
根據本發明概念的半導體元件可使用絕緣層上矽（SOI）基底來製造，且因此閘極電極可直接安置於內埋絕緣層上。在此情況下，通道可不形成於閘極電極的最下部分下方，且因此有可能藉由精細圖案防止洩漏電流的發生。另外，源極/汲極圖案可與內埋絕緣層間隔開，且因此可減少或最小化源極/汲極圖案形成中的堆疊缺陷以改良半導體元件的可靠性及電特性。
雖然已參考實例實施例描述本發明概念，但所屬技術領域中具有通常知識者將顯而易見，可在不脫離本發明概念的精神及範疇的情況下進行各種改變及修改。因此，應理解，上述實施例並非限制性的，而是說明性的。因此，本發明概念的範疇應由以下申請專利範圍及其等效物的最廣泛容許解釋來判定，且不應受到前述描述約束或限制。
100:支撐基底 101:絕緣層 102:半導體層 102a:第一半導體圖案 102b:第二半導體圖案 102T、102U、TS、L2:頂部表面 110:第一層間絕緣層 120:第二層間絕緣層 130:第三層間絕緣層 140:第四層間絕緣層 200:犧牲半導體層 200L:犧牲線 200P:第一犧牲圖案 300、MAP:遮罩圖案 400:氧化矽圖案 aa、bb、cc、dd:部分 A-A'、B-B'、C-C'、D-D':線 AC:源極/汲極觸點 ACL:主動層 ACL1:最下主動層 ACP:主動圖案 B1、B2:最底部表面 BL:下部部分 BM:障壁圖案 BS、L1:底部表面 CH1:第一通道結構 CH2:第二通道結構 D1:第一方向 D2:第二方向 D3:第三方向 EL1:第一延伸部 EL2:第二延伸部 ET1:第一空白空間 ET2:第二空白空間 ET3:第三空白空間 FM:導電圖案 GC:閘極觸點 GE:閘極電極 GI:閘極絕緣層 GP:閘極封蓋圖案 GS:閘極間隔件 H1、H2、H3、T1、T2:厚度 IP:絕緣圖案 J1、J2、J3、W1、W2、W3:寬度 LC:邏輯單元 M1:第一金屬層 M1_I:下部互連線 M1_R1:第一下部電力互連線 M1_R2:第二下部電力互連線 M2:第二金屬層 M2_I:上部互連線 MP:硬遮罩圖案 NR:NMOSFET區 OP:開口 P1:第一間距 PO1:第一部分 PO2:第二部分 PO3:第三部分 PO4:第四部分 PP:第三犧牲圖案 PR:PMOSFET區 RS1:第一凹部 RS2:第二凹部 SAL:犧牲層 SAP:第二犧牲圖案 SC:矽化物圖案 SD1:第一源極/汲極圖案 SD2:第二源極/汲極圖案 SP:單通道圖案 SP1:第一通道圖案 SP2:第二通道圖案 SP3:第三通道圖案 SW:側壁 UIP:上部絕緣圖案 VI1:下部通孔 VI2:上部通孔
鑒於附圖及隨附詳細描述，本發明概念將變得更顯而易見。 圖1是說明根據本發明概念的一些實施例的半導體元件的平面圖。 圖2A、圖2B、圖2C以及圖2D是分別沿圖1的線A-A'、線B-B'、線C-C'以及線D-D'截取的橫截面圖。 圖3A是圖2A的一部分『aa』的放大圖。 圖3B是圖2B的一部分『bb』的放大圖。 圖4A是根據本發明概念的一些實施例的對應於圖2A的部分『aa』的放大圖。 圖4B是根據本發明概念的一些實施例的對應於圖2B的部分『bb』的放大圖。 圖5A是根據本發明概念的一些實施例的對應於圖2A的部分『aa』的放大圖。 圖5B是根據本發明概念的一些實施例的對應於圖2B的部分『bb』的放大圖。 圖6A至圖14C是說明根據本發明概念的一些實施例的製造半導體元件的方法的橫截面圖。 圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A、圖13A以及圖14A是對應於圖1的線A-A'的橫截面圖。 圖10B、圖11B、圖12B、圖13B以及圖14B是對應於圖1的線B-B'的橫截面圖。 圖6B、圖7B、圖8B、圖10C、圖11C以及圖12C是對應於圖1的線C-C'的橫截面圖。 圖6C、圖7C、圖8C、圖9B、圖12D、圖13C以及圖14C是對應於圖1的線D-D'的橫截面圖。 圖15A至圖15C是說明根據本發明概念的一些實施例的形成圖6A的犧牲線的方法的橫截面圖。 圖16A及圖16B是分別沿圖1的線A-A'及線B-B'截取的橫截面圖，以說明根據本發明概念的一些實施例的半導體元件。 圖17A是圖16A的一部分『cc』的放大圖。 圖17B是圖16B的一部分『dd』的放大圖。 圖18A、圖18B以及圖18C是分別沿圖1的線A-A'、線B-B'以及線D-D'截取的橫截面圖，以說明根據本發明概念的一些實施例的半導體元件。
101:絕緣層
102a:第一半導體圖案
aa:部分
AC:源極/汲極觸點
B1:最底部表面
BM:障壁圖案
L1:底部表面
L2:頂部表面
CH1:第一通道結構
D2:第二方向
D3:第三方向
FM:導電圖案
GE:閘極電極
GI:閘極絕緣層
H1、H2、H3:厚度
PO1:第一部分
PO2:第二部分
PO3:第三部分
SD1:第一源極/汲極圖案
SP1:第一通道圖案
SP2:第二通道圖案
SP3:第三通道圖案

Claims (20)

  1. 一種半導體元件，包括： 電絕緣層； 半導體圖案，在所述電絕緣層上延伸且接觸所述電絕緣層； 一對源極/汲極圖案，延伸至所述半導體圖案中； 通道結構，在所述一對源極/汲極圖案之間延伸，所述通道結構包括彼此間隔開的通道圖案的堆疊；以及 閘極電極，在所述通道圖案之間的空間中延伸，所述閘極電極包含第一閘極部分，所述第一閘極部分在所述通道結構與所述電絕緣層之間延伸，且所述第一閘極部分具有相對於所述一對源極/汲極圖案中的每一者的最底部表面更靠近所述電絕緣層延伸的底部表面。
  2. 如請求項1所述的半導體元件，其中所述一對源極/汲極圖案中的每一者的所述最底部表面相對於所述通道結構的最底部表面更靠近所述電絕緣層延伸。
  3. 如請求項1所述的半導體元件，其中所述一對源極/汲極圖案中的每一者的所述最底部表面相對於所述第一閘極部分的最上表面更靠近所述電絕緣層延伸。
  4. 如請求項1所述的半導體元件，其中所述第一閘極部分藉由閘極絕緣層與所述通道結構分離，所述閘極絕緣層包圍所述第一閘極部分的至少一部分且接觸所述電絕緣層。
  5. 如請求項1所述的半導體元件，其中所述通道圖案的堆疊包含第一通道圖案及第二通道圖案；其中所述第一閘極部分在所述電絕緣層與所述第一通道圖案之間延伸；且其中所述閘極電極更包含在所述第一通道圖案與所述第二通道圖案之間延伸的第二閘極部分。
  6. 如請求項1所述的半導體元件，其中所述一對源極/汲極圖案與所述半導體圖案形成各別異質接面。
  7. 如請求項6所述的半導體元件，其中所述一對源極/汲極圖案包括SiGe；且其中所述半導體圖案包括單晶矽（Si）。
  8. 如請求項1所述的半導體元件，其中所述電絕緣層在半導體基底上延伸；且其中所述半導體圖案、所述電絕緣層以及所述半導體基底共同限定絕緣層上半導體（SOI）基底。
  9. 一種半導體元件，包括： 支撐基底； 絕緣層，位於所述支撐基底上； 半導體圖案，位於所述絕緣層上，所述半導體圖案與所述絕緣層接觸； 一對源極/汲極圖案，位於所述半導體圖案上； 通道結構，安置於所述一對源極/汲極圖案之間，所述通道結構包括堆疊且彼此間隔開的通道圖案；以及 閘極電極，與所述通道結構相交且在第一方向上延伸， 其中所述閘極電極包含安置於所述通道結構與所述絕緣層之間的第一部分，且 其中所述第一部分的底部表面的水平面低於所述源極/汲極圖案的最底部表面的水平面。
  10. 如請求項9所述的半導體元件，其中所述源極/汲極圖案的所述最底部表面的所述水平面低於所述通道結構的最底部表面的水平面。
  11. 如請求項9所述的半導體元件，更包括： 閘極絕緣層，位於所述閘極電極與所述通道結構之間， 其中所述閘極絕緣層與所述絕緣層接觸。
  12. 如請求項9所述的半導體元件，其中所述通道圖案包含依序堆疊的第一通道圖案及第二通道圖案， 其中所述第一部分安置於所述絕緣層與所述第一通道圖案之間， 其中所述閘極電極更包含安置於所述第一通道圖案與所述第二通道圖案之間的第二部分， 其中所述閘極電極的所述第一部分位於所述通道圖案中的最下者下方，且 其中所述閘極電極的所述第一部分穿透所述半導體圖案。
  13. 如請求項12所述的半導體元件，其中所述源極/汲極圖案的所述最底部表面位於所述第一部分的頂部表面與所述第一部分的所述底部表面之間的水平面處。
  14. 如請求項12所述的半導體元件，其中所述第一部分的厚度大於所述第二部分的厚度。
  15. 如請求項14所述的半導體元件，其中所述第一部分的所述厚度介於所述第二部分的所述厚度的200%至300%之間的範圍內。
  16. 如請求項12所述的半導體元件，其中所述第一部分在水平方向上的寬度自所述絕緣層朝向所述第一通道圖案變得更大。
  17. 如請求項12所述的半導體元件，其中所述第一部分的厚度小於所述第二部分的厚度。
  18. 如請求項12所述的半導體元件，其中所述第一部分更包含延伸至所述半導體圖案的頂部表面上且覆蓋所述半導體圖案的所述頂部表面的延伸部， 其中所述延伸部安置於所述源極/汲極圖案之間，且 其中所述延伸部的鄰近於所述源極/汲極圖案的部分藉由插入於其間的所述半導體圖案而與所述絕緣層間隔開。
  19. 一種半導體元件，包括： 支撐基底； 絕緣層，位於所述支撐基底上； 半導體圖案，設置於所述絕緣層上且與所述絕緣層接觸； 一對源極/汲極圖案，位於所述半導體圖案上； 通道結構，安置於所述一對源極/汲極圖案之間，所述通道結構包括至少一個通道圖案；以及 閘極電極，與所述通道結構相交且在第一方向上延伸， 其中所述閘極電極包含安置於所述絕緣層與所述通道結構的最下部分之間的一個部分，且所述一個部分穿透所述半導體圖案， 其中所述源極/汲極圖案的下部部分位於所述半導體圖案中，且 其中所述源極/汲極圖案藉由插入於其間的所述半導體圖案而與所述絕緣層間隔開。
  20. 如請求項19所述的半導體元件，其中所述絕緣層距所述源極/汲極圖案的距離大於所述絕緣層距所述閘極電極的距離。
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Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US3987794A (en) 1974-10-31 1976-10-26 Colgate-Palmolive Company Diaper with elastic crotch means
DE112011105995B4 (de) 2011-12-23 2020-08-06 Intel Corporation Herstellungsverfahren für eine nicht-planare Rundum-Gate-Schaltung
US9660028B1 (en) * 2016-10-31 2017-05-23 International Business Machines Corporation Stacked transistors with different channel widths
US9935014B1 (en) 2017-01-12 2018-04-03 International Business Machines Corporation Nanosheet transistors having different gate dielectric thicknesses on the same chip
US9876015B1 (en) 2017-02-16 2018-01-23 International Business Machines Corporation Tight pitch inverter using vertical transistors
CN109390400A (zh) 2017-08-08 2019-02-26 中芯国际集成电路制造(上海)有限公司 环栅场效应晶体管及其形成方法
US10141403B1 (en) 2017-11-16 2018-11-27 International Business Machines Corporation Integrating thin and thick gate dielectric nanosheet transistors on same chip
US10332803B1 (en) 2018-05-08 2019-06-25 Globalfoundaries Inc. Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
US11152510B2 (en) 2018-07-25 2021-10-19 International Business Machines Corporation Long channel optimization for gate-all-around transistors
KR102537527B1 (ko) 2018-09-10 2023-05-26 삼성전자 주식회사 집적회로 소자
KR102662537B1 (ko) 2019-05-10 2024-05-02 삼성전자 주식회사 이중 대역 안테나 및 그것을 포함하는 전자 장치
KR20220017554A (ko) * 2020-08-04 2022-02-14 삼성전자주식회사 반도체 소자

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