TW202203391A - 封裝 - Google Patents

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Publication number
TW202203391A
TW202203391A TW109132100A TW109132100A TW202203391A TW 202203391 A TW202203391 A TW 202203391A TW 109132100 A TW109132100 A TW 109132100A TW 109132100 A TW109132100 A TW 109132100A TW 202203391 A TW202203391 A TW 202203391A
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Taiwan
Prior art keywords
die
package
reinforcement structure
conductive
groove
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TW109132100A
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English (en)
Inventor
黃松輝
侯上勇
黃冠育
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台灣積體電路製造股份有限公司
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Publication of TW202203391A publication Critical patent/TW202203391A/zh

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Abstract

一種封裝包括第一晶粒、第二晶粒、半導體框架以及加強結構。第一晶粒具有第一表面及與第一表面相對的第二表面。第一晶粒包括在第一表面上的凹槽。第二晶粒及半導體框架並排配置在第一晶粒的第一表面上。半導體框架具有暴露出第一晶粒的凹槽的至少一個凹口。加強結構配置在第一晶粒的第二表面上。加強結構包括與凹槽對準的第一部分。

Description

封裝
本發明實施例是有關於一種封裝，且特別是有關於一種具有加強結構的封裝。
用於各種電子裝置（例如手機及其它移動電子設備）中的半導體裝置及積體電路通常在單個半導體晶圓（semiconductor wafer）上製造。晶圓的晶粒可在晶圓級（wafer level）下與其它半導體裝置或晶粒一起被處理及封裝，且已開發了針對晶圓級封裝的各種技術。如何確保晶圓級封裝的可靠性已成為本領域中的挑戰。
一種封裝包括第一晶粒、第二晶粒、半導體框架以及加強結構。所述第一晶粒具有第一表面及與所述第一表面相對的第二表面。所述第一晶粒包括在所述第一表面上的凹槽。所述第二晶粒及所述半導體框架並排配置在所述第一晶粒的所述第一表面上。所述半導體框架具有暴露出所述第一晶粒的所述凹槽的至少一個凹口。所述加強結構配置在所述第一晶粒的所述第二表面上。所述加強結構包括與所述凹槽對準的第一部分。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下描述元件和佈置的具體實例來簡化本公開。當然，這些元件和佈置僅為實例且並不意圖為限制性的。舉例來說，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且還可包含額外特徵可在第一特徵與第二特徵之間形成從而使得第一特徵與第二特徵可以不直接接觸的實施例。此外，本公開可在各種實例中重複附圖標號和/或字母。這種重複是出於簡化和清楚的目的，且本身並不規定所論述的各種實施例和/或配置之間的關係。
此外，為易於描述，本文中可使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”以及類似術語的空間相對術語來描述如圖式中所示出的一個元件或特徵相對於另一元件或特徵的關係。除圖式中所描繪的定向之外，空間相關術語意圖涵蓋器件在使用或操作中的不同定向。裝置可以其它方式定向（旋轉90度或處於其它定向）且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional；3D）封裝或三維積體電路（three-dimensional integrated circuit；3DIC）裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或在基板上形成的測試接墊，以使得能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法來使用，以提高良率並降低成本。
圖1A到圖1O是根據本公開的一些實施例的封裝10的製造流程的示意性剖視圖。參考圖1A，提供晶圓基板（wafer substrate）WS1。在一些實施例中，晶圓基板WS1可由以下製成：合適的元素半導體材料，例如結晶矽、金剛石或鍺；合適的化合物半導體材料，例如砷化鎵、碳化矽、砷化銦或磷化銦；或合適的合金半導體材料，例如碳化矽鍺、磷化鎵砷或磷化鎵銦。
在一些實施例中，半導體晶片WS1包括形成於其中的多個溝槽TR。在一些實施例中，自俯視角度來看，每一溝槽TR呈現環形。在一些實施例中，溝槽TR以陣列佈置。在一些實施例中，晶圓基板WS1更包括形成於其中的多個對位凹部AR。在一些實施例中，自俯視角度來看，每一對位凹部AR呈現L形或十字形。如圖1A中所示出，溝槽TR及對位凹部AR從晶圓基板WS1的頂表面向下延伸到晶圓基板WS1的內部中。在一些實施例中，對位凹部AR的深度小於溝槽TR的深度。另一方面，對位凹部AR的深度及溝槽TR的深度均小於晶圓基板WS1的厚度。舉例來說，溝槽TR的深度可介於約50微米到約600微米的範圍內，且所述範圍為晶圓基板WS1的厚度的約7%到約80%。對位凹部AR的深度可介於約30微米到約300微米範圍內，且所述範圍為晶圓基板WS1的厚度的約4%到約40%。也就是說，溝槽TR及對位凹部AR並不穿透晶圓基板WS1。在一些實施例中，溝槽TR及對位凹部AR可通過蝕刻或其它合適的製程形成。在一些實施例中，對位凹部AR可為可選的。應注意的是，圖1A中所示出的溝槽TR的數目及對位元凹部AR的數目僅出於說明性目的，且本公開並不限於此。在一些替代性實施例中，取決於佈局設計，晶圓基板WS1中可包含更少或更多溝槽TR及對位凹部AR。
參考圖1B，用介電材料部分地填充半導體晶片WS1的溝槽TR以形成虛設環102。舉例來說，虛設環102覆蓋溝槽TR的底表面及溝槽TR的側壁的一部分。另一方面，溝槽TR的側壁的另一部分並不被虛設環102覆蓋。在一些實施例中，介電材料還填充在對位凹部AR中以形成對位標記AM。在一些實施例中，介電材料完全地填充對位凹部AR以形成對位標記AM。在一些實施例中，介電材料進一步沉積在半導體晶片WS1的頂表面的部分上以形成保護塗層104。舉例來說，保護塗層104覆蓋晶圓基板WS1的頂表面的由溝槽TR包繞（enclosed）的部分。如圖1B中所示出，虛設環102及對位標記AM嵌入在晶圓基板WS1中，且並不被保護塗層104覆蓋。由於虛設環102部分地填充溝槽TR且並不從晶圓基板WS1的頂表面突起，因此虛設環102不與保護塗層104直接接觸。在一些實施例中，虛設環102的頂表面低於晶圓基板WS1的頂表面，且虛設環102的頂表面與晶圓基板WS1的頂表面之間的水平高度差介於約3微米到約50微米的範圍內。
在一些實施例中，虛設環102、對位標記AM以及保護塗層104同時形成。也就是說，虛設環102、對位標記AM以及保護塗層104由相同材料製成。舉例來說，虛設環102、對位標記AM以及保護塗層104的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（benzocyclobutene；BCB）、聚苯並噁唑（polybenzooxazole；PBO）或任何其它合適的聚合物系介電材料。然而，本公開並不限於此。在一些替代性實施例中，虛設環102、對位標記AM以及保護塗層104可分別由不同材料形成。在一些實施例中，虛設環102、對位標記AM以及保護塗層104可由三維印刷製程形成。替代地，虛設環102、對位標記AM以及保護塗層104可由沉積製程形成，所述沉積製程例如化學氣相沉積（chemical vapor deposition；CVD）、電漿增強化學氣相沉積（plasma-enhanced chemical vapor deposition；PECVD）或類似製程。
參考圖1B和圖1C，單體化圖1B中所示出的晶圓基板WS1以形成多個虛設晶粒100。在一些實施例中，切割製程（dicing process）或單體化製程通常涉及利用旋轉刀片（rotating blade）或雷射光束進行切割。換句話說，切割製程或單體化製程是例如雷射切削製程、機械切削製程或其它合適的製程。如圖1C中所示出，每一虛設晶粒100包括半導體基板106、虛設環102、對位標記AM以及保護塗層104。虛設環102及對位標記AM嵌入在半導體基板106中，且保護塗層104配置在半導體基板106的表面上。在一些實施例中，溝槽TR及虛設環102將半導體基板106劃分為內部部分106a及外部部分106b。如圖1C中所示出，內部部分106a及外部部分106b通過半導體基板106的底部部分彼此連接。在一些實施例中，虛設晶粒100可不含主動元件及被動元件。替代地，虛設晶粒100可包含主動元件及被動元件，但這些元件的功能被禁用。
參考圖1D，提供晶圓基板WS2。在一些實施例中，晶圓基板WS2包括半導體基板202及嵌入在半導體基板202中的多個半導體穿孔（through semiconductor via；TSV）204。在一些實施例中，半導體基板202可由以下製成：合適的元素半導體材料，例如結晶矽、金剛石或鍺；合適的化合物半導體材料，例如砷化鎵、碳化矽、砷化銦或磷化銦；或合適的合金半導體材料，例如碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些實施例中，半導體基板202具有形成於其中的多個半導體元件（例如，電晶體、電容器、光電二極體、其組合或類似元件）及多個光學器件（例如，波導管、濾光片、光電二極體、發光二極體、其組合或類似元件）。在一些實施例中，TSV 204的深度小於半導體基板202的厚度。也就是說，在這個階段，TSV 204並不穿透半導體基板202。
在一些實施例中，晶圓基板WS2具有第一表面T1及與第一表面T1相對的第二表面T2。如圖1D中所示出，多個凹槽GR形成於晶圓基板WS2的第一表面T1上。在一些實施例中，凹槽GR可以是通過蝕刻、雷射切割或其它合適的製程形成的V凹槽（繪示於圖3A中）。應注意的是，圖1D中所示出的凹槽的數目僅出於說明性目的，且本公開並不限於此。在一些替代性實施例中，取決於佈局設計，晶圓基板WS2中可形成更少或更多的凹槽GR。
如圖1D中所示出，在半導體晶片WS2的第一表面T1上形成多個連接結構300及擋牆結構400。在一些實施例中，每一連接結構300包括導電柱302及配置在導電柱302上的導電凸塊304。如圖1D中所示出，導電柱302對應於TSV 204設置。在一些實施例中，連接結構300被稱作「微凸塊（micro bump）」。在一些實施例中，連接結構300可通過以下步驟形成。首先，晶種層（未繪示）毯覆式地形成於晶圓基板WS2上。晶種層可通過例如濺鍍製程、物理氣相沉積（physical vapor deposition；PVD）製程或類似製程形成。在一些實施例中，晶種層可包括例如銅、鈦銅合金或其它合適的材料的選擇。接著，在晶種層上形成光阻圖案層（未繪示）。光阻圖案層具有暴露出部分晶種層的開口。在一些實施例中，晶種層被暴露出的部分的位置對應於晶圓基板WS2的TSV 204的位置。此後，依序沉積導電材料（未繪示）及焊料材料（未繪示）到被暴露出的晶種層上。也就是說，導電材料及焊料材料位於光阻圖案層的開口內。在一些實施例中，導電材料及焊料材料可通過鍍覆製程形成。鍍覆製程例如為電鍍、無電鍍、浸鍍或類似製程。在一些實施例中，導電材料包括例如銅、銅合金或類似物。在導電材料及焊料材料形成之後，移除光阻圖案層。在移除光阻圖案層後，晶種層的未被導電材料及焊料材料覆蓋的部分被暴露出。在一些實施例中，光阻圖案層可通過例如蝕刻、灰化或其它合適的移除製程移除/剝除。隨後，移除未被導電材料及焊料材料覆蓋的晶種層。晶種層的被暴露出的部分可通過蝕刻製程移除。在一些實施例中，剩餘的晶種層及導電材料構成導電柱302。此後，對焊料材料執行回焊製程以將焊料材料轉換為導電凸塊304。
在一些實施例中，擋牆結構400形成為包圍凹槽GR的。另一方面，擋牆結構400被連接結構300包圍。在一些實施例中，擋牆結構400包括導電環402及配置在導電環402上的導電突起部404。在一些實施例中，連接結構300及擋牆結構400可同時形成。舉例來說，連接結構300的導電柱302及擋牆結構400的導電環402可通過同一製程步驟形成。另一方面，連接結構300的導電凸塊304及擋牆結構400的導電突起部404也可通過同一製程步驟形成。在一些實施例中，自俯視角度來看，擋牆結構400可呈現為包繞凹槽GR的環形。在一些實施例中，擋牆結構400的尺寸（即，厚度及寬度）、位置及形狀可設計為對應於圖1C中的虛設晶粒100的溝槽TR。舉例來說，擋牆結構400的高度可介於約5微米到約50微米的範圍內。
參考圖1E，在晶圓基板WS2的第一表面T1上形成黏合層500。在一些實施例中，黏合層500的材料包括可熱固化聚合物（thermally curable polymer）。在一些實施例中，黏合層500通過分配製程（dispensing process）、網版印刷製程、噴墨印刷製程、三維印刷製程或類似製程形成於晶圓基板WS2的第一表面T1上。在一些實施例中，黏合層500位於連接結構300與擋牆結構400之間。在一些實施例中，自俯視角度來看，黏合層500呈現環形。也就是說，黏合層500包圍擋牆結構400。在一些實施例中，黏合層500可與擋牆結構400保持側向距離。然而，本公開並不限於此。在一些替代性實施例中，黏合層500可黏附到擋牆結構400。如圖1E中所示出，黏合層500的厚度小於擋牆結構400的高度。在一些實施例中，黏合層500的分佈可對應於圖1C中的虛設晶粒100的半導體基板106的外部部分106b。
參考圖1F，將圖1C中所示出的虛設晶粒100及晶粒600放置在晶圓基板WS2的第一表面T1上。在一些實施例中，虛設晶粒100及晶粒600可通過取放製程（pick-and-place process）放置。在一些實施例中，虛設晶粒100及晶粒600並排配置在晶圓基板WS2的第一表面T1上。舉例來說，虛設晶粒100可放置在兩個相鄰的晶粒600之間。如圖1F中所示出，虛設晶粒100放置為覆蓋凹槽GR、擋牆結構400以及黏合層500，而晶粒600放置為覆蓋連接結構300。
在一些實施例中，虛設晶粒100可通過以下步驟放置在晶圓基板WS2上。首先，使虛設晶粒100的溝槽TR與擋牆結構400對準。在一些實施例中，虛設晶粒100的溝槽TR與擋牆結構400之間的對位可通過對位標記AM的輔助來實現。此後，向下移動虛設晶粒100以將擋牆結構400裝配到虛設晶粒100的溝槽TR中。也就是說，將擋牆結構400插入到溝槽TR中。同時，將虛設晶粒100的半導體基板106的外部部分106b附接到黏合層500。換句話說，黏合層500包夾在晶圓基板WS2與虛設晶粒100之間。通過將擋牆結構400裝配到溝槽TR中且通過使虛設晶粒100的半導體基板106的外部部分106b附接到黏合層500，可暫時使虛設晶粒100固定就位。接著，將虛設晶粒100往黏合層500按壓以確保虛設晶粒100的半導體基板106的外部部分106b牢固地固定到黏合層500上。此後，固化黏合層500以增強晶圓基板WS2與虛設晶粒100的半導體基板106的外部部分106b之間的粘合力。如圖1F中所示出，擋牆結構400與虛設晶粒100的虛設環102間隔開。然而，本公開並不限於此。在一些替代性實施例中，擋牆結構400與虛設晶粒100的虛設環102直接接觸。
如圖1F中所示出，虛設晶粒100的保護塗層104覆蓋晶圓基板WS2的凹槽GR。在一些實施例中，保護塗層104用於保護凹槽GR免受破壞。在一些實施例中，保護塗層104與晶圓基板WS2的第一表面T1直接接觸。然而，本公開並不限於此。在一些替代性實施例中，保護塗層104可與晶圓基板WS2的第一表面T1間隔開。
在一些實施例中，晶粒600包括半導體基板602及形成於半導體基板602上的多個導電墊604。在一些實施例中，半導體基板602可由以下製成：合適的元素半導體材料，例如結晶矽、金剛石或鍺；合適的化合物半導體材料，例如砷化鎵、碳化矽、砷化銦或磷化銦；或合適的合金半導體材料，例如碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些實施例中，半導體基板602可包括形成於其中的主動元件（例如，電晶體或類似元件）及可選的被動元件（例如，電阻器、電容器、電感器或類似元件）。導電墊604分布在半導體基板602上。在一些實施例中，導電墊604包括例如鋁墊、銅墊或其它合適的金屬墊。如圖1F中所示出，晶粒600放置為使得晶粒600的導電墊604附接到連接結構300。舉例來說，每一導電墊604與對應的導電凸塊304直接接觸。在晶粒600放置在連接結構300上之後，可執行回焊製程以將導電墊604固定到導電凸塊304上。由此，通過連接結構300可實現晶粒600與晶圓基板WS2之間的電性連接。也就是說，連接結構300配置在晶圓基板WS2與晶粒600之間，且晶粒600通過連接結構300電性連接到晶圓基板WS2。
在一些實施例中，在接合晶粒600之前執行虛設晶粒100的附接。然而，本公開並不限於此。在一些替代性實施例中，在附接虛設晶粒100之前執行晶粒600的接合。
參考圖1G，在晶粒600與晶圓基板WS2之間形成底部填充膠層（underfill layer）UF1。舉例來說，底部填充膠層UF1可形成為包覆晶粒600的導電墊604及連接結構300以保護這些元件。在一些實施例中，底部填充膠層UF1不僅能保護導電墊604及連接結構300免於金屬疲勞（fatigue），且能提高晶粒600與晶圓基板WS2之間的接合可靠性。在一些實施例中，底部填充膠層UF1可為可選的。
參考圖1H，在晶圓基板WS2上形成包封材料700a以包封虛設晶粒100、晶粒600、底部填充膠層UF1以及黏合層500。在一些實施例中，包封材料700a為模塑化合物、模塑底部填充膠、樹脂（例如環氧樹脂）或類似物。在一些實施例中，包封材料700a包含填料（filler）。填料可為由矽石（silica）、二氧化鋁或類似物製成的粒子。包封材料700a可通過模塑製程（例如壓縮模塑製程）形成。在一些實施例中，虛設晶粒100及晶粒600完全被包封材料700a包封。舉例來說，包封材料700a的頂表面T700a 位於高於虛設晶粒100的頂表面T100 及晶粒600的頂表面T600 的水平高度處。換句話說，虛設晶粒100及晶粒600未顯露出且由包封材料700a很好地保護住。如圖1F中所示出，晶圓基板WS2的凹槽GR由虛設晶粒100、擋牆結構400以及黏合層500密封，因此包封材料700a並不填充到凹槽GR中。
參考圖1H和圖1I，移除包封材料700a的一部分直到虛設晶粒100及晶粒600被顯露出。在虛設晶粒100及晶粒600被顯露出之後，進一步減小虛設晶粒100的厚度、晶粒600的厚度以及包封材料700a的厚度直到填充在虛設晶粒100的溝槽TR中的虛設環102被顯露出。在一些實施例中，可通過研磨製程（例如機械研磨製程、化學機械拋光（chemical mechanical polishing；CMP）製程或另一合適的機制）來移除包封材料700a的部分、虛設晶粒100的部分以及晶粒600的部分。在研磨包封材料700a之後，包封體700形成於晶圓基板WS2上以側向包封虛設晶粒100及晶粒600。在研磨製程之後，虛設環102的頂表面T102 、包封體700的頂表面T700 、虛設晶粒100的頂表面T100 以及晶粒600的頂表面T600 實質上共面。如圖1I中所示出，在研磨製程之後，溝槽TR穿透虛設晶粒100。在這個階段，虛設晶粒100的半導體基板106的內部部分106a及外部部分106b彼此分隔開。舉例來說，虛設環102包夾在虛設晶粒100的半導體基板106的內部部分106a與外部部分106b之間以使內部部分106a與外部部分106b分隔開。
參考圖1I和圖1J，對晶圓基板WS2的第二表面T2執行平坦化製程。在一些實施例中，平坦化製程包括機械研磨製程及/或CMP製程。在一些實施例中，平坦化半導體基板202直到顯露出TSV 204。舉例來說，在平坦化製程之後，TSV 204穿透半導體基板202。TSV 204允許晶圓基板WS2的前側與背側之間的電性連通。在一些實施例中，在TSV 204被顯露出之後，可進一步研磨晶圓基板WS2以減小其總體厚度。
參考圖1K，在晶圓基板WS2的第二表面T2上形成多個導電端子800及加強結構900。在一些實施例中，每一導電端子800包括導電柱802及配置在導電柱802上的導電凸塊804。在一些實施例中，導電端子800被稱作「可控塌陷晶片連接（controlled collapse chip connection；C4）凸塊」。在一些實施例中，至少一些導電端子800對應於TSV 204設置。在一些實施例中，導電端子800可通過以下步驟形成。首先，晶種層（未繪示）毯覆式地形成於晶圓基板WS2的第二表面T2上。晶種層可通過例如濺鍍製程、PVD製程或類似製程形成。在一些實施例中，晶種層可包括例如銅、鈦銅合金或其它合適的材料的選擇。接著，在晶種層上形成光阻圖案層（未繪示）。光阻圖案層具有暴露出部分晶種層的開口。此後，依序沉積導電材料（未繪示）及焊料材料（未繪示）到被暴露出的晶種層上。也就是說，導電材料及焊料材料位於光阻圖案層的開口內。在一些實施例中，導電材料及焊料材料可通過鍍覆製程形成。鍍覆製程例如為電鍍、無電鍍、浸鍍或類似製程。在一些實施例中，導電材料包括例如銅、銅合金或類似物。在導電材料及焊料材料形成之後，移除光阻圖案層。在移除光阻圖案層後，晶種層的未被導電材料及焊料材料覆蓋的部分被暴露出。在一些實施例中，光阻圖案層可通過例如蝕刻、灰化或其它合適的移除製程移除/剝除。隨後，移除未被導電材料及焊料材料覆蓋的晶種層。晶種層的被暴露出的部分可通過蝕刻製程移除。在一些實施例中，剩餘的晶種層及導電材料構成導電柱802。此後，對焊料材料執行回焊製程以將焊料材料轉換為導電凸塊804。在一些實施例中，導電端子800以陣列佈置。
如圖1K中所示出，加強結構900的一部分形成為與晶圓基板WS2的凹槽GR垂直對準。舉例來說，加強結構900的一部分直接位於凹槽GR下。也就是說，凹槽GR的沿垂直於晶圓基板WS2的第一表面T1的方向D1的投影與加強結構900的一部分交疊。如圖1K中所示出，加強結構900被導電端子800包圍。在一些實施例中，加強結構900包括基底圖案902及配置在基底圖案902上的突起部904。在一些實施例中，導電端子800及加強結構900可同時形成。舉例來說，導電端子800的導電柱802及加強結構900的基底圖案902可通過同一製程步驟形成。另一方面，導電端子800的導電凸塊804及加強結構900的突起部904也可通過同一製程步驟形成。也就是說，導電端子800及加強結構900由相同材料製成。在一些實施例中，導電端子800的導電柱802的材料與加強結構900的基底圖案902的材料相同，且導電端子800的導電凸塊804的材料與加強結構900的突起部904的材料相同。舉例來說，導電柱802及基底圖案902兩者都由導電材料製成。然而，本公開並不限於此。在一些替代性實施例中，導電端子800及加強結構900可在獨立的步驟中形成。舉例來說，導電端子800可由導電材料形成，而加強結構900可由介電材料（例如聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、BCB、PBO或類似物）製成。
在一些實施例中，加強結構900的大小大於每一導電端子800的大小。舉例來說，每一導電端子800具有介於約50微米到約200微米的範圍內的直徑。另一方面，加強結構900具有介於約1公釐到約200公釐的範圍內的長度或寬度。如圖1K中所示出，每一導電端子800的高度大於加強結構900的高度。然而，本公開並不限於此。在一些替代性實施例中，每一導電端子800的高度可實質上等於加強結構900的高度。稍後將結合圖1O、圖2A到圖2B以及圖3A到圖3B更詳細地論述加強結構900及凹槽GR的相對配置。
在一些實施例中，重佈線結構（未繪示）可形成於晶圓基板WS2的第二表面T2上。也就是說，重佈線結構可可選地形成於晶圓基板WS2與導電端子800之間以及晶圓基板WS2與加強結構900之間。在一些實施例中，重佈線結構包括交替堆疊的多個介電層（未繪示）及多個重佈線導電層（未繪示）。在一些實施例中，重佈線結構電性連接TSV 204與導電端子800，且同時重新分佈電路徑的佈線。
參考圖1K和圖1L，移除虛設晶粒100的一部分。舉例來說，移除半導體基板106的內部部分106a及虛設環102。在一些實施例中，通過以下步驟移除內部部分106a。首先，對被暴露出的虛設環102執行切割製程。在一些實施例中，切割製程可包括雷射鑽孔製程、機械鑽孔製程、其組合或任何其它合適的分割製程。在一些實施例中，在切割製程期間完全地移除虛設環102。然而，本公開並不限於此。在一些替代性實施例中，在切割製程期間部分地移除虛設環102。舉例來說，可切穿虛設環102，使得虛設環102的一部分留在半導體基板106的外部部分106b的側壁上，且虛設環102的另一部分留在半導體基板106的內部部分106a的側壁上。在切割製程之後，內部部分106a及外部部分106b彼此斷開。接著，移除內部部分106a。另一方面，剩餘的外部部分106b形成具有開口OP的半導體框架SF。在一些實施例中，半導體框架SF為電性浮置的。如圖1L中所示出，半導體框架SF的開口OP暴露出擋牆結構400及凹槽GR。
參考圖1L和圖1M，對圖1L中所示出的結構執行單體化製程以形成多個單體化結構SS。也就是說，單體化半導體框架SF、晶圓基板WS2以及加強結構900。在一些實施例中，切割製程或單體化製程通常涉及利用旋轉刀片或雷射光束進行切割。換句話說，切割製程或單體化製程是例如雷射切削製程、機械切削製程或其它合適的製程。在一些實施例中，半導體晶片WS2的厚度並不均一。舉例來說，與未被凹槽GR佔據的區域相比，被凹槽GR佔據的區域具有更小的厚度。因此，在晶圓基板WS2的單體化期間，被凹槽GR佔據的區域處會產生應力，而在晶圓基板WS2中引起裂痕（crack）。然而，如上文所提及，由於加強結構900與凹槽GR對準，因此可由加強結構900補償被凹槽GR佔據的區域的厚度的不足。由此，由於存在加強結構900，在單體化製程期間晶圓基板WS2中的裂痕問題可被緩解，從而提高隨後形成的封裝的良率及可靠性。
在一些實施例中，在單體化製程期間，將晶圓基板WS2劃分為多個晶粒200。如圖1M中所示出，每一晶粒200包括半導體基板202及嵌入在半導體基板202中的TSV 204。晶粒200具有第一表面T1及與第一表面T1相對的第二表面T2。在一些實施例中，晶粒200包括在第一表面T1上的凹槽GR。如圖1M中所示出，晶粒600及半導體框架SF並排配置在晶粒200的第一表面T1上。此外，包封體700配置在晶粒200的第一表面T1上以側向包封晶粒600。此外，擋牆結構400也配置在晶粒200的第一表面T1上。在一些實施例中，半導體框架SF具有暴露出擋牆結構400及凹槽GR的凹口N。在一些實施例中，擋牆結構400沿凹口N的邊緣配置（繪示於圖2A中）。在一些實施例中，導電端子800及加強結構900配置在晶粒200的第二表面T2上。如圖1M中所示出，在這個階段，加強結構900的突起部904具有沿切割線的實質上筆直的側壁。也就是說，加強結構900的突起部904的側壁中的一個與晶粒200的側壁對齊。
參考圖1N，將圖1M中所示出的單體化結構SS安裝到電路基板1000上。在一些實施例中，安裝單體化結構SS從而使電路基板1000處於晶粒200的第二表面T2上。在一些實施例中，電路基板1000包括印刷電路板（printed circuit board；PCB）或類似基板。在一些實施例中，在將單體化結構SS附接到電路基板1000之後，對導電端子800及加強結構900執行回焊製程以重塑（reshape）加強結構900。換句話說，在回焊製程期間，加強結構900的突起部904的圓化（rounding）會發生。在回焊製程之後，突起部904的側壁不再與晶粒200的側壁對齊。在一些實施例中，單體化結構SS的導電端子800電性連接到電路基板1000的導線。舉例來說，單體化結構SS的導電端子800與電路基板1000直接接觸以得到電性連接。另一方面，加強結構900與電路基板1000電性絕緣。如上文所提及，每一導電端子800的高度大於加強結構900的高度。因此，當導電端子800抵接（abut）電路基板1000時，加強結構900與電路基板1000間隔開。因此，加強結構900與電路基板1000電性絕緣。然而，本公開並不限於此。在一些替代性實施例中，每一導電端子800的高度實質上等於加強結構900的高度。因此，導電端子800及加強結構900兩者都會與電路基板1000直接接觸。儘管如此，在這種情境下，加強結構900不會與電路基板1000的導線直接接觸。因此，加強結構900仍與電路基板1000電性絕緣。在一些實施例中，加強結構900為電性浮置的。
在一些實施例中，底部填充膠UF2可可選地形成於電路基板1000上以側向包封晶粒200、導電端子800以及加強結構900。在一些實施例中，底部填充膠UF2可用於保護這些元件。
如圖1N中所示出，多個導電端子1100及多個裝置1200與單體化結構SS相對地形成於電路基板1000上。在一些實施例中，導電端子1100為焊料球、球柵陣列封裝（ball grid array；BGA）球或類似物。在一些實施例中，導電端子1100由具有低電阻率的導電材料製成，所述導電材料例如Sn、Pb、Ag、Cu、Ni、Bi或其合金。在一些實施例中，裝置1200可包括被動元件，例如電阻器、電容器、電感器或類似元件。
參考圖1O，將光纖FB放置在凹槽GR中以形成封裝10。在一些實施例中，光纖FB側向插入到凹槽GR中。光纖FB沿凹槽GR側向延伸且光學上耦合到晶粒200的光學裝置。在一些實施例中，圖1O中所示出的封裝結構10可稱作「基板上晶圓上晶片（Chip on Wafer on Substrate；CoWoS）封裝」。如圖1O中所示出，晶粒200包夾在或插入於晶粒600與電路基板1000之間。因此，在一些實施例中，晶粒200可稱作「插入板（interposer）」。
下文將結合圖1O、圖2A到圖2B以及圖3A到圖3B論述加強結構900及凹槽GR的相對配置。
圖2A是圖1O中的封裝10的俯視圖。圖2B是圖1O中的封裝10的仰視圖。圖3A是沿線II-II’截取的圖2A中的封裝10的示意性剖視圖。圖3B是沿線III-III’截取的圖2A中的封裝10的示意性剖視圖。應注意的是，圖1O是沿線I-I’截取的圖2A中的封裝10的示意性剖視圖。此外，為簡單起見，在圖2B中省略導電端子1100及裝置1200。參考圖1O、圖2A到圖2B以及圖3A到圖3B，加強結構900包括主幹部分900a及從主幹部分900a向外延伸的多個分支部分900b。在一些實施例中，在圖2A到圖2B中用來標示主幹部分900a及分支部分900b的虛線可對應於加強結構900的基底圖案902的形狀或輪廓。在一些實施例中，分支部分900b連接到主幹部分900a。舉例來說，如圖2A到圖2B中所繪示，自俯視角度來看，加強結構900呈現梳狀。如圖2A到圖2B中所示出，主幹部分900a沿方向D2延伸，而分支部分900b沿垂直於方向D2的方向D3延伸。在一些實施例中，加強結構900的主幹部分900a沿晶粒200的邊緣配置。
如圖1O、圖2A到圖2B以及圖3A到圖3B中所示出，自俯視角度來看，加強結構900的分支部分900b與凹槽GR對準。舉例來說，加強結構900的分支部分900b位於凹槽GR的正下方。也就是說，凹槽GR的沿方向D1的投影與加強結構900的分支部分900b交疊。另一方面，自俯視角度來看，主幹部分900a可與凹槽GR相交。也就是說，自俯視角度來看，加強結構900的主幹部分900a的一部分與每一凹槽GR的一部分對準。舉例來說，加強結構900的主幹部分900a的一部分位於凹槽GR的正下方。也就是說，每一凹槽GR的一部分的沿方向D1的投影與加強結構900的主幹部分900a的一部分交疊。儘管圖2A示出每一分支部分900b的沿方向D2的寬度（即，分支部分900b的基底圖案902的寬度）大於每一凹槽GR的沿方向D2的寬度，但本公開並不限於此。在一些替代性實施例中，每一分支部分900b的沿方向D2的寬度（即，分支部分900b的基底圖案902的寬度）可等於每一凹槽GR的沿方向D2的寬度。也就是說，凹槽GR的沿方向D1的投影會與分支部分900b匹配（match）。
在一些實施例中，分支部分900b可被統稱為加強結構900的第一部分，而主幹部分900a可稱作加強結構900的第二部分。
如圖2B中所示出，導電端子800以陣列佈置。主幹部分900a位於導電端子800的陣列旁。在一些實施例中，分支部分900b與導電端子800的一些列（row）對準。另一方面，分支部分900b包夾在導電端子800的其它列的部分之間。
如圖1O和圖3A中所示出，晶粒200的厚度並不均一。舉例來說，與未被凹槽GR佔據的區域相比，被凹槽GR佔據的區域具有更小的厚度。因此，在晶圓基板WS2的單體化期間（繪示於圖1M中），被凹槽GR佔據的區域處會產生應力，而在晶粒200中引起裂痕。然而，由於加強結構900的分支部分900b與凹槽GR對準，因此可由分支部分900b補償被凹槽GR佔據的區域的厚度的不足。此外，由於主幹部分900a在單體化製程期間沿切割線配置，因此主幹部分900a可進一步提高抵抗所產生應力的結構硬度。由此，由於存在加強結構900，晶粒200中的源於單體化製程的裂痕問題可被緩解，從而提高封裝10的良率及可靠性。
圖4A是根據本公開的一些替代性實施例的封裝20的俯視圖。圖4B是圖4A中的封裝20的仰視圖。圖5A是沿線I-I’截取的圖4A中的封裝20的示意性剖視圖。圖5B是沿線II-II’截取的圖4A中的封裝20的示意性剖視圖。圖5C是沿線III-III’截取的圖4A中的封裝20的示意性剖視圖。為簡單起見，在圖4B中省略導電端子1100及裝置1200。參考圖4A到圖4B以及圖5A到圖5C，圖4A到圖4B以及圖5A到圖5C中的封裝20與圖1O、圖2A到圖2B以及圖3A到圖3B中的封裝10類似，因此類似元件由相同附圖標號標示，且在本文中省略其詳細描述。圖2A中的封裝10與圖4A中的封裝20之間的差別在於，在封裝20中，多個凹口N形成於半導體框架SF中。圖4A的封裝20中的每一凹口N小於圖2A的封裝10中的凹口N。如圖4A中所示出，凹口N的數目對應於凹槽GR的數目。也就是說，每一凹口N容納一個凹槽GR。與封裝10的加強結構900類似，封裝20的加強結構900也包括主幹部分900a及從主幹部分900a向外延伸的多個分支部分900b。如圖4A到圖4B以及圖5A到5C中所示出，自俯視角度來看，加強結構900的分支部分900b與凹槽GR對準。另一方面，自俯視角度來看，主幹部分900a可與凹槽GR相交。
如圖5A和圖5B中所示出，晶粒200的厚度並不均一。舉例來說，與未被凹槽GR佔據的區域相比，被凹槽GR佔據的區域具有更小的厚度。因此，在晶圓基板WS2的單體化期間（繪示於圖1M中），被凹槽GR佔據的區域處會產生應力，而在晶粒200中引起裂痕。然而，由於加強結構900的分支部分900b與凹槽GR對準，因此可由分支部分900b補償被凹槽GR佔據的區域的厚度的不足。此外，封裝20中的較小凹口N允許在圖1L中所繪示的步驟期間移除較少的半導體材料，故可充分保持半導體框架SF的結構硬度。因此，可充分抑制在封裝20的製造流程期間所產生的翹曲（warpage）。另外，由於主幹部分900a在單體化製程期間沿切割線配置，因此主幹部分900a可進一步提高抵抗所產生應力的結構硬度。由此，由於存在加強結構900，晶粒200中的源於單體化製程的裂痕問題可被緩解，從而提高封裝20的良率及可靠性。
圖6A是根據本公開的一些替代性實施例的封裝30的俯視圖。圖6B是圖6A中的封裝30的仰視圖。圖7A是沿線I-I’截取的圖6A中的封裝30的示意性剖視圖。圖7B是沿線II-II’截取的圖6A中的封裝30的示意性剖視圖。圖7C是沿線III-III’截取的圖6A中的封裝30的示意性剖視圖。為簡單起見，在圖6B中省略導電端子1100及裝置1200。參考圖6A到圖6B以及圖7A到圖7C，圖6A到圖6B以及圖7A到圖7C中的封裝30與圖1O、圖2A到圖2B以及圖3A到圖3B中的封裝10類似，因此類似元件由相同附圖標號標示，且在本文中省略其詳細描述。圖2A中的封裝10與圖6A中的封裝30之間的差別在於，在封裝30中，加強結構900更包括從主幹部分900a的一個端部延伸到主幹部分900a的另一端部的延伸部分900c。在一些實施例中，主幹部分900a沿晶粒200的一個邊緣配置。另一方面，延伸部分900c沿晶粒200的其它三個邊緣配置。換句話說，主幹部分900a及延伸部分900c沿晶粒200的四個邊緣形成閉合環路（closed loop）。如圖6A到圖6B以及圖7A到圖7C中所示出，自俯視角度來看，加強結構900的分支部分900b與凹槽GR對準。另一方面，自俯視角度來看，主幹部分900a可與凹槽GR相交。在一些實施例中，延伸部分900c的寬度介於約50微米到約200微米的範圍內。在一些實施例中，延伸部分900c的寬度小於主幹部分900a的寬度及/或分支部分900b的寬度。然而，本公開並不限於此。在一些替代性實施例中，主幹部分900a、分支部分900b以及延伸部分900c的寬度可相同。
在一些實施例中，分支部分900b可被統稱為加強結構900的第一部分，而主幹部分900a及延伸部分900c可被統稱為加強結構900的第二部分。如圖6B中所示出，主幹部分900a及延伸部分900c一起包圍導電端子800。換句話說，加強結構900的第二部分包圍導電端子800。
如圖7A和圖7B中所示出，晶粒200的厚度並不均一。舉例來說，與未被凹槽GR佔據的區域相比，被凹槽GR佔據的區域具有更小的厚度。因此，在晶圓基板WS2的單體化期間（繪示於圖1M中），被凹槽GR佔據的區域處會產生應力，而在晶粒200中引起裂痕。然而，由於加強結構900的分支部分900b與凹槽GR對準，因此可由分支部分900b補償被凹槽GR佔據的區域的厚度的不足。此外，由於主幹部分900a在單體化製程期間沿切割線配置，且延伸部分900c沿晶粒200的三個邊緣配置，因此主幹部分900a及延伸部分900c可進一步提高抵抗所產生應力的結構硬度。另外，由於主幹部分900a及延伸部分900c沿晶粒200的四個邊緣配置，故可防止晶粒200與底部填充膠UF2之間的尖角介面（sharp-corner interface）。因此，可充分消除底部填充膠UF2中的裂痕問題。由此，由於存在加強結構900，晶粒200中的源於單體化製程的裂痕問題可被緩解，從而提高封裝30的良率及可靠性。
圖8A是根據本公開的一些替代性實施例的封裝40的俯視圖。圖8B是圖8A中的封裝40的仰視圖。圖9A是沿線I-I’截取的圖8A中的封裝40的示意性剖視圖。圖9B是沿線II-II’截取的圖8A中的封裝40的示意性剖視圖。圖9C是沿線III-III’截取的圖8A中的封裝40的示意性剖視圖。為簡單起見，在圖8B中省略導電端子1100及裝置1200。參考圖8A到圖8B以及圖9A到圖9C，圖8A到圖8B以及圖9A到圖9C中的封裝40與圖6A到圖6B以及圖7A到圖7C中的封裝30類似，因此類似元件由相同附圖標號標示，且在本文中省略其詳細描述。圖6A中的封裝30與圖8A中的封裝40之間的差別在於，在封裝40中，多個凹口N形成於半導體框架SF中。圖8A的封裝40中的每一凹口N小於圖6A的封裝30中的凹口N。如圖8A中所示出，凹口N的數目對應於凹槽GR的數目。也就是說，每一凹口N容納一個凹槽GR。與封裝30的加強結構900類似，封裝40的加強結構900也包括主幹部分900a、從主幹部分900a向外延伸的多個分支部分900b以及從主幹部分900a的一個端部延伸到主幹部分900a的另一端部的延伸部分900c。如圖8A到圖8B以及圖9A到9C中所示出，自俯視角度來看，加強結構900的分支部分900b與凹槽GR對準。另一方面，自俯視角度來看，主幹部分900a可與凹槽GR相交。
如圖9A和圖9B中所示出，晶粒200的厚度並不均一。舉例來說，與未被凹槽GR佔據的區域相比，被凹槽GR佔據的區域具有更小的厚度。因此，在晶圓基板WS2的單體化期間（繪示於圖1M中），被凹槽GR佔據的區域處會產生應力，而在晶粒200中引起裂痕。然而，由於加強結構900的分支部分900b與凹槽GR對準，因此可由分支部分900b補償被凹槽GR佔據的區域的厚度的不足。此外，封裝40中的較小凹口N允許在圖1L中所繪示的步驟期間移除較少的半導體材料，故可充分保持半導體框架SF的結構硬度。因此，可充分抑制在封裝40的製造流程期間所產生的翹曲。另外，由於主幹部分900a在單體化製程期間沿切割線配置，且延伸部分900c沿晶粒200的三個邊緣配置，因此主幹部分900a及延伸部分900c可進一步提高抵抗所產生應力的結構硬度。由此，由於存在加強結構900，晶粒200中的源於單體化製程的裂痕問題可被緩解，從而提高封裝40的良率及可靠性。
根據本公開的一些實施例，一種封裝包括第一晶粒、第二晶粒、半導體框架以及加強結構。所述第一晶粒具有第一表面及與所述第一表面相對的第二表面。所述第一晶粒包括在所述第一表面上的凹槽。所述第二晶粒及所述半導體框架並排配置在所述第一晶粒的所述第一表面上。所述半導體框架具有暴露出所述第一晶粒的所述凹槽的至少一個凹口。所述加強結構配置在所述第一晶粒的所述第二表面上。所述加強結構包括與所述凹槽對準的第一部分。
根據本公開的一些實施例，所述凹槽的沿垂直於所述第一晶粒的所述第一表面的方向的投影與所述加強結構的所述第一部分交疊。
根據本公開的一些實施例，所述加強結構更包括連接到所述第一部分的第二部分，且所述第二部分沿所述第一晶粒的至少一個邊緣配置。
根據本公開的一些實施例，所述加強結構的所述第一部分沿第一方向延伸，且所述加強結構的所述第二部分沿垂直於所述第一方向的第二方向延伸。
根據本公開的一些實施例，所述加強結構的所述第二部分沿所述第一晶粒的四個邊緣配置。
根據本公開的一些實施例，所述加強結構為電性浮置的。
根據本公開的一些實施例，所述封裝更包括包封體、擋牆結構、光纖、導電端子以及電路基板。所述包封體位於所述第一晶粒上。所述包封體側向包封所述第二晶粒。所述擋牆結構沿所述至少一個凹口的邊緣配置。所述光纖位於所述凹槽中。所述導電端子配置在所述第一晶粒的所述第二表面上。所述電路基板位於所述第一晶粒的所述第二表面上。
根據本公開的一些實施例，所述導電端子與所述電路基板直接接觸，且所述加強結構與所述電路基板間隔開。
根據本公開的一些替代性實施例，一種封裝包括電路基板、插入板（interposer）、晶粒、半導體框架、擋牆結構、導電端子以及加強結構。所述插入板配置於所述電路基板上。所述插入板包括凹槽，所述凹槽在所述插入板的與所述電路基板相對的表面上。所述晶粒及所述半導體框架並排配置在所述插入板上的與所述電路基板相對側。所述半導體框架具有暴露出所述插入板的所述凹槽的至少一個凹口。所述擋牆結構配置在所述插入板上且被所述半導體框架包圍。所述導電端子包夾在所述電路基板與所述插入板之間。所述加強結構位於所述電路基板與所述插入板之間。所述加強結構包括主幹部分及從所述主幹部分向外延伸的分支部分。
根據本公開的一些替代性實施例，所述導電端子及所述加強結構由相同材料製成。
根據本公開的一些替代性實施例，所述加強結構的所述分支部分與所述凹槽對準。
根據本公開的一些替代性實施例，所述加強結構的所述主幹部分沿所述插入板的邊緣延伸。
根據本公開的一些替代性實施例，所述加強結構更包括從所述主幹部分的一個端部延伸到所述主幹部分的另一端部的延伸部分。
根據本公開的一些替代性實施例，所述加強結構為電性浮置的。
根據本公開的一些替代性實施例，所述封裝更包括包封體以及光纖。所述包封體位於所述插入板上。所述包封體側向包封所述晶粒。所述光纖位於所述凹槽中。
根據本公開的一些實施例，一種製造封裝的方法包括至少以下步驟。提供具有第一表面及與所述第一表面相對的第二表面的晶圓基板。所述晶圓基板包括形成於所述第一表面上的凹槽。在所述晶圓基板的所述第一表面上放置晶粒及虛設晶粒。所述虛設晶粒覆蓋所述凹槽。由包封體側向包封所述晶粒及所述虛設晶粒。在所述晶圓基板的所述第二表面上形成導電端子及加強結構。所述加強結構的一部分與所述凹槽對準。移除所述虛設晶粒的一部分以形成具有暴露出所述凹槽的至少一個開口的半導體框架。單體化所述半導體框架、所述晶圓基板以及所述加強結構以形成單體化結構。
根據本公開的一些實施例，所述製造封裝的方法更包括在所述晶圓基板的所述第一表面上形成擋牆結構，且所述擋牆結構包圍所述凹槽。
根據本公開的一些實施例，所述虛設晶粒包括溝槽，且在所述晶圓基板的所述第一表面上放置所述晶粒的步驟包括將所述擋牆結構裝配到所述溝槽中。
根據本公開的一些實施例，所述製造封裝的方法更包括至少以下步驟。將所述單體化結構安裝到電路基板上。對所述導電端子及所述加強結構執行回焊製程以重塑所述加強結構。
根據本公開的一些實施例，所述製造封裝的方法更包括將光纖放置在所述凹槽中。
前文概述若干實施例的特徵，使得本領域的技術人員可更好地理解本公開的各方面。本領域的技術人員應瞭解，其可易於使用本公開作為用於設計或修改用於進行本文中所引入的實施例的相同目的和/或達成相同優點的其它製程和結構的基礎。本領域的技術人員還應認識到，這類等效構造並不脫離本公開的精神和範圍，且本領域的技術人員可在不脫離本公開的精神和範圍的情況下在本文中作出各種改變、替代以及更改。
10、20、30、40:封裝 100:虛設晶粒 102:虛設環 104:保護塗層 106、202、602:半導體基板 106a:內部部分 106b:外部部分 200、600:晶粒 204:半導體穿孔 300:連接結構 302、802:導電柱 304、804:導電凸塊 400:擋牆結構 402:導電環 404:導電突起部 500:黏合層 604:導電墊 700:包封體 700a:包封材料 800、1100:導電端子 900:加強結構 900a:主幹部分 900b:分支部分 900c:延伸部分 902:基底圖案 904:突起部 1000:電路基板 1200:裝置 AM:對位標記 AR:對位凹部 D1、D2、D3:方向 FB:光纖 GR:凹槽 N:凹口 OP:開口 SF:半導體框架 SS:單體化結構 T1:第一表面 T2:第二表面 T100 、T102 、T600 、T700 、T700a :頂表面 TR:溝槽 UF1:底部填充膠層 UF2:底部填充膠 WS1、WS2:晶圓基板
圖1A到圖1O是根據本公開的一些實施例的封裝的製造流程的示意性剖視圖。 圖2A是圖1O中的封裝的俯視圖。 圖2B是圖1O中的封裝的仰視圖。 圖3A是沿線II-II’截取的圖2A中的封裝的示意性剖視圖。 圖3B是沿線III-III’截取的圖2A中的封裝的示意性剖視圖。 圖4A是根據本公開的一些替代性實施例的封裝的俯視圖。 圖4B是圖4A中的封裝的仰視圖。 圖5A是沿線I-I’截取的圖4A中的封裝的示意性剖視圖。 圖5B是沿線II-II’截取的圖4A中的封裝的示意性剖視圖。 圖5C是沿線III-III’截取的圖4A中的封裝的示意性剖視圖。 圖6A是根據本公開的一些替代性實施例的封裝的俯視圖。 圖6B是圖6A中的封裝的仰視圖。 圖7A是沿線I-I’截取的圖6A中的封裝的示意性剖視圖。 圖7B是沿線II-II’截取的圖6A中的封裝的示意性剖視圖。 圖7C是沿線III-III’截取的圖6A中的封裝的示意性剖視圖。 圖8A是根據本公開的一些替代性實施例的封裝的俯視圖。 圖8B是圖8A中的封裝的仰視圖。 圖9A是沿線I-I’截取的圖8A中的封裝的示意性剖視圖。 圖9B是沿線II-II’截取的圖8A中的封裝的示意性剖視圖。 圖9C是沿線III-III’截取的圖8A中的封裝的示意性剖視圖。
10:封裝
200、600:晶粒
300:連接結構
302、802:導電柱
304、804:導電凸塊
400:擋牆結構
402:導電環
404:導電突起部
500:黏合層
700:包封體
800、1100:導電端子
900:加強結構
900a:主幹部分
900b:分支部分
902:基底圖案
904:突起部
1000:電路基板
1200:裝置
D1、D2、D3:方向
FB:光纖
GR:凹槽
N:凹口
SF:半導體框架
UF1:底部填充膠層
UF2:底部填充膠

Claims (1)

  1. 一種封裝，包括： 第一晶粒，具有第一表面及與所述第一表面相對的第二表面，其中所述第一晶粒包括在所述第一表面上的凹槽； 第二晶粒及半導體框架，並排配置在所述第一晶粒的所述第一表面上，其中所述半導體框架具有暴露出所述第一晶粒的所述凹槽的至少一個凹口；以及 加強結構，配置在所述第一晶粒的所述第二表面上，其中所述加強結構包括與所述凹槽對準的第一部分。
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