TW202143485A - 半導體電晶體裝置及其形成方法 - Google Patents

半導體電晶體裝置及其形成方法 Download PDF

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TW202143485A
TW202143485A TW110116681A TW110116681A TW202143485A TW 202143485 A TW202143485 A TW 202143485A TW 110116681 A TW110116681 A TW 110116681A TW 110116681 A TW110116681 A TW 110116681A TW 202143485 A TW202143485 A TW 202143485A
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source
drain
backside
gate
drain epitaxial
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TW110116681A
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TWI783477B (zh
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朱熙甯
江國誠
王志豪
藍文廷
程冠倫
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台灣積體電路製造股份有限公司
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Abstract

一種半導體電晶體裝置，包括通道結構、閘極結構、第一源極∕汲極磊晶結構、第二源極∕汲極磊晶結構、閘極接觸件與背側源極∕汲極接觸件。閘極結構包繞通道結構。第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構設置於通道結構的兩端。閘極接觸件設置於閘極結構上。背側源極∕汲極接觸件設置於第一源極∕汲極磊晶結構下。第一源極∕汲極磊晶結構具有接觸背側源極∕汲極接觸件的凹狀底表面。

Description

半導體電晶體裝置及其形成方法
本發明實施例是關於一種半導體裝置及其製造方法，特別是關於一種奈米結構場效電晶體裝置及其製造方法。
半導體積體電路產業歷經指數性的成長。積體電路材料與設計的科技進展產生了各個世代的積體電路，其中各世代相較於先前世代具有較小且較為複雜的電路。積體電路演進期間，功能密度（亦即，單位晶片面積的內連線裝置數目）通常會增加而幾何尺寸（亦即，可利用製程生產的最小元件（或線））卻減少。此微縮化的過程通常會提高生產效率以及降低相關成本而提供助益。這樣的微縮化也會增加加工與製造積體電路的複雜度。
本發明實施例提供一種半導體電晶體裝置。半導體電晶體裝置包括：通道結構；閘極結構，包繞通道結構；第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構，設置於通道結構的兩端；閘極接觸件，設置於閘極結構上；以及背側源極∕汲極接觸件，設置於第一源極∕汲極磊晶結構下；其中第一源極∕汲極磊晶結構具有接觸背側源極∕汲極接觸件的凹狀底表面。
本發明實施例亦提供一種半導體電晶體裝置。半導體電晶體裝置包括：通道結構；閘極結構，包繞通道結構；第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構，設置於通道結構的兩端；閘極接觸件，設置於閘極結構上；背側源極∕汲極接觸件，設置於第一源極∕汲極磊晶結構下並與第一源極∕汲極磊晶結構接觸；以及背側介電蓋，設置於第二源極∕汲極磊晶結構下並與第二源極∕汲極磊晶結構及該閘極結構接觸。
本發明實施例亦提供一種半導體電晶體裝置的形成方法。半導體電晶體裝置的形成方法包括：交替堆疊第一半導體層與第二半導體層而於基板之上形成鰭片結構；於鰭片結構之上形成虛置閘極結構；移除鰭片結構沒有被虛置閘極結構覆蓋的一部分；於第一半導體層剩餘部分的兩側形成內間隔物；於鰭片結構的兩端形成第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構；以金屬閘極結構取代虛置閘極結構與第一半導體層；移除基板且形成背側蓋溝槽，以露出金屬閘極結構的底表面與第二源極∕汲極磊晶結構的底表面，其中第二源極∕汲極磊晶結構的底表面被凹蝕；於背側蓋溝槽中形成背側介電蓋；以及於第一源極∕汲極磊晶結構下形成與第一源極∕汲極磊晶結構接觸的背側源極∕汲極接觸件。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同部件。各部件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一部件形成在第二部件之上，可能包含第一和第二部件直接接觸的實施例，也可能包含額外的部件形成在第一和第二部件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複元件符號以及∕或字母。這樣的重複是出於簡易與清楚起見，而其本身並不是用以表示所討論的各種實施例及∕或配置之間的關係。
再者，本文可能使用空間相對用詞，例如「在……下方」、「在……之下」、「下方的」、「在……之上」、「上方的」等類似用詞，是為了便於描述圖式中一個（些）元件或部件與另一個（些）元件或部件之間的關係。空間相對用詞意欲涵蓋使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
如本文所使用，「約（about）」、「大約（approximately或around）」或「實質上（substantially）」一般而言將指的是一給定數值或範圍的20%之內、或10%之內或5%之內。本文所給出的數值為近似值，表示若沒有明確說明，則可以推斷出「約」、「大約」或「實質上」等用詞。
可利用任何合適的方法圖案化全繞式閘極（gate all around, GAA）電晶體結構。例如，可使用一或多道光學微影製程來圖案化，光學微影製程包括雙重圖案化或多重圖案化製程。一般來說，雙重圖案化或多重圖案化製程結合了微影製程與自對準製程，以創建出例如，比使用單一、直接微影製程所得的節距更小的圖案。例如，在一實施例中，在基板上方形成犧牲層，並使用微影製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。之後去除犧牲層，然後可以使用剩餘的間隔物圖案化鰭片。形成全繞式閘極電晶體結構之後，可於全繞式閘極電晶體結構之上形成內連線結構，內連線結構包括設置於層間介電層之中的電源軌（power rail）與訊號線。
當半導體製程持續縮小如超過3奈米時，現行的電源軌設計在後段製程（back-end-of-line, BEOL）將經歷複雜的金屬層佈線（routing）。由於複雜的金屬層佈線而需要更多的遮罩，且當金屬線越來越薄時會存在電壓降（voltage drop，也稱為IR降）的問題。
基於上述，本發明實施例是關於具有背側電源軌的半導體電晶體裝置及其製造方法。藉由將電源軌從半導體電晶體裝至的前側移至後側，而使後段製程中的金屬層佈線較為寬鬆。因此，所需要的遮罩較少、改善電壓降並放大電源軌區域與主動區兩者。
更詳細而言，本發明的一些實施例是關於全繞式閘極裝置。全繞式閘極裝置包括通道結構、包繞通道結構的閘極結構、設置於通道結構兩端的第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構以及設置於閘極結構上的閘極接觸件。全繞式閘極裝置更包括坐落於第一源極∕汲極磊晶結構凹蝕的底表面上的背側源極∕汲極接觸件，以及設置於背側源極∕汲極接觸件下並與其接觸的背側電源軌。例如，背側源極∕汲極接觸件與背側電源軌可包括金屬材料。在一些實施例中，可凹蝕第一源極∕汲極磊晶結構的底表面至垂直方向上比閘極結構或通道結構的底表面更深的位置。因此，可減少元件電容。
在一些實施例中，形成第一源極∕汲極磊晶結構之前，透過形成犧牲背側接觸件而自對準形成背側源極∕汲極接觸件。之後選擇性地移除虛置背側接觸件並以背側源極∕汲極接觸件取代，以消除接觸落點（contact landing）的疊對位移（overlay shift）。
在一些額外的實施例中，全繞式閘極裝置更包括設置於閘極結構與第二源極∕汲極磊晶結構下的背側介電蓋。背側介電蓋可包括氧化物、氮化物、碳氮化物或低介電常數介電材料。背側介電蓋取代原本的半導體主體材料，且因此減少元件電容並解決漏電流的問題，例如閘極結構與背側源極∕汲極接觸件之間的漏電流。
再者，第二源極∕汲極磊晶結構可具有凹狀（concave）底表面。可凹蝕第二源極∕汲極磊晶結構的底表面至與閘極結構的底表面垂直對準或甚至更深的位置。因此，可進一步減少元件電容。
本文呈現的全繞式閘極裝置包括p型全繞式閘極裝置或n型全繞式閘極裝置。再者，全繞式閘極裝置可具有與單一、相連的閘極結構或多閘極結構相關聯的一或多個通道區（例如，半導體奈米線（nanowire）或奈米點（nanodot）等）。具有通常知識者可認知到受益於本發明態樣的其他半導體電晶體裝置範例。全繞式閘極裝置可以是積體電路的一部份，積體電路可包括靜態隨機存取記憶體（static random access memory, SRAM）、邏輯電路、被動組件及∕或主動組件，被動組件如電阻器、電容器與電感器，且主動組件如p型場效電晶體、n型場效電晶體、多閘極場效電晶體、金屬氧化物半導體場效電晶體、互補式金屬氧化物半導體電晶體、雙極電晶體（bipolar transistor）、高電壓電晶體、高頻電晶體、其他記憶體單元與前述之組合。
第1圖根據一些實施例繪示出半導體電晶體裝置100的剖面圖。半導體電晶體裝置100包括通道結構102與包繞通道結構102的閘極結構104。通道結構102可包括半導體層堆疊，半導體層堆疊被閘極結構104的金屬組件堆疊所分隔與圍繞。第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108設置於通道結構102的兩端。內間隔物128設置於閘極結構104金屬組件的兩端，以將閘極結構104與第一源極∕汲極磊晶結構106及第二源極∕汲極磊晶結構108隔離。在一些實施例中，閘極間隔物134沿著閘極結構104上部的兩側側壁設置。內間隔物128的外表面可實質上與通道結構102及∕或閘極間隔物134的外表面共平面。在一些實施例中，上隔離結構220設置於閘極間隔物134之間的溝槽中。上隔離結構220提供閘極結構104之間的電性隔離。作為範例，通道結構102可以是未以p型與n型雜質（impurity）摻雜的純矽層。通道結構102的厚度可介於約3nm至約15nm之間的範圍。作為範例，閘極結構104可包括如高介電常數（介電常數大於7）材料的閘極介電材料、功函數金屬材料以及如鎢或鋁的填充金屬材料。閘極結構104的厚度可介於約2nm至約10nm之間的範圍。在一些實施例中，第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108包括半導體材料如矽、鍺或矽鍺。第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108可為六角形或類鑽石的形狀。在一些實施例中，第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108具有不同的導電型態。例如，第一源極∕汲極磊晶結構106可為n型磊晶結構，且第二源極∕汲極磊晶結構108可為p型磊晶結構，或反之亦然。第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108可分別為半導體電晶體裝置100的源極與汲極。
在半導體電晶體裝置100的前側，前側內連線結構114可設置於閘極結構104、第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108之上。前側內連線結構114可包括設置於前側層間介電層112之中且被前側層間介電層112圍繞的複數層前側金屬層116。前側金屬層116包括如導孔或接觸件的垂直內連線以及如金屬線的水平內連線。前側內連線結構114電性連接半導體電晶體裝置的各個部件或結構。例如，閘極接觸件110可設置於閘極結構104上並透過前側金屬層116連接外部電路。
在半導體電晶體裝置100的背側，在一些實施例中，背側源極∕汲極接觸件120設置於第一源極∕汲極磊晶結構106下方，且將第一源極∕汲極磊晶結構106連接至設置於背側源極∕汲極接觸件120下的背側電源軌122。在一些實施例中，介電側壁間隔物118沿著背側源極∕汲極接觸件120的側壁設置，且隔離背側源極∕汲極接觸件120與背側介電蓋126。背側源極∕汲極接觸件120與背側電源軌122可包括如金屬材料。例如，背側源極∕汲極接觸件120可包括金屬如鎢（W）、鈷（Co）、銣（Ru）、鋁（Al）、銅（Cu）或其他合適的材料。因此，第一源極∕汲極磊晶結構106可透過背側源極∕汲極接觸件120從半導體電晶體裝置100的背側連接外部電路。從而提供較高的金屬佈線彈性且可減少元件電容。
再者，背側源極∕汲極接觸件120可坐落於第一源極∕汲極磊晶結構106凹蝕的底表面106b上。在一些實施例中，第一源極∕汲極磊晶結構106的底表面106b可被凹蝕成凸狀（convex），並在垂直方向上達到比閘極結構104的底表面104b更深的位置。
亦在半導體電晶體裝置100的背側，在一些實施例中，背側介電蓋126設置於閘極結構104下。背側介電蓋126也可於第二源極∕汲極磊晶結構108下延伸。背側介電蓋126取代原本的半導體主體材料，有助於隔離且絕緣閘極結構104與背側源極∕汲極接觸件120，且因此減少元件電容並解決漏電流的問題，例如閘極結構104與背側源極∕汲極接觸件120之間的漏電流。背側介電蓋126可包括氧化物、氮化物、碳氮化物或低介電常數介電材料。
第2圖根據一些實施例繪示出具有背側電源軌的半導體電晶體裝置200的剖面圖。除了參照第1圖所揭示的部件之外，在更一些實施例中，第一源極∕汲極磊晶結構106的底表面106b可被凹蝕更深入至垂直方向上超過通道結構102底表面102b的位置。與第1圖的半導體電晶體裝置100相比，進一步減少元件電容，其中第一源極∕汲極磊晶結構106的底表面106b位於通道結構102最底部之下。
第3圖根據一些實施例繪示出具有背側電源軌的半導體電晶體裝置300的剖面圖。除了參照第1與2圖所揭示的部件之外，在更一些實施例中，可回凹蝕第二源極∕汲極磊晶結構108的底表面108b，且將如第1與2圖所示的凹狀表面達到與閘極結構104底表面104b齊平的位置。與第1、2圖的半導體電晶體裝置100、200相比，可進一步減少元件電容。
第4圖根據一些實施例繪示出具有背側電源軌的半導體電晶體裝置400的剖面圖。除了前文所揭示的部件之外，在更一些實施例中，可凹蝕第二源極∕汲極磊晶結構108的底表面108b至垂直方向上比閘極結構104的底表面104b更深的位置，且與第1、2、3圖的半導體電晶體裝置100、200、300相比，可進一步減少元件電容。
第5圖根據一些實施例繪示出第4圖的半導體電晶體裝置400的透視圖。第4圖可視為沿著第5圖的x方向擷取的剖面圖。第6A至6C圖可視為分別沿著第5圖的閘極區、第一源極∕汲極區與第二源極∕汲極區中的y方向擷取的剖面圖。或者，第4-5、6A-6C圖及之後的其他圖式也可為獨立而呈現各式各樣的實施例，且與一圖式相關聯所討論的部件在可適用的情況下可併入至另一圖式。
如第5、6A-6C圖所示，在一些實施例中，下隔離結構160、中間隔離結構132與硬遮罩136可共同作為絕緣結構，並沿著y方向隔離兩個半導體電晶體裝置400a、400b。如第6A圖所示，在一些實施例中，閘極結構104包括閘極介電層232與閘極電極230。閘極電極230包括一或多層功函數金屬層與填充金屬。可順應地形成閘極介電層232使其內襯於閘極電極230的外表面。閘極介電層232可直接接觸下隔離結構160與通道結構102。在一些實施例中，閘極介電層232包括高介電常數材料（介電常數大於7）如氧化鉿（HfO2 ）、氧化鋯（ZrO2 ）、氧化鑭（La2 O3 ）、氧化鉿鋁（HfAlO2 ）、氧化鉿矽（HfSiO2 ）、氧化鋁（Al2 O3 ）或其他合適的材料。
如第5與6C圖所示，第一源極∕汲極磊晶結構106可具有凹蝕的底表面（例如，凸狀），且背側源極∕汲極接觸件120電性耦接至凹蝕的底表面。如第5、6A與6B圖所示，第二源極∕汲極磊晶結構108可具有凹蝕的底表面（例如，凸狀），且背側介電蓋126設置於第二源極∕汲極磊晶結構108與閘極結構104的正下方。背側介電蓋126可被中間隔離結構160圍繞。在一些實施例中，可形成氣隙（air gap）192圍繞第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108的下部。
第7至13圖、第14A至14D圖、第15A與15B圖、第16A至16C圖、第17A至17D圖、第18A至18D圖、第19A至19C圖、第20與21圖、第22A至22C圖、第23A至23C圖、第24A至24D圖、第25A至25D圖、第26A至26C圖以及第27A與27B圖根據本發明的一些實施例繪示出半導體電晶體裝置在各種階段的製造方法。在一些實施例中，第7至13圖、第14A至14D圖、第15A與15B圖、第16A至16C圖、第17A至17D圖、第18A至18D圖、第19A至19C圖、第20與21圖、第22A至22C圖、第23A至23C圖、第24A至24D圖、第25A至25D圖、第26A至26C圖以及第27A與27B圖所示的半導體電晶體裝置可以是在加工積體電路或其部分時所製造的中間裝置，積體電路可包括靜態隨機存取記憶體、邏輯電路、被動組件及∕或主動組件，被動組件如電阻器、電容器與電感器，且主動組件如p型場效電晶體、n型場效電晶體、多閘極場效電晶體、金屬氧化物半導體場效電晶體、互補式金屬氧化物半導體電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、其他記憶體單元與前述之組合。
如第7圖的透視圖所示，在一些實施例中，堆疊結構150形成於基板140上。在一些實施例中，基板140可以是部分的晶圓，且可包括矽（Si）、鍺（Ge）、矽鍺（SiGe）、砷化鎵（GaAs）或其他合適的半導體材料。在一些實施例中，基板140為絕緣體上覆半導體（semiconductor-on-insulator, SOI）結構，絕緣體上覆半導體結構包括塊狀（bulk）基板142、塊狀基板142上的絕緣基板144以及絕緣基板144上的半導體基板層146。在各種實施例中，基板140可包括任何各式各樣的基板結構與材料。
堆疊結構150包括交替堆疊的第一半導體層152與第二半導體層154。第一半導體層152將作為半導體電晶體裝置的通道區，且第二半導體層154為後續將被移除並以閘極材料取代的犧牲層。第一半導體層152與第二半導體層154由具有不同晶格常數（lattice constant）的材料所形成，且可包括一或多層的Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP。在一些實施例中，第一半導體層152與第二半導體層154由Si、Si化合物、SiGe、Ge或Ge化合物所形成。可利用磊晶法於基板140上形成堆疊結構150，使得堆疊結構150形成結晶層（crystalline layer）。雖然第7圖繪示出4層第一半導體層152與三層第二半導體層154，但膜層的數量並非以此為限且各層可以少至1層。在一些實施例中，第一半導體層與第二半導體層各形成2至10層。可透過調整堆疊層的數量而調整半導體電晶體裝置的驅動電流（driving current）。
在一些實施例中，第一半導體層152可以是不含有鍺的純矽層。第一半導體層152也可以是實質上純矽層，例如具有小於約1%的鍺原子百分比。再者，第一半導體層152可以是固有的（intrinsic）而未以p型或n型雜質摻雜。在一些實施例中，第一半導體層152的厚度在約3nm至約15nm之間的範圍內。
在一些實施例中，第二半導體層154可以是具有大於0的鍺原子百分比的SiGe層。在一些實施例中，第二半導體層154的鍺百分比在約10%至約50%之間的範圍內。在一些實施例中，第二半導體層154的厚度在約2nm至約10nm之間的範圍內。
如第8圖的透視圖所示，在一些實施例中，圖案化堆疊結構150（參照第7圖）以形成鰭片結構156以及於X方向延伸的溝槽158。在一些實施例中，以使用圖案化的遮罩層157作為蝕刻遮罩的蝕刻製程來圖案化堆疊結構150，以移除堆疊結構150沒有被遮罩層157覆蓋的部分。半導體基板層146在此製程中也可被部分或完全移除。遮罩層157可包括第一遮罩層與第二遮罩層。第一遮罩層可以是利用熱氧化且由氧化矽所形成的墊氧化物（pad oxide）層。第二遮罩層可由氮化矽所形成，且可利用化學氣相沉積（chemical vapor deposition, CVD）、物理氣相沉積（physical vapor deposition, PVD）、原子層沉積（atomic layer deposition, ALD）或其他合適的製程形成第二遮罩層，化學氣相沉積包括低壓化學氣相沉積（low pressure CVD, LPCVD）以及電漿增強化學氣相沉積（plasma enhanced CVD, PECVD）。可利用各種多重圖案化技術來圖案化遮罩層157。第8圖繪示出排列於Y方向且彼此相互平行的兩個鰭片結構156，但鰭片結構的數量並非以此為限，且可以少至1個以及3或更多個。在一些實施例中，在鰭片結構156的兩側形成一或多個虛置（dummy）鰭片結構，以改善圖案化操作步驟中的圖案精確度。
如第9圖的透視圖所示，在一些實施例中，於溝槽158下部中的絕緣基板層144之上形成下隔離結構160，下隔離結構160也稱為淺溝槽隔離（shallow trench isolation, STI）結構。鰭片結構156的上部從下隔離結構160露出。可透過在絕緣基板層144之上形成絕緣材料並進行平坦化操作步驟而形成下隔離結構160。接著，凹蝕絕緣材料以形成下隔離結構160，使鰭片結構156的上部得以露出。絕緣材料可包括介電材料如氮化物（例如，氮化矽、氮氧化矽、碳氮氧化矽、碳氮化矽）、碳化物（例如，碳化矽、碳氧化矽）、氧化物（例如，氧化矽）、硼矽酸鹽玻璃（borosilicate glass, BSG）、磷矽酸鹽玻璃（phosphoric silicate glass, PSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass, BPSG）或介電常數小於7的低介電常數介電材料（例如，摻碳氧化物、SiCOH）等。在一些實施例中，透過各種步驟形成下隔離結構160，包括熱氧化或沉積製程（例如，物理氣相沉積、化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、濺鍍（sputtering）等）以及移除製程（例如，濕式蝕刻、乾式蝕刻、化學機械平坦化（chemical mechanical planarization, CMP）等）。
如第10圖的透視圖所示，在一些實施例中，於鰭片結構156的外表面之上形成披覆（cladding）半導體層161。在一些實施例中，披覆半導體層161包括半導體材料如鍺或矽鍺等。在一些實施例中，披覆半導體層161包括與第二半導體層154相同的材料。再者，在一些實施例中，可利用磊晶成長製程或沉積製程（例如，物理氣相沉積、化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、濺鍍等）形成披覆半導體層161。
如第11圖的透視圖所示，在一些實施例中，於鰭片結構156之間的下隔離結構160之上形成中間隔離結構132。介電襯層（liner）130可沿著披覆半導體層161與下隔離結構160的側壁形成於中間隔離結構132與下隔離結構160之間。接著，可於中間隔離結構132與介電襯層130的頂部上形成硬遮罩136。中間隔離結構132與介電襯層130提供鰭片結構156之間的電性絕緣，且硬遮罩136在之後的圖案化步驟時防止中間隔離結構132的耗損。
在一些實施例中，利用沉積（例如，物理氣相沉積、化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、濺鍍等）與移除（例如，蝕刻、化學機械平坦化等）製程形成介電襯層130、中間隔離結構132與硬遮罩136。中間隔離結構132可具有位於鰭片結構156之下的頂表面。在沒有繪示於第11圖的一些實施例中，硬遮罩136的平坦化製程也可從鰭片結構156之上移除披覆半導體層161。硬遮罩136可具有與鰭片結構156的頂表面共平面的頂表面。在一些實施例中，介電襯層130、中間隔離結構132與下隔離結構160可各包括介電常數小於7的低介電常數介電材料，例如氮氧化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、氮化矽或一些其他合適的低介電常數介電材料。為了選擇性移除製程，介電襯層130可包括與中間隔離結構132不同的材料。硬遮罩136可包括介電常數大於7的高介電常數介電材料，例如氧化鉿、氧化鋯、氧化鉿鋁、氧化鉿矽、氧化鋁或一些其他合適的高介電常數介電材料。
如第12圖的透視圖所示，在一些實施例中，從鰭片結構156的頂部選擇性移除硬遮罩136。移除製程可露出第一半導體層152與披覆半導體層161的頂表面。在一些實施例中，利用如乾式蝕刻製程及∕或濕式蝕刻製程選擇性地蝕刻硬遮罩136。
如第13圖的透視圖所示，在一些實施例中，沿著y方向於鰭片結構156之上形成在x方向彼此相互分隔的虛置閘極結構170。在一些實施例中，虛置閘極結構170可包括以所述順序層層堆疊的犧牲閘極介電層162、犧牲閘極電極層164、墊層166與遮罩層168。雖然第13圖中繪示出兩個虛置閘極結構170，但虛置閘極結構170的數量並非以此為限，且可為更多個或少於2個。在一些實施例中，犧牲閘極介電層162可包括介電材料如氮化物（例如，氮化矽、氮氧化矽）、碳化物（例如，碳化矽）、氧化矽（例如，氧化矽）或一些其他合適的材料。犧牲閘極電極層164可包括如多晶矽。墊層166與遮罩層168可包括熱氧化物、氮化物及∕或其他硬遮罩材料且利用光學微影製程所形成。
接著，沿著虛置閘極結構170的兩側側壁形成閘極間隔物134。例如，利用電漿增強化學氣相沉積、低壓化學氣相沉積或次大氣壓化學氣相沉積（sub-atmospheric CVD, SACVD）等順應地形成側壁間隔物的絕緣材料毯覆層以覆蓋虛置閘極結構170。毯覆層是以順應的方式所沉積以使其在虛置閘極結構170的如側壁的垂直表面、水平表面與頂部上具有實質上相等的厚度。在一些實施例中，毯覆層的絕緣材料可包括氮化矽基材料。接著利用非等向性（anisotropic）製程蝕刻毯覆層以於虛置閘極結構170的兩側側壁上形成閘極間隔物134。
如第14A圖的透視圖、在閘極區x方向的第14B圖剖面圖與閘極區y方向的第14C圖剖面圖、以及在源極區或汲極區y方向的第14D圖剖面圖所示，在一些實施例中，進行移除製程而從根據虛置閘極結構170的第一源極∕汲極區176與第二源極∕汲極區178移除鰭片結構156。因此，第一半導體層152與第二半導體層154沿著x方向縮短且可垂直地對準閘極間隔物134。作為範例，利用應變（strained）源極∕汲極蝕刻製程移除鰭片結構156的露出部分。可以各種方式進行應變源極∕汲極蝕刻製程。在一些實施例中，可以使用電漿源與反應氣體的乾式化學蝕刻進行應變源極∕汲極蝕刻製程。電漿源可以是感應耦合電漿（inductively coupled plasma, ICR）蝕刻、變壓器耦合電漿（transformer coupled plasma, TCP）蝕刻、電子迴旋加速器共振（electron cyclotron resonance, ECR）蝕刻或反應離子蝕刻（reactive ion etch, RIE）等，且反應氣體可以是氟基氣體、氯氣（Cl2 ）、溴化氫（HBr）、氧氣（O2 ）等或前述之組合。在一些其他的實施例中，可利用濕式化學蝕刻進行應變源極∕汲極蝕刻製程，濕式化學蝕刻如使用氨水過氧化氫混合物（ammonium peroxide mixture, APM）、氫氧化銨（NH4 OH）、四甲基氫氧化銨（tetramethylammonium hydroxide, TMAH）等或前述之組合。在更一些其他的實施例中，可利用乾式化學蝕刻與濕式化學蝕刻的組合進行應變源極∕汲極蝕刻製程。再者，在一些實施例中，在移除最底部的第一半導體層152之後，移除製程也可移除半導體基板層146在虛置閘極結構170之間的上部。半導體基板層146或最底部的第一半導體層152在第一源極∕汲極區176與第二源極∕汲極區178中沿著x方向可具有凹狀頂表面。頂表面於下隔離結構160之間可被凹蝕。
此外，移除製程也可包括等向性蝕刻劑以進一步移除第二半導體層154在閘極間隔物134及∕或虛置閘極結構170下的端部。因此，移除製程之後，第一半導體層152在x方向比第二半導體層154更寬。移除製程之後，第一半導體層152可形成作為電晶體裝置的通道結構。將能理解通道結構可呈現如第14B圖剖面圖及其他圖式所示的堆疊類長方形形狀，而在其他實施例中，通道結構可呈現其他形狀如圓形、八邊形、橢圓形或鑽石形等。
如第15A圖透視圖與第15B圖x方向剖面圖所示，在一些實施例中，內間隔物128形成於第二半導體層154在x方向具有最外部側壁的端部。內間隔物128的最外部側壁可實質上與第一半導體層152及∕或閘極間隔物134的外表面共平面。在一些實施例中，利用沉積製程（例如，物理氣相沉積、化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、濺鍍等）並接著進行選擇性移除製程（例如，蝕刻）而形成內間隔物128。例如，在一些實施例中，可先於虛置閘極結構170之上並沿著側壁形成連續層。接著，可進行垂直蝕刻製程移除連續層在垂直方向上沒有被閘極間隔物134覆蓋的部分以形成內間隔物128。再者，在一些實施例中，內間隔物128包括低介電常數介電材料（亦即，介電常數小於7）如氮氧化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、氮化矽或一些其他合適的材料。
如第16A圖透視圖、在第一源極∕汲極區x方向的第16B圖剖面圖以及在第一源極∕汲極區y方向的第16C圖剖面圖所示，在一些實施例中，第一犧牲源極∕汲極接觸件180形成於第一源極∕汲極區176下，且硬遮罩層182覆蓋第二源極∕汲極區178。在一些實施例中，先蝕刻第一半導體層152及∕或半導體基板層146位於第一源極∕汲極區176正下方的一部份而形成溝槽。接著，於溝槽中填充犧牲材料以形成第一犧牲源極∕汲極接觸件180。在一些實施例中，第一犧牲源極∕汲極接觸件180可包括鍺原子百分比大於0的SiGe材料。在一些實施例中，第一犧牲源極∕汲極接觸件180的鍺百分比在約10%至約50%之間的範圍內。在一些實施例中，第一犧牲源極∕汲極接觸件180包括與第二半導體材料154相同的材料。再者，在一些實施例中，可利用磊晶成長製程或沉積製程（例如，物理氣相沉積、化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、濺鍍等）形成第一犧牲源極∕汲極接觸件180。透過形成溝槽以及在溝槽中形成第一犧牲源極∕汲極接觸件180，可於後續取代第一犧牲源極∕汲極接觸件180而自對準形成源極∕汲極接觸件，以消除接觸落點的疊對位移。
如第17A圖透視圖、在第一源極∕汲極區x方向的第17B圖剖面圖、在第一源極∕汲極區y方向的第17C圖剖面圖、以及在第二源極∕汲極區y方向的第17D圖剖面圖所示，在一些實施例中，第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108形成於虛置閘極結構170的兩側（參照第17B圖）。在一些實施例中，第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108可直接接觸第一半導體層152的端部。第一源極∕汲極磊晶結構106可形成於第一犧牲源極∕汲極接觸件180上（參照第17C圖）。第二源極∕汲極磊晶結構108可形成於最底部的第一半導體層152或半導體基板層146上（參照第17D圖）。第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108可分別為半導體電晶體裝置的源極與汲極。在一些實施例中，第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108包括半導體材料。例如，第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108可包括矽、鍺或矽鍺。在一些實施例中，利用磊晶成長製程形成第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108。第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108可以是六角形或類鑽石形狀。可形成氣隙192圍繞第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108的下部。
如第18A圖透視圖、在第一源極∕汲極區x方向的第18B圖剖面圖、在第一源極∕汲極區y方向的第18C圖剖面圖、以及在第二源極∕汲極區y方向的第18D圖剖面圖所示，在一些實施例中，上隔離結構220形成於先前形成的結構之上且覆蓋第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108。接著，進行平坦化製程降低閘極間隔物134且在相同水平平面上露出犧牲閘極介電層162與犧牲閘極電極層164。雖然沒有繪示於圖式中，但在形成上隔離結構220之前，可順應地形成蝕刻停止襯層使其內襯於先前形成的結構。蝕刻停止襯層可具有伸張應力（tensile stress）且可由Si3 N4 所形成。在一些其他的實施例中，蝕刻停止襯層包括如氮氧化物的材料。在一些其他的實施例中，蝕刻停止襯層可具有包括複數層的複合結構，例如氮化矽層位於氧化矽層上方。可利用電漿增強化學氣相沉積形成蝕刻停止襯層，然而，也可使用其他合適的方法如低壓化學氣相沉積或原子層沉積等。可利用化學氣相沉積、高密度電漿化學氣相沉積、旋轉塗佈（spin-on）、濺鍍或其他合適的方法形成上隔離結構220。在一些實施例中，上隔離結構220包括氧化矽。在一些其他的實施例中，上隔離結構220可包括氮氧化矽、氮化矽、包括Si、O、C及∕或H的化合物（例如，氧化矽、SiCOH與SiOC）、低 介電常數材料或有機材料（例如，聚合物）。平坦化操作步驟可包括化學機械研磨製程。
如第19A圖的透視圖、在閘極區x方向的第19B圖剖面圖與閘極區y方向的第19C圖剖面圖所示，在一些實施例中，進行取代閘極製程以形成閘極結構104。移除犧牲閘極介電層162與犧牲閘極電極層164而露出第一半導體層152與第二半導體層152。上隔離結構220在移除移除犧牲閘極介電層162與犧牲閘極電極層164時保護第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108。可利用電漿乾式蝕刻及∕或濕式蝕刻移除犧牲閘極電極層164。當犧牲閘極電極層164為多晶矽且上隔離結構220為氧化矽時，可使用如四甲基氫氧化銨的濕式蝕刻劑來選擇性地移除犧牲閘極電極層164。接著也移除犧牲閘極介電層162。如此一來，露出第一半導體層152與第二半導體層154。
接著，使用以與蝕刻第一半導體層152相比更快的蝕刻速率選擇性地蝕刻第二半導體層154與披覆半導體層161的蝕刻劑，來移除或蝕刻第二半導體層154與披覆半導體層161（參照第14C圖）。內間隔物128保護第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108不受用於蝕刻第二半導體層154與披覆半導體層161的蝕刻劑影響，因為內間隔物128是由對第二半導體層154與披覆半導體層161材料具有蝕刻選擇性的材料所形成。
接著，閘極結構104形成及∕或填充於閘極間隔物134與內間隔物128之間。亦即，閘極結構104包圍（或圍繞或包覆）第一半導體層152，其中第一半導體層152視為半導體電晶體裝置的通道。閘極間隔物134設置於閘極結構104的兩側。閘極結構104包括閘極介電層232與閘極電極230。閘極電極230包括一或多層功函數金屬層與填充層。可順應地形成閘極介電層232。亦即，閘極介電層232接觸下隔離結構160與第一半導體層152。在一些實施例中，閘極介電層232包括高介電常數材料（介電常數大於7）如氧化鉿（HfO2 ）、氧化鋯（ZrO2 ）、氧化鑭（La2 O3 ）、氧化鉿鋁（HfAlO2 ）、氧化鉿矽（HfSiO2 ）、氧化鋁（Al2 O3 ）或其他合適的材料。在一些實施例中，可進行原子層沉積製程或其他合適的製程來形成閘極介電層232。
在一些實施例中，閘極電極230的功函數金屬層形成於閘極介電層232上，且功函數金屬層圍繞第一半導體層152。功函數金屬層可包括材料如氮化鈦（TiN）、氮化鉭（TaN）、鈦鋁矽（TiAlSi）、氮化鈦矽（TiSiN）、鈦鋁（TiAl）、鉭鋁（TaAl）或其他合適的材料。在一些實施例中，可進行原子層沉積製程或其他合適的製程來形成功函數金屬層。閘極電極230的填充金屬填充閘極間隔物134之間與內間隔物128之間的剩餘空間。亦即，功函數金屬層接觸並位於閘極介電層232與填充金屬之間。填充金屬可包括如鎢或鋁的材料。在沉積閘極介電層232與閘極電極230之後，可接著進行如化學機械研磨製程的平坦化製程移除閘極介電層232與閘極電極230過多的部分以形成閘極結構104。
在一些實施例中，形成閘極結構104以圍繞第一半導體層152露出的表面與半導體基板層146露出的表面之前，可視需要地形成界面層（未繪示）。在各種實施例中，界面層可包括介電材料如氧化矽（SiO2 ）或氮氧化矽（SiON），且可利用化學氧化、熱氧化、原子層沉積、化學氣相沉積及∕或其他合適的方法形成界面層。
如第20圖的透視圖所示，在一些實施例中，前側內連線結構114形成於閘極結構104、第一源極∕汲極磊晶結構106與第二源極∕汲極磊晶結構108之上。前側內連線結構114可包括設置於前側層間介電層112之中且被前側層間介電層112圍繞的複數層前側金屬層116。前側內連線結構114電性連接半導體電晶體裝置的各個部件或結構（例如，閘極接觸件110及∕或其他接觸件）。前側金屬層116包括如導孔或接觸件的垂直內連線以及如金屬線的水平內連線。各種內連線部件可採用各種導電材料如銅、鎢與矽化物。在一些範例中，可使用鑲嵌（damascene）製程形成銅多層內連線結構。接著，於前側內連線結構114之上形成承載基板（carrier substrate）240。例如，將承載基板240接合至前側內連線結構114。在一些實施例中，承載基板240為藍寶石。在一些其他的實施例中，承載基板240為矽、熱塑性聚合物、氧化物、碳化物或其他合適的材料。
如第21圖的透視圖所示，在一些實施例中，上下翻轉工件並將其薄化，以從背側露出第一犧牲源極∕汲極接觸件180與半導體基板層146。移除塊狀基板142、絕緣基板層144與下隔離結構160的至少上部。塊狀基板142與下隔離結構160可在複數道製程操作步驟中被移除，例如，先移除塊狀基板142再接著移除下隔離結構160。在一些實施例中，移除製程包括使用如化學機械研磨、氫氟酸-硝酸-醋酸（hydrofluoric acid-nitric acid-acetic acid, HNA）混合物及∕或四甲基氫氧化銨蝕刻來移除塊狀基板142與下隔離結構160。
如第22A圖透視圖、在第一源極∕汲極區x方向的第22B圖剖面圖、以及在第一源極∕汲極區y方向的第22C圖剖面圖所示，在一些實施例中，移除第一犧牲源極∕汲極接觸件180且從第一源極∕汲極磊晶結構106的背側凹蝕下方的第一源極∕汲極磊晶結構106，以形成凹蝕進第一源極∕汲極磊晶結構106上部的背側源極∕汲極接觸溝槽234。可利用以與蝕刻周圍介電材料相比更快的蝕刻速率選擇性地蝕刻第一源極∕汲極磊晶結構106的蝕刻劑，來凹蝕或蝕刻第一源極∕汲極磊晶結構106。
如第23A圖透視圖、在第一源極∕汲極區x方向的第23B圖剖面圖、以及在第一源極∕汲極區y方向的第23C圖剖面圖所示，在一些實施例中，於背側源極∕汲極接觸溝槽234中填充第二犧牲源極∕汲極接觸件236。在一些實施例中，於背側源極∕汲極接觸溝槽234中填充如氮化矽的介電材料並進行平坦化製程移除過多的部分以形成第二犧牲源極∕汲極接觸件236，第二犧牲源極∕汲極接觸件236可與下隔離結構160及半導體基板層146共平面。
如第24A圖透視圖、在第二源極∕汲極區x方向的第24B圖剖面圖、以及在第二源極∕汲極區y方向的第24C圖剖面圖所示，在一些實施例中，移除半導體基板層146以於第二源極∕汲極磊晶結構108與閘極結構104之上形成介電蓋溝槽238。可露出下方的第二源極∕汲極磊晶結構108與閘極結構104。在一些實施例中，從背側將第二源極∕汲極磊晶結構108凹蝕至第二源極∕汲極磊晶結構108的上部之中。
如第25A圖透視圖、在閘極區x方向的第25B圖剖面圖、在閘極區y方向的第25C圖剖面圖、以及在第二源極∕汲極區y方向的第25D圖剖面圖所示，在一些實施例中，背側介電蓋126形成於背側蓋溝槽238（參照第24A圖）中。背側介電蓋126可形成於第二源極∕汲極磊晶結構108與閘極結構104正上方。可利用如沉積製程於背側蓋溝槽238中沉積介電材料，且接著利用化學機械研磨製程移除背側蓋溝槽238之外過多的介電材料以形成背側介電蓋126。在一些實施例中，背側介電蓋126包括與第二犧牲源極∕汲極接觸件236不同的介電材料，例如氧化矽。其他適合的材料可包括SiO2 、SiN、SiCN、SiOCN、Al2 O3 、AlON、ZrO2 、HfO2 等或前述之組合。在一些實施例中，背側介電蓋126在背側介電蓋126與第二源極∕汲極磊晶結構108之間的界面具有凸狀頂表面126s。
如第26A圖透視圖、在第一源極∕汲極區x方向的第26B圖剖面圖以及在第一源極∕汲極區y方向的第26C圖剖面圖所示，在一些實施例中，於至少一部分的背側源極∕汲極接觸溝槽234中形成背側源極∕汲極接觸件120以取代第二犧牲源極∕汲極接觸件236（參照第23A圖）。在一些實施例中，第二犧牲源極∕汲極接觸件236的外部於背側源極∕汲極接觸溝槽234中保留作為隔離背側源極∕汲極接觸件120與背側介電蓋126的介電側壁間隔物118。背側源極∕汲極接觸件120達到第一源極∕汲極磊晶結構106凹蝕的底表面106b。可在如第22A至22C圖所示的先前步驟時凹蝕底表面106b。在一些實施例中，形成背側源極∕汲極接觸件120之前，背側金屬合金層可形成於第一源極∕汲極磊晶結構106上。背側金屬合金層可以是利用自對準矽化物製程形成的矽化物層。背側金屬合金層可包括選自於下列的材料：鈦矽化物、鈷矽化物、鎳矽化物、鉑矽化物、鎳鉑矽化物、鉺矽化物、鈀矽化物、前述之組合或其他合適的材料。在一些實施例中，背側金屬合金層可包括鍺。在一些實施例中，背側源極∕汲極接觸件120可由金屬如W、Co、Ru、Al、Cu或其他合適的材料所形成。沉積源極∕汲極接觸件120之後，可接著進行如化學機械平坦化製程的平坦化製程。在一些實施例中，形成源極∕汲極接觸件120之前，可於背側源極∕汲極接觸溝槽234中形成阻障層。阻障層可由TiN、TaN或前述之組合所形成。
如第27A圖透視圖與第27B圖的x方向剖面圖所示，在一些實施例中，形成背側電源軌122與背側內連線結構124電性耦接至源極∕汲極接觸件120。
第28圖繪示出因空氣間隔物結構與高介電常數介電間隔物結構而具有多個電晶體裝置及高裝置密度的積體電路形成方法2800一些實施例的流程圖。
雖然第28圖於下文係繪示及描述為一系列的步驟或事件，但將能理解這些步驟或事件的順序並非以限制的方式而作出詮釋。例如，一些步驟可以不同順序進行及∕或與本文所述步驟或事件之外的步驟或事件同時進行。此外，對於實施本文的一或多種態樣或實施例，並非所有所述步驟皆為必要。再者，本文所描繪的一或多個步驟可在一個或多個單獨的步驟和/或階段中進行。
在步驟2802，於基板上形成複數個堆疊第一半導體層與第二半導體層的鰭片結構。隔離結構形成於鰭片結構之間（參照如第7至12圖）。第7至12圖繪示出對應步驟2802的一些實施例的透視圖。
在步驟2804，於鰭片結構上方形成複數個虛置閘極結構。第13圖繪示出對應步驟2804的一些實施例的透視圖。
在步驟2806，從虛置閘極結構兩側蝕刻且移除鰭片結構沒有被虛置閘極結構覆蓋的部分。從第一半導體層水平地凹蝕第二半導體層。第14A至14C圖繪示出對應步驟2806的一些實施例的各種示意圖。
在步驟2808，於第二半導體層的兩端形成內間隔物。第15A與15B圖繪示出對應步驟2808的一些實施例的各種示意圖。
在步驟2810，於基板中形成第一虛置背側接觸件。第16A至16C圖繪示出對應步驟2810的一些實施例的各種示意圖。
在步驟2812，於凹蝕的鰭片結構兩側形成第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構。第17A至17D圖繪示出對應步驟2812的一些實施例的各種示意圖。
在步驟2814，以金屬閘極結構取代第二半導體層。第18A-18D圖與第19A-19C圖繪示出對應步驟2814的一些實施例的各種示意圖。
在步驟2816，形成閘極接觸件與前側內連線結構。第20圖繪示出對應步驟2816的一些實施例的透視圖。
在步驟2818，凹蝕第一源極∕汲極磊晶結構的底表面。第21與22A-22C圖繪示出對應步驟2818的一些實施例的各種示意圖。
在步驟2820，形成第二虛置背側接觸件使其達到第一源極∕汲極磊晶結構凹蝕的底表面。第23A至23C圖繪示出對應步驟2820的一些實施例的各種示意圖。
在步驟2822，凹蝕第二源極∕汲極磊晶結構的底表面。第24A至24D圖繪示出對應步驟2822的一些實施例的各種示意圖。
在步驟2824，於第二源極∕汲極磊晶結構的底表面上形成背側介電蓋。第25A至25D圖繪示出對應步驟2824的一些實施例的各種示意圖。
在步驟2826，形成背側源極∕汲極接觸件使其達到第一源極∕汲極磊晶結構的底表面。第26A至26C圖繪示出對應步驟2826的一些實施例的各種示意圖。
在步驟2828，形成背側電源軌與背側內連線結構。第27A與27B圖繪示出對應步驟2828的一些實施例的各種示意圖。
因此，在一些實施例中，本發明實施例是關於一種半導體電晶體裝置。半導體電晶體裝置包括通道結構與包繞通道結構的閘極結構。半導體電晶體裝置更包括設置於通道結構兩端的第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構，以及設置於第一源極∕汲極磊晶結構下的背側源極∕汲極接觸件。第一源極∕汲極磊晶結構具有接觸背側源極∕汲極接觸件的凹狀底表面。半導體電晶體裝置更包括設置於閘極結構上的閘極接觸件。在一些實施例中，半導體電晶體裝置更包括背側介電蓋，背側介電蓋設置於第二源極∕汲極磊晶結構下並與第二源極∕汲極磊晶結構直接接觸。在一些實施例中，第二源極∕汲極磊晶結構具有接觸背側介電蓋的凹狀底表面。在一些實施例中，背側介電蓋於閘極結構下延伸。在一些實施例中，背側介電蓋與閘極結構直接接觸。在一些實施例中，半導體電晶體裝置更包括中間隔離結構，中間隔離結構圍繞閘極結構、第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構。在一些實施例中，半導體電晶體裝置更包括下隔離結構，下隔離結構設置於中間隔離結構下並圍繞背側介電蓋。在一些實施例中，半導體電晶體裝置更包括介電側壁間隔物，介電側壁間隔物沿著背側源極∕汲極接觸件的側壁設置。在一些實施例中，半導體電晶體裝置更包括內間隔物，內間隔物將閘極結構與第一源極∕汲極磊晶結構及第二源極∕汲極磊晶結構隔離。在一些實施例中，通道結構包括半導體奈米線堆疊。
在其他實施例中，本發明實施例是關於一種半導體電晶體裝置。半導體電晶體裝置包括通道結構與包繞通道結構的閘極結構。半導體電晶體裝置更包括設置於通道結構兩端的第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構，以及設置於第一源極∕汲極磊晶結構下並與第一源極∕汲極磊晶結構接觸的背側源極∕汲極接觸件。半導體電晶體裝置更包括設置於閘極結構上的閘極接觸件，以及設置於第二源極∕汲極磊晶結構下並與第二源極∕汲極磊晶結構及閘極結構接觸的背側介電蓋。在一些實施例中，第二源極∕汲極磊晶結構具有比閘極結構的底表面更高的底表面。在一些實施例中，背側源極∕汲極接觸件具有比閘極結構的底表面更高的頂表面。在一些實施例中，半導體電晶體裝置更包括介電側壁間隔物，介電側壁間隔物設置於背側源極∕汲極接觸件與背側介電蓋之間。在一些實施例中，閘極結構包括閘極電極以及閘極電極與通道結構之間的閘極介電質。在一些實施例中，通道結構包括半導體奈米線堆疊。在一些實施例中，半導體電晶體裝置更包括內間隔物，內間隔物將閘極結構與第一源極∕汲極磊晶結構及第二源極∕汲極磊晶結構隔離。在一些實施例中，背側介電蓋包括SiO2 、SiN、SiCN、SiOCN、Al2 O3 、AlON、ZrO2 、HfO2 或前述之組合。
在更一些其他的實施例中，本發明實施例是關於半導體電晶體裝置的製造方法。半導體電晶體裝置的製造方法包括交替堆疊第一半導體層與第二半導體層而於基板之上形成鰭片結構，以及於鰭片結構之上形成虛置閘極結構。半導體電晶體裝置的製造方法更包括移除鰭片結構沒有被虛置閘極結構覆蓋的一部分，以及於第一半導體層剩餘部分的兩側形成內間隔物。半導體電晶體裝置的製造方法更包括於鰭片結構的兩端形成第一源極∕汲極磊晶結構與第二源極∕汲極磊晶結構。半導體電晶體裝置的製造方法更包括以金屬閘極結構取代虛置閘極結構與第一半導體層。半導體電晶體裝置的製造方法更包括移除基板且形成背側蓋溝槽，以露出金屬閘極結構的底表面與第二源極∕汲極磊晶結構的底表面。第二源極∕汲極磊晶結構的底表面被凹蝕。半導體電晶體裝置的製造方法更包括於背側蓋溝槽中形成背側介電蓋，以及於第一源極∕汲極磊晶結構下形成與第一源極∕汲極磊晶結構接觸的背側源極∕汲極接觸件。在一些實施例中，形成背側源極∕汲極接觸件的步驟包括：在形成內間隔物的步驟之後，形成背側接觸溝槽；利用犧牲半導體材料填充背側接觸溝槽；在形成背側蓋溝槽的步驟之前，移除犧牲半導體材料並以側壁間隔物介電材料取代；移除至少一部份的側壁間隔物介電材料；以及在形成背側介電蓋的步驟之後，以背側源極∕汲極接觸件取代。
以上概述數個實施例之特徵，以使本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且可在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。
100,200,300,400,400a,400b:半導體電晶體裝置 102:通道結構 104:閘極結構 104b,106b,108b:底表面 106:第一源極/汲極磊晶結構 108:第二源極/汲極磊晶結構 110:閘極接觸件 112:前側層間介電層 114:前側內連線結構 116:前側金屬層 118:介電側壁間隔物 120:背側源極/汲極接觸件 122:背側電源軌 124:背側內連線結構 126:背側介電蓋 126s:頂表面 128:內間隔物 130:介電襯層 132:中間隔離結構 134:閘極間隔物 136:硬遮罩 140:基板 142:塊狀基板 144:絕緣基板 146:半導體基板層 150:堆疊結構 152:第一半導體層 154:第二半導體層 156:鰭片結構 157,168:遮罩層 158:溝槽 160:下隔離結構 161:披覆半導體層 162:犧牲閘極介電層 164:犧牲閘極電極層 166:墊層 170:虛置閘極結構 176:第一源極/汲極區 178:第二源極/汲極區 180:第一犧牲源極∕汲極接觸件 182:硬遮罩層 192:氣隙 220:上隔離結構 230:閘極電極 232:閘極介電層 234:背側源極/汲極接觸溝槽 236: 背側源極/汲極接觸件 238:介電蓋溝槽 240:承載基板 2800:方法 2802,2804,2806,2808,2810,2812,2814,2816,2818,2820,2822,2824,2826,2828:步驟 A-A’,B-B’,C-C’:線段
以下實施方式與所附圖式一併閱讀較容易理解本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製且僅用以說明例示。事實上，可任意地放大或縮小各種部件的尺寸，以清楚地表現出本發明實施例的特徵。 第1圖繪示出具有背側電源軌的半導體電晶體裝置一些實施例的剖面圖。 第2圖繪示出具有背側電源軌的半導體電晶體裝置一些額外實施例的剖面圖。 第3圖繪示出具有背側電源軌的半導體電晶體裝置一些額外實施例的剖面圖。 第4圖繪示出具有背側電源軌的半導體電晶體裝置一些額外實施例的剖面圖。 第5圖繪示出具有背側電源軌的半導體電晶體裝置一些實施例的透視圖。 第6A圖為沿著第5圖線段A-A’擷取的半導體電晶體裝置一些實施例的剖面圖。 第6B圖為沿著第5圖線段B-B’擷取的半導體電晶體裝置一些實施例的剖面圖。 第6C圖為沿著第5圖線段C-C’擷取的半導體電晶體裝置一些實施例的剖面圖。 第7至13圖、第14A至14D圖、第15A與15B圖、第16A至16C圖、第17A至17D圖、第18A至18D圖、第19A至19C圖、第20與21圖、第22A至22C圖、第23A至23C圖、第24A至24D圖、第25A至25D圖、第26A至26C圖以及第27A與27B圖繪示出具有背側電源軌的半導體電晶體裝置在各種階段的形成方法一些實施例的各種示意圖。 第28圖繪示出對應至第7至13圖、第14A至14D圖、第15A與15B圖、第16A至16C圖、第17A至17D圖、第18A至18D圖、第19A至19C圖、第20與21圖、第22A至22C圖、第23A至23C圖、第24A至24D圖、第25A至25D圖、第26A至26C圖以及第27A與27B圖的方法一些實施例的流程圖。
100:半導體電晶體裝置
102:通道結構
104:閘極結構
104b,106b:底表面
106:第一源極/汲極磊晶結構
108:第二源極/汲極磊晶結構
110:閘極接觸件
112:前側層間介電層
114:前側內連線結構
116:前側金屬層
118:介電側壁間隔物
120:背側源極/汲極接觸件
122:背側電源軌
124:背側內連線結構
126:背側介電蓋
128:內間隔物
134:閘極間隔物
220:上隔離結構

Claims (20)

  1. 一種半導體電晶體裝置，包括： 一通道結構； 一閘極結構，包繞該通道結構； 一第一源極∕汲極磊晶結構與一第二源極∕汲極磊晶結構，設置於該通道結構的兩端； 一閘極接觸件，設置於該閘極結構上；以及 一背側源極∕汲極接觸件，設置於該第一源極∕汲極磊晶結構下； 其中該第一源極∕汲極磊晶結構具有接觸該背側源極∕汲極接觸件的一凹狀（concave）底表面。
  2. 如請求項1所述之半導體電晶體裝置，更包括一背側介電蓋，該背側介電蓋設置於該第二源極∕汲極磊晶結構下並與該第二源極∕汲極磊晶結構直接接觸。
  3. 如請求項2所述之半導體電晶體裝置，其中該第二源極∕汲極磊晶結構具有接觸該背側介電蓋的一凹狀底表面。
  4. 如請求項2所述之半導體電晶體裝置，其中該背側介電蓋於該閘極結構下延伸。
  5. 如請求項4所述之半導體電晶體裝置，其中該背側介電蓋與該閘極結構直接接觸。
  6. 如請求項2所述之半導體電晶體裝置，更包括一中間隔離結構，該中間隔離結構圍繞該閘極結構、該第一源極∕汲極磊晶結構與該第二源極∕汲極磊晶結構。
  7. 如請求項6所述之半導體電晶體裝置，更包括一下隔離結構，該下隔離結構設置於該中間隔離結構下並圍繞該背側介電蓋。
  8. 如請求項1所述之半導體電晶體裝置，更包括一介電側壁間隔物，該介電側壁間隔物沿著該背側源極∕汲極接觸件的側壁設置。
  9. 如請求項1所述之半導體電晶體裝置，更包括一內間隔物，該內間隔物將該閘極結構與該第一源極∕汲極磊晶結構及該第二源極∕汲極磊晶結構隔離。
  10. 如請求項1所述之半導體電晶體裝置，其中該通道結構包括一半導體奈米線堆疊。
  11. 一種半導體電晶體裝置，包括： 一通道結構； 一閘極結構，包繞該通道結構； 一第一源極∕汲極磊晶結構與一第二源極∕汲極磊晶結構，設置於該通道結構的兩端； 一閘極接觸件，設置於該閘極結構上； 一背側源極∕汲極接觸件，設置於該第一源極∕汲極磊晶結構下並與該第一源極∕汲極磊晶結構接觸；以及 一背側介電蓋，設置於該第二源極∕汲極磊晶結構下並與該第二源極∕汲極磊晶結構及該閘極結構接觸。
  12. 如請求項11所述之半導體電晶體裝置，其中該第二源極∕汲極磊晶結構具有比該閘極結構的一底表面更高的一底表面。
  13. 如請求項11所述之半導體電晶體裝置，其中該背側源極∕汲極接觸件具有比該閘極結構的一底表面更高的一頂表面。
  14. 如請求項11所述之半導體電晶體裝置，更包括一介電側壁間隔物，該介電側壁間隔物設置於該背側源極∕汲極接觸件與該背側介電蓋之間。
  15. 如請求項11所述之半導體電晶體裝置，其中該閘極結構包括： 一閘極電極；以及 一閘極介電質，位於該閘極電極與該通道結構之間。
  16. 如請求項11所述之半導體電晶體裝置，其中該通道結構包括一半導體奈米線堆疊。
  17. 如請求項11所述之半導體電晶體裝置，更包括一內間隔物，該內間隔物將該閘極結構與該第一源極∕汲極磊晶結構及該第二源極∕汲極磊晶結構隔離。
  18. 如請求項11所述之半導體電晶體裝置，其中該背側介電蓋包括SiO2 、SiN、SiCN、SiOCN、Al2 O3 、AlON、ZrO2 、HfO2 或前述之組合。
  19. 一種半導體電晶體裝置的形成方法，包括： 交替堆疊多個第一半導體層與多個第二半導體層而於一基板之上形成一鰭片結構； 於該鰭片結構之上形成一虛置（dummy）閘極結構； 移除該鰭片結構沒有被該虛置閘極結構覆蓋的一部分； 於該些第一半導體層剩餘部分的兩側形成多個內間隔物； 於該鰭片結構的兩端形成一第一源極∕汲極磊晶結構與一第二源極∕汲極磊晶結構； 以一金屬閘極結構取代該虛置閘極結構與該些第一半導體層； 移除該基板且形成一背側蓋溝槽，以露出該金屬閘極結構的一底表面與該第二源極∕汲極磊晶結構的一底表面，其中該第二源極∕汲極磊晶結構的該底表面被凹蝕； 於該背側蓋溝槽中形成一背側介電蓋；以及 於該第一源極∕汲極磊晶結構下形成與該第一源極∕汲極磊晶結構接觸的一背側源極∕汲極接觸件。
  20. 如請求項19所述之半導體電晶體裝置的形成方法，其中形成該背側源極∕汲極接觸件的步驟包括： 在形成該些內間隔物的步驟之後，形成一背側接觸溝槽； 利用一犧牲半導體材料填充該背側接觸溝槽； 在形成該背側蓋溝槽的步驟之前，移除該犧牲半導體材料並以一側壁間隔物介電材料取代； 移除至少一部份的該側壁間隔物介電材料；以及 在形成該背側介電蓋的步驟之後，以該背側源極∕汲極接觸件取代。
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