TW202135270A - 高效率微裝置 - Google Patents
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Abstract
本發明係關於一種固態微裝置結構,其包括:形成於基板上之該微裝置;p及n摻雜層;至少該兩個摻雜層之間的活性層,同時墊經耦合至各摻雜層,其中該等摻雜層之該至少一者小於該活性層且處於該活性層之周長內;及該兩個耦合墊位於其中該摻雜層較小之相同側。
Description
本發明係關於垂直固態裝置、垂直固態裝置之橫向傳導操控及其製造方法。本發明亦係關於微裝置積體陣列之製作。微裝置陣列由裝置基板或系統基板上之接點陣列界定。
將微光電裝置整合至系統基板中可提供高效能及高功能系統。為改良成本且創建較高像素密度裝置,應減小光電裝置之大小。光電裝置之實例係感測器及發光裝置,諸如(例如)發光二極體(LED)。然而,當減小此等裝置之大小,裝置效能可開始受影響。針對效能降低之一些原因包含(但不限於)歸因於缺陷之較高洩漏電流、介面處電荷擁擠、不平衡電荷及無用復合之諸如奧格復合及非輻射復合。發光二極體(LED)及LED陣列可分類為垂直固態裝置。仍需要改良垂直固態裝置。
本發明之目的係提供一種偏壓半導體裝置之壁以鈍化缺陷及/或重新導向電流或平衡該裝置中之電荷之方法。
本發明亦係關於一種固態微裝置結構,其包括:形成於基板上之微裝置;p及n摻雜層;至少該兩個摻雜層之間的活性層,同時墊經耦合至各摻雜層,其中該摻雜層之該至少一者小於該活性層且處於該活性層之周長內;及該兩個耦合墊位於其中該摻雜層較小之相同側。另外,其中該n摻雜層經調變使朝向該裝置邊緣之導電性較低。
除非另有界定,否則本文中所使用之所有科技術語具有相同於由本發明所屬領域之一般技術者通常理解之含義的含義。如本說明書及申請專利範圍中所使用,單數形式「一」及「該」包含複數個指涉物,除非內文另有清楚指示。如本文中所使用之術語「包括」將被理解為意謂以下清單係非詳盡的且可或可不包含任何其他額外適合項目,例如適當的一或多個進一步特徵、組件及/或元件。術語「裝置」及「微裝置」及「光電裝置」可互換用於本文中。熟習技術者將明白本文所描述之實施例獨立於裝置大小。術語「施體基板」及「時間基板」可互換用於本文中。然而,熟習技術者明白本文中所描述之實施例獨立於基板。術語「系統基板」及「接收器基板」可互換用於本文中。然而,熟習技術者明白本文所描述之實施例獨立於基板類型。
發光二極體(LED)及LED陣列可分類為垂直固態裝置。微裝置可為感測器、發光二極體(LED)或生長、沈積或單片製作於基板上之任何其他固體裝置。基板可為裝置層之同質基板或將裝置層或固態裝置轉移至其中之接收器基板。
系統基板可為任何基板且可為剛性或柔性的。系統基板可由玻璃、矽、塑膠或任何其他常用材料製成。系統基板亦可具有有源電子組件,諸如(但不限於)電晶體、電阻器、電容器或通常用於系統基板中之任何其他電子組件。在一些情況中,系統基板可為具有電信號列及行之基板。在一實例中,裝置基板可為具有其之頂部上單片生長之LED層之藍寶石基板且系統基板可為具有得到微LED裝置之電路系統之底板。作為垂直裝置之部分,金屬絕緣體半導體(MIS)結構可由金屬層、絕緣材料層及半導體材料層形成。
各種轉移及接合方法可用於將裝置層轉移及接合至系統基板。在一實例中,熱及壓力可用於將裝置層接合至系統基板。在垂直固態裝置中,垂直方向上之電流主要界定裝置之功能。由於發光二極體(LED)可分類為垂直固態裝置,因此所提出之製作方法可用於限制此等裝置之橫向電流。
將LED圖案化至微大小裝置中以創建用於顯示應用之LED陣列時會出現包含資料利用率、有限PPI及缺陷產生之若干問題。在一實例中,在垂直固態裝置中,垂直方向上之電流主要界定裝置之功能。
本發明係關於用於垂直固態裝置(尤其是光電裝置)之橫向傳導操控之方法。更明確言之,本發明係關於微或奈米光電裝置,其中裝置之效能受大小減小影響。亦描述一種在不隔離活性層之情況下由修改橫向傳導創建垂直裝置陣列之方法。使用垂直導電工程之LED陣列能够在水平方向上傳輸電流且經控制至像素區域,因此無需圖案化LED。
在圖1中所呈現之實施例中,微裝置100形成於基板102上。此程序可藉由沈積或轉移或其他形式完成。微裝置100與基板102之間可存在緩衝層/黏合層104。微裝置在p摻雜層108與n摻雜層110之間具有活性層106 (多量子阱、阻擋層等等)。接觸層112及114形成於摻雜層108及110之表面上。接點112及114可為歐姆層及墊/接合層之組合。在此結構中,n摻雜層110經調變使朝向裝置邊緣之導電性較低。在一情況中,n摻雜層110小於活性層106表面 (處於其內部)且處於活性層之周長內。阻擋層亦可經蝕刻回至與摻雜層110相同之大小。鈍化層可用於形成於n摻雜層之表面/側壁及活性層之暴露表面上。在一特定情況中,鈍化層可為金屬絕緣體半導體(MIS)結構之形式。在另一實施例中,摻雜層之至少一者小於活性層且兩個墊位於其中摻雜層較小之相同側。
圖2呈現形成於基板202上之微裝置200。此處,微裝置200與基板202之間可存在緩衝層/黏合層204。微裝置在p摻雜層208與n摻雜層210之間具有活性層206 (多量子阱、阻擋層等等)。接觸層212及214形成於摻雜層208及210之表面上。接點212及214可為歐姆層及墊/接合層之組合。在此結構中,絕緣體層216及金屬層218形成MIS裝置。MIS結構可圍繞n摻雜層之側壁或表面。其可覆蓋半導體(MIS)結構。MIS亦可覆蓋諸如活性層之其他層。可使用負電壓偏壓MIS以減少通過n側壁之電流。在一實施例中,使用小於MIS之臨限值電壓之電壓來偏壓MIS以減少洩漏電流。圖2中所呈現之MIS結構可應用於本申請案中之其他裝置及實施例。
圖3A呈現形成於基板302上之微裝置300。此處,微裝置300與基板302之間可存在緩衝層/黏合層304。微裝置在p與n摻雜層308與310之間具有活性層306 (多量子阱、阻擋層等等)。接觸層312及314形成於摻雜層308及310之表面上。接點312及314可為歐姆層及墊/接合層之組合。在此結構中,摻雜層308及310之一者(例如n層)小於活性層306。此處,VIA將接點自裝置之一側帶至另一側。VIA被介電層332及耦合至摻雜層310之導電層330鈍化(或假使存在接觸層314,則導電層330耦合至接觸層314)。在一情況中,其中導電層330耦合至摻雜層310,其可含有歐姆層以創建與摻雜層之較佳連接。此處,導電層330與摻雜層310之間將不存在鈍化。
若由頂側(對應於摻雜層310之側)形成VIA,或由底側(對應於摻雜層308之側)形成VIA,則在自VIA區域移除摻雜層之後,在底側之VIA外部仍可存在一些導電層330。墊336經形成以提供接入至導電層330。墊336藉由介電層334與下層分離。
圖3B展示微裝置300自底面之視圖。此處,墊312及336可用於將微裝置連接或接合至系統基板。分離墊336與下層306之介電層334可延伸於表面之另一部分上。墊312可小於或大於摻雜層308。
圖4A呈現形成於基板402上之微裝置400。此處,微裝置400與基板402之間可存在緩衝層/黏合層404。微裝置在p及n摻雜層408-A、408-B、408-C及410之間具有活性層406 (多量子阱、阻擋層等等)。接觸層412及414形成於摻雜層408-B及410之表面上。接點412及414可為歐姆層及墊/接合層之組合。在此結構中,摻雜層408-B及410之一者(例如n層)小於活性層406。摻雜層可經圖案化成若干較小區域且區域之一者用於透過在其頂部上形成墊412來連接至裝置。其他區域可作為其他部分之載台。此處,VIA將接點自裝置之側帶至另一側。VIA被介電層432及耦合至摻雜層410之導電層430鈍化(或假使存在接觸層414,則導電層430耦合至接觸層414)。在一情況中,其中導電層430耦合至摻雜層410,其可含有歐姆層以創建與摻雜層之較佳連接。此處,導電層430與摻雜層410之間將不存在鈍化。
若由頂側(對應於摻雜層410之側)形成VIA,或由底側(對應於摻雜層408-A、408-B及408-C之側)形成VIA,則在自VIA區域移除摻雜層之後,在底側之VIA外部仍可存在一些導電層430。墊436經形成以提供接入至導電層430。墊436藉由介電層434與下層分離。若墊436未形成與摻雜層408-C之歐姆層,則可忽略介電層434。
圖4B展示微裝置400自底面之視圖。此處,墊412及436可用於將微裝置連接或接合至系統基板。分離墊436與下層408-C之介電層434可延伸於表面之另一部分上。墊412可小於或大於摻雜層408-B。摻雜層408-A、408-C之其他部分可用於承載或不使用。一些部分可為連續的。一些部分可連接至用於調變微裝置400之內場之電壓以獲得較佳效能。
圖5A呈現形成於基板502上之微裝置500。此處,微裝置500與基板502之間可存在緩衝層/黏合層504。微裝置在p與n摻雜層508-A、508-B及508-C與510之間具有活性層506 (多量子阱、阻擋層等等)。接觸層512及514形成於摻雜層508-B及510之表面上。接點512及514可為歐姆層及墊/接合層之組合。在此結構中,摻雜層508-B及510之一者(例如n層)小於活性層506。摻雜層可經圖案化成若干較小區域且區域之一者用於透過形成墊512-A連接至裝置且透過在摻雜層之意欲區域之頂部上延伸之導電/歐姆層512-B連接至裝置。其他部分可作為其他部分之載台。此處,VIA將接點自裝置之一側帶至另一側。VIA被介電層532及耦合至摻雜層510之導電層530鈍化(或假使存在接觸層514,則導電層530耦合至接觸層514)。在一情況中,其中導電層530耦合至摻雜層510,其可含有歐姆層以創建與摻雜層之較佳連接。且導電層530與摻雜層510之間將不存在鈍化。
若由頂側(對應於摻雜層510之側)形成VIA,或由底側(對應於摻雜層508之側)形成VIA,則在自VIA區域移除摻雜層之後,在底側之VIA外部仍可存在一些導電層530。墊536經形成以提供接入至導電層530。墊536藉由介電層534與下層分離。若墊536未形成與摻雜層508-C之歐姆層,則可忽略介電層534。
圖5B展示微裝置500自底面之視圖。此處,墊512及536可用於將微裝置連接或接合至系統基板。分離墊536與下層508-C之介電層534可延伸於表面之另一部分上。墊512可小於或大於摻雜層508-B。摻雜層508-A、508-C之其他部分可用於承載或不使用。一些部分可為連續的。一些部分可連接至用於調變微裝置500之內場之電壓以獲得較佳效能。
圖6A呈現形成於基板602上之微裝置600。此處,微裝置600與基板602之間可存在緩衝層/黏合層604。微裝置在p與n摻雜層608與610之間具有活性層606 (多量子阱、阻擋層等等)。接觸層612及614形成於摻雜層608及610之表面上。接點612及614可為歐姆層及墊/接合層之組合。在此結構中,摻雜層608及610之一者(例如n層)小於活性層606。平坦化/鈍化層640可覆蓋微裝置之底面(其可使摻雜層608之表面暴露)。此處,VIA將接點自裝置之一側帶至另一側,其中VIA 642之部分位於平坦化層內部。VIA被介電層632及耦合至摻雜層610之導電層630鈍化(或假使存在接觸層614,則導電層630耦合至接觸層614)。假使,其中導電層630耦合至摻雜層610,其可含有歐姆層以創建與摻雜層之較佳連接。此處,導電層630與摻雜層610之間將不存在鈍化。
若由頂側(對應於摻雜層610之側)形成VIA,或由底側(對應於摻雜層608之側)形成VIA,則在自VIA區域移除摻雜層之後,在底側之VIA外部仍可存在一些導電層630。墊636經形成以提供接入至導電層630。墊636藉由介電層634與下層分離。若墊636未形成與摻雜層608之歐姆層,則可忽略介電層634。
圖6B展示微裝置600自底面之視圖。此處,墊612及636可用於將微裝置連接或接合至系統基板。鈍化層640延伸於微裝置600之底面上。墊612可小於或大於摻雜層608。
圖7A至圖7B、圖7C呈現形成於基板702上之微裝置700。此處,微裝置700與基板702之間可存在緩衝層/黏合層704。微裝置在p與n摻雜層708與710之間具有活性層706 (多量子阱、阻擋層等等)。接觸層712及714形成於摻雜層708及710之表面上。接點712及714可為歐姆層及墊/接合層之組合。在此結構中,摻雜層708及710之一者(例如n層)小於活性層706。平坦化/鈍化層740可覆蓋微裝置之底面(其可使摻雜層708之表面暴露)。此處,VIA將接點自裝置之一側帶至另一側,其中VIA 742之部分位於平坦化層內部。VIA被介電層732及耦合至摻雜層710之導電層730鈍化(或假使存在接觸層714,則導電層730耦合至接觸層714)。假使,其中導電層730耦合至摻雜層710,其可含有歐姆層以創建與摻雜層之較佳連接。且導電層730與摻雜層710之間將不存在鈍化。
若由頂側(對應於摻雜層710之側)形成VIA,或由底側(對應於摻雜層708之側)形成VIA,則在自VIA區域移除摻雜層之後,在底側之VIA外部仍可存在一些導電層730。墊736經形成以提供接入至導電層730。墊736藉由介電層734與下層分離。此處,接觸墊712具有兩個部分712-A及712-B。導電層712-B將墊712-A連接至摻雜層708。導電層712-B可含有歐姆層以提供較佳接入至摻雜層708。
圖7B展示微裝置700自底面之視圖。此處,墊712及736可用於將微裝置連接或接合至系統基板。鈍化層740延伸於微裝置700之底面上。墊712可小於或大於摻雜層708。在圖7C中,鈍化層740可為介電質。
儘管本發明可接受各種修改及替代形式,但特定實施例或實施方案已依舉例方式展示於圖式中且詳細描述於本文中。然而,應瞭解,本發明不意欲受限於所揭示之特定形式。確切而言,本發明意欲涵蓋落於由隨附申請專利範圍界定之本發明之精神及範疇內之所有修改、等效物及替代品。
100:微裝置
102:基板
104:緩衝層/黏合層
106:活性層
108:p摻雜層
110:n摻雜層
112:接觸層/接點
114:接觸層/接點
200:微裝置
202:基板
204:緩衝層/黏合層
206:活性層
208:p摻雜層
210:n摻雜層
212:接觸層/接點
214:接觸層/接點
216:絕緣體層
218:金屬層
300:微裝置
302:基板
304:緩衝層/黏合層
306:活性層/下層
308:p摻雜層
310:n摻雜層
312:接觸層/接點/墊
314:接觸層/接點
330:導電層
332:介電層
334:介電層
336:墊
400:微裝置
402:基板
404:緩衝層/黏合層
406:活性層
408-A:摻雜層
408-B:摻雜層
408-C:摻雜層/下層
412:接觸層/接點/墊
414:接觸層/接點
430:導電層
432:介電層
434:介電層
436:墊
500:微裝置
502:基板
504:緩衝層/黏合層
506:活性層
508-A:摻雜層
508-B:摻雜層
508-C:摻雜層/下層
510:n摻雜層
512:接觸層/接點/墊
512-A:墊
512-B:導電/歐姆層
514:接觸層/接點
530:導電層
532:介電層
534:介電層
536:墊
600:微裝置
602:基板
604:緩衝層/黏合層
606:活性層
608:p摻雜層
610:n摻雜層
612:接觸層/接點
614:接觸層/接點
630:導電層
632:介電層
634:介電層
636:墊
640:平坦化/鈍化層
642:VIA
700:微裝置
702:基板
704:緩衝層/黏合層
706:活性層
708:p摻雜層
710:n摻雜層
712-A:墊
712-B:導電層
714:接觸層/接點
730:導電層
732:介電層
734:介電層
736:墊
740:平坦化/鈍化層
742:VIA
在閱讀以下詳細描述及參考圖式之後將明白本發明之以上及其他優點。
圖1展示形成於基板上之微裝置。
圖2展示形成於基板上之具有MIS結構之微裝置。
圖3A展示形成於基板上之具有活性層及VIA之微裝置。
圖3B展示圖3A中之微裝置自底面之視圖。
圖4A展示形成於基板上之具有活性層、VIA及圖案化摻雜層之微裝置。
圖4B展示圖4A中之微裝置自底面之視圖。
圖5A展示形成於基板上之具有活性層、VIA及透過形成墊連接至裝置之圖案化摻雜層之微裝置。
圖5B展示圖5A中之微裝置自底面之視圖。
圖6A展示形成於基板上之具有活性層、VIA及摻雜層之微裝置,其中摻雜層之一者小於活性層。
圖6B展示圖6A中之微裝置自底面之視圖。
圖7A展示形成於基板上之具有活性層、VIA及摻雜層及具有兩個部分之接觸墊之微裝置。
圖7B展示圖7A中之微裝置自底面之視圖。
圖7C展示形成於基板上之具有活性層、VIA及摻雜層及在微裝置之底面上延伸之鈍化層之微裝置。
100:微裝置
102:基板
104:緩衝層/黏合層
106:活性層
108:p摻雜層
110:n摻雜層
112:接觸層/接點
114:接觸層/接點
Claims (28)
- 一種固態微裝置結構,其包括: 該微裝置,其形成於基板上; p及n摻雜層; 活性層,其處於至少該兩個摻雜層之間,同時墊經耦合至各摻雜層,其中該等摻雜層之該至少一者小於該活性層且處於該活性層之周長內;及 該兩個耦合墊,其等位於其中該摻雜層較小之相同側。
- 如請求項1之裝置,其中接觸層形成於該等摻雜層之表面上,其中該等接觸層可為歐姆層及墊或接合層之組合。
- 如請求項1之裝置,其中「n」摻雜層經調變使朝向該裝置邊緣之導電性較低。
- 如請求項1之裝置,其中鈍化層可用於形成於n摻雜層之表面或側壁及該等活性層之暴露表面上。
- 如請求項4之裝置,其中該鈍化層可為金屬絕緣體半導體(MIS)結構之形式。
- 如請求項1之裝置,其中該等活性層係多量子阱或阻擋層。
- 如請求項6之裝置,其中該阻擋層經蝕刻回至該摻雜層之大小。
- 如請求項1之裝置,其中絕緣體層及金屬層形成MIS結構。
- 如請求項8之裝置,其中該MIS結構可圍繞該n摻雜層之側壁或表面且亦可覆蓋諸如該等活性層之其他層。
- 如請求項8之裝置,其中使用負電壓偏壓該MIS結構以減少通過該n摻雜層之該等側壁之電流。
- 如請求項1之裝置,其中VIA將接點自該裝置之一側帶至另一側,其中進一步該VIA以介電層及耦合至該摻雜層之導電層鈍化。
- 如請求項11之裝置,其中該導電層經耦合至接觸層。
- 如請求項11之裝置,其中該導電層含有歐姆層以創建與該摻雜層之較佳連接,其中進一步該導電層與該摻雜層之間不存在鈍化。
- 如請求項11之裝置,其中由頂側形成該VIA或由底側形成該VIA,使得在自該VIA區域移除該等摻雜層之後,在該底側之該VIA外部仍存在該導電層之部分。
- 如請求項14之裝置,其中墊經形成以提供接入至該導電層,使得該墊藉由介電層與下層分離。
- 如請求項15之裝置,其中墊可用於將該微裝置連接或接合至系統基板且其中進一步,分離該墊與該等下層之該介電層可延伸於表面之另一部分上。
- 如請求項16之裝置,其中該墊可小於或大於摻雜層。
- 如請求項2之裝置,其中該摻雜層可經圖案化成若干較小區域且該等區域之一者用於透過在其頂部上形成墊來連接至該裝置,同時其他區域可作為其他部分之載台。
- 如請求項15之裝置,其中該墊未形成與摻雜層之歐姆層,無該介電層。
- 如請求項15之裝置,其中該等下層係可用於承載或不使用之該摻雜層之部分。其中進一步,該摻雜層之一些該等部分可為連續的,同時其他部分可連接至用於調變微裝置之內場之電壓以獲得較佳效能。
- 如請求項15之裝置,其中該墊透過在該摻雜層之意欲區域之頂部上延伸之該導電層或該歐姆層來連接至該裝置。
- 如請求項2之裝置,其中平坦化層或鈍化層可覆蓋該微裝置之底面,其中進一步該平坦化層或鈍化層可使該摻雜層之該表面暴露。
- 如請求項22之裝置,其中VIA將該接點自該裝置之一側帶至另一側,其中該VIA之部分位於該平坦化層內部。
- 如請求項2之裝置,其中該墊可小於或大於摻雜層。
- 如請求項2之裝置,其中該墊具有兩個部分:第二導電層及第二墊,其中該第二導電層將該第二墊連接至該摻雜層,其中進一步該第二導電層可含有歐姆層以提供較佳接入至該摻雜層。
- 如請求項22之裝置,其中該鈍化層可為介電質。
- 如請求項9之裝置,其中使用小於該MIS之臨限值電壓之電壓來偏壓該MIS以減少洩漏電流。
- 如請求項1之裝置,其中該「n」摻雜層小於該活性層。
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US20110198609A1 (en) * | 2010-02-12 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-Emitting Devices with Through-Substrate Via Connections |
KR101125025B1 (ko) * | 2010-07-23 | 2012-03-27 | 엘지이노텍 주식회사 | 발광소자 및 그 제조방법 |
DE102012217957B4 (de) * | 2012-10-01 | 2014-10-09 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung einer Mikro-LED-Matrix |
US8674470B1 (en) * | 2012-12-22 | 2014-03-18 | Monolithic 3D Inc. | Semiconductor device and structure |
US11600743B2 (en) * | 2017-03-30 | 2023-03-07 | Vuereal Inc. | High efficient microdevices |
-
2020
- 2020-12-03 US US17/782,050 patent/US20220416119A1/en active Pending
- 2020-12-03 TW TW109142612A patent/TW202135270A/zh unknown
- 2020-12-03 CN CN202080082956.4A patent/CN114787987A/zh active Pending
- 2020-12-03 WO PCT/CA2020/051656 patent/WO2021108909A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2021108909A1 (en) | 2021-06-10 |
US20220416119A1 (en) | 2022-12-29 |
CN114787987A (zh) | 2022-07-22 |
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