JP7256124B2 - 成長基板の裏面をエッチングするステップを含む光電子デバイスの製造方法 - Google Patents
成長基板の裏面をエッチングするステップを含む光電子デバイスの製造方法 Download PDFInfo
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- JP7256124B2 JP7256124B2 JP2019534658A JP2019534658A JP7256124B2 JP 7256124 B2 JP7256124 B2 JP 7256124B2 JP 2019534658 A JP2019534658 A JP 2019534658A JP 2019534658 A JP2019534658 A JP 2019534658A JP 7256124 B2 JP7256124 B2 JP 7256124B2
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Description
a)互いに対向する表面及び裏面を含む、半導体材料からなる、いわゆる成長基板を供給し、
b)前記表面上に、複数のダイオードを形成し、各ダイオードは前記基板上に載置された下面を含み、
c)少なくとも前記ダイオードの一部の前記下面を解放するために、前記基板の少なくとも一部分を前記裏面から除去し、除去された一部分は、最初は前記ダイオードの一部の反対側に配置され、
-ステップa)は、前記ダイオードの反対側にそれぞれ延在する前記基板の下部及び上部を製造することを含み、前記下部及び前記上部は、同一の導電型に従ってドープされており、前記下部は第1ドーピングレベルを有し、前記上部は前記第1ドーピングレベルより低い第2ドーピングレベルを有し、前記表面から前記下部に向かって均一な厚さで延び、
-ステップc)は、前記上部に対して選択的化学エッチングによって前記下部を除去することを含む。
-例えばシリコンから形成される成長基板10の表面10sから出発して、例えば、窒化ガリウム(GaN)から形成される複数のダイオード20を形成する。
-全てのダイオード20を封入する誘電体層31を堆積し、次いで、ここでは接着剤33を用いて保持用のグリップ32を封入層上に固定する。
-ダイオード20の下面20iを解放するために基板10の少なくとも一部をその全厚にわたって除去する。除去された部分は、最初はダイオード20の少なくとも一部と反対側に位置する。
-任意選択で、ダイオード20の解放された下面20i上に少なくとも1つの導電スタッド(図示せず)を形成する。
Claims (14)
- a)互いに対向する表面(10s)及び裏面(10i)を含む、半導体材料からなる、成長基板(10)を供給し、
b)前記表面(10s)上に、複数のダイオード(20)を形成し、各ダイオード(20)は前記成長基板(10)上に載置された下面(20i)を含み、
c)少なくとも前記ダイオード(20)の一部の前記下面(20i)を解放するために、前記成長基板(10)の少なくとも一部分を前記裏面(10i)から除去し、除去された一部分は、最初は前記ダイオード(20)の一部の反対側に配置され、
-ステップa)は、前記ダイオード(20)の反対側にそれぞれ延在する前記成長基板(10)の下部(11)及び上部(12)を製造することを含み、前記下部(11)及び前記上部(12)は、同一の導電型に従ってドープされており、前記下部(11)は第1ドーピングレベルを有し、前記上部(12)は前記第1ドーピングレベルより低い第2ドーピングレベルを有し、前記表面(10s)から前記下部(11)に向かって均一な厚さ(eref)で延び、
-ステップc)は、前記上部(12)に対して選択的化学エッチングによって前記下部(11)を除去することを含み、
-ステップb)において、前記ダイオード(20)は、該ダイオード(20)の複数の別々のアセンブリ(D)として空間的に分散され、
-前記上部(12)は、前記表面(10s)に平行な平面内で、側部(14)によって互いに分離された中央部(13)を含み、各中央部(13)は、前記ダイオード(20)の前記アセンブリ(D)に対向して位置し、前記側部(14)は前記ダイオード(20)の前記アセンブリ(D)の間に位置し、
-ステップc)は、前記表面(10s)に平行な平面内で、前記上部(12)を部分的に除去して前記中央部(13)を取り除き、前記側部(14)を保存して、保持側壁(15)を形成することを含み、
前記成長基板(10)の少なくとも一部分は、前記上部(12)及び前記中央部(13)を含む、
ことを特徴とする、
光電子デバイス(1)を製造する方法。 - ステップc)は、前記表面(10s)と平行な平面内で、化学エッチングによって前記成長基板(10)の前記上部(12)を完全に又は部分的に除去するステップをさらに含み、前記ダイオード(20)の前記下面(20i)を解放する、
請求項1に記載の方法。 - 各ダイオード(20)は、前記ダイオード(20)のp-n接合を形成することに関与する半導体素子(21)を含み、各ダイオード(20)の前記下面(20i)は、前記半導体素子(21)に電気的に接触しており、
前記方法は、前記ダイオード(20)の一部の前記下面(20i)と接触する少なくとも1つの第1導電スタッド(41)を形成するステップd)を含む、
請求項1又は2に記載の方法。 - -ステップb)において、各アセンブリ(D)は前記光電子デバイス(1)の画素(Px)を形成することを意図しており、
-ステップd)において、複数の別々の第1導電スタッド(41)が形成され、各第1導電スタッド(41)は同一のアセンブリ(D)の前記ダイオード(20)の前記下面(20i)と接触している、
請求項3に記載の方法。 - ステップc)において、前記中央部(13)がウェット又はドライエッチングによってエッチングされる、
請求項4に記載の方法。 - -ステップa)は、前記中央部(13)が前記第1ドーピングレベル以上のドーピングレベルを有するように、前記上部(12)の局所的ドーピングによって前記中央部(13)を製造することを含み、前記側部(14)は前記第2ドーピングレベルを有し、各中央部(13)は前記側部(14)の1つによって隣接する前記中央部(13)から分離され、各中央部(13)は前記上部(12)の厚さ(eref)より厳密に小さい厚さ(e13)を有し、
-ステップc)は、前記下部(11)の除去に続いて、前記裏面(10i)が前記中央部(13)上に解放される(open)ように、前記成長基板(10)を薄くし、次いで前記中央部(13)を前記側部(14)に対する選択的化学エッチングによって除去するステップを含み、前記ダイオード(20)の前記アセンブリ(D)の前記下面(20i)を解放し(free)、前記側部(14)が前記保持側壁(15)を形成する、
請求項4又は5に記載の方法。 - 前記上部(12)の前記厚さ(eref)が0.5μmから20μmの間であり、ステップc)の終わりに、前記保持側壁(15)は0.5μmから20μmの高さを有する、
請求項4から6のいずれか1項に記載の方法。 - -ステップb)は、電気絶縁材料で形成された核形成層(23)から始まる前記半導体素子(21)のエピタキシーを含み、
-ステップc)は、ステップd)の終わりに、前記第1導電スタッド(41)が、前記ダイオード(20)の前記下面(20i)を形成する前記半導体素子(21)の下面(21i)と接触するように、前記核形成層(23)の一部を除去することをさらに含む、
請求項4から7のいずれか1項に記載の方法。 - -ステップb)は、導電性材料又は半導体性材料により形成された核形成層(23)から始まる半導体要素(21)のエピタキシーを含み、ステップd)の終わりに、前記第1導電スタッド(41)が、前記ダイオード(20)の前記下面(20i)を形成する前記核形成層(23)の下面に接触する、
請求項4から7のいずれか1項に記載の方法。 - ステップb)は、全ての前記ダイオード(20)を覆う、少なくとも部分的に透明な導電性の電極層(25)を堆積させることを含み、第2導電スタッド(42)が前記電極層(25)と電気的に接触している、
請求項8又は9に記載の方法。 - 前記第2導電スタッド(42)が、前記下面(20i)の方を向いている前記電極層(25)の下面側に配置されているか、又は、該下面側とは反対側の前記電極層(25)の上面側に配置されている、
請求項10に記載の方法。 - ステップb)は、前記成長基板(10)の前記表面(10s)上又は前記核形成層(23)上に誘電体層(24)を堆積させることを含み、1つ以上の第1導電スタッド(41)が、前記ダイオード(20)の前記下面(20i)と接触し、前記誘電体層(24)によって前記電極層(25)から電気的に絶縁されている、
請求項10又は11に記載の方法。 - 各ダイオード(20)が三次元の半導体素子(21)を含む、
請求項1から12のいずれか1項に記載の方法。 - 前記成長基板(10)の前記半導体材料は、p型又はn型の導電性でドープされたシリコンである、
請求項1から13のいずれか1項に記載の方法。
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US20160126416A1 (en) | 2013-05-14 | 2016-05-05 | Commissariat Á L'energie Atomique Et Aux Énergies Alternatives | Optoelectronic device and method for manufacturing same |
WO2016108021A1 (fr) | 2014-12-30 | 2016-07-07 | Aledia | Dispositif optoélectronique a diodes électroluminescentes |
JP2016535434A (ja) | 2013-09-30 | 2016-11-10 | コミサリア ア エナジー アトミック エ オックス エナジーズ オルタネティヴ | 発光ダイオードを備えた光電子デバイスを製造する方法 |
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US20160126416A1 (en) | 2013-05-14 | 2016-05-05 | Commissariat Á L'energie Atomique Et Aux Énergies Alternatives | Optoelectronic device and method for manufacturing same |
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