TW202133380A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW202133380A
TW202133380A TW109132107A TW109132107A TW202133380A TW 202133380 A TW202133380 A TW 202133380A TW 109132107 A TW109132107 A TW 109132107A TW 109132107 A TW109132107 A TW 109132107A TW 202133380 A TW202133380 A TW 202133380A
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Taiwan
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die
integrated circuit
logic die
logic
wafer
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TW109132107A
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TWI741793B (zh
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邱文智
余振華
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台灣積體電路製造股份有限公司
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Priority claimed from US16/890,019 external-priority patent/US11594571B2/en
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Abstract

提供一種半導體裝置以及形成其之方法。所述半導體裝置包括：第一邏輯晶粒，包括第一穿孔；影像感測器晶粒，混合接合至第一邏輯晶粒；以及第二邏輯晶粒，接合至第一邏輯晶粒。第一邏輯晶粒的前側面對影像感測器晶粒的前側。第二邏輯晶粒的前側面對第一邏輯晶粒的後側。第二邏輯晶粒包括電性耦合至第一穿孔的第一導電墊。

Description

堆疊式影像感測器裝置及其形成方法
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的積體密度持續提高，半導體行業經歷了快速發展。在很大程度上，積體密度提高起因於最小特徵大小（minimum feature size）的持續減小，此使得更多元件能夠被整合至給定面積中。隨著對縮小電子裝置的需求的增長，對更小且更具創造性的半導體晶粒封裝技術的需求已經浮現。此種封裝系統的實例是疊層封裝（Package-on-Package，PoP）技術。在PoP裝置中，頂部半導體封裝體堆疊於底部半導體封裝體頂上，以提供高積體度及高元件密度。PoP技術一般而言能夠生產功能得到增強且在印刷電路板（printed circuit board，PCB）上佔用面積小的半導體裝置。
以下揭露提供用於實施本揭露的不同特徵的許多不同實施例或實例。以下闡述元件及排列的具體實例以簡化本揭露。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「位於…下方（below）」、「下部的（lower）」、「位於…上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
將針對特定上下文中的實施例（即封裝體，例如多層堆疊式（multi-tier）影像感測器封裝體以及形成其之方法）來闡述實施例。本文中所呈現的各種實施例使得能夠形成用於邊緣人工智慧（artificial intelligence，AI）應用（例如可能需要快速處理速度的自動化汽車）的封裝體。實施例（例如本文中揭露的實施例）將邏輯晶粒及/或記憶體（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶片）整合於多層堆疊式影像感測器封裝體內，以用於處理影像資訊，進而提高處理速度以滿足邊緣AI應用的功能及處理速度要求。
圖1示出根據一些實施例的積體電路晶粒10的剖視圖。積體電路晶粒10將在後續處理中被封裝以形成積體電路封裝體。積體電路晶粒10可為邏輯晶粒（例如，中央處理單元（central processing unit，CPU）、圖形處理單元（graphics processing unit，GPU）、系統晶片（system-on-a-chip，SoC）、應用處理器（application processor，AP）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電源管理晶粒（例如，電源管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end，AFE）晶粒）、類似晶粒或其組合。
積體電路晶粒10可形成於晶圓中，所述晶圓可包括不同的的多個裝置區，該些裝置區在後續步驟中被單體化以形成多個積體電路晶粒。可根據適用於形成積體電路的製造製程對積體電路晶粒10進行處理。舉例而言，積體電路晶粒10包括基底52，例如經摻雜的或未經摻雜的矽或絕緣體上有半導體（semiconductor-on-insulator，SOI）基底的主動層。基底52可包含其他半導體材料，例如：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用其他基底，例如多層式基底（multi-layered substrate）或梯度基底（gradient substrate）。基底52具有有時被稱作前側的主動表面（例如，在圖1中面朝上的表面）以及有時被稱作後側的非主動表面（例如，在圖1中面朝下的表面）。
在基底52的前表面處可形成有多個裝置（被表示為電晶體）54。裝置54可為主動裝置（例如，電晶體、二極體等）、電容器、電阻器、電感器、類似裝置或其組合。層間介電質（inter-layer dielectric，ILD）56位於基底52的前表面之上。層間介電質56環繞裝置54且可覆蓋裝置54。層間介電質56可包括由例如以下材料形成的一或多個介電層：磷矽酸鹽玻璃（Phospho-Silicate Glass，PSG）、硼矽酸鹽玻璃（Boro-Silicate Glass，BSG）、摻雜硼的磷矽酸鹽玻璃（Boron-Doped Phospho-Silicate Glass，BPSG）、未經摻雜的矽酸鹽玻璃（undoped Silicate Glass，USG）等，且可使用旋轉塗佈（spin coating）、疊層（lamination）、原子層沈積（atomic layer deposition，ALD）、化學氣相沈積（chemical vapor deposition，CVD）等形成層間介電質56。
導電插頭（conductive plug）58延伸穿過層間介電質56以電性耦合及在實體上耦合裝置54。舉例而言，當裝置54是電晶體時，導電插頭58可對所述電晶體的閘極及源極/汲極區進行耦合。導電插頭58可由鎢、鈷、鎳、銅、銀、金、鋁、類似材料或其組合形成。內連結構（interconnect structure）60位於層間介電質56及導電插頭58之上。內連結構60對多個裝置54進行內連以形成積體電路。可藉由例如層間介電質56上的多個介電層中的多個金屬化圖案形成內連結構60。金屬化圖案包括形成於一或多個低介電常數（low-k）介電層中的多個金屬線及多個通孔。在一些實施例中，內連結構60可由交替的介電材料（例如，低介電常數介電材料）層與導電材料（例如，銅）層形成，且具有對導電材料層進行內連的多個通孔，並可藉由任何合適的製程（例如沈積、鑲嵌、雙鑲嵌等）形成內連結構60。內連結構60的金屬化圖案藉由導電插頭58電性耦合至裝置54。
積體電路晶粒10更包括進行外部連接的多個墊62（例如鋁墊）。墊62位於積體電路晶粒10的主動表面上，例如位於內連結構60中及/或內連結構60上。絕緣層64位於積體電路晶粒10上，使得墊62嵌置於絕緣層64中。絕緣層64亦可被稱為鈍化層。在一些實施例中，絕緣層64可包括一或多層氧化矽、氮化矽、氮氧化矽、類似材料或其組合，且可使用ALD、CVD等形成絕緣層64。在一些實施例中，可藉由以下方式形成墊62及絕緣層64：在內連結構60之上形成導電材料並將所述導電材料圖案化以形成墊62，在內連結構60及墊62之上形成絕緣層64的絕緣材料，且將絕緣材料平坦化以暴露出墊62。
在其他實施例中，可藉由以下方式形成墊62及絕緣層64：在內連結構60之上形成絕緣層64的絕緣材料，將絕緣材料圖案化以形成墊62的多個開口，在開口中沈積墊62的導電材料，且將導電材料平坦化以移除對開口進行過填充的導電材料的部分。剩餘在開口中的導電材料的部分形成墊62。在一些實施例中，平坦化製程可包括化學機械研磨（chemical mechanical polishing，CMP）、磨削（grinding）、蝕刻（etching）、其組合等。在一些實施例中，在平坦化製程的製程變動（process variation）內，絕緣層64的頂表面與墊62的頂表面實質上齊平或實質上共面。
在一些實施例中，對積體電路晶粒10執行晶片探針（chip probe，CP）測試。可對積體電路晶粒10執行CP測試以確定積體電路晶粒10是否是已知良好晶粒（known good die，KGD）。因此，只有作為KGD的積體電路晶粒10會經受後續處理且被封裝，而未通過CP測試的晶粒不會被封裝。
在一些實施例中，積體電路晶粒10是包括多個基底52的堆疊式裝置。舉例而言，積體電路晶粒10可為記憶體裝置，例如混合記憶體立方體（hybrid memory cube，HMC）模組、高頻寬記憶體（high bandwidth memory，HBM）模組或包括多個記憶體晶粒的類似模組。在此種實施例中，積體電路晶粒10包括由多個基底穿孔（through-substrate via，TSV）（未示出）進行內連的多個基底52。基底52中的每一者可具有（或可不具有）內連結構60。
圖2示出根據一些實施例的積體電路晶粒20的剖視圖。積體電路晶粒20將在後續處理中被封裝以形成積體電路封裝體。在一些實施例中，積體電路晶粒20相似於積體電路晶粒10（參見圖1），其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖1闡述的製程步驟形成積體電路晶粒20，且在本文中不再予以贅述。在所示出的實施例中，積體電路晶粒20包括延伸穿過基底52的多個基底穿孔66。在一些實施例中，基底穿孔66可包含合適的導電材料，例如銅等。
圖3示出根據一些實施例的積體電路晶粒30的剖視圖。積體電路晶粒30將在後續處理中被封裝以形成積體電路封裝體。在一些實施例中，積體電路晶粒30相似於積體電路晶粒10（參見圖1），其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖1闡述的製程步驟形成積體電路晶粒30，且在本文中不再予以贅述。
在所示出的實施例中，絕緣層64位於積體電路晶粒30上，例如位於內連結構60的部分及墊62的部分上。多個開口穿過絕緣層64延伸至墊62。多個凸塊下金屬（under-bump metallization，UBM）68延伸穿過絕緣層64中的開口且在實體上耦合至及電性耦合至墊62中的相應的墊62。凸塊下金屬68可由一或多種合適的導電材料形成。
在形成凸塊下金屬68之後，在凸塊下金屬68上形成導電連接件70。導電連接件70可為球柵陣列（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊或類似凸塊等。導電連接件70可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中，藉由以下方式形成導電連接件70：首先藉由蒸鍍（evaporation）、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）等方式或類似方式來形成一層焊料層。一旦已在所述結構上形成焊料層，便可執行回焊（reflow），以將所述焊料層的材料塑形成期望的凸塊形狀。在另一實施例中，導電連接件70包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱（例如銅柱）。金屬柱可為無焊料的且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合，且可藉由鍍覆製程形成。
圖4示出根據一些實施例的積體電路晶粒40的剖視圖。積體電路晶粒40將在後續處理中被封裝以形成積體電路封裝體。在一些實施例中，積體電路晶粒40相似於積體電路晶粒30（參見圖3），其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖1及圖3闡述的製程步驟形成積體電路晶粒40，且在本文中不再予以贅述。在所示出的實施例中，積體電路晶粒40包括延伸穿過基底52的多個基底穿孔66。在一些實施例中，基底穿孔66可包含合適的導電材料，例如銅等。
圖5至圖18示出根據一些實施例的形成封裝體1000的過程期間的中間步驟的剖視圖。圖5示出根據一些實施例的晶圓100的晶粒區100A的剖視圖。晶圓100亦可被稱為邏輯晶圓。在一些實施例中，晶圓100包括多個晶粒區（例如晶粒區100A）。在一些實施例中，晶圓100包括基底102。可使用與上方參照圖1闡述的基底52相似的材料及方法形成基底102，且在本文中不再予以贅述。基底102具有有時被稱作前側的主動表面（例如，在圖5中面朝上的表面）以及有時被稱作後側的非主動表面（例如，在圖5中面朝下的表面）。在一些實施例中，在基底102中形成多個基底穿孔104。在一些實施例中，基底穿孔104可包含合適的導電材料，例如銅等。基底穿孔104自基底102的前側朝基底102的後側延伸。
可在基底102的前表面處形成多個裝置（被表示為電晶體）106。裝置106可為主動裝置（例如，電晶體、二極體等）、電容器、電阻器、電感器、類似裝置或其組合。層間介電質108位於基底102的前表面之上。層間介電質108環繞裝置106且可覆蓋裝置106。可使用與上方參照圖1闡述的層間介電質56相似的材料及方法形成層間介電質108，且在本文中不再予以贅述。
導電插頭110延伸穿過層間介電質108以電性耦合及在實體上耦合裝置106。舉例而言，當裝置106是電晶體時，導電插頭110可對所述電晶體的閘極及源極/汲極區進行耦合。可使用與上方參照圖1闡述的導電插頭58相似的材料及方法形成導電插頭110，且在本文中不再予以贅述。
內連結構112位於層間介電質108及導電插頭110之上。內連結構112對多個裝置106進行內連以形成積體電路。可藉由例如層間介電質108上的多個介電層中的多個金屬化圖案形成內連結構112。金屬化圖案包括形成於一或多個低介電常數介電層中的多個金屬線及多個通孔。可使用與上方參照圖1闡述的內連結構60相似的材料及方法形成內連結構112，且在本文中不再予以贅述。
在一些實施例中，晶圓100更包括絕緣層116及嵌置於絕緣層116中的多個墊114。可使用與上方參照圖1闡述的墊62相似的材料及方法形成墊114，且在本文中不再予以贅述。可使用與上方參照圖1闡述的絕緣層64相似的材料及方法形成絕緣層116，且在本文中不再予以贅述。在一些實施例中，在平坦化製程的製程變動內，絕緣層116的頂表面與墊114的頂表面實質上齊平或實質上共面。
圖6示出根據一些實施例的晶圓200的晶粒區200A的剖視圖。晶圓200亦可被稱為影像感測器晶圓。在一些實施例中，晶圓200包括多個晶粒區（例如晶粒區200A）。在一些實施例中，晶圓200包括基底202。可使用與上方參照圖1闡述的基底52相似的材料及方法形成基底202，且在本文中不再予以贅述。基底202具有有時被稱作前側的主動表面（例如，在圖6中面朝上的表面）以及有時被稱作後側的非主動表面（例如，在圖6中面朝下的表面）。
在基底202的前側（或稱上表面或前表面）處形成多個感光性畫素（photosensitive pixel）218。感光性畫素218包括相應的感光性裝置（未示出），所述感光性裝置可例如藉由將合適的雜質離子（impurity ion）注入至基底202中來形成。感光性裝置被配置成將光訊號（例如，光子）轉換成電訊號，且可為PN接面光二極體（PN junction photo-diode）、PNP光電晶體、NPN光電晶體等。舉例而言，感光性裝置可包括形成於p型半導體層（例如，基底202的至少一部分）內的n型注入區。在此種實施例中，p型基底可隔離並減少感光性畫素218的相鄰的多個光主動區（photo-active region）之間的電性串擾（cross-talk）。在一個實施例中，感光性畫素218自基底202的前側朝基底202的後側（或稱下表面或後表面）延伸且形成感光性畫素陣列。在一些實施例中，當自頂部觀察時，感光性畫素218形成二維矩形陣列。在一些實施例中，每一感光性畫素218可更包括轉移閘極電晶體（未示出）及浮動擴散電容器（未示出）。在每一感光性畫素218中，對應的轉移閘極電晶體的第一源極/汲極區電性耦合至相應的感光性裝置，對應的轉移閘極電晶體的第二源極/汲極區電性耦合至相應的浮動擴散電容器。
在一些實施例中，在鄰近的感光性畫素218之間的基底202中形成多個隔離區（isolation region）220，以防止感光性畫素218之間的電性串擾。在一些實施例中，隔離區220可包括淺溝槽隔離（shallow trench isolation，STI）結構。在一些實施例中，可藉由以下方式形成STI結構：將基底202的前表面圖案化以在基底202中形成多個溝槽，且使用合適的介電材料填充溝槽以形成多個STI結構。在一些實施例中，使用合適的微影及蝕刻製程將基底202圖案化。在其他實施例中，隔離區220可包括使用合適的注入製程（implanting process）形成的各種摻雜區。
可在基底202的前側處形成多個裝置（表示為電晶體）206。裝置206可為主動裝置（例如，電晶體、二極體等）、電容器、電阻器、電感器、類似裝置或其組合。層間介電質208位於基底202的前側之上。層間介電質208環繞裝置206且可覆蓋裝置206。可使用與上方參照圖1闡述的層間介電質56相似的材料及方法形成層間介電質208，且在本文中不再予以贅述。
導電插頭210延伸穿過層間介電質208以電性耦合及在實體上耦合裝置206。舉例而言，當裝置206是電晶體時，導電插頭210可對所述電晶體的閘極及源極/汲極區進行耦合。可使用與上方參照圖1闡述的導電插頭58相似的材料及方法形成導電插頭210，且在本文中不再予以贅述。
內連結構212位於層間介電質208及導電插頭210之上。內連結構212對多個裝置206進行內連以形成積體電路。可藉由例如層間介電質208上的多個介電層中的多個金屬化圖案形成內連結構212。金屬化圖案包括形成於一或多個低介電常數介電層中的多個金屬線及多個通孔。可使用與上方參照圖1闡述的內連結構60相似的材料及方法形成內連結構212，且在本文中不再予以贅述。
在一些實施例中，晶圓200更包括絕緣層216及嵌置於絕緣層216中的多個墊214。可使用與上方參照圖1闡述的墊62相似的材料及方法形成墊214，且在本文中不再予以贅述。可使用與上方參照圖1闡述的絕緣層64相似的材料及方法形成絕緣層216，且在本文中不再予以贅述。在一些實施例中，在平坦化製程的製程變動內，絕緣層216的頂表面與墊214的頂表面實質上齊平或實質上共面。
圖7示出將晶圓100接合至晶圓200。在一些實施例中，使用混合接合（bybrid bonding）方法將晶圓100接合至晶圓200。混合接合方法包括將晶圓100的墊114直接接合至晶圓200的相應的墊214以及將晶圓100的絕緣層116直接接合至晶圓200的絕緣層216。在一些實施例中，將晶圓100接合至晶圓200，使得晶圓100的晶粒區（例如晶粒區100A）接合至晶圓200的相應的晶粒區（例如晶粒區200A）。
圖8示出對晶圓100的基底102的後側執行的薄化製程。在一些實施例中，薄化製程包括CMP、磨削、蝕刻、其組合等。薄化製程會移除基底102的一部分且暴露出形成於基底102內的基底穿孔104。在一些實施例中，在薄化製程的製程變動內，基底102的後表面與基底穿孔104的被暴露出的表面實質上齊平或實質上共面。
圖9至圖14示出在晶圓100的後側上形成晶圓級封裝結構3000。晶圓級封裝結構3000亦可被稱為晶圓級積體扇出型（integrated fan-out，InFO）結構。晶圓級封裝結構3000包括多個晶粒區，例如晶粒區3000A。晶圓級封裝結構3000的晶粒區3000A對應於晶圓100的晶粒區100A及晶圓200的晶粒區200A。
圖9示出在晶圓100的後側上形成絕緣層304及多個墊306。可使用與上方參照圖1闡述的墊62相似的材料及方法形成墊306，且在本文中不再予以贅述。可使用與上方參照圖1闡述的絕緣層64相似的材料及方法形成絕緣層304，且在本文中不再予以贅述。在一些實施例中，在平坦化製程的製程變動內，絕緣層304的頂表面與墊306的頂表面實質上齊平或實質上共面。在一些實施例中，絕緣層304與墊306形成重佈線結構302。在所示出的實施例中，重佈線結構302包括單個導電層及單個絕緣層。在其他實施例中，重佈線結構302可包括多個導電層及多個絕緣層。
圖10示出在重佈線結構302的墊306之上形成多個穿孔（through vias）308。作為形成穿孔308的實例，在絕緣層304及墊306之上形成晶種層（未示出）。在一些實施例中，晶種層是金屬層，可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積（physical vapor deposition，PVD）等形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於穿孔/導通孔。所述圖案化會形成穿過光阻的多個開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電鍍覆）等形成所述導電材料。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等進行可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成穿孔308。
在圖11中，將多個積體電路晶粒10（例如，積體電路晶粒（又稱第一積體電路晶粒）10A及積體電路晶粒（又稱第二積體電路晶粒）10B）接合至晶圓100的後側。將期望的類型及數量的積體電路晶粒10接合於晶粒級區（die-level region）中的每一者中。在所示出的實施例中，第一積體電路晶粒10A與第二積體電路晶粒10B彼此相鄰地接合。第一積體電路晶粒10A可為邏輯裝置，例如中央處理單元（CPU）、圖形處理單元（GPU）、系統晶片（SoC）、微控制器等。在一些實施例中，第一積體電路晶粒10A可包括被配置成用於邊緣AI應用的積體電路。
第二積體電路晶粒10B可為記憶體裝置，例如動態隨機存取記憶體（DRAM）晶粒、靜態隨機存取記憶體（SRAM）晶粒、混合記憶體立方體（HMC）模組、高頻寬記憶體（HBM）模組等。在一些實施例中，第一積體電路晶粒10A與積體電路晶粒10B可為相同類型的晶粒，例如SoC晶粒。第一積體電路晶粒10A與第二積體電路晶粒10B可在相同技術節點（technology node）的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，第一積體電路晶粒10A可具有較第二積體電路晶粒10B更先進的製程節點。積體電路晶粒10A與積體電路晶粒10B可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
在一些實施例中，使用混合接合方法將積體電路晶粒10A及10B接合至重佈線結構302的絕緣層304及墊306。混合接合方法包括將積體電路晶粒10A及10B的墊62直接接合至重佈線結構302的相應的墊306以及將積體電路晶粒10A及10B的絕緣層64直接接合至重佈線結構302的絕緣層304。
在圖12中，在積體電路晶粒10A及10B以及穿孔308上形成圍繞積體電路晶粒10A及10B以及穿孔308的包封體310。包封體310可為模製化合物、環氧樹脂等。可藉由壓縮模製（compression molding）、轉移模製（transfer molding）等施加包封體310，且可在經接合的晶圓100與晶圓200之上形成包封體310，使得積體電路晶粒10A及10B以及穿孔308被隱埋（buried）或被覆蓋。可以透過液體或半液體形式施加包封體310且隨後接著將包封體310固化。
在圖13中，對包封體310執行平坦化製程以暴露出穿孔308。平坦化製程亦可移除穿孔308的部分。在所示出的實施例中，在執行平坦化製程之後，積體電路晶粒10A及10B的後表面被包封體310覆蓋。在其他實施例中，在執行平坦化製程之後，積體電路晶粒10A及10B的後表面被暴露出。在平坦化製程的製程變動內，包封體310的頂表面與穿孔308的頂表面實質上共面。平坦化製程可包括CMP、磨削、蝕刻、其組合等。在一些實施例中，舉例而言，若已暴露出穿孔308，則可省略平坦化。
在圖14中，在包封體310、積體電路晶粒10A及10B以及穿孔308之上形成重佈線結構312。重佈線結構312包括多個絕緣層314、318、322及326以及多個金屬化圖案316、320及324。金屬化圖案亦可被稱為重佈線層或重佈線走線。重佈線結構312被示出為具有三層金屬化圖案的實例。可在重佈線結構312中形成更多或更少的絕緣層及金屬化圖案。若欲形成更少的絕緣層及金屬化圖案，則可省略以下論述的步驟及製程。若欲形成更多的絕緣層及金屬化圖案，則可重複進行以下論述的步驟及製程。
在一些實施例中，在包封體310、積體電路晶粒10A及10B以及穿孔308上沈積絕緣層314。在一些實施例中，絕緣層314由可使用微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide，PI）、苯並環丁烯（benzocyclobutene，BCB）等）形成。可藉由旋轉塗佈、疊層、CVD、類似製程或其組合形成絕緣層314。在其他實施例中，絕緣層314可包含非感光性材料（例如氧化矽、氮化矽、氮氧化矽等），且可藉由ALD、CVD、類似製程或其組合來形成。接著將絕緣層314圖案化。圖案化會在絕緣層314中形成暴露出穿孔308的一些部分的的多個開口。可藉由可接受的製程進行圖案化，例如藉由在絕緣層314是感光性材料時將絕緣層314暴露至光並進行顯影或者藉由在絕緣層314是非感光性材料時使用例如非等向性蝕刻（anisotropic etch）進行蝕刻來進行。
接著形成金屬化圖案316。金屬化圖案316包括多個導電元件，所述導電元件沿絕緣層314的主表面延伸且延伸穿過絕緣層314以在實體上耦合至及電性耦合至穿孔308。作為形成金屬化圖案316的實例，在絕緣層314之上以及延伸穿過絕緣層314的開口中形成晶種層。在一些實施例中，晶種層是金屬層，可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案316。所述圖案化會形成穿過光阻的多個開口以暴露出晶種層。接著在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電鍍覆）等形成所述導電材料。導電材料可包括金屬，例如銅、鈦、鎢、鋁等。導電材料與晶種層的下伏部分的組合形成金屬化圖案316。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等進行可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。
在形成金屬化圖案316之後，在金屬化圖案316及絕緣層314上沈積絕緣層318。可使用與絕緣層314相似的材料及方法形成絕緣層318。
接著形成金屬化圖案320。金屬化圖案320包括位於絕緣層318的主表面上且沿絕緣層318的主表面延伸的部分。金屬化圖案320更包括延伸穿過絕緣層318以在實體上耦合至及電性耦合至金屬化圖案316的部分。可使用與金屬化圖案316相似的材料及方式形成金屬化圖案320。在一些實施例中，金屬化圖案320具有與金屬化圖案316不同的大小。舉例而言，金屬化圖案320的導電線及/或導通孔可寬於或厚於金屬化圖案316的導電線及/或導通孔。此外，金屬化圖案320可被形成為具有較金屬化圖案316大的節距。
在形成金屬化圖案320之後，在金屬化圖案320及絕緣層318上沈積絕緣層322。可使用與絕緣層314相似的材料及方法形成絕緣層322。
接著形成金屬化圖案324。金屬化圖案324包括位於絕緣層322的主表面上且沿絕緣層322的主表面延伸的部分。金屬化圖案324更包括延伸穿過絕緣層322以在實體上耦合至及電性耦合至金屬化圖案320的部分。可使用與金屬化圖案316相似的材料及方式形成金屬化圖案324。金屬化圖案324是重佈線結構312的最頂部金屬化圖案。藉此，重佈線結構312所有的中間金屬化圖案（例如，金屬化圖案316及320）皆設置於金屬化圖案324與包封體310之間。在一些實施例中，金屬化圖案324具有與金屬化圖案316及320不同的大小。舉例而言，金屬化圖案324的導電線及/或導通孔可寬於或厚於金屬化圖案316及320的導電線及/或導通孔。此外，金屬化圖案324可被形成為具有較金屬化圖案316及320大的節距。
在形成金屬化圖案324之後，在金屬化圖案324及絕緣層322上沈積絕緣層326。可使用與絕緣層314相似的材料及方法形成絕緣層326。絕緣層326是重佈線結構312的最頂部絕緣層。藉此，重佈線結構312所有的金屬化圖案（例如，金屬化圖案316、320及324）皆設置於絕緣層326與包封體310之間。此外，重佈線結構312所有的中間絕緣層（例如，絕緣層314、318、322）皆設置於絕緣層326與包封體310之間。
此外，在圖14中，在形成重佈線結構312之後，形成多個凸塊下金屬328以對重佈線結構312進行外部連接。凸塊下金屬328具有凸塊部分且具有通孔部分，凸塊部分位於絕緣層326的主表面上且沿絕緣層326的主表面延伸，通孔部分延伸穿過絕緣層326以在實體上耦合至及電性耦合至金屬化圖案324。因此，凸塊下金屬328透過重佈線結構312電性耦合至穿孔308以及積體電路晶粒10A及10B。凸塊下金屬328可由與金屬化圖案324相同的材料形成。在一些實施例中，凸塊下金屬328具有與金屬化圖案316、320及324不同的大小。
在形成凸塊下金屬328之後，在凸塊下金屬328上形成導電連接件330。導電連接件330可為球柵陣列（BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（ENEPIG）形成的凸塊或類似凸塊等。可使用與上方參照圖3闡述的導電連接件70相似的材料及方法形成導電連接件330，且在本文中不再予以贅述。
在圖15中，對圖14所示堆疊式晶圓級結構進行翻轉，且使用黏合劑334將所述堆疊式晶圓級結構貼合至載體基底（carrier substrate）332。載體基底332可為玻璃載體基底、陶瓷載體基底、類似的載體基底等。隨後，對晶圓200的基底202的後側執行薄化製程。在一些實施例中，薄化製程包括CMP、磨削、蝕刻、其組合等。薄化製程會移除基底202的一部分且減小基底202的後表面與感光性畫素218之間的距離。
在圖16中，在晶圓200的基底202的後側之上形成彩色濾光器（color filter）（又稱濾色器）336。在一些實施例中，彩色濾光器336與感光性畫素218對準。彩色濾光器336可用於使得特定波長的光通過，同時反射其他波長的光，進而使得影像感測器能夠確定由感光性畫素218接收的光的顏色。彩色濾光器336可發生變化，例如拜耳圖案（Bayer pattern）中使用的紅色、綠色及藍色彩色濾光器。亦可使用其他組合，例如青色（cyan）、黃色及品紅（magenta）。不同顏色的彩色濾光器336的數目亦可發生變化。彩色濾光器336可包含包括有色色素（colored pigment）的聚合材料或樹脂，例如聚甲基丙烯酸甲酯（polymethyl-methacrylate，PMMA）、聚甲基丙烯酸縮水甘油酯（polyglycidyl-methacrylate，PGMA）等。在一些實施例中，沿彩色濾光器336的側壁形成多個反射導向層（未示出）。反射導向層由能夠反射光的金屬或其他高折射率材料（例如銅、鋁、氮化鉭、氮化鈦、鎢、氮化矽、類似材料或其組合）形成。
此外，在圖16中，在晶圓200的基底202的後側之上形成壩結構（dam structure）338且壩結構338環繞彩色濾光器336。在一些實施例中，壩結構338在平面圖中具有環狀結構（annular structure）。在一些實施例中，環狀結構可為環形（ring）形狀、方形（squre）形狀的環狀結構等。壩結構338可包含環氧樹脂、矽酮、類似材料或其組合。在一些實施例中，在晶圓200的晶粒區200A內設置壩結構338。隨後，將蓋體（cover）340貼合至壩結構338。蓋體340可包含透明材料，例如玻璃等。在一些實施例中，使用黏合劑（未示出）將蓋體340貼合至壩結構338。
在圖17中，將圖16所示堆疊式晶圓級結構自載體基底332（參見圖16）剝離並放置於切割帶（dicing tape）342上。隨後，藉由沿多個切割道區（例如，在堆疊式晶圓級結構中相鄰的晶粒區之間）進行鋸切來執行單體化製程344。所述鋸切將多個晶粒區自堆疊式晶圓級結構單體化且形成多個封裝體1000。封裝體1000中的每一者包括晶圓100的晶粒區100A、晶圓200的晶粒區200A及晶圓級封裝結構3000的晶粒區3000A。
在圖18中，使用導電連接件330將封裝體1000安裝至封裝基底（package substrate）400。在一些實施例中，封裝基底400包括基底芯體（substrate core）402及位於基底芯體402之上的多個接合墊（bonding pad）404。基底芯體402可由例如矽、鍺、金剛石等半導體材料製成。作為另外一種選擇，亦可使用化合物材料，例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些的組合等。另外，基底芯體402可為SOI基底。一般而言，SOI基底包括例如磊晶矽、鍺、矽鍺、SOI、絕緣體上有矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料形成的層。在一個替代實施例中，基底芯體402是基於例如被玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料是玻璃纖維樹脂（例如FR4）。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪（bismaleimide-triazine，BT）樹脂，或者作為另外一種選擇，為其他印刷電路板（PCB）材料或膜。可對基底芯體402使用例如味之素構成膜（Ajinomoto Build up Film，ABF）等構成膜或其他疊層。
基底芯體402可包括多個主動裝置及多個被動裝置（未示出）。可使用例如電晶體、電容器、電阻器、該些的組合等各種各樣的裝置來產生所得裝置的設計的結構性要求及功能性要求。可使用任何合適的方法形成所述裝置。
基底芯體402亦可包括多個金屬化層及多個通孔（未示出），其中接合墊404在實體上耦合至及/或電性耦合至所述金屬化層及通孔。金屬化層可形成於主動裝置及被動裝置之上且被設計成連接各個裝置以形成功能性電路系統。金屬化層可由交替的多個介電材料（例如，低介電常數介電材料）層與多個導電材料（例如，銅）層形成，且具有對導電材料層進行內連的多個通孔，並可藉由任何合適的製程（例如沈積、鑲嵌、雙鑲嵌等）形成。在一些實施例中，基底芯體402實質上不具有主動裝置及被動裝置。
在一些實施例中，對導電連接件330進行回焊以將封裝體1000貼合至接合墊404。導電連接件330將封裝基底400（包括基底芯體402中的金屬化層）電性耦合至及/或在實體上耦合至封裝體1000。在一些實施例中，在基底芯體402上形成阻焊劑（solder resist）406。導電連接件330可在阻焊劑406中的多個開口中被設置成電性耦合至及機械耦合至接合墊404。阻焊劑406可用於保護基底芯體402的一些區域免受外部損壞。
在一些實施例中，可在封裝體1000與封裝基底400之間形成底部填充膠408且底部填充膠408環繞導電連接件330。可在將封裝體1000貼合至封裝基底400之後藉由毛細流動製程（capillary flow process）形成底部填充膠408，或者可在將封裝體1000貼合至封裝基底400之前藉由合適的沈積方法形成底部填充膠408。
在一些實施例中，亦可將被動裝置（例如，表面安裝裝置（surface mount device，SMD），未示出）貼合至封裝體1000（例如，貼合至凸塊下金屬328）或者貼合至封裝基底400（例如，貼合至接合墊404）。舉例而言，可將被動裝置接合至封裝體1000或封裝基底400的與導電連接件330相同的表面。被動裝置可在將封裝體1000安裝於封裝基底400上之前貼合至封裝體1000，或者可在將封裝體1000安裝於封裝基底400上之前或之後貼合至封裝基底400。
圖19示出根據一些實施例的接合至封裝基底400的封裝體1100的剖視圖。在一些實施例中，封裝體1100相似於圖18中所示的封裝體1000，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖5至圖18闡述的製程步驟形成封裝體1100，且在本文中不再予以贅述。封裝體1100的晶粒區3100A相似於封裝體1000的晶粒區3000A，區別在於，在製程變動內，晶粒區3100A的包封體310的下表面與穿孔的下表面以及積體電路晶粒10A及10B的後表面實質上齊平。在所示出的實施例中，重佈線結構312的絕緣層314與積體電路晶粒10A及10B的後表面進行實體接觸。在一些實施例中，將包封體310平坦化，使得除穿孔308之外亦暴露出積體電路晶粒10A及10B的後表面。
圖20示出根據一些實施例的接合至封裝基底400的封裝體1200的剖視圖。在一些實施例中，封裝體1200相似於圖18中所示的封裝體1000，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖5至圖18闡述的製程步驟形成封裝體1200，且在本文中不再予以贅述。封裝體1200的晶粒區3200A相似於封裝體1000的晶粒區3000A，區別在於，取代積體電路晶粒10，被包封的是積體電路晶粒30（參見圖3）。在所示出的實施例中，積體電路晶粒30（例如積體電路晶粒（又稱第一積體電路晶粒）30A及積體電路晶粒（又稱第二積體電路晶粒）30B）彼此相鄰地接合至晶粒區100A的後側。積體電路晶粒30A及30B使用導電連接件70接合至重佈線結構302的墊306。第一積體電路晶粒30A可為邏輯裝置，例如CPU、GPU、SoC、微控制器等。在一些實施例中，第一積體電路晶粒30A可包括被配置成用於邊緣AI應用的積體電路。
第二積體電路晶粒30B可為記憶體裝置，例如DRAM晶粒、SRAM晶粒、HMC模組、高頻寬記憶體HBM模組等。在一些實施例中，積體電路晶粒30A與積體電路晶粒30B可為相同類型的晶粒，例如SoC晶粒。第一積體電路晶粒30A與第二積體電路晶粒30B可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，第一積體電路晶粒30A可具有較第二積體電路晶粒30B更先進的製程節點。積體電路晶粒30A與積體電路晶粒30B可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
圖21示出根據一些實施例的接合至封裝基底400的封裝體1300的剖視圖。在一些實施例中，封裝體1300相似於圖20中所示的封裝體1200，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖5至圖18以及圖20闡述的製程步驟形成封裝體1300，且在本文中不再予以贅述。封裝體1300的晶粒區3300A相似於封裝體1200的晶粒區3200A，區別在於，在製程變動內，晶粒區3300A的包封體310的下表面與穿孔308的下表面以及積體電路晶粒30A及30B的後表面實質上齊平。在所示出的實施例中，重佈線結構312的絕緣層314與積體電路晶粒30A及30B的後表面進行實體接觸。在一些實施例中，將包封體310平坦化，使得除穿孔308之外亦暴露出積體電路晶粒30A及30B的後表面。
圖22至圖27示出根據一些實施例的形成封裝體1400的過程期間的中間步驟的剖視圖。參照圖22至圖27闡述的一些特徵及製程步驟可相似於上方參照圖5至圖18闡述的特徵及製程步驟，且在本文中不再對相似的特徵及製程步驟予以贅述。圖22至圖24示出在將晶圓100接合至晶圓200之後，在晶圓100的後側上形成晶圓級封裝結構3400。可如上方參照圖7所述般將晶圓100接合至晶圓200，且在本文中不再予以贅述。
在圖22中，對晶圓100的後側進行薄化以暴露出基底穿孔104，且在晶圓100的後側上形成包括絕緣層304及多個墊306的重佈線結構302。在一些實施例中，如上方參照圖8所述般對晶圓100的後側進行薄化，且在本文中不再予以贅述。在一些實施例中，如上方參照圖9所述般形成重佈線結構302，且在本文中不再予以贅述。隨後，使用重佈線結構302的絕緣層304及墊306將多個積體電路晶粒10（例如，第一積體電路晶粒10A及第二積體電路晶粒10B）接合至晶圓100的後側。在一些實施例中，如上方參照圖11所述般將第一積體電路晶粒10A及第二積體電路晶粒10B接合至晶圓100的後側，且在本文中不再予以贅述。
在圖23中，如上方參照圖12所述般在積體電路晶粒10A及10B上形成圍繞積體電路晶粒10A及10B的包封體310，且在本文中不再予以贅述。
在圖24中，對包封體310執行平坦化製程，以暴露出積體電路晶粒10A及10B的後表面。平坦化製程亦可移除積體電路晶粒10A及10B的後側的一些部分。在平坦化製程的製程變動內，包封體310的頂表面與積體電路晶粒10A及10B的後表面實質上共面或實質上齊平。平坦化製程可包括CMP、磨削、蝕刻、其組合等。
在圖25中，對圖24所示堆疊式晶圓級結構進行翻轉，且使用黏合劑334將堆疊式晶圓級結構貼合至載體基底332。隨後，如上方參照圖15所述般對晶圓200的基底202的後側執行薄化製程，且在本文中不再予以贅述。在執行薄化製程之後，如上方參照圖16所述般在晶圓200的基底202的後側之上形成多個彩色濾光器336，且在本文中不再予以贅述。在一些實施例中，如上方參照圖16所述般在晶圓200的基底202的後表面之上形成壩結構338且壩結構338環繞彩色濾光器336，且在本文中不再予以贅述。隨後，如上方參照圖16所述般將蓋體340貼合至壩結構338，且在本文中不再予以贅述。在一些實施例中，在晶圓200的基底202的後側上形成多個墊346。在一些實施例中，墊346設置於壩結構338以外，但在晶圓200的晶粒區200A以內。在一些實施例中，墊346可包含與上方參照圖1闡述的墊62相似的材料，且在本文中不再予以贅述。墊346可用於將所得封裝體耦合至外部裝置。
在圖26中，將圖25所示堆疊式晶圓級結構自載體基底332（參見圖25）剝離並放置於切割帶342上。隨後，藉由沿多個切割道區（例如，在堆疊式晶圓級結構中相鄰的晶粒區之間）進行鋸切來執行單體化製程344。所述鋸切將多個晶粒區自堆疊式晶圓級結構單體化且形成多個封裝體1400。封裝體1400中的每一者包括晶圓100的晶粒區100A、晶圓200的晶粒區200A及晶圓級封裝結構3400的晶粒區3400A。
在圖27中，使用黏合劑350將封裝體1400貼合至封裝基底400。在一些實施例中，藉由使用多個配線連接件（wire connector）348將封裝體1400的墊346耦合至封裝基底400的接合墊404來將封裝體1400電性耦合至封裝基底400。在一些實施例中，使用熱壓接合（thermocompression bonding）、超音波接合（ultrasonic bonding）、熱超音波接合（thermosonic bonding）等將配線連接件348接合至墊346及接合墊404。
圖28示出根據一些實施例的接合至封裝基底400的封裝體1500的剖視圖。在一些實施例中，封裝體1500相似於圖27中所示的封裝體1400，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖22至圖27闡述的製程步驟形成封裝體1500，且在本文中不再予以贅述。封裝體1500的晶粒區3500A相似於封裝體1400的晶粒區3400A，區別在於，包封體310的一部分插置於黏合劑350與積體電路晶粒10A及10B的後側之間。在此種實施例中，將包封體310平坦化，使得在執行平坦化製程之後，積體電路晶粒10A及10B的後側不被暴露出。
圖29示出根據一些實施例的接合至封裝基底400的封裝體1600的剖視圖。在一些實施例中，封裝體1600相似於圖27中所示的封裝體1400，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖22至圖27闡述的製程步驟形成封裝體1600，且在本文中不再予以贅述。封裝體1600的晶粒區3600A相似於封裝體1400的晶粒區3400A，區別在於，取代積體電路晶粒10，被包封的是積體電路晶粒30（參見圖3）。在所示出的實施例中，積體電路晶粒30（例如第一積體電路晶粒30A及第二積體電路晶粒30B）彼此相鄰地接合至晶粒區100A的後側。積體電路晶粒30A及30B使用導電連接件70接合至重佈線結構302的墊306。第一積體電路晶粒30A可為邏輯裝置，例如CPU、GPU、SoC、微控制器等。在一些實施例中，第一積體電路晶粒30A可包括被配置成用於邊緣AI應用的積體電路。
第二積體電路晶粒30B可為記憶體裝置，例如DRAM晶粒、SRAM晶粒、HMC模組、高頻寬記憶體HBM模組等。在一些實施例中，積體電路晶粒30A與積體電路晶粒30B可為相同類型的晶粒，例如SoC晶粒。第一積體電路晶粒30A與第二積體電路晶粒30B可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，第一積體電路晶粒30A可具有較第二積體電路晶粒30B更先進的製程節點。積體電路晶粒30A與積體電路晶粒30B可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
圖30示出根據一些實施例的接合至封裝基底400的封裝體1700的剖視圖。在一些實施例中，封裝體1700相似於圖29中所示的封裝體1600，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖22至圖27以及圖29闡述的製程步驟形成封裝體1700，且在本文中不再予以贅述。封裝體1700的晶粒區3700A相似於封裝體1600的晶粒區3600A（參見圖29），區別在於，包封體310的一部分插置於黏合劑350與積體電路晶粒30A及30B的後側之間。在此種實施例中，將包封體310平坦化，使得在執行平坦化製程之後，積體電路晶粒30A及30B的後側不被暴露出。
圖31至圖36示出根據一些實施例的形成封裝體1800的過程期間的中間步驟的剖視圖。參照圖31至圖36闡述的一些特徵及製程步驟可相似於上方參照圖5至圖18闡述的特徵及製程步驟，且在本文中不再對相似的特徵及製程步驟予以贅述。圖31至圖33示出在將晶圓100接合至晶圓200之後，在晶圓100的後側上形成晶圓級封裝結構3800。晶圓級封裝結構3800亦可被稱為晶圓級積體扇出型（InFO）結構。可如上方參照圖7所述般將晶圓100接合至晶圓200，且在本文中不再予以贅述。
在圖31中，對晶圓100的後側進行薄化以暴露出基底穿孔104，且在薄化之後在晶圓100的後側上形成包括絕緣層304及多個墊306的重佈線結構302。在一些實施例中，如上方參照圖8所述般對晶圓100的後側進行薄化，且在本文中不再予以贅述。在一些實施例中，如上方參照圖9所述般形成重佈線結構302，且在本文中不再予以贅述。
隨後，將多個積體電路晶粒20（參見圖2）（例如，積體電路晶粒（又稱第一積體電路晶粒）20A及積體電路晶粒（又稱第二積體電路晶粒）20B）接合至晶圓100的後側。將期望的類型及數量的積體電路晶粒20接合於晶圓100的多個晶粒區中的每一者（例如晶粒區100A）中。在所示出的實施例中，第一積體電路晶粒20A與第二積體電路晶粒20B彼此相鄰地接合。第一積體電路晶粒20A可為邏輯裝置，例如CPU、GPU、SoC、微控制器等。在一些實施例中，第一積體電路晶粒20A可包括被配置成用於邊緣AI應用的積體電路。
第二積體電路晶粒20B可為記憶體裝置，例如DRAM晶粒、SRAM晶粒、HMC模組、HBM模組等。在一些實施例中，積體電路晶粒20A與積體電路晶粒20B可為相同類型的晶粒，例如SoC晶粒。第一積體電路晶粒20A與第二積體電路晶粒20B可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，第一積體電路晶粒20A可具有較第二積體電路晶粒20B更先進的製程節點。積體電路晶粒20A與積體電路晶粒20B可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
在一些實施例中，使用混合接合方法將積體電路晶粒20A及20B接合至重佈線結構302的絕緣層304及墊306。混合接合方法包括將積體電路晶粒20A及20B的墊62直接接合至重佈線結構302的相應的墊306以及將積體電路晶粒20A及20B的絕緣層64直接接合至重佈線結構302的絕緣層304。
在圖32中，如上方參照圖12所述般在積體電路晶粒20A及20B上形成圍繞積體電路晶粒20A及20B的包封體310，且在本文中不再予以贅述。隨後，對包封體310執行平坦化製程以暴露出積體電路晶粒20A及20B的後表面。平坦化製程亦暴露出積體電路晶粒20A及20B的基底穿孔66。平坦化製程亦可移除積體電路晶粒20A及20B的後側的一些部分以及基底穿孔66的一些部分。在平坦化製程的製程變動內，包封體310的頂表面、積體電路晶粒20A及20B的後表面以及基底穿孔66的被暴露出的表面實質上共面或實質上齊平。平坦化製程可包括CMP、磨削、蝕刻、其組合等。
在圖33中，在包封體310以及積體電路晶粒20A及20B之上形成重佈線結構502。重佈線結構502包括多個絕緣層504、508、512及516以及多個金屬化圖案506、510及514。金屬化圖案亦可被稱為重佈線層或重佈線走線。重佈線結構502被示出為具有三層金屬化圖案的實例。可在重佈線結構502中形成更多或更少的絕緣層及金屬化圖案。可使用與上方參照圖14闡述的重佈線結構312相似的材料及方法形成重佈線結構502，且在本文中不再予以贅述。可使用與上方參照圖14闡述的絕緣層314相似的材料及方法形成絕緣層504、508、512及516，且在本文中不再予以贅述。可使用與上方參照圖14闡述的金屬化圖案316相似的材料及方法形成金屬化圖案506、510及514，且在本文中不再予以贅述。在形成重佈線結構502之後，如上方參照圖14所述般在重佈線結構502之上形成多個凸塊下金屬328及對應的多個導電連接件330，且在本文中不再予以贅述。
在圖34中，對圖33所示堆疊式晶圓級結構進行翻轉，且使用黏合劑334將堆疊式晶圓級結構貼合至載體基底332。隨後，如上方參照圖15所述般對晶圓200的基底202的後側執行薄化製程，且在本文中不再予以贅述。在執行薄化製程之後，如上方參照圖16所述般在晶圓200的基底202的後側之上形成彩色濾光器336，且在本文中不再予以贅述。在一些實施例中，如上方參照圖16所述般在晶圓200的基底202的後側之上形成壩結構338且壩結構338環繞彩色濾光器336，且在本文中不再予以贅述。隨後，如上方參照圖16所述般將蓋體340貼合至壩結構338，且在本文中不再予以贅述。
在圖35中，將圖34所示堆疊式晶圓級結構自載體基底332（參見圖34）剝離並放置於切割帶342上。隨後，藉由沿多個切割道區（例如，在堆疊式晶圓級結構中相鄰的晶粒區之間）進行鋸切來執行單體化製程344。所述鋸切將多個晶粒區自堆疊式晶圓級結構單體化且形成多個封裝體1800。封裝體1800中的每一者包括晶圓100的晶粒區100A、晶圓200的晶粒區200A及晶圓級封裝結構3800的晶粒區3800A。
在圖36中，如上方參照圖18所述般使用導電連接件330將封裝體1800貼合至封裝基底400。隨後，如上方參照圖18所述般在封裝體1800與封裝基底400之間形成底部填充膠408且底部填充膠408環繞導電連接件330。
圖37示出根據一些實施例的接合至封裝基底400的封裝體1900的剖視圖。在一些實施例中，封裝體1900相似於圖36中所示的封裝體1800，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖31至圖36闡述的製程步驟形成封裝體1900，且在本文中不再予以贅述。封裝體1900的晶粒區3900A相似於封裝體1800的晶粒區3800A，區別在於，取代積體電路晶粒20，被包封得是積體電路晶粒40（參見圖4）。在所示出的實施例中，積體電路晶粒40（例如積體電路晶粒（又稱第一積體電路晶粒）40A及積體電路晶粒（又稱第二積體電路晶粒）40B）彼此相鄰地接合至晶粒區100A的後側。積體電路晶粒40A及40B使用導電連接件70接合至重佈線結構302的墊306。第一積體電路晶粒40A可為邏輯裝置，例如CPU、GPU、SoC、微控制器等。在一些實施例中，第一積體電路晶粒40A可包括被配置成用於邊緣AI應用的積體電路。
第二積體電路晶粒40B可為記憶體裝置，例如DRAM晶粒、SRAM晶粒、HMC模組、高頻寬記憶體HBM模組等。在一些實施例中，積體電路晶粒40A與積體電路晶粒40B可為相同類型的晶粒，例如SoC晶粒。第一積體電路晶粒40A與第二積體電路晶粒40B可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，第一積體電路晶粒40A可具有較第二積體電路晶粒40B更先進的製程節點。積體電路晶粒40A與積體電路晶粒40B可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
圖38至圖43示出根據一些實施例的形成封裝體2000的過程期間的中間步驟的剖視圖。參照圖33至圖43闡述的一些特徵及製程步驟可相似於上方參照圖5至圖18闡述的特徵及製程步驟，且在本文中不再對相似的特徵及製程步驟予以贅述。圖38至圖40示出在將晶圓100接合至晶圓200之後，在晶圓100的後側上形成晶圓級封裝結構4000。晶圓級封裝結構4000亦可被稱為晶圓級積體扇出型（InFO）結構。可如上方參照圖7所述般將晶圓100接合至晶圓200，且在本文中不再予以贅述。
在圖38中，對晶圓100的後側進行薄化以暴露出基底穿孔104，且在薄化之後在晶圓100的後側上形成包括絕緣層304及多個墊306的重佈線結構302。在一些實施例中，如上方參照圖8所述般對晶圓100的後側進行薄化，且在本文中不再予以贅述。在一些實施例中，如上方參照圖9所述般形成重佈線結構302，且在本文中不再予以贅述。在形成重佈線結構302之後，如上方參照圖10所述般在重佈線結構302的墊306之上形成多個穿孔308，且在本文中不再予以贅述。
隨後，將多個晶粒堆疊（例如包括積體電路晶粒10及積體電路晶粒20的晶粒堆疊606）接合至晶圓100的後側。積體電路晶粒20可為邏輯裝置，例如CPU、GPU、SoC、微控制器等。在一些實施例中，積體電路晶粒20可包括被配置成用於邊緣AI應用的積體電路。積體電路晶粒10可為記憶體裝置，例如DRAM晶粒、SRAM晶粒、HMC模組、HBM模組等。積體電路晶粒10與積體電路晶粒20可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，積體電路晶粒20可具有較積體電路晶粒10更先進的製程節點。積體電路晶粒10與積體電路晶粒20可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
在一些實施例中，藉由將積體電路晶粒10接合至積體電路晶粒20來形成晶粒堆疊606。在一些實施例中，在積體電路晶粒20的後側上形成絕緣層604及多個墊602。可分別使用與上方參照圖1闡述的絕緣層64及墊62相似的材料及方法形成絕緣層604及墊602，且在本文中不再予以贅述。可使用混合接合方法將積體電路晶粒10接合至積體電路晶粒20。混合接合方法包括將積體電路晶粒10的墊62直接接合至積體電路晶粒20的相應的墊602以及將積體電路晶粒10的絕緣層64直接接合至積體電路晶粒20的絕緣層604。
在形成晶粒堆疊606之後，使用混合接合方法將晶粒堆疊606貼合至晶圓100的後側。混合接合方法包括將積體電路晶粒20的墊62直接接合至重佈線結構302的相應的墊306以及將積體電路晶粒20的絕緣層64直接接合至重佈線結構302的絕緣層304。
在圖39中，如上方參照圖12所述般在晶粒堆疊606及穿孔308上形成圍繞晶粒堆疊606及穿孔308的包封體310，且在本文中不再予以贅述。
在圖40中，對包封體310執行平坦化製程以暴露出穿孔308。在一些實施例中，在執行平坦化製程之後，包封體310的一部分覆蓋積體電路晶粒10的後側。平坦化製程亦可移除穿孔308的一些部分。在平坦化製程的製程變動內，包封體310的頂表面與穿孔308的被暴露出的表面實質上共面或實質上齊平。平坦化製程可包括CMP、磨削、蝕刻、其組合等。在執行平坦化製程之後，如上方參照圖14所述般在包封體310及穿孔308之上形成重佈線結構312，且在本文中不再予以贅述。在形成重佈線結構312之後，如上方參照圖14所述般在重佈線結構312之上形成多個凸塊下金屬328及對應的多個導電連接件330，且在本文中不再予以贅述。
在圖41中，對圖40所示堆疊式晶圓級結構進行翻轉，且使用黏合劑334將堆疊式晶圓級結構貼合至載體基底332。隨後，如上方參照圖15所述般對晶圓200的基底202的後側執行薄化製程，且在本文中不再予以贅述。在執行薄化製程之後，如上方參照圖16所述般在晶圓200的基底202的後側之上形成彩色濾光器336，且在本文中不再予以贅述。在一些實施例中，如上方參照圖16所述般在晶圓200的基底202的後側之上形成壩結構338且壩結構338環繞彩色濾光器336，且在本文中不再予以贅述。隨後，如上方參照圖16所述般將蓋體340貼合至壩結構338，且在本文中不再予以贅述。
在圖42中，將圖41所示堆疊式晶圓級結構自載體基底332（參見圖41）剝離並放置於切割帶342上。隨後，藉由沿多個切割道區（例如，在堆疊式晶圓級結構中相鄰的晶粒區之間）進行鋸切來執行單體化製程344。所述鋸切將多個晶粒區自堆疊式晶圓級結構單體化且形成多個封裝體2000。封裝體2000中的每一者包括晶圓100的晶粒區100A、晶圓200的晶粒區200A及晶圓級封裝結構4000的晶粒區4000A。
在圖43中，如上方參照圖18所述般使用導電連接件330將封裝體2000貼合至封裝基底400。隨後，如上方參照圖18所述般在封裝體2000與封裝基底400之間形成底部填充膠408且底部填充膠408環繞導電連接件330。
圖44示出根據一些實施例的接合至封裝基底400的封裝體2100的剖視圖。在一些實施例中，封裝體2100相似於圖43中所示的封裝體2000，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖38至圖43闡述的製程步驟形成封裝體2100，且在本文中不再予以贅述。封裝體2100的晶粒區4100A相似於封裝體2000的晶粒區4000A，區別在於，晶粒區4100A的包封體310的下表面與穿孔308的下表面及晶粒堆疊606的積體電路晶粒10的後表面實質上共面或實質上齊平。在所示出的實施例中，重佈線結構312的絕緣層314與積體電路晶粒10的後表面進行實體接觸。在此種實施例中，將包封體310平坦化，使得除穿孔308之外亦暴露出積體電路晶粒10的後表面。
圖45示出根據一些實施例的接合至封裝基底400的封裝體2200的剖視圖。在一些實施例中，封裝體2200相似於圖43中所示的封裝體2000，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖38至圖43闡述的製程步驟形成封裝體2200，且在本文中不再予以贅述。封裝體2200的晶粒區4200A相似於封裝體2000的晶粒區4000A，區別在於，取代晶粒堆疊606，被包封的是晶粒堆疊608。晶粒堆疊608包括接合至積體電路晶粒40（參見圖4）的積體電路晶粒10（參見圖1）。在一些實施例中，使用上方參照圖38闡述的混合接合方法將積體電路晶粒10接合至積體電路晶粒40，且在本文中不再予以贅述。晶粒堆疊608使用積體電路晶粒40的導電連接件70接合至重佈線結構302的墊306。積體電路晶粒40可為邏輯裝置，例如CPU、GPU、SoC、微控制器等。在一些實施例中，積體電路晶粒40可包括被配置成用於邊緣AI應用的積體電路。
積體電路晶粒10可為記憶體裝置，例如DRAM晶粒、SRAM晶粒、HMC模組、高頻寬記憶體HBM模組等。在一些實施例中，積體電路晶粒10與積體電路晶粒40可為相同類型的晶粒，例如SoC晶粒。積體電路晶粒10與積體電路晶粒40可在相同技術節點的製程中形成，或者可在不同技術節點的製程中形成。舉例而言，積體電路晶粒40可具有較積體電路晶粒10更先進的製程節點。積體電路晶粒10與積體電路晶粒40可具有不同的大小（例如，不同的高度及/或表面積），或者可具有相同的大小（例如，相同的高度及/或表面積）。
圖46示出根據一些實施例的接合至封裝基底400的封裝體2300的剖視圖。在一些實施例中，封裝體2300相似於圖45中所示的封裝體2200，其中相似的特徵標記有相似的數字參考編號，且在本文中不再對相似的特徵予以贅述。在一些實施例中，可使用上方參照圖38至圖43闡述的製程步驟形成封裝體2300，且在本文中不再予以贅述。封裝體2300的晶粒區4300A相似於封裝體2200的晶粒區4200A，區別在於，晶粒區4300A的包封體310的下表面與穿孔308的下表面及晶粒堆疊608的積體電路晶粒10的後表面實質上共面或實質上齊平。在所示出的實施例中，重佈線結構312的絕緣層314與積體電路晶粒10的後表面進行實體接觸。在此種實施例中，將包封體310平坦化，使得除穿孔308之外亦暴露出積體電路晶粒10的後表面。
圖47是示出根據一些實施例的形成封裝體的方法4700的流程圖。方法4700自步驟4701開始，在步驟4701中，將邏輯晶圓（例如圖7中所示的晶圓100）接合至影像感測器晶圓（例如圖7中所示的晶圓200），如上方參照圖7所述。在步驟4703中，在邏輯晶圓的後側上形成第一重佈線結構（例如圖9中所示的重佈線結構302），如上方參照圖9所述。在步驟4705中，在第一重佈線結構上形成第一導電柱（例如圖10中所示的穿孔308）及第二導電柱（例如圖10中所示的穿孔308），如上方參照圖10所述。在步驟4707中，將第一積體電路晶粒（例如圖11中所示的積體電路晶粒10A）及第二積體電路晶粒（例如圖11中所示的積體電路晶粒10B）接合至第一重佈線結構，如上方參照圖11所述。在一些實施例中，第一積體電路晶粒是邏輯晶粒。在一些實施例中，使用混合接合方法將第一積體電路晶粒及第二積體電路晶粒接合至第一重佈線結構。在其他實施例中，使用導電連接件將第一積體電路晶粒及第二積體電路晶粒接合至第一重佈線結構。在又一些其他實施例中，將第一積體電路晶粒及第二積體電路晶粒接合至第一重佈線結構，使得第一積體電路晶粒與第二積體電路晶粒在第一重佈線結構之上形成晶粒堆疊。在步驟4709中，將第一積體電路晶粒及第二積體電路晶粒包封於包封體（例如圖12中所示的包封體310）中，如上方參照圖12所述。在步驟4711中，在包封體、第一積體電路晶粒及第二積體電路晶粒以及第一導電柱及第二導電柱之上形成第二重佈線結構（例如圖14中所示的重佈線結構302），如上方參照圖14所述。在步驟4713中，在影像感測器晶圓的後側上形成彩色濾光器（例如圖16中所示的彩色濾光器336），如上方參照圖16所述。在步驟4715中，形成圍繞彩色濾光器的壩結構（例如圖16中所示的壩結構338），如上方參照圖16所述。在步驟4717中，將蓋體（例如圖16中所示的蓋體340）貼合至彩色濾光器之上的壩結構，如上方參照圖16所述。在其他實施例中，可省略步驟4705。在又一些其他實施例中，可省略步驟4705及4711。
亦可包括其他特徵及製程。舉例而言，可包括測試結構以幫助對三維（three-dimensional，3D）封裝體或三維積體電路（three-dimensional integrated circuit，3DIC）裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試墊（test pad），以便能夠對3D封裝或3DIC裝置進行測試、使用探針及/或探針卡（probe card）等。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可與包含對已知良好晶粒進行中間驗證的測試方法接合使用以提高良率並降低成本。
根據實施例，一種半導體裝置包括：第一邏輯晶粒，包括第一穿孔；影像感測器晶粒，混合接合至所述第一邏輯晶粒，所述第一邏輯晶粒的前側面對所述影像感測器晶粒的前側；以及第二邏輯晶粒，接合至所述第一邏輯晶粒，所述第二邏輯晶粒的前側面對所述第一邏輯晶粒的後側，所述第二邏輯晶粒包括電性耦合至所述第一穿孔的第一導電墊。在一個實施例中，所述第二邏輯晶粒混合接合至所述第一邏輯晶粒。在一個實施例中，所述第二邏輯晶粒使用多個第一連接件接合至所述第一邏輯晶粒。在一個實施例中，所述半導體裝置更包括記憶體晶粒，所述記憶體晶粒接合至所述第一邏輯晶粒，所述記憶體晶粒的前側面對所述第一邏輯晶粒的所述後側。在一個實施例中，記憶體晶粒混合接合至所述第一邏輯晶粒。在一個實施例中，記憶體晶粒使用多個第二連接件接合至所述第一邏輯晶粒。在一個實施例中，所述半導體裝置更包括記憶體晶粒，所述記憶體晶粒混合接合至所述第二邏輯晶粒，所述記憶體晶粒的前側面對所述第二邏輯晶粒的後側。
根據另一實施例，一種半導體裝置包括：第一邏輯晶粒，所述第一邏輯晶粒的前側包括第一絕緣層及第一導電墊，所述第一邏輯晶粒的後側包括第二絕緣層及第二導電墊；影像感測器晶粒，接合至所述第一邏輯晶粒，所述影像感測器晶粒的前側包括第三絕緣層及第三導電墊，所述第三導電墊與所述第一導電墊實體接觸，所述第三絕緣層與所述第一絕緣層實體接觸；以及第二邏輯晶粒，接合至所述第一邏輯晶粒，所述第二邏輯晶粒的前側包括第四絕緣層及第四導電墊，所述第四絕緣層面對所述第二絕緣層。在一個實施例中，所述第二絕緣層與所述第四絕緣層實體接觸，且所述第二導電墊與所述第四導電墊實體接觸。在一個實施例中，所述半導體裝置更包括導電連接件，所述導電連接件將所述第二導電墊電性耦合至及機械耦合至所述第四導電墊。在一個實施例中，所述半導體裝置更包括包封體，所述包封體沿所述第二邏輯晶粒的側壁延伸。在一個實施例中，所述半導體裝置更包括穿孔，所述穿孔延伸穿過與所述第二邏輯晶粒相鄰的所述包封體。在一個實施例中，所述半導體裝置更包括重佈線結構，所述重佈線結構電性耦合至所述穿孔，所述第二邏輯晶粒插置於所述重佈線結構與所述第一邏輯晶粒之間。在一個實施例中，所述包封體的一部分插置於所述第二邏輯晶粒與所述重佈線結構之間。
根據又一實施例，一種方法包括將邏輯晶圓接合至影像感測器晶圓。所述邏輯晶圓的前側包括第一導電墊。所述影像感測器晶圓的前側包括第二導電墊。將所述邏輯晶圓接合至所述影像感測器晶圓包括將所述第一導電墊直接接合至所述第二導電墊。在所述邏輯晶圓的後側上形成第一重佈線結構。將邏輯晶粒接合至所述第一重佈線結構。所述邏輯晶粒的前側包括第三導電墊。所述第三導電墊電性耦合至所述第一重佈線結構。在一個實施例中，將所述邏輯晶粒接合至所述第一重佈線結構包括：將所述邏輯晶粒的所述第三導電墊直接接合至所述第一重佈線結構的第四導電墊。在一個實施例中，將所述邏輯晶粒接合至所述第一重佈線結構包括：使用導電連接件將所述邏輯晶粒的所述第三導電墊電性耦合至及機械耦合至所述第一重佈線結構的第四導電墊。在一個實施例中，所述方法更包括在所述第一重佈線結構上以及形成圍繞所述邏輯晶粒的包封體。在一個實施例中，所述方法更包括：形成與所述第一重佈線結構電性接觸的第二重佈線結構，所述邏輯晶粒插置於所述第一重佈線結構與所述第二重佈線結構之間。在一個實施例中，所述方法更包括：在將所述邏輯晶粒接合至所述第一重佈線結構之前，在所述第一重佈線結構之上形成導電柱，所述導電柱將所述第一重佈線結構電性耦合至所述第二重佈線結構。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替及變更。
10、20、30、40:積體電路晶粒 10A、20A、30A、40A:第一積體電路晶粒/積體電路晶粒 10B、20B、30B、40B:第二積體電路晶粒/積體電路晶粒 52、102、202:基底 54、106、206:裝置 56、108、208:層間介電質 58、110、210:導電插頭 60、112、212:內連結構 62、114、214、306、346、602:墊 64、116、216、304、314、318、322、326、504、508、512、516、604:絕緣層 66、104:基底穿孔 68、328:凸塊下金屬 70:導電連接件 100、200:晶圓 100A、200A、3000A、3100A、3200A、3300A、3400A、3500A、3600A、3700A、3800A、3900A、4000A、4100A、4200A、4300A:晶粒區 218:感光性畫素 220:隔離區 302、312、502:重佈線結構 308:穿孔 310:包封體 316、320、324、506、510、514:金屬化圖案 330:導電連接件 332:載體基底 334、350:黏合劑 336:彩色濾光器 338:壩結構 340:蓋體 342:切割帶 344:單體化製程 348:配線連接件 400:封裝基底 402:基底芯體 404:接合墊 406:阻焊劑 408:底部填充膠 606、608:晶粒堆疊 1000、1100、1200、1300、1400、1500、1600、1700、1800、1900、2000、2100、2200、2300:封裝體 3000、3400、3800、4000:晶圓級封裝結構 4700:方法 4701、4703、4705、4707、4709、4711、4713、4715、4717:步驟
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出根據一些實施例的積體電路晶粒的剖視圖。 圖2示出根據一些實施例的積體電路晶粒的剖視圖。 圖3示出根據一些實施例的積體電路晶粒的剖視圖。 圖4示出根據一些實施例的積體電路晶粒的剖視圖。 圖5至圖18示出根據一些實施例的形成封裝體的過程期間的中間步驟的剖視圖。 圖19示出根據一些實施例的封裝體的剖視圖。 圖20示出根據一些實施例的封裝體的剖視圖。 圖21示出根據一些實施例的封裝體的剖視圖。 圖22至圖27示出根據一些實施例的形成封裝體的過程期間的中間步驟的剖視圖。 圖28示出根據一些實施例的封裝體的剖視圖。 圖29示出根據一些實施例的封裝體的剖視圖。 圖30示出根據一些實施例的封裝體的剖視圖。 圖31至圖36示出根據一些實施例的形成封裝體的過程期間的中間步驟的剖視圖。 圖37示出根據一些實施例的封裝體的剖視圖。 圖38至圖43示出根據一些實施例的形成封裝體的過程期間的中間步驟的剖視圖。 圖44示出根據一些實施例的封裝體的剖視圖。 圖45示出根據一些實施例的封裝體的剖視圖。 圖46示出根據一些實施例的封裝體的剖視圖。 圖47是示出根據一些實施例的形成封裝體的方法的流程圖。
10A:第一積體電路晶粒/積體電路晶粒
10B:第二積體電路晶粒/積體電路晶粒
52、102、202:基底
60、112、212:內連結構
62、114、214、306:墊
64、116、216、304:絕緣層
100A、200A、3000A:晶粒區
104:基底穿孔
106、206:裝置
108、208:層間介電質
110、210:導電插頭
218:感光性畫素
220:隔離區
302、312:重佈線結構
308:穿孔
310:包封體
328:凸塊下金屬
330:導電連接件/連接件
336:彩色濾光器
338:壩結構
340:蓋體
400:封裝基底
402:基底芯體
404:接合墊/墊
406:阻焊劑
408:底部填充膠
1000:封裝體

Claims (20)

  1. 一種半導體裝置，包括： 第一邏輯晶粒，包括第一穿孔； 影像感測器晶粒，混合接合至所述第一邏輯晶粒，所述第一邏輯晶粒的前側面對所述影像感測器晶粒的前側；以及 第二邏輯晶粒，接合至所述第一邏輯晶粒，所述第二邏輯晶粒的前側面對所述第一邏輯晶粒的後側，所述第二邏輯晶粒包括電性耦合至所述第一穿孔的第一導電墊。
  2. 如請求項1所述的半導體裝置，其中所述第二邏輯晶粒混合接合至所述第一邏輯晶粒。
  3. 如請求項1所述的半導體裝置，其中所述第二邏輯晶粒使用多個第一連接件接合至所述第一邏輯晶粒。
  4. 如請求項1所述的半導體裝置，更包括記憶體晶粒，所述記憶體晶粒接合至所述第一邏輯晶粒，所述記憶體晶粒的前側面對所述第一邏輯晶粒的所述後側。
  5. 如請求項4所述的半導體裝置，其中所述記憶體晶粒混合接合至所述第一邏輯晶粒。
  6. 如請求項4所述的半導體裝置，其中所述記憶體晶粒使用多個第二連接件接合至所述第一邏輯晶粒。
  7. 如請求項1所述的半導體裝置，更包括記憶體晶粒，所述記憶體晶粒混合接合至所述第二邏輯晶粒，所述記憶體晶粒的前側面對所述第二邏輯晶粒的後側。
  8. 一種半導體裝置，包括： 第一邏輯晶粒，所述第一邏輯晶粒的前側包括第一絕緣層及第一導電墊，所述第一邏輯晶粒的後側包括第二絕緣層及第二導電墊； 影像感測器晶粒，接合至所述第一邏輯晶粒，所述影像感測器晶粒的前側包括第三絕緣層及第三導電墊，所述第三導電墊與所述第一導電墊實體接觸，所述第三絕緣層與所述第一絕緣層實體接觸；以及 第二邏輯晶粒，接合至所述第一邏輯晶粒，所述第二邏輯晶粒的前側包括第四絕緣層及第四導電墊，所述第四絕緣層面對所述第二絕緣層。
  9. 如請求項8所述的半導體裝置，其中所述第二絕緣層與所述第四絕緣層實體接觸，且其中所述第二導電墊與所述第四導電墊實體接觸。
  10. 如請求項8所述的半導體裝置，更包括導電連接件，所述導電連接件將所述第二導電墊電性耦合至及機械耦合至所述第四導電墊。
  11. 如請求項8所述的半導體裝置，更包括包封體，所述包封體沿所述第二邏輯晶粒的側壁延伸。
  12. 如請求項11所述的半導體裝置，更包括穿孔，所述穿孔延伸穿過與所述第二邏輯晶粒相鄰的所述包封體。
  13. 如請求項12所述的半導體裝置，更包括重佈線結構，所述重佈線結構電性耦合至所述穿孔，所述第二邏輯晶粒插置於所述重佈線結構與所述第一邏輯晶粒之間。
  14. 如請求項13所述的半導體裝置，其中所述包封體的一部分插置於所述第二邏輯晶粒與所述重佈線結構之間。
  15. 一種方法，包括： 將邏輯晶圓接合至影像感測器晶圓，所述邏輯晶圓的前側包括第一導電墊，所述影像感測器晶圓的前側包括第二導電墊，其中將所述邏輯晶圓接合至所述影像感測器晶圓包括將所述第一導電墊直接接合至所述第二導電墊； 在所述邏輯晶圓的後側上形成第一重佈線結構；以及 將邏輯晶粒接合至所述第一重佈線結構，所述邏輯晶粒的前側包括第三導電墊，其中所述第三導電墊電性耦合至所述第一重佈線結構。
  16. 如請求項15所述的方法，其中將所述邏輯晶粒接合至所述第一重佈線結構包括將所述邏輯晶粒的所述第三導電墊直接接合至所述第一重佈線結構的第四導電墊。
  17. 如請求項15所述的方法，其中將所述邏輯晶粒接合至所述第一重佈線結構包括使用導電連接件將所述邏輯晶粒的所述第三導電墊電性耦合至及機械耦合至所述第一重佈線結構的第四導電墊。
  18. 如請求項15所述的方法，更包括： 在所述第一重佈線結構上形成圍繞所述邏輯晶粒的包封體。
  19. 如請求項15所述的方法，更包括： 形成與所述第一重佈線結構電性接觸的第二重佈線結構，所述邏輯晶粒插置於所述第一重佈線結構與所述第二重佈線結構之間。
  20. 如請求項19所述的方法，更包括： 在將所述邏輯晶粒接合至所述第一重佈線結構之前，在所述第一重佈線結構之上形成導電柱，所述導電柱將所述第一重佈線結構電性耦合至所述第二重佈線結構。
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