TW202129907A - 被動元件模組 - Google Patents
被動元件模組 Download PDFInfo
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- TW202129907A TW202129907A TW109117102A TW109117102A TW202129907A TW 202129907 A TW202129907 A TW 202129907A TW 109117102 A TW109117102 A TW 109117102A TW 109117102 A TW109117102 A TW 109117102A TW 202129907 A TW202129907 A TW 202129907A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 434
- 239000011229 interlayer Substances 0.000 claims abstract description 62
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 239000008393 encapsulating agent Substances 0.000 abstract 4
- 235000012431 wafers Nutrition 0.000 description 259
- 239000010410 layer Substances 0.000 description 139
- 238000000034 method Methods 0.000 description 33
- 239000000463 material Substances 0.000 description 29
- 238000004519 manufacturing process Methods 0.000 description 25
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 24
- 239000000758 substrate Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 239000011241 protective layer Substances 0.000 description 14
- 230000000149 penetrating effect Effects 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- JMYNPQVCVQVODQ-OWOJBTEDSA-N 1,3-dichloro-5-[(e)-2-(4-chlorophenyl)ethenyl]benzene Chemical compound C1=CC(Cl)=CC=C1\C=C\C1=CC(Cl)=CC(Cl)=C1 JMYNPQVCVQVODQ-OWOJBTEDSA-N 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 7
- 101150094737 pdm2 gene Proteins 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005672 polyolefin resin Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/224—Housing; Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一種被動元件模組包含第一層級、第二層級以及連接端子。第一層級包含第一半導體晶片和第一封裝體。第一半導體晶片具有接觸柱。封裝體封裝第一半導體晶片。第二層級設置在第一層級上,且包含第二半導體晶片、層間貫穿壁以及第二封裝體。層間貫穿壁定位成在第二半導體晶片的側壁旁側並面向第二半導體晶片的側壁,且電性連接到接觸柱。第二封裝體封裝第二半導體晶片和層間貫穿壁。連接端子設置在第二層級上方且經由層間貫穿壁電性連接到第一半導體晶片。第一半導體晶片和第二半導體晶片包含被動元件。
Description
本發明的實施例是有關於一種被動元件模組。
通常在單個半導體晶圓上製造用於各種電子裝置的半導體元件和積體電路,所述電子裝置例如行動電話和其它移動電子設備。晶圓的晶粒可在晶圓級與其它半導體元件或晶粒一起處理和封裝,且已針對晶圓級封裝研發各種技術和應用。多個半導體元件的整合已成為所述領域中的挑戰。為響應於對於小型化、更高速度以及更好電氣性能(例如更低傳輸損耗和插入損耗)的增大的需求,積極研究更具創造性的封裝和組裝技術。
本發明實施例的一種被動元件模組,包括:第一層級,包含:第一半導體晶片,具有接觸柱;以及第一封裝體,封裝所述第一半導體晶片;第二層級,設置在所述第一層級上且包含:第二半導體晶片;層間貫穿壁,位於所述第二半導體晶片的側壁旁側並面向所述第二半導體晶片的側壁,且電性連接到所述接觸柱;以及第二封裝體,封裝所述第二半導體晶片和所述層間貫穿壁;以及連接端子,設置在所述第二層級上方且經由所述層間貫穿壁電性連接到所述第一半導體晶片,其中所述第一半導體晶片和所述第二半導體晶片包含被動元件。
本發明實施例的一種半導體封裝,包括:第一重佈線結構,具有第一側和與所述第一側相對的第二側;半導體晶粒,設置在所述重佈線結構的所述第一側上;導電端子,設置在所述重佈線結構的所述第二側上;以及被動元件模組,設置在所述重佈線結構的所述第二側上,所述被動元件模組包含:第一半導體晶片;第一層間貫穿壁,設置在所述第一半導體晶片旁側;第一封裝體,橫向環繞所述第一半導體晶片和所述第一層間貫穿壁;第二半導體晶片,與所述第一半導體晶片豎直地堆疊且電性連接到所述第一層間貫穿壁;第二封裝體,橫向環繞所述第二半導體晶片;以及連接端子,其中至少一個連接端子與所述第一層間貫穿壁中的一個層間貫穿壁接觸,其中所述第一半導體晶片和所述第二半導體晶片包含被動元件。
本發明實施例的一種被動元件模組的製造方法,包括:設置第一半導體晶片;將所述第一半導體晶片封裝在第一封裝體中;在所述第一封裝體上方形成第一層間貫穿壁,其中所述第一層間貫穿壁與所述第一半導體晶片電性連接;設置豎直地堆疊在所述第一半導體晶片上的第二半導體晶片;形成封裝所述第二半導體晶片和所述第一層間貫穿壁的第二封裝體;以及形成經由所述第一層間貫穿壁電性連接到所述第一半導體晶片的連接端子,其中所述第一半導體晶片和所述第二半導體晶片包含被動元件。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同實施例或實例。下文描述組件和佈置的特定實例來簡化本發明。當然,這些組件和佈置只是實例且並不意欲為限制性的。舉例來說,在以下描述中,第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵和第二特徵直接接觸地形成的實施例,並且還可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵和第二特徵可不直接接觸的實施例。另外,本發明可在各種實例中重複附圖標號和/或字母。這種重複是出於簡化和清楚的目的並且本身並不指示所論述的各種實施例和/或配置之間的關係。
此外,為易於描述,本文中可使用例如「在…之下」、「在…下方」、「下部」、「在…上方」、「上部」以及類似術語的空間相對術語來描述如圖中所示出的一個元件或特徵與另一元件或特徵的關係。除圖中所描繪的定向以外,空間相對術語意欲涵蓋元件在使用或操作中的不同定向。裝置可以其它方式定向(旋轉90度或處於其它定向),且本文中所使用的空間相對描述詞可以同樣相應地進行解釋。
還可包含其它特徵和製程。舉例來說,可包含測試結構以輔助對3D封裝或3DIC元件的校驗測試。測試結構可包含例如形成在重佈線層中或基底上的測試襯墊,所述基底允許對3D封裝或3DIC的測試、對探針和/或探針卡的使用以及類似操作。可對中間結構以及最終結構進行校驗測試。另外,本文中所公開的結構和方法可與並有已知良好晶粒的中間校驗的測試方法結合使用以增加良率並降低成本。
圖1A到圖1G是在根據本發明的一些實施例的被動元件模組PDM1的製造方法的各個階段處產生的結構的示意性側視圖。圖1A到圖1G的示意性側視圖是使用方向Y作為視角截取的。因此,元件繪示於由方向X和方向Z定義的平面中,其中方向X、方向Y以及方向Z可形成一組笛卡爾坐標的正交軸。本發明的示意性側視圖中可繪製屬於XZ平面的沿Y方向設置於不同點處的元件。參考圖1A,設置載體100。在一些實施例中,載體100是玻璃基底、金屬板、塑料支撐板或類似物,但可使用其它合適的基底材料,只要所述材料能夠承受製程的後續步驟即可。在一些實施例中,剝離層102設置在載體100上以便於在製造製程中需要時將載體100從結構上剝離下來。在一些實施例中,剝離層102包含光熱轉換(light-to-heat conversion,LTHC)釋放層。
在一些實施例中,半導體晶片110A、半導體晶片110B設置在載體100上。在一些實施例中,半導體晶片110A、半導體晶片110B經由取放方法放置到載體100上。貫穿本發明,在沒有必要區分半導體晶片110A與半導體晶片110B時,半導體晶片110A和半導體晶片110B可統稱為半導體晶片110。針對下文描述的其它元件採用相同命名法。雖然圖1A出於說明性目的僅呈現兩個半導體晶片110,但可在載體100上設置多個半導體晶片110以利用晶圓級封裝技術產生多個被動元件模組。在一些實施例中,個別半導體晶片110包含半導體基底111、接觸襯墊113、接觸柱115以及保護層117。接觸襯墊113可形成在半導體基底111的頂部表面111t處。接觸柱115可在接觸襯墊113上方延伸。每一接觸柱115可接觸多個接觸襯墊113,且包含由在半導體基底111上延伸的部分1152接合的在接觸襯墊113上延伸的部分1151。保護層117可覆蓋由接觸柱115暴露的半導體基底111的前表面111t。
半導體基底111可由半導體材料製成,所述半導體材料例如週期表的III族至V族的半導體材料。在一些實施例中,半導體基底111包含:元素半導體材料,例如結晶矽、金剛石或鍺;化合物半導體材料,例如碳化矽、鎵砷(gallium arsenic)、砷化銦或磷化銦;或合金半導體材料,例如矽鍺、碳化矽鍺、磷化鎵砷或磷化鎵銦。在某些實施例中,接觸襯墊113和接觸柱115包含鋁、銅或其它合適的金屬。在一些實施例中,接觸襯墊113和接觸柱115的材料包含銅、銅合金或其它導電材料,且可通過沉積、鍍覆或其它合適的技術形成。保護層117可以是單層或多層結構,且可包含氧化矽、氮化矽、氮氧化矽、其它合適的介電材料或其組合。保護層117可由合適的製作技術形成,所述合適的製作技術例如旋塗法、化學氣相沉積(chemical vapor deposition,CVD)或類似方法。
在一些實施例中,保護層117可覆蓋接觸柱115且(暫時地)構成半導體晶片110的頂部表面110t。在一些實施例中,半導體晶片110放置在載體100上方,其中半導體基底111的前表面111t背對載體100。半導體基底111的與前表面111t相對的後表面111r可形成半導體晶片110的後表面110r,且可由晶粒貼合膜(die attach film)120的部分緊固到載體100或剝離層102。在一些實施例中,晶粒貼合膜120包括熱塑性材料、熱固性材料或光固化材料。晶粒貼合膜120可包括環氧樹脂、苯酚樹脂、聚烯烴樹脂或其它合適的材料。然而,本發明不限於此,且可使用可與半導體處理環境兼容的其它材料或聚合物。晶粒貼合膜120可經由疊層、旋轉塗布或其它合適的技術應用。在一些實施例中,半導體晶片110是整合式被動元件的晶片且充當電容器、電感器、電阻器或類似物。在一些實施例中,半導體晶片110充當具有不同電容值、諧振頻率和/或不同尺寸的電容器。
參考圖1B,封裝體130形成在載體100上方以橫向封裝半導體晶片110。在一些實施例中,封裝體130包含模制化合物(molding compound)、模制底膠(molding underfill)、樹脂(例如環氧樹脂)或類似物。在一些實施例中,封裝體130通過包覆模制製程形成。在一些實施例中,封裝體130通過壓縮模制製程形成。在一些實施例中,封裝體130的形成包含形成完全覆蓋半導體晶片110的封裝材料(未繪示),隨後由平坦化製程移除封裝材料的一部分直到半導體晶片110的接觸柱115暴露為止。在一些實施例中,可在平坦化製程期間移除保護層117的一部分以暴露接觸柱115。在一些實施例中,封裝材料的平坦化包含執行機械研磨製程和/或化學機械拋光(chemical mechanical polishing,CMP)製程。在一些實施例中,在平坦化步驟期間移除接觸柱115的部分。在平坦化之後,半導體晶片110的頂部表面110t可由保護層117的頂部表面117t和接觸柱115定義。也就是說,在平坦化步驟之後,接觸柱115可暴露且可供用於使半導體晶片110電性連接到後續形成的組件或元件。在一些實施例中,暴露接觸柱115的半導體晶片110的頂部表面110t表示為接觸表面。在一些實施例中,半導體晶片110的接觸表面110t可與封裝體130的頂部表面130t大體上共面。在一些實施例中,如圖1B中所繪示,封裝體130填充半導體晶片110之間的間隙。在一些實施例中,在封裝體130形成的情況下,獲得重建構晶圓。在一些實施例中,重建構晶圓包含多個被動元件模組單元PDMU。換句話說,示範性製程可在重建構晶圓級處執行,以使得多個被動元件模組單元PDMU以重建構晶圓的形式經處理。在圖1B的橫截面圖中,為簡單起見繪示一個被動元件模組單元PDMU,但當然,這僅出於說明性目的,且本發明並不受重建構晶圓中產生的被動元件模組單元PDMU的數目限制。在一些實施例中,可將半導體晶片110和封裝體130(所述半導體晶片110嵌入到所述封裝體130中)視為被動元件模組單元PDMU的下部層級(tier)T1。
參考圖1B,在一些實施例中,介電層140形成在半導體晶片110和封裝體130上。介電層140經圖案化以包含暴露下層接觸柱115的開口142。在一些實施例中,開口142可暴露接觸柱115的上覆接觸襯墊113的部分1151,同時接觸柱115的部分1152仍然由介電層140覆蓋。然而,本發明不限於此,且在一些替代實施例中,也可暴露部分1152。介電層140可以是單層或多層結構,且可包含例如PBO的聚合物、其它合適的介電材料或其組合。介電層140可由合適的製作技術形成,所述合適的製作技術例如旋塗法、化學氣相沉積(CVD)或類似物。
參考圖1C和圖1D,在一些實施例中,絕緣體貫穿壁(through insulator wall,TIW)150形成在半導體晶片110上方。在一些實施例中,TIW 150鍍覆在接觸柱115的暴露部分(例如部分1151)上。在一些實施例中,TIW 150可具有在第一方向(例如X方向)上的細長形狀,所述第一方向不同於半導體晶片110的厚度方向(即,Z方向)。在一些實施例中,TIW 150突出穿過介電層140以建立與半導體晶片110的電性連接。在一些實施例中,TIW 150可如下文所描述形成。首先,晶種材料層(未繪示)形成在介電層140上方。在一些實施例中,晶種材料層包含鈦/銅複合層,且通過濺鍍製程形成以共形地覆蓋介電層140。晶種材料層可在開口142內延伸以接觸接觸柱115的暴露部分。此後,具有開口O的圖案化輔助罩幕M1形成在晶種材料層上。輔助罩幕M1的開口O暴露用於後續形成的TIW 150的預期位置。舉例來說,對應於開口142的位置形成輔助罩幕M1的開口O。在一些實施例中,輔助罩幕M1的個別開口O可暴露多個開口142。然後,執行鍍敷製程以在由輔助罩幕M1的開口O暴露的晶種材料層上形成金屬材料層150a(例如銅層)。隨後,例如經由剝除製程和蝕刻製程移除並不由金屬材料層150a覆蓋的輔助罩幕M1和晶種材料層以形成TIW 150。然而,本發明不限於此。在一些替代實施例中,可利用其它合適的方法來形成TIW 150。舉例來說,可對應於開口142將預製的TIW 150(例如預製的銅塊)取放到介電層140上。
參考圖1E,在一些實施例中,半導體晶片160A、半導體晶片160B設置在介電層140上位於TIW 150旁側。在一些實施例中,半導體晶片160A、半導體晶片160B經由取放方法放置到介電層140上。半導體晶片160A可與半導體晶片110A豎直地堆疊,且半導體晶片160B可與半導體晶片110B豎直地堆疊。也就是說,半導體晶片160A與半導體晶片110A至少部分地交疊,且半導體晶片160B與半導體晶片110B至少部分地交疊。半導體晶片160A、半導體晶片160B可與半導體晶片110A、半導體晶片110B類似。簡單來說,半導體晶片160可包含半導體基底161、接觸襯墊163、接觸柱165以及保護層167。接觸柱165可在多個接觸襯墊163上方延伸,且包含直接在接觸襯墊163上方延伸的部分1651和在半導體基底161上方延伸的部分1652。在一些實施例中,半導體晶片160A、半導體晶片160B是整合式被動元件的晶片。
在一些實施例中,封裝體170形成在介電層140上方以橫向封裝TIW 150和半導體晶片160。在一些實施例中,可遵循與封裝體130類似的製程且利用類似的材料產生封裝體170。在一些實施例中,封裝體130和封裝體170可包含不同材料。在一些替代實施例中,封裝體130的材料和封裝體170的材料可相同。封裝體170形成為使得TIW 150的頂部表面150t以及接觸柱165在半導體晶片160的頂部表面160t處保持暴露。在一些實施例中,TIW 150的頂部表面150t、半導體晶片160的頂部表面160t以及封裝體170的頂部表面170t可相對於彼此大體上齊平。在一些實施例中,將TIW 150、半導體晶片160以及封裝體170視為被動元件模組單元PDMU的上部層級T2的部分。
參考圖1F,在一些實施例中,連接端子180形成在TIW 150的暴露頂部表面150t和接觸柱165上。連接端子180可包含焊球、球柵陣列封裝(ball grid array,BGA)連接件、金屬支柱、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、經由無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold,ENEPIG)形成的凸塊、其組合(例如具有貼合的焊料球的金屬支柱)或類似物。連接端子180經由TIW 150電性連接到半導體晶片110。在一些實施例中,在連接端子180的形成之後,可例如通過沿切割道SC進行切割來分割重建構晶圓,以分離個別被動元件模組單元PDMU。在一些實施例中,可移除載體100和剝離層102以產生圖1G中繪示的被動元件模組PDM1。
圖1G是根據本發明的一些實施例的被動元件模組PDM1的示意性側視圖。圖2A是根據本發明的一些實施例的被動元件模組PDM1的示意性橫截面圖。圖2A的橫截面圖是沿Z方向上的水平高度I-I(圖1G中繪示)在由方向X和方向Y定義的平面中截取的。在圖2A中,出於論述目的將半導體晶片110A、半導體晶片110B的覆蓋區繪示為點劃線,即使半導體晶片110A、半導體晶片110B並不在XY平面(在所述XY平面處截取所述橫截面圖)內延伸。圖2B和圖2C是根據本發明的一些實施例的在由X方向和Z方向定義的平面中截取的被動元件模組PDM1的示意性橫截面圖。圖2B的示意性截面圖是沿圖2A中所示出的Y方向上的水平高度II-II截取的。圖2C的示意性截面圖是沿圖2A中所示出的Y方向上的水平高度III-III截取的。參考圖1G和圖2A到圖2C,在一些實施例中,被動元件模組PDM1包含下部層級T1中的封裝在封裝體130中的半導體晶片110和上部層級T2中的封裝在封裝體170中的半導體晶片160。在一些實施例中,半導體晶片110面向上層半導體晶片160的後表面160r。上部層級T2的半導體晶片160與下部層級T1的半導體晶片110部分地交疊。也就是說,下部層級T1的半導體晶片110的至少一部分並不由上部層級T2的半導體晶片160覆蓋。舉例來說,半導體晶片110可具有最長側沿Y方向設置的細長輪廓(例如矩形覆蓋區),且半導體晶片160可具有最長側沿X方向設置的細長輪廓(例如矩形覆蓋區)。因此,相比於上覆的半導體晶片160,半導體晶片110可在Y方向上具有更大的延伸。TIW 150可形成在並不由半導體晶片160覆蓋的接觸柱115上。在一些實施例中,如圖2A中所示出,半導體晶片110可在Y方向上從半導體晶片160的兩個相對側突出,且TIW 150可設置在半導體晶片160的相對側上。因此,半導體晶片160的相對側表面160s1、相對側表面160s2可皆沿Y方向面向TIW 150。TIW 150可在半導體晶片160的側面上延伸穿過封裝體170,以提供形成在上部層級T2上的連接端子180與半導體晶片110之間的電性連接。在一些實施例中,TIW 150可具有細長輪廓,其中沿X方向(側表面160s1和側表面160s2的方向)的尺寸D1大於沿Y方向的尺寸D2。在一些實施例中,尺寸D1與尺寸D2的比率介於1到5範圍內。如圖2B中所示出,在一些實施例中,沿Y方向上的水平高度II-II(圖2A中繪示)截取的被動元件模組PDM1的橫截面圖可展現僅下部層級T1的半導體晶片110,以及上層TIW 150。類似地,在圖2C中,沿Y方向上的水平高度III-III(圖2A中繪示)截取的被動元件模組PDM1的橫截面圖可展現堆疊的半導體晶片110、半導體晶片160,而TIW 150可能並不可見。在一些實施例中,連接端子180可用於將被動元件模組PDM1整合在較大元件(未繪示)中。在一些實施例中,通過封裝如本文中所公開的半導體晶片110、半導體晶片160,有可能在被動元件模組PDM1內實現整合式被動元件的更高密度,從而減小所述被動元件模組PDM1的外觀尺寸和寄生電感。
圖2D是根據本發明的一些實施例的被動元件模組PDM1B的示意性橫截面圖。圖2D的橫截面圖是沿圖2A的橫截面圖的相同水平高度I-I(圖1G中繪示)截取的。在一些實施例中,圖2D的被動元件模組PDM1B與圖2A的被動元件模組PDM1之間的區別在於TIW 150的定向。也就是說,被動元件模組PDM1B的TIW 150可具有沿X方向的尺寸D1,所述沿X方向的尺寸D1小於沿Y方向的尺寸D2。換句話說,TIW 150可具有比相鄰半導體晶片160(TIW 150直接面向半導體晶片160)的面向側表面(例如160s1)的延伸方向(例如方向X)更大的沿不同方向(例如方向Y)定向的尺寸(例如尺寸D2)。在一些實施例中,尺寸D1和尺寸D2是相同的大小。
圖2E是根據本發明的一些實施例的被動元件模組PDM1C的示意性側視圖。在一些實施例中,圖2E的被動元件模組PDM1C與圖1G的被動元件模組PDM1之間的區別在於半導體晶片110、半導體晶片160中的一個或多個已由包含主動元件的半導體晶粒替換。舉例來說,半導體晶粒110D替代半導體晶片110B設置於下部層級T1中。半導體晶粒110D包含形成在半導體基底111D中的主動元件,且可充當邏輯晶粒。在一些替代實施例中,半導體晶粒110D可充當記憶體晶粒。也就是說,半導體晶粒110D可以是主動元件或充當主動元件。在一些實施例中,被動元件模組比主動元件包含更大數目的整合式被動元件。
圖3A是根據本發明的一些實施例的被動元件模組PDM2的示意性側視圖。在一些實施例中,被動元件模組PDM2與圖1G的被動元件模組PDM1類似,且進一步包含形成在上部層級T2上並插入於半導體晶片160A、半導體晶片160B、TIW 150與連接端子180之間的重佈線結構190。在一些實施例中,重佈線結構190包含介電層192、重佈線導電層194以及多個凸塊下金屬196。為簡單起見,介電層192示出為單個介電層,且重佈線導電層194示出為嵌入於介電層192中。儘管如此,從製造製程的角度來看,介電層192由至少兩個介電層構成。重佈線導電層194可由多個重佈線導電圖案構成。重佈線導電層194的重佈線導電圖案包夾在兩個相鄰介電層之間。重佈線導電圖案中的一些可豎直地延伸穿過介電層192,以在重佈線結構190的不同金屬化層級之間建立電性連接。在一些實施例中,(最外)介電層192可經圖案化以暴露下層重佈線導電層194。凸塊下金屬196可任選地在暴露重佈線導電層194的(最外)介電層192的開口中共形地形成,且可進一步在(最外)介電層192的暴露表面的部分上方延伸。在一些實施例中,凸塊下金屬196包含多個堆疊層。舉例來說,凸塊下金屬196可包含堆疊在晶種層上的一個或多個金屬層。
在一些實施例中,重佈線導電層194和凸塊下金屬196的材料包含鋁、鈦、銅、鎳、鎢或其合金。重佈線導電層194和凸塊下金屬196可由例如電鍍、沉積和/或光微影(photolithography)以及蝕刻形成。在一些實施例中,介電層192的材料包含聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯(benzocyclobutene,BCB)、聚苯並惡唑(polybenzooxazole,PBO)或任何其它合適的聚合物類介電材料。介電層192可例如由合適的製作技術形成,所述合適的製作技術例如旋塗法、化學氣相沉積(CVD)、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)或類似物。應注意,圖3A中所示出的重佈線導電層194的數目和介電層192的數目僅為達成說明性目的,且本發明不限於此。在一些替代實施例中,可取決於電路設計而形成更少或更多層的重佈線導電層194和更少或更多層的介電層192。在需要更多層的重佈線導電層194和更多層的介電層192時,重佈線導電層194的層仍與介電層192的層交替地堆疊。
在一些實施例中,可遵循上文相對於圖1A到圖1F針對被動元件模組PDM1所描述的類似製程制作圖3A的被動元件模組PDM2。舉例來說,重佈線結構190可在形成連接端子180之前形成在圖1E中所示出的結構上。此後,可設置連接端子180,可分割被動元件模組PDM2,且可移除載體100。
圖3B是根據本發明的一些實施例的被動元件模組PDM2B的示意性側視圖。在一些實施例中,被動元件模組PDM2B與圖3A的被動元件模組PDM2類似,且進一步包含形成在下部層級T1上並插入於下部層級T1與上部層級T2之間的重佈線結構144。在一些實施例中,重佈線結構144可包含介電層140和嵌入於介電層140中的重佈線導電層146。在一些實施例中,重佈線導電層144可互連下部層級T1的半導體晶片110A、半導體晶片110B,且進一步提供半導體晶片110A、半導體晶片110B與TIW 150之間的電性連接。
圖4A是根據本發明的一些實施例的被動元件模組PDM3的示意性側視圖。圖4B是沿Z方向上的水平高度IV-IV(圖4A中繪示)截取的在XY平面中的圖4A的被動元件模組PDM3的示意性橫截面圖。在一些實施例中,半導體晶片110、半導體晶片160以及TIW 150可沿與先前論述的被動元件模組PDM1和被動元件模組PDM2中示出的方向不同的方向定向。舉例來說,在半導體元件PDM3中,下部層級T1的半導體晶片110A可相對於上部層級T2的上層半導體晶片160A沿X方向突出,且下部層級T1的另一半導體晶片110B可相對於上部層級T2的上層半導體晶片160B沿Y方向突出。在一些實施例中,半導體晶片110、半導體晶片160可具有細長形狀(例如矩形覆蓋區)。在一些實施例中,半導體晶片110A可具有沿X方向延伸的覆蓋區的較長側,且半導體晶片110B可具有沿Y方向延伸的較長側。在一些實施例中,半導體晶片160A可具有沿Y方向延伸的較長側,且半導體晶片160B可具有沿X方向延伸的較長側。在一些實施例中,半導體晶片160B可與下部層級T1的半導體晶片110A和半導體晶片110B兩者部分地交疊。在一些實施例中,形成在半導體晶片110A上的TIW 150A可具有細長形狀,其中沿Y方向延伸的尺寸更長。TIW 150A中的一些可設置在上部層級T2的半導體晶片160A與半導體晶片160B之間。形成在半導體晶片110B上的TIW 150B也可具有細長形狀,其中沿X方向延伸的尺寸更長。在一些實施例中,半導體晶片160B可面向形成在半導體晶片110A和半導體晶片110B中的每一個上的TIW 150A和TIW 150B。在一些實施例中,半導體晶片160B具有沿三個側面延伸的TIW 150A和TIW 150B。在一些實施例中,半導體晶片160A具有保護層167A以及接觸柱165A,半導體晶片160B具有保護層167B以及接觸柱165B。
圖5A到圖5G是在被動元件模組PDM4的製造製程期間產生的結構的示意性側視圖。參考圖5A,設置載體200(任選地具有形成在其上的剝離層202)。在一些實施例中,載體200是玻璃基底、金屬板、塑料支撐板或類似物,但可使用其它合適的基底材料,只要所述材料能夠承受製程的後續步驟即可。在一些實施例中,剝離層202包含光熱轉換(LTHC)層釋放層。在一些實施例中,背側重佈線結構210形成在載體200上。背側重佈線結構210包含介電層212和嵌入於介電層212中的重佈線導電層214。在一些實施例中,介電層212在載體200上方毯覆式地延伸,且包含遠離載體200的表面210a的開口216。重佈線導電層214的部分經由開口216暴露。在一些實施例中,可遵循如上文針對重佈線結構190所描述的類似製程製作背側重佈線結構210。在一些實施例中,TIW 220可對應於開口216形成在背側重佈線結構210上。TIW 220可填充開口216以接觸重佈線導電層214。簡單來說,TIW 220可通過將導電材料沉積在後續移除的輔助罩幕(未繪示)的開口中來製作,或可通過將預製的金屬塊取放在背側重佈線結構210上來形成。
參考圖5B,半導體晶片230可在TIW 220之間設置在背側重佈線結構210上。在一些實施例中,每一半導體晶片230包含半導體基底231、形成在半導體基底231上的接觸襯墊233、形成在接觸襯墊233上的接觸柱235以及覆蓋半導體基底231的頂部表面的保護層237。在一些實施例中,半導體晶片230以正面朝上的配置設置,具有其中接觸柱235暴露的遠離背側重佈線結構210的頂部表面230t(接觸表面)。在一些實施例中,半導體晶片230是整合式被動元件的晶片。在一些實施例中,封裝體240形成在背側重佈線結構210上以橫向環繞TIW 220和半導體晶片230。在一些實施例中,封裝體240的材料和製造製程可與上文針對封裝體130所論述的材料和製造製程類似。在一些實施例中,封裝體的頂部表面240t與TIW 220的頂部表面220t、半導體晶片230的接觸表面230t與保護層237的頂部表面237t大體上齊平。在一些實施例中,可將嵌入於封裝體240中的半導體晶片230和TIW 220視為被動元件模組單元PDMU的下部層級T1。
參考圖5C,在一些實施例中,介電層250形成在TIW 220、半導體晶片230以及封裝體240上。介電層250經圖案化以包含暴露半導體晶片230的下層接觸柱235和TIW 220的頂部表面220t的開口252。介電層250可以是單層或多層結構,且可包含例如PBO的聚合物、其它合適的介電材料或其組合。介電層250可由合適的製作技術形成,所述合適的製作技術例如旋塗法、化學氣相沉積(CVD)或類似物。在一些實施例中,TIW 260形成在TIW 220上方,且TIW 270形成在半導體晶片230上方。在一些實施例中,對於TIW 220,TIW 260和TIW 270可分別鍍覆在TIW 220和接觸柱235的暴露部分上,或可以是預製的金屬塊。在一些實施例中,TIW 260經由TIW 220電性連接到背側重佈線結構210。也就是說,TIW 260可堆疊在TIW 220上方,且TIW 270可堆疊在半導體晶片230上方。
參考圖5D,在一些實施例中,半導體晶片280設置在介電層250上位於TIW 260旁側。在一些實施例中,半導體晶片280經由取放方法放置到介電層250上。半導體晶片280可設置在介電層250上,具有遠離介電層250的暴露接觸柱285的頂部表面280t。半導體晶片280可與半導體晶片230豎直地堆疊且部分地交疊。也就是說,每一半導體晶片230的至少一部分可由上層半導體晶片280暴露。半導體晶片280可與半導體晶片230類似。在一些實施例中,半導體晶片280是整合式被動元件。在一些實施例中,封裝體290形成在介電層250上方以橫向封裝TIW 260、TIW 270以及半導體晶片280。在一些實施例中,可遵循如上文針對封裝體130所描述的類似製程且利用類似材料產生封裝體290。封裝體290形成為使得TIW 260、TIW 270的頂部表面260t、頂部表面270t以及接觸柱285在半導體晶片280的頂部表面280t處保持暴露。在一些實施例中,TIW 260、TIW 270的頂部表面260t、頂部表面270t,半導體晶片280的頂部表面280t以及封裝體290的頂部表面290t可相對於彼此大體上齊平。在一些實施例中,將TIW 260、TIW 270、半導體晶片280以及封裝體290視為被動元件模組單元PDMU的上部層級T2的部分。
參考圖5E,在一些實施例中,重佈線結構300可形成在封裝體290、半導體晶片280以及TIW 260、TIW 270上方。重佈線結構300包含介電層302、嵌入於介電層302中的重佈線導電層304以及任選地相對於半導體晶片280設置在重佈線結構300的相對側上的凸塊下金屬306。在一些實施例中,重佈線結構300直接電性連接到半導體晶片280,經由TIW 270電性連接到半導體晶片230,且經由TIW 260和TIW 220電性連接到背側重佈線結構210。連接端子310可設置在凸塊下金屬306上。重佈線結構300和連接端子310的材料和製造製程可分別與先前針對重佈線結構190和連接端子180描述的材料和製造製程類似。
參考圖5E和圖5F,重建構晶圓可在支撐框架SF上方翻轉以繼續製造製程。在一些實施例中,其中已形成連接端子310的重佈線結構300的表面設置為更接近於支撐框架SF。移除載體200以暴露背側重佈線結構210以供用於進一步處理。在一些實施例中,連接端子310可嵌入於保護帶(未繪示)中。在一些實施例中,開口218可例如由雷射鑽孔形成在背側重佈線結構210的介電層212中以暴露重佈線導電層214的部分。連接端子315可對應於開口218形成以與重佈線導電層214電性連接。在一些實施例中,可任選地在形成連接端子315之前形成凸塊下金屬(未繪示)。在一些實施例中,在連接端子315的形成之後,可例如通過沿切割道SC進行切割來分割重建構晶圓,以分離個別被動元件模組單元PDMU。
圖5G是根據本發明的一些實施例的被動元件模組PDM4的示意性側視圖。圖6是被動元件模組PDM4的示意性橫截面圖。圖6的橫截面圖是沿Z方向上的水平高度V-V(圖5G中繪示)在由方向X和方向Y定義的平面中截取的。在圖6中,出於論述目的將半導體晶片230的覆蓋區繪示為點劃線,即使半導體晶片230並不在XY平面(在所述XY平面處截取圖6的橫截面圖)內延伸。參考圖5G和圖6,在一些實施例中,被動元件模組PDM4包含包夾在重佈線結構300與背側重佈線結構210之間的下部層級T1的半導體晶片230和上部層級T2的半導體晶片280。下部層級T1的半導體晶片230由封裝體240封裝,且TIW 220從背側重佈線結構210穿過封裝體240朝向上部層級T2延伸。上部層級T2的半導體晶片280由封裝體290封裝,且TIW 260從下部層級T1穿過封裝體290朝向重佈線結構300延伸。TIW 270也從下部層級T1穿過封裝體290朝向重佈線結構300延伸。連接端子310和連接端子315分別設置在重佈線結構300和背側重佈線結構210上,以實現被動元件模組PDM4的雙側豎直整合。在一些實施例中,TIW 260和TIW 270具有細長形狀。在一些實施例中,TIW 260和TIW 270的伸長方向可能不同。舉例來說,TIW 260可具有大體上沿Y方向延伸的最長尺寸,同時TIW 270可具有大體上沿X方向延伸的最長尺寸。在一些實施例中,TIW 260可設置在上部層級T2的半導體晶片280之間。在一些實施例中,相比於半導體晶片280,半導體晶片230在TIW 260的伸長方向(例如圖6中的Y方向)上的延伸可能更大,且TIW 270可沿TIW 260的伸長方向形成為面向半導體晶片280的兩個相對側。也就是說,半導體晶片280在四個側面上可由TIW 260和TIW 270包圍。在一些實施例中,在下部層級T1中,TIW 220可具有大體上與上層TIW 260的覆蓋區相對應的覆蓋區。也就是說,TIW 220可沿半導體晶片230的側面且在半導體晶片230之間延伸。在一些實施例中,半導體晶片230的兩個相對側表面可沿X方向面向TIW 220。在一些實施例中,TIW 260和TIW 220的覆蓋區(提供重佈線結構300與背側重佈線結構210之間的豎直電性連接)可大於TIW 270的覆蓋區(提供半導體晶片230與重佈線結構300之間的電性連接)。在一些實施例中,分別形成在半導體晶片230A與半導體晶片230B上的TIW 270A與TIW 270B可具有細長形狀,其中沿X方向延伸的尺寸更長。
圖7是根據本發明的一些實施例的被動元件模組PDM5的示意性側視圖。在被動元件模組PDM5中,連接端子315可直接形成在TIW 220上。也就是說,可省略背側重佈線結構210(圖5G中繪示)的形成。在一些實施例中,被動元件模組PDM5可遵循與針對被動元件模組PDM4所描述的製程類似的製程形成,省略背側重佈線結構210(圖5A中繪示)的形成。舉例來說,TIW 220和半導體晶片230可直接設置在載體200(或剝離層202,皆在圖5A中繪示)上。此外,在重建構晶圓在支撐框架SF(如圖5F中所繪示)上方翻轉時,連接端子315可直接形成在TIW 220上。
圖8A是根據本發明的一些實施例的被動元件模組PDM6的示意性側視圖。圖8B是沿Z方向上的水平高度VI-VI(圖8A中繪示)截取的在XY平面中的圖8A的被動元件模組PDM6的示意性橫截面圖。在一些實施例中,半導體晶片230、半導體晶片280以及TIW 270可沿與先前論述的針對被動元件模組PDM4和被動元件模組PDM5所示出的方向不同的方向定向。舉例來說,在半導體元件PDM6中,下部層級T1的半導體晶片230A可相對於上部層級T2的上層半導體晶片280A沿X方向突出,且下部層級T1的另一半導體晶片230B可相對於上部層級T2的上層半導體晶片280B沿Y方向突出。在一些實施例中,半導體晶片230、半導體晶片280可具有細長形狀(例如矩形覆蓋區)。在一些實施例中,半導體晶片230A可具有沿X方向延伸的最長側,且半導體晶片230B可具有沿Y方向延伸的最長側。在一些實施例中,半導體晶片280A可具有沿Y方向延伸的最長側,且半導體晶片280B可具有沿X方向延伸的最長側。在一些實施例中,半導體晶片280B可與下部層級T1的半導體晶片230A和半導體晶片230B兩者部分地交疊。在一些實施例中,形成在半導體晶片230A上的TIW 270A可具有細長形狀,其中沿Y方向延伸的尺寸更長。在一些實施例中,形成在半導體晶片230B上的TIW 270B可具有細長形狀,其中沿X方向延伸的尺寸更長。TIW 270A中的一些可設置在半導體晶片280A與半導體晶片280B之間。也就是說,在被動元件模組PDM6中,TIW 270A(而非TIW 260)可插入於半導體晶片280A與半導體晶片280B之間(如針對圖6中的被動元件模組PDM4所繪示)。在一些實施例中,TIW 270A可插入於半導體晶片280A與TIW 260之間,同時半導體晶片280B可直接面向TIW 260。
圖9是根據本發明的一些實施例的被動元件模組PDM7的示意性側視圖。在被動元件模組PDM7中,連接端子315可直接形成在TIW 220上。也就是說,可省略背側重佈線結構210(圖8A中繪示)的形成。在被動元件模組PDM7中,半導體晶片230A、半導體晶片230B、半導體晶片280A、半導體晶片280B的設置可與圖8B中所示出的用於被動元件模組PDM7的設置類似。舉例來說,半導體晶片230A和半導體晶片280B可具有沿方向X延伸的較長側和沿方向Y延伸的較短側,同時半導體晶片230B和半導體晶片280A可具有沿方向Y延伸的較長側和沿方向X延伸的較短側。在一些實施例中,半導體晶片280B與下部層級T1的多個半導體晶片230A、半導體晶片230B部分地交疊。在一些實施例中,重佈線結構300以及TIW 260、TIW 220可在下部層級T1的半導體晶片230A、半導體晶片230B中的一或多個與連接端子315之間建立電性連接。
圖10A到圖10G是在根據本發明的一些實施例的被動元件模組PDM8的製造方法期間產生的結構的示意性橫截面圖。參考圖10A,在一些實施例中,設置載體320,其任選地具有形成在其上的剝離層322。介電層330可毯覆式地設置在載體320上方。此後,TIW 340可形成在介電層330上。圖10A的橫截面圖是沿Y方向上的水平在XZ平面中截取的,其中TIW 340不可見。出於這個原因,將TIW 340在圖10A的XZ平面中的投射繪示為點劃線。在一些實施例中,半導體晶片350設置在介電層330上,其中接觸柱352遠離介電層330。在一些實施例中,半導體晶片350可由晶粒貼合膜354的部分緊固到介電層。封裝體360可形成在介電層330上以橫向覆蓋半導體晶片350和TIW 340。在一些實施例中,封裝體的頂部表面360t、半導體晶片350的頂部表面350t以及TIW 340的頂部表面大體上齊平。在一些實施例中,可將封裝的TIW 340和半導體晶片350視為被動元件模組單元PDMU的最低層級T1。在圖10A的橫截面圖中,出於說明的目的繪示兩個被動元件模組單元PDMU,但本發明不限於此。
參考圖10B,重佈線結構370可形成在最低層級T1上以使半導體晶片350與屬於相同被動元件模組單元PDMU的相鄰TIW 340互連。在一些實施例中,重佈線結構370包含介電層372和重佈線導電層374,所述重佈線導電層374可經由接觸柱352與半導體晶片350電接觸且與TIW 340電接觸。參考圖10C,介電層372可經圖案化以暴露重佈線導電層374的部分。TIW 380可隨後形成在重佈線結構370上方。TIW 380填充介電層372的開口376以建立與重佈線導電層374的電接觸。在一些實施例中,TIW 380可形成為不與最低層級T1的TIW 340豎直地對準。舉例來說,TIW 380和TIW 340可不沿Y方向豎直地對準。因此,TIW 380可在圖10C的視圖的XZ平面中為可見的,同時TIW 340可在視圖的相同XZ平面中為不可見的。半導體晶片390可設置在TIW 380旁側,其中頂部表面390t背對重佈線結構370。半導體晶片390可與最低層級T1的半導體晶片350豎直地堆疊。
參考圖10D,TIW 380和半導體晶片390可橫向封裝在封裝體400中,且統稱為被動元件模組單元PDMU的下部中間層級T2。包括介電層412和重佈線導電層414的重佈線結構410可設置在下部中間層級T2上方,以使半導體晶片390與相同被動元件模組單元PDMU的TIW 380電互連。在一些實施例中,TIW 380提供最低層級T1上的重佈線結構370與下部中間層級T2上的重佈線結構410之間的豎直電性連接。也就是說,TIW 380可豎直地延伸穿過封裝體400以接觸重佈線導電層374和重佈線導電層414。
參考圖10E,在一些實施例中,上部中間層級T3和最高層級T4可添加在重佈線結構410上方,遵循如先前針對層級T1和層級T2所描述的類似製程。簡單來說,重佈線結構410的介電層412經圖案化以暴露重佈線導電層414的部分。TIW 420形成在重佈線結構410上,電性連接到重佈線導電層414。TIW 420可相對於下部中間層級T2的TIW 380豎直地不對準(在Y方向上),同時可與最低層級T1的TIW 340豎直地交疊。也就是說,在被動模組單元中,形成在每一其它層級中的TIW(例如層級T3的TIW 420和層級T1的TIW 340)可彼此豎直地對準。半導體晶片430設置在TIW 420旁側,分別與下部層級T2和下部層級T1的半導體晶片390和半導體晶片350豎直地堆疊。半導體晶片430可相對於下層重佈線結構410以正面朝上的配置設置(例如其中接觸表面遠離重佈線結構410)。封裝體440形成為橫向環繞半導體晶片430和TIW 420。重佈線結構450包含介電層452,且重佈線導電層454形成在上部中間層級T3上。包括TIW 460、半導體晶片470以及封裝體480的最高層級T4形成在上部中間層級T3上方,之後為重佈線結構490。在一些實施例中,重佈線結構490的上部表面490t(在Z方向上的遠離半導體晶片470的表面)可保留而不經圖案化。也就是說,重佈線結構490的重佈線導電層494可在一個側面上與半導體晶片470和TIW 460連接,同時在相對側上由介電層492覆蓋。
在一些實施例中,可通過沿切割道SC1切割包含多個被動元件模組單元PDMU的重建構晶圓來執行單一化製程。在一些實施例中,同一被動元件模組單元PDMU的層級T1到層級T4的TIW 340、TIW 380、TIW 420以及TIW 460的外邊緣在X方向上進一步遠離屬於同一被動元件模組單元PDMU的皆大體上處於同一YZ平面內的半導體晶片350、半導體晶片390、半導體晶片430、半導體晶片470。也就是說,在TIW 340、TIW 380、TIW 420以及TIW 460可由於其沿Y方向分佈而不豎直地對準(當在YZ平面中查看時)時,TIW 340、TIW 380、TIW 420以及TIW 460的外邊緣可沿X方向位在同一水平處。在一些實施例中,切割道SC1可沿TIW 340、TIW 380、TIW 420以及TIW 460的對準的外邊緣延伸。也就是說,可通過在TIW 340、TIW 380、TIW 420以及TIW 460與對應封裝體360、封裝體400、封裝體440、封裝體480之間的界面處進行切割來單一化被動元件模組單元PDMU。在一些實施例中,半導體晶片350、半導體晶片390、半導體晶片430、半導體晶片470可在被動元件模組單元PDMU的一個側面處豎直地交疊,同時TIW 340、TIW 380、TIW 420以及TIW 460可在被動元件模組單元PDMU的相對側處交替地豎直對準。舉例來說,在給定層級(例如下部層級T1)中,TIW(例如TIW 340)可設置在左手側上,且半導體晶片(例如半導體晶片350)可設置在右手側上。可在被動元件模組單元的所有層級(例如T2到T4)中重複類似分佈。因此,即使在單一化之前,給定層級(例如層級T2)中的半導體晶片(例如半導體晶片390)可在沿X方向的兩側上具有TIW(例如TIW 380),重佈線結構370、重佈線結構410、重佈線結構450或重佈線結構490仍可使半導體晶片與僅設置在半導體晶片的一個側面處的TIW互連。在一些實施例中,遵循單一化步驟,被動元件模組單元PDMU可大體上為平行六面體,且暴露以下各項:三個側面上的介電層330,若干層級T1到層級T4的封裝體360、封裝體400、封裝體440以及封裝體480和重佈線結構370、重佈線結構410、重佈線結構450、重佈線結構490的介電層372、介電層412、介電層452、介電層492;第四側上的介電層330;第五側上的介電層492;以及第六側上的封裝體360、封裝體400、封裝體440以及封裝體480,介電層330、介電層372、介電層412、介電層452、介電層492以及TIW 340、TIW 380、TIW 420、TIW 460。
參考圖10E和圖10F,在一些實施例中,可移除載體320,且單一化被動元件模組單元PDMU可旋轉且設置在支撐框架SF上方。在一些實施例中,執行90度(或同等)旋轉,以將被動模組單元PDMU設置在支撐框架SF上,其中第六側(暴露TIW 340、TIW 380、TIW 420、TIW 460的側)暴露且可供用於進一步處理(例如具有與面向支撐框架SF的第六側相對的側)。在一些實施例中,連接端子510安裝在TIW 340、TIW 380、TIW 420以及TIW 460的暴露的外邊緣上。也就是說,層級T2到層級T4的TIW 380、TIW 420、TIW 460可包夾在相鄰重佈線結構370、重佈線結構410、重佈線結構450、重佈線結構490的對之間,具有連接到所述對的一個重佈線結構的一個端部和連接到所述對的其它重佈線結構的另一端部,且進一步具有設置在暴露的外邊緣上的連接端子510。也就是說,TIW 380可直接電性連接到三個不同元件(例如兩個重佈線結構和一個連接端子510)。在一些實施例中,連接端子510相對於半導體晶片350、半導體晶片390、半導體晶片430以及半導體晶片470的接觸表面以90度的角度安裝。連接端子510可用於與更大元件(未繪示)整合。參考圖10F和圖10G,在一些實施例中,在移除支撐框架SF之後,獲得被動元件模組PDM8。
圖10G是根據本發明的一些實施例的被動元件模組PDM8的XZ平面中的示意性橫截面圖。圖11A是根據本發明的一些實施例的被動元件模組PDM8的透視三維圖。圖11B是根據本發明的一些實施例的被動元件模組PDM8的ZY平面中的示意性橫截面圖。圖11B的橫截面圖可沿圖11A中示出的X方向在水平高度VII-VII處截取。圖11C是根據本發明的一些實施例的被動元件模組PDM8的XY平面中的示意性橫截面圖。圖11C的橫截面圖可沿圖11A中示出的Z方向在水平高度VIII-VIII處截取。參考圖10G和圖11A到圖11C,被動元件模組PDM8可包含多個堆疊的層級T1到層級T4,每一層級T1到層級T4包括封裝的半導體晶片350、半導體晶片390、半導體晶片430、半導體晶片470以及TIW 340、TIW 380、TIW 420、TIW 460。TIW 340、TIW 380、TIW 420以及TIW 460可在被動元件模組PDM8的一個側面處暴露,且具有設置在其上的連接端子510。在一些實施例中,TIW 340、TIW 380、TIW 420、TIW 460以及封裝體360、封裝體400、封裝體440、封裝體480可在被動元件模組PDM8的側面上暴露以便定義棋盤形圖案。也就是說,在給定層級(例如層級T2)內沿Y方向移動,封裝體400和TIW 380的暴露部分可交替。類似地,貫穿不同層級T1到層級T4沿Z方向移動,封裝體的部分和TIW的部分可交替地暴露。舉例來說,在給定Y水平處沿Z方向繼續進行,層級T1和層級T3的TIW 340和TIW 420以及層級T2和層級T4的封裝體400和封裝體480的部分相遇。在不同Y水平處,層級T2和層級T4的TIW 380和TIW 460以及封裝體360和封裝體440相遇。在相鄰層級之間設置中間重佈線結構370、重佈線結構410、重佈線結構450的介電層。如圖11A和圖11C中所示出,在給定Z水平處,層級(例如層級T3)的封裝體(例如封裝體440)可在所有側面上暴露,同時TIW(例如TIW 420)可僅在一個側面上暴露。
圖12A是在根據本發明的一些實施例的被動元件模組PDM9(圖12B中繪示)的製造方法期間產生的結構的示意性橫截面圖。圖12B是根據本發明的一些實施例的被動元件模組PDM9的透視圖。圖12C是沿圖12B中繪示的水平高度XII-XII截取的在XY平面中的被動元件模組PDM9的示意性橫截面圖。在一些實施例中,圖12A的結構可遵循如相對於圖10A到圖10E所描述的類似製程形成。圖12A的結構與圖10E的結構之間的區別在於半導體晶片350、半導體晶片390、半導體晶片430以及半導體晶片470電性連接到沿X方向設置在每一側上的TIW 340、TIW 380、TIW 420、TIW 460。也就是說,以下部中間層級T2為例,半導體晶片390電性連接到在圖12A中示出為在其右手側上和在其左手側上的TIW 380。在一些實施例中,在單一化重建構晶圓之前,屬於相鄰被動元件模組單元PDMU的半導體晶片可連接到同一TIW(共享TIW)。在一些實施例中,通過沿延伸穿過若干層級T1到層級T4的TIW 340、TIW 380、TIW 420、TIW 460的切割道SC2進行切割來單一化被動元件模組單元PDMU。因此,TIW 340、TIW 380、TIW 420以及TIW 460在被動元件模組PDM9的兩個相對側處暴露。如圖12B中所示出,連接端子510可安裝在於一個側面處暴露的TIW 340、TIW 380、TIW 420、TIW 460上,且連接端子520可在相對側上安裝在TIW 340、TIW 380、TIW 420、TIW 460上。在一些實施例中,沿圖12B的水平高度IX-IX或水平高度XI-XI的在YZ平面中截取的被動元件模組PDM9的橫截面圖與圖11B中示出的被動元件模組PDM8的橫截面圖類似。如圖12C中所示出,在一些實施例中,設置於給定層級(例如層級T2)的半導體晶片(例如半導體晶片390)的相對側處的TIW(例如TIW 380)可沿X方向對準(可沿Y方向設置於同一水平處)。然而,本發明並不限於此。
在一些實施例中,本文中所公開的被動元件模組可整合在任何類型的半導體封裝中。圖13A到圖13C繪示根據本發明的一些實施例的示範性半導體封裝SP1到半導體封裝SP3的示意性側視圖。然而,本發明並不受限於其中可整合被動元件模組的半導體封裝的類型。應注意,雖然半導體封裝SP1到半導體封裝SP3示出為具有整合於其中的被動元件模組PDM1,但可在半導體封裝中使用屬於本發明的範圍內的任何其它被動元件模組。參考圖13A,半導體封裝SP1包含半導體晶粒530,電性連接到重佈線結構540。在一些實施例中,半導體晶粒530中的每一個可獨立地為或包含邏輯晶粒或記憶體晶粒。在一些實施例中,重佈線結構540形成在半導體晶粒530的主動表面530t上。半導體晶粒530可設置在重佈線結構540的第一側540a上且由封裝體550封裝。導電端子560可設置在重佈線結構540的與第一側540a相對的第二側540b上。在一些實施例中,被動元件模組(例如被動元件模組PDM1)可從第二側540b連接到重佈線結構540。也就是說,被動元件模組可在導電端子560之間設置在重佈線結構540的第二側540b上。在一些實施例中,被動元件模組的連接端子(例如被動元件模組PDM1的連接端子180)可建立重佈線結構540與被動元件模組之間的電性連接。在一些實施例中,多個被動元件模組可連接到重佈線結構540。舉例來說,被動元件模組可與設置在重佈線結構590上的半導體晶粒530中的每一個對應地(與所述半導體晶粒中的每一個豎直地交疊)設置。在一些實施例中,半導體封裝SP1可以是整合的扇出型半導體元件。
在一些實施例中,半導體封裝SP2可以是疊層封裝半導體元件。半導體封裝SP2可包含下部封裝570和連接到下部封裝的上部封裝575。在一些實施例中,下部封裝570包含連接到重佈線結構590的第一側590a的半導體晶粒580。重佈線結構590可形成在半導體晶粒580的主動表面580t上,且被稱為前側重佈線結構。在一些實施例中,半導體晶粒580可由封裝體600封裝,且背側重佈線結構610可相對於前側重佈線結構590的相對側上在封裝體600和半導體晶粒580上方延伸。絕緣體通孔620可使前側重佈線結構590與背側重佈線結構610電性連接。在一些實施例中,導電端子630設置在重佈線結構590的與第一側590a相對的第二側590b上。在一些實施例中,下部封裝570的半導體晶粒580為邏輯晶粒或包含邏輯晶粒。在一些實施例中,上部封裝575包含連接到插入件650的一或多個半導體晶粒640。在一些實施例中,半導體晶粒640是記憶體晶粒或包含記憶體晶粒。半導體晶粒640可任選地由封裝體660封裝。上部封裝575可經由導電端子670連接到下部封裝570的背側重佈線結構610。在一些實施例中,被動元件模組(例如被動元件模組PDM1)可從第二側590b連接到前側重佈線結構590。也就是說,被動元件模組可在導電端子630之間設置在重佈線結構590的第二側590b上。在一些實施例中,被動元件模組的連接端子(例如被動元件模組PDM1的連接端子180)可建立重佈線結構590與被動元件模組之間的電性連接。
根據本發明的一些實施例,半導體封裝SP3可以是大型(例如晶圓尺寸或面板尺寸)半導體封裝。在一些實施例中,大型半導體封裝SP3包含電性連接到重佈線結構690的第一側690a的多個半導體晶粒680。半導體晶粒680可在重佈線結構690上以陣列方式並排地設置。在一些實施例中,半導體晶粒680的主動表面680t與重佈線結構690接觸。封裝體700可形成在重佈線結構690上以封裝半導體晶粒680。在一些實施例中,散熱器710可相對於重佈線結構690在相對側上任選地設置在封裝體700上。導電端子720可設置在重佈線結構690的與第一側690a相對的第二側690b上,且可建立與插口730的電性連接。額外模組740(例如晶片、功率模組、射頻模組等)可設置在插口730上。在一些實施例中,一個或多個被動元件模組從第二側690b連接到重佈線結構690。被動元件模組(例如被動元件模組PDM1、被動元件模組PDM7)可設置在導電端子720之間,且可定位於插口730與重佈線結構690之間。
在一些實施例中,在使用與被動元件模組PDM8(圖11A中繪示)或被動元件模組PDM9(圖12A中繪示)類似的被動元件模組時,包含在被動元件模組中的半導體晶片的接觸表面(具有接觸柱)可能處於相對於半導體晶粒530、半導體晶粒580或半導體晶粒680的主動表面所處的平面分散(非並行)的平面中。在一些實施例中,半導體晶片的接觸表面的平面和半導體晶粒的主動表面的平面可相交,從而定義直角。
在一些實施例中,通過將被動元件整合在根據本發明的被動元件模組中,有可能實現整合式被動元件模組的更高密度,從而減小外觀尺寸、寄生電阻以及電感。因此,可增強包含根據本發明的被動元件模組的半導體封裝的性能。在一些實施例中,由於被動元件整合在被動元件模組中,可在不造成尺寸損失的情況下實現半導體封裝的性能的增強。
根據本發明的一些實施例,提供一種被動元件模組。被動元件模組包含第一層級、第二層級以及連接端子。第一層級包含第一半導體晶片和第一封裝體。第一半導體晶片具有接觸柱。封裝體封裝第一半導體晶片。第二層級設置在第一層級上,且包含第二半導體晶片、層間貫穿壁(through interlayer wall)以及第二封裝體。層間貫穿壁位於第二半導體晶片的側壁旁側並面向第二半導體晶片的側壁,且電性連接到接觸柱。第二封裝體封裝第二半導體晶片和層間貫穿壁。連接端子設置在第二層級上方且經由層間貫穿壁電性連接到第一半導體晶片。第一半導體晶片和第二半導體晶片包含被動元件。
在一些實施例中,進一步包括設置在所述第一半導體晶片或所述第二半導體晶片中的一者旁側的半導體晶粒,其中所述半導體晶粒包含主動元件。在一些實施例中,所述第二半導體晶片跨越所述第一半導體晶片且與所述第一半導體晶片豎直地交疊。在一些實施例中,所述層間貫穿壁中的至少一個層間貫穿壁設置在兩個第二半導體晶片之間。在一些實施例中,連接到所述第一半導體晶片的所述接觸柱的所述層間貫穿壁是第一層間貫穿壁,所述第二層級進一步包含設置在所述第二半導體晶片和所述第一層間貫穿壁旁側的第二層間貫穿壁,所述第一層級進一步包含設置在所述第一半導體晶片旁側的第三層間貫穿壁。在一些實施例中,進一步包括設置在所述第二層級上方的重佈線結構,其中所述連接端子經由所述重佈線結構連接到所述層間貫穿壁和所述第二半導體晶片。在一些實施例中,進一步包括設置在所述第一層級與所述第二層級之間的第一重佈線結構和設置在所述第二層級上的第二重佈線結構,其中所述層間貫穿壁中的一個層間貫穿壁的第一端部連接到所述第一重佈線結構,所述一個層間貫穿壁的第二端部連接到所述第二重佈線結構,且所述連接端子中的一個連接端子位於所述一個層間貫穿壁的側邊緣上。
根據本發明的一些實施例,提供一種半導體封裝。半導體封裝包含第一重佈線結構、半導體晶粒、導電端子以及被動元件。重佈線結構具有第一側和與第一側相對的第二側。半導體晶粒設置在重佈線結構的第一側上。導電端子電性設置在重佈線結構的第二側上。被動元件模組設置在重佈線結構的第二側上。被動元件模組包含第一半導體晶片、第一層間貫穿壁、第一封裝體、第二半導體晶片、第二封裝體以及連接端子。第一層間貫穿壁設置在第一半導體晶片旁側。第一封裝體橫向環繞第一半導體晶片和第一層間貫穿壁。第二半導體晶片與第一半導體晶片豎直地堆疊且電性連接到第一層間貫穿壁。第二封裝體橫向環繞第二半導體晶片。至少一個連接端子與第一層間貫穿壁中的一個層間貫穿壁接觸。第一半導體晶片和第二半導體晶片包含被動元件。
在一些實施例中,所述被動元件模組進一步包含:第二重佈線結構,設置在所述第二封裝體和所述第二半導體晶片上方。在一些實施例中,所述被動元件模組進一步包含第二層間貫穿壁,所述第二層間貫穿壁設置在所述第二半導體晶片旁側、由所述第二封裝體封裝且豎直地堆疊在所述第一層間貫穿壁上,且其中所述第一半導體晶片經由所述第二重佈線結構和所述第二層間貫穿壁中的至少一個第二層間貫穿壁連接到所述第一層間貫穿壁中的至少所述一個層間貫穿壁。在一些實施例中,進一步包括設置在所述第二半導體晶片旁側且由所述第二封裝體封裝的第二層間貫穿壁,其中所述第二層間貫穿壁中的一個層間貫穿壁具有沿第一方向的細長橫截面,所述第二層間貫穿壁中的另一個層間貫穿壁具有沿第二方向的細長橫截面,所述橫截面是在同一平面中截取的,且所述第一方向與所述第二方向正交。在一些實施例中,所述第二層間貫穿壁中的一些位於所述第一半導體晶片的接觸柱上。在一些實施例中,所述至少一個連接端子直接設置在所述一個層間貫穿壁上。在一些實施例中,所述第一半導體晶片的接觸表面相對於所述半導體晶粒的主動表面傾斜。
根據本發明的一些實施例,提供一種被動元件模組的製造方法。所述方法至少包含以下步驟。設置第一半導體晶片。第一半導體晶片封裝在第一封裝體中。第一層間貫穿壁形成在第一封裝體上方。第一層間貫穿壁電性連接到第一半導體晶片。設置第二半導體晶片。第二半導體晶片豎直地堆疊在第一半導體晶片上。形成第二封裝體。第二封裝體封裝第一半導體晶片和第一層間貫穿壁。連接端子形成為經由第一層間貫穿壁連接到第一半導體晶片。第一半導體晶片和第二半導體晶片包含被動元件。
在一些實施例中,進一步包括:在形成所述連接端子之前在所述第二封裝體上形成重佈線結構,其中所述重佈線結構與所述第一層間貫穿壁和所述第二半導體晶片直接連接。在一些實施例中,所述重佈線結構使所述第二半導體晶片中的兩個半導體晶片電性連接到所述第一層間貫穿壁中的一個層間貫穿壁,且所述製造方法進一步包括切穿所述一個層間貫穿壁以便使所述兩個半導體晶片彼此電隔離。在一些實施例中,進一步包括:在切穿所述一個層間貫穿壁之後在所述一個層間貫穿壁的切穿側壁上形成所述連接端子中的一個連接端子。在一些實施例中,所述連接端子形成在所述重佈線結構上,且經由所述重佈線結構電性連接到所述第一層間貫穿壁。在一些實施例中,進一步包括:形成第一重佈線結構;在設置所述第一半導體晶片之前在所述第一重佈線結構上形成第二層間貫穿壁;在所述第二封裝體上形成第二重佈線結構,其中所述連接端子形成在所述第二重佈線結構上;以及在所述第一重佈線結構上形成額外連接端子。
前文概述若干實施例的特徵以使所屬領域的技術人員可更好地理解本發明的各個方面。所屬領域的技術人員應瞭解,其可很容易地將本發明用作設計或修改用於實現本文中所引入的實施例的相同目的和/或達成相同優勢的其它製程和結構的基礎。所屬領域的技術人員還應認識到,這類等效構造並不脫離本發明的精神和範圍,且其可在不脫離本發明的精神和範圍的情況下在本文中進行各種改變、替代以及更改。
100、200、320:載體
102、202、322:剝離層
110、110A、110B、160、160A、160B、230、230A、230B、280、280A、280B、350、390、430、470:半導體晶片
110D、530、580、640、680:半導體晶粒
110t、160t、230t、280t、350t、390t:半導體晶片的頂部表面
110r、160r:半導體晶片的後表面
111、111D、161、231:半導體基底
111t:半導體基底的前表面
111r:半導體基底的後表面
113、163、233:接觸襯墊
115、165、165A、165B、235、285、352:接觸柱
117、167、167A、167B、237:保護層
117t、237t:保護層的頂部表面
120、354:晶粒貼合膜
130、170、240、290、360、400、440、480、550、600、660、700:封裝體
130t、170t、240t、290t、360t:封裝體的頂部表面
140、192、212、250、302、330、372、412、452、492:介電層
142、216、218、252、376、O:開口
144、190、300、370、410、450、490、540、590、690:重佈線結構
146、194、214、304、374、414、454、494:重佈線導電層
150、150A、150B、220、260、270、270A、270B、340、380、420、460:絕緣體貫穿壁
150a:金屬材料層
150t、220t、260t、270t:絕緣體貫穿壁的頂部表面
160s1、160s2:側表面
180、310、315、510、520:連接端子
196、306:凸塊下金屬
210、610:背側重佈線結構
210a:表面
490t:重佈線結構的上部表面
530t、580t、680t:主動表面
540a、590a、690a:重佈線結構的第一側
540b、590b、690b:重佈線結構的第二側
560、630、670、720:導電端子
570:下部封裝
575:上部封裝
620:絕緣體通孔
650:插入件
710:散熱器
730:插口
740:額外模組
1151、1152、1651、1652:接觸柱的部分
D1、D2:尺寸
I-I、II-II、III-III、IV-IV、V-V、VI-VI、VII-VII、VIII-VIII、XII-XII、IX-IX、XI-XI:水平高度
M1:圖案化輔助罩幕
SC、SC1、SC2:切割道
SF:支撐框架
SP1、SP2、SP3:半導體封裝
T1:下部層級
T2:上部層級
T3:上部中間層級
T4:最高層級
PDM1、PDM1B、PDM1C、PDM2、PDM2B、PDM3、PDM4、PDM5、PDM6、PDM7、PDM8、PDM9:被動元件模組
PDMU:被動元件模組單元
X、Y、Z:方向
當結合附圖閱讀時,根據以下詳細描述最好地理解本發明的各方面。應注意,根據業界中的標準慣例,各個特徵未按比例繪製。實際上,為了論述清楚起見,可以任意增大或減小各個特徵的尺寸。
圖1A到圖1G是在根據本發明的一些實施例的被動元件模組的製造方法的各個階段處產生的結構的示意性側視圖。
圖2A到圖2D是根據本發明的一些實施例的被動元件模組的示意性橫截面圖。
圖2E是根據本發明的一些實施例的被動元件模組的示意性側視圖。
圖3A和圖3B是根據本發明的一些實施例的被動元件模組的示意性側視圖。
圖4A是根據本發明的一些實施例的被動元件模組的示意性側視圖。
圖4B是根據本發明的一些實施例的被動元件模組的示意性橫截面圖。
圖5A到圖5G是在根據本發明的一些實施例的被動元件模組的製造方法的各個階段處產生的結構的示意性側視圖。
圖6是根據本發明的一些實施例的被動元件模組的示意性橫截面圖。
圖7是根據本發明的一些實施例的被動元件模組的示意性側視圖。
圖8A是根據本發明的一些實施例的被動元件模組的示意性側視圖。
圖8B是根據本發明的一些實施例的被動元件模組的示意性橫截面圖。
圖9是根據本發明的一些實施例的被動元件模組的示意性側視圖。
圖10A到圖10G是在根據本發明的一些實施例的被動元件模組的製造方法的各個階段處產生的結構的示意性橫截面圖。
圖11A是根據本發明的一些實施例的被動元件模組的示意性三維圖。
圖11B和圖11C是根據本發明的一些實施例的被動元件模組的示意性橫截面圖。
圖12A是在根據本發明的一些實施例的被動元件模組的製造方法期間產生的結構的示意性橫截面圖。
圖12B是根據本發明的一些實施例的被動元件模組的示意性三維圖。
圖12C是根據本發明的一些實施例的被動元件模組的示意性截面圖。
圖13A到圖13C是根據本發明的一些實施例的半導體封裝的示意性側視圖。
110A、110B、160A、160B:半導體晶片
115、165:接觸柱
120:晶粒貼合膜
130、170:封裝體
140:介電層
150:絕緣體貫穿壁
160r:半導體晶片的後表面
180:連接端子
I-I:水平高度
T1:下部層級
T2:上部層級
PDM1:被動元件模組
X、Y、Z:方向
Claims (1)
- 一種被動元件模組,包括: 第一層級,包含: 第一半導體晶片,具有接觸柱;以及 第一封裝體,封裝所述第一半導體晶片; 第二層級,設置在所述第一層級上且包含: 第二半導體晶片; 層間貫穿壁,位於所述第二半導體晶片的側壁旁側並面向所述第二半導體晶片的側壁,且電性連接到所述接觸柱;以及 第二封裝體,封裝所述第二半導體晶片和所述層間貫穿壁;以及 連接端子,設置在所述第二層級上方且經由所述層間貫穿壁電性連接到所述第一半導體晶片, 其中所述第一半導體晶片和所述第二半導體晶片包含被動元件。
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US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
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