CN113161325A - 无源器件模块 - Google Patents
无源器件模块 Download PDFInfo
- Publication number
- CN113161325A CN113161325A CN202110056766.1A CN202110056766A CN113161325A CN 113161325 A CN113161325 A CN 113161325A CN 202110056766 A CN202110056766 A CN 202110056766A CN 113161325 A CN113161325 A CN 113161325A
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- semiconductor chip
- tiw
- device module
- passive device
- semiconductor
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- 239000004065 semiconductor Substances 0.000 claims abstract description 400
- 239000011229 interlayer Substances 0.000 claims abstract description 58
- 238000007789 sealing Methods 0.000 claims abstract description 28
- 230000000149 penetrating effect Effects 0.000 claims abstract description 6
- 230000035515 penetration Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 142
- 239000008393 encapsulating agent Substances 0.000 abstract description 28
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 42
- 239000000463 material Substances 0.000 description 30
- 230000008569 process Effects 0.000 description 26
- 239000000758 substrate Substances 0.000 description 22
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 20
- 239000011241 protective layer Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000001465 metallisation Methods 0.000 description 8
- JMYNPQVCVQVODQ-OWOJBTEDSA-N 1,3-dichloro-5-[(e)-2-(4-chlorophenyl)ethenyl]benzene Chemical compound C1=CC(Cl)=CC=C1\C=C\C1=CC(Cl)=CC(Cl)=C1 JMYNPQVCVQVODQ-OWOJBTEDSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000004806 packaging method and process Methods 0.000 description 7
- 101150094737 pdm2 gene Proteins 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 101100082633 Drosophila melanogaster nub gene Proteins 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004299 exfoliation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001152 differential interference contrast microscopy Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005672 polyolefin resin Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/224—Housing; Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种无源器件模块包含第一层级、第二层级以及连接端子。第一层级包含第一半导体芯片和第一密封体。第一半导体芯片具有接触柱。密封体密封第一半导体芯片。第二层级设置在第一层级上,且包含第二半导体芯片、层间贯穿壁以及第二密封体。层间贯穿壁位于第二半导体芯片的侧壁旁侧并面向第二半导体芯片的侧壁,且电连接到接触柱。第二密封体密封第二半导体芯片和层间贯穿壁。连接端子设置在第二层级上方且经由层间贯穿壁电连接到第一半导体芯片。第一半导体芯片和第二半导体芯片包含无源器件。本公开可减小外观尺寸、寄生电阻以及电感。
Description
技术领域
本公开的实施例涉及一种无源器件模块。
背景技术
通常在单个半导体晶片上制造用于各种电子装置的半导体器件和集成电路,所述电子装置例如行动电话和其它移动电子设备。晶片的管芯可在晶片级与其它半导体器件或管芯一起处理和封装,且已针对晶片级封装研发各种技术和应用。多个半导体器件的整合已成为所述领域中的挑战。为响应于对于小型化、更高速度以及更好电气性能(例如更低传输损耗和插入损耗)的增大的需求,积极研究更具创造性的封装和组装技术。
发明内容
本公开实施例的一种无源器件模块,包括:第一层级,包含:第一半导体芯片,具有接触柱;以及第一密封体,密封所述第一半导体芯片;第二层级,设置在所述第一层级上且包含:第二半导体芯片;层间贯穿壁,位于所述第二半导体芯片的侧壁旁侧并面向所述第二半导体芯片的侧壁,且电连接到所述接触柱;以及第二密封体,密封所述第二半导体芯片和所述层间贯穿壁;以及连接端子,设置在所述第二层级上方且经由所述层间贯穿壁电连接到所述第一半导体芯片,其中所述第一半导体芯片和所述第二半导体芯片包含无源器件。
本公开实施例的一种半导体封装,包括:第一重布线结构,具有第一侧和与所述第一侧相对的第二侧;半导体管芯,设置在所述重布线结构的所述第一侧上;导电端子,设置在所述重布线结构的所述第二侧上;以及无源器件模块,设置在所述重布线结构的所述第二侧上,所述无源器件模块包含:第一半导体芯片;第一层间贯穿壁,设置在所述第一半导体芯片旁侧;第一密封体,横向环绕所述第一半导体芯片和所述第一层间贯穿壁;第二半导体芯片,与所述第一半导体芯片竖直地堆叠且电连接到所述第一层间贯穿壁;第二密封体,横向环绕所述第二半导体芯片;以及连接端子,其中至少一个连接端子与所述第一层间贯穿壁中的一个层间贯穿壁接触,其中所述第一半导体芯片和所述第二半导体芯片包含无源器件。
本公开实施例的一种无源器件模块的制造方法,包括:设置第一半导体芯片;将所述第一半导体芯片密封在第一密封体中;在所述第一密封体上方形成第一层间贯穿壁,其中所述第一层间贯穿壁与所述第一半导体芯片电连接;设置竖直地堆叠在所述第一半导体芯片上的第二半导体芯片;形成密封所述第二半导体芯片和所述第一层间贯穿壁的第二密封体;以及形成经由所述第一层间贯穿壁电连接到所述第一半导体芯片的连接端子,其中所述第一半导体芯片和所述第二半导体芯片包含无源器件。
附图说明
当结合附图阅读时,根据以下详细描述最好地理解本公开的各方面。应注意,根据业界中的标准惯例,各个特征未按比例绘制。实际上,为了论述清楚起见,可以任意增大或减小各个特征的尺寸。
图1A到图1G是在根据本公开的一些实施例的无源器件模块的制造方法的各个阶段处产生的结构的示意性侧视图。
图2A到图2D是根据本公开的一些实施例的无源器件模块的示意性横截面图。
图2E是根据本公开的一些实施例的无源器件模块的示意性侧视图。
图3A和图3B是根据本公开的一些实施例的无源器件模块的示意性侧视图。
图4A是根据本公开的一些实施例的无源器件模块的示意性侧视图。
图4B是根据本公开的一些实施例的无源器件模块的示意性横截面图。
图5A到图5G是在根据本公开的一些实施例的无源器件模块的制造方法的各个阶段处产生的结构的示意性侧视图。
图6是根据本公开的一些实施例的无源器件模块的示意性横截面图。
图7是根据本公开的一些实施例的无源器件模块的示意性侧视图。
图8A是根据本公开的一些实施例的无源器件模块的示意性侧视图。
图8B是根据本公开的一些实施例的无源器件模块的示意性横截面图。
图9是根据本公开的一些实施例的无源器件模块的示意性侧视图。
图10A到图10G是在根据本公开的一些实施例的无源器件模块的制造方法的各个阶段处产生的结构的示意性横截面图。
图11A是根据本公开的一些实施例的无源器件模块的示意性三维图。
图11B和图11C是根据本公开的一些实施例的无源器件模块的示意性横截面图。
图12A是在根据本公开的一些实施例的无源器件模块的制造方法期间产生的结构的示意性横截面图。
图12B是根据本公开的一些实施例的无源器件模块的示意性三维图。
图12C是根据本公开的一些实施例的无源器件模块的示意性截面图。
图13A到图13C是根据本公开的一些实施例的半导体封装的示意性侧视图。
附图标号说明
100、200、320:载体;
102、202、322:剥离层;
110、110A、110B、160、160A、160B、230、230A、230B、280、280A、280B、350、390、430、470:半导体芯片;
110D、530、580、640、680:半导体管芯;
110t、160t、230t、280t、350t、390t:半导体芯片的顶部表面;
110r、160r:半导体芯片的后表面;
111、111D、161、231:半导体衬底;
111t:半导体衬底的前表面;
111r:半导体衬底的后表面;
113、163、233:接触衬垫;
115、165、165A、165B、235、285、352:接触柱;
117、167、167A、167B、237:保护层;
117t、237t:保护层的顶部表面;
120、354:管芯贴合膜;
130、170、240、290、360、400、440、480、550、600、660、700:密封体;
130t、170t、240t、290t、360t:密封体的顶部表面;
140、192、212、250、302、330、372、412、452、492:介电层;
142、216、218、252、376、O:开口;
144、190、300、370、410、450、490、540、590、690:重布线结构;
146、194、214、304、374、414、454、494:重布线导电层;
150、150A、150B、220、260、270、270A、270B、340、380、420、460:绝缘体贯穿壁;
150a:金属材料层;
150t、220t、260t、270t:绝缘体贯穿壁的顶部表面;
160s1、160s2:侧表面;
180、310、315、510、520:连接端子;
196、306:凸块下金属;
210、610:背侧重布线结构;
210a:表面;
490t:重布线结构的上部表面;
530t、580t、680t:有源表面;
540a、590a、690a:重布线结构的第一侧;
540b、590b、690b:重布线结构的第二侧;
560、630、670、720:导电端子;
570:下部封装;
575:上部封装;
620:绝缘体穿孔;
650:插入件;
710:散热器;
730:插口;
740:额外模块;
1151、1152、1651、1652:接触柱的部分;
D1、D2:尺寸;
I-I、II-II、III-III、IV-IV、V-V、VI-VI、VII-VII、VIII-VIII、XII-XII、IX-IX、XI-XI:水平高度;
M1:图案化辅助掩模;
SC、SC1、SC2:切割道;
SF:支撑框架;
SP1、SP2、SP3:半导体封装;
T1:下部层级;
T2:上部层级;
T3:上部中间层级;
T4:最高层级;
PDM1、PDM1B、PDM1C、PDM2、PDM2B、PDM3、PDM4、PDM5、PDM6、PDM7、PDM8、PDM9:无源器件模块;
PDMU:无源器件模块单元;
X、Y、Z:方向。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例来简化本公开。当然,这些组件和布置只是实例且并不意欲为限制性的。举例来说,在以下描述中,第一特征在第二特征上方或第二特征上的形成可包含第一特征和第二特征直接接触地形成的实施例,并且还可包含额外特征可在第一特征与第二特征之间形成使得第一特征和第二特征可不直接接触的实施例。另外,本公开可在各种实例中重复附图标号和/或字母。这种重复是出于简化和清楚的目的并且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外,为易于描述,本文中可使用例如“在…之下”、“在…下方”、“下部”、“在…上方”、“上部”以及类似术语的空间相对术语来描述如图中所示出的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向以外,空间相对术语意欲涵盖器件在使用或操作中的不同定向。装置可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述词可以同样相应地进行解释。
还可包含其它特征和工艺。举例来说,可包含测试结构以辅助对3D封装或3DIC器件的校验测试。测试结构可包含例如形成在重布线层中或衬底上的测试衬垫,所述衬底允许对3D封装或3DIC的测试、对探针和/或探针卡的使用以及类似操作。可对中间结构以及最终结构进行校验测试。另外,本文中所公开的结构和方法可与并有已知良好管芯的中间校验的测试方法结合使用以增加良率并降低成本。
图1A到图1G是在根据本公开的一些实施例的无源器件模块PDM1的制造方法的各个阶段处产生的结构的示意性侧视图。图1A到图1G的示意性侧视图是使用方向Y作为视角截取的。因此,元件绘示于由方向X和方向Z定义的平面中,其中方向X、方向Y以及方向Z可形成一组笛卡尔坐标的正交轴。本公开的示意性侧视图中可绘制属于XZ平面的沿Y方向设置于不同点处的元件。参考图1A,设置载体100。在一些实施例中,载体100是玻璃衬底、金属板、塑料支撑板或类似物,但可使用其它合适的衬底材料,只要所述材料能够承受工艺的后续步骤即可。在一些实施例中,剥离层102设置在载体100上以便于在制造工艺中需要时将载体100从结构上剥离下来。在一些实施例中,剥离层102包含光热转换(light-to-heatconversion,LTHC)释放层。
在一些实施例中,半导体芯片110A、半导体芯片110B设置在载体100上。在一些实施例中,半导体芯片110A、半导体芯片110B经由取放方法放置到载体100上。贯穿本公开,在没有必要区分半导体芯片110A与半导体芯片110B时,半导体芯片110A和半导体芯片110B可统称为半导体芯片110。针对下文描述的其它元件采用相同命名法。虽然图1A出于说明性目的仅呈现两个半导体芯片110,但可在载体100上设置多个半导体芯片110以利用晶片级封装技术产生多个无源器件模块。在一些实施例中,个别半导体芯片110包含半导体衬底111、接触衬垫113、接触柱115以及保护层117。接触衬垫113可形成在半导体衬底111的顶部表面111t处。接触柱115可在接触衬垫113上方延伸。每一接触柱115可接触多个接触衬垫113,且包含由在半导体衬底111上延伸的部分1152接合的在接触衬垫113上延伸的部分1151。保护层117可覆盖由接触柱115暴露的半导体衬底111的前表面111t。
半导体衬底111可由半导体材料制成,所述半导体材料例如周期表的III族至V族的半导体材料。在一些实施例中,半导体衬底111包含:元素半导体材料,例如结晶硅、金刚石或锗;化合物半导体材料,例如碳化硅、镓砷(gallium arsenic)、砷化铟或磷化铟;或合金半导体材料,例如硅锗、碳化硅锗、磷化镓砷或磷化镓铟。在某些实施例中,接触衬垫113和接触柱115包含铝、铜或其它合适的金属。在一些实施例中,接触衬垫113和接触柱115的材料包含铜、铜合金或其它导电材料,且可通过沉积、镀覆或其它合适的技术形成。保护层117可以是单层或多层结构,且可包含氧化硅、氮化硅、氮氧化硅、其它合适的介电材料或其组合。保护层117可由合适的制作技术形成,所述合适的制作技术例如旋涂法、化学气相沉积(chemical vapor deposition,CVD)或类似方法。
在一些实施例中,保护层117可覆盖接触柱115且(暂时地)构成半导体芯片110的顶部表面110t。在一些实施例中,半导体芯片110放置在载体100上方,其中半导体衬底111的前表面111t背对载体100。半导体衬底111的与前表面111t相对的后表面111r可形成半导体芯片110的后表面110r,且可由管芯贴合膜120(die attach film)的部分紧固到载体100或剥离层102。在一些实施例中,管芯贴合膜120包括热塑性材料、热固性材料或光固化材料。管芯贴合膜120可包括环氧树脂、苯酚树脂、聚烯烃树脂或其它合适的材料。然而,本公开不限于此,且可使用可与半导体处理环境兼容的其它材料或聚合物。管芯贴合膜120可经由叠层、旋转涂布或其它合适的技术应用。在一些实施例中,半导体芯片110是整合式无源器件的芯片且充当电容器、电感器、电阻器或类似物。在一些实施例中,半导体芯片110充当具有不同电容值、谐振频率和/或不同大小的电容器。
参考图1B,密封体130形成在载体100上方以横向密封半导体芯片110。在一些实施例中,密封体130包含模制化合物(molding compound)、模制底胶(molding underfill)、树脂(例如环氧树脂)或类似物。在一些实施例中,密封体130通过包覆模制工艺形成。在一些实施例中,密封体130通过压缩模制工艺形成。在一些实施例中,密封体130的形成包含形成完全覆盖半导体芯片110的密封材料(未绘示),随后由平坦化工艺移除密封材料的一部分直到半导体芯片110的接触柱115暴露为止。在一些实施例中,可在平坦化工艺期间移除保护层117的一部分以暴露接触柱115。在一些实施例中,密封材料的平坦化包含执行机械研磨工艺和/或化学机械抛光(chemical mechanical polishing,CMP)工艺。在一些实施例中,在平坦化步骤期间移除接触柱115的部分。在平坦化之后,半导体芯片110的顶部表面110t可由保护层117的顶部表面117t和接触柱115定义。也就是说,在平坦化步骤之后,接触柱115可暴露且可供用于使半导体芯片110电连接到后续形成的组件或元件。在一些实施例中,暴露接触柱115的半导体芯片110的顶部表面110t表示为接触表面。在一些实施例中,半导体芯片110的接触表面110t可与密封体130的顶部表面130t大体上共面。在一些实施例中,如图1B中所绘示,密封体130填充半导体芯片110之间的间隙。在一些实施例中,在密封体130形成的情况下,获得重建构晶片。在一些实施例中,重建构晶片包含多个无源器件模块单元PDMU。换句话说,示范性工艺可在重建构晶片级处执行,以使得多个无源器件模块单元PDMU以重建构晶片的形式经处理。在图1B的横截面图中,为简单起见绘示一个无源器件模块单元PDMU,但当然,这仅出于说明性目的,且本公开并不受重建构晶片中产生的无源器件模块单元PDMU的数目限制。在一些实施例中,可将半导体芯片110和密封体130(所述半导体芯片110嵌入到所述密封体130中)视为无源器件模块单元PDMU的下部层级(tier)T1。
参考图1B,在一些实施例中,介电层140形成在半导体芯片110和密封体130上。介电层140经图案化以包含暴露下层接触柱115的开口142。在一些实施例中,开口142可暴露接触柱115的上覆接触衬垫113的部分1151,同时接触柱115的部分1152仍然由介电层140覆盖。然而,本公开不限于此,且在一些替代实施例中,也可暴露部分1152。介电层140可以是单层或多层结构,且可包含例如PBO的聚合物、其它合适的介电材料或其组合。介电层140可由合适的制作技术形成,所述合适的制作技术例如旋涂法、化学气相沉积(CVD)或类似物。
参考图1C和图1D,在一些实施例中,绝缘体贯穿壁(through insulator wall,TIW)150形成在半导体芯片110上方。在一些实施例中,TIW 150镀覆在接触柱115的暴露部分(例如部分1151)上。在一些实施例中,TIW 150可具有在第一方向(例如X方向)上的细长形状,所述第一方向不同于半导体芯片110的厚度方向(即,Z方向)。在一些实施例中,TIW150突出穿过介电层140以建立与半导体芯片110的电连接。在一些实施例中,TIW 150可如下文所描述形成。首先,晶种材料层(未绘示)形成在介电层140上方。在一些实施例中,晶种材料层包含钛/铜复合层,且通过溅镀工艺形成以共形地覆盖介电层140。晶种材料层可在开口142内延伸以接触接触柱115的暴露部分。此后,具有开口O的图案化辅助掩模M1形成在晶种材料层上。辅助掩模M1的开口O暴露用于后续形成的TIW 150的预期位置。举例来说,对应于开口142的位置形成辅助掩模M1的开口O。在一些实施例中,辅助掩模M1的个别开口O可暴露多个开口142。然后,执行镀敷工艺以在由辅助掩模M1的开口O暴露的晶种材料层上形成金属材料层150a(例如铜层)。随后,例如经由剥除工艺和刻蚀工艺移除并不由金属材料层150a覆盖的辅助掩模M1和晶种材料层以形成TIW 150。然而,本公开不限于此。在一些替代实施例中,可利用其它合适的方法来形成TIW 150。举例来说,可对应于开口142将预制的TIW 150(例如预制的铜块)取放到介电层140上。
参考图1E,在一些实施例中,半导体芯片160A、半导体芯片160B设置在介电层140上位于TIW 150旁侧。在一些实施例中,半导体芯片160A、半导体芯片160B经由取放方法放置到介电层140上。半导体芯片160A可与半导体芯片110A竖直地堆叠,且半导体芯片160B可与半导体芯片110B竖直地堆叠。也就是说,半导体芯片160A与半导体芯片110A至少部分地交叠,且半导体芯片160B与半导体芯片110B至少部分地交叠。半导体芯片160A、半导体芯片160B可与半导体芯片110A、半导体芯片110B类似。简单来说,半导体芯片160可包含半导体衬底161、接触衬垫163、接触柱165以及保护层167。接触柱165可在多个接触衬垫163上方延伸,且包含直接在接触衬垫163上方延伸的部分1651和在半导体衬底161上方延伸的部分1652。在一些实施例中,半导体芯片160A、半导体芯片160B是整合式无源器件的芯片。
在一些实施例中,密封体170形成在介电层140上方以横向密封TIW 150和半导体芯片160。在一些实施例中,可遵循与密封体130类似的工艺且利用类似的材料产生密封体170。在一些实施例中,密封体130和密封体170可包含不同材料。在一些替代实施例中,密封体130的材料和密封体170的材料可相同。密封体170形成为使得TIW 150的顶部表面150t以及接触柱165在半导体芯片160的顶部表面160t处保持暴露。在一些实施例中,TIW 150的顶部表面150t、半导体芯片160的顶部表面160t以及密封体170的顶部表面170t可相对于彼此大体上齐平。在一些实施例中,将TIW 150、半导体芯片160以及密封体170视为无源器件模块单元PDMU的上部层级T2的部分。
参考图1F,在一些实施例中,连接端子180形成在TIW 150的暴露顶部表面150t和接触柱165上。连接端子180可包含焊料球、球栅阵列封装(ball grid array,BGA)连接件、金属支柱、受控塌陷芯片连接(controlled collapse chip connection,C4)凸块、微凸块、经由无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersiongold,ENEPIG)形成的凸块、其组合(例如具有贴合的焊料球的金属支柱)或类似物。连接端子180经由TIW 150电连接到半导体芯片110。在一些实施例中,在连接端子180的形成之后,可例如通过沿切割道SC进行切割来分割重建构晶片,以分离个别无源器件模块单元PDMU。在一些实施例中,可移除载体100和剥离层102以产生图1G中绘示的无源器件模块PDM1。
图1G是根据本公开的一些实施例的无源器件模块PDM1的示意性侧视图。图2A是根据本公开的一些实施例的无源器件模块PDM1的示意性横截面图。图2A的横截面图是沿Z方向上的水平高度I-I(图1G中绘示)在由方向X和方向Y定义的平面中截取的。在图2A中,出于论述目的将半导体芯片110A、半导体芯片110B的覆盖区绘示为点划线,即使半导体芯片110A、半导体芯片110B并不在XY平面(在所述XY平面处截取所述横截面图)内延伸。图2B和图2C是根据本公开的一些实施例的在由X方向和Z方向定义的平面中截取的无源器件模块PDM1的示意性横截面图。图2B的示意性截面图是沿图2A中所示出的Y方向上的水平高度II-II截取的。图2C的示意性截面图是沿图2A中所示出的Y方向上的水平高度III-III截取的。参考图1G和图2A到图2C,在一些实施例中,无源器件模块PDM1包含下部层级T1中的密封在密封体130中的半导体芯片110和上部层级T2中的密封在密封体170中的半导体芯片160。在一些实施例中,半导体芯片110面向上层半导体芯片160的后表面160r。上部层级T2的半导体芯片160与下部层级T1的半导体芯片110部分地交叠。也就是说,下部层级T1的半导体芯片110的至少一部分并不由上部层级T2的半导体芯片160覆盖。举例来说,半导体芯片110可具有最长侧沿Y方向设置的细长轮廓(例如矩形覆盖区),且半导体芯片160可具有最长侧沿X方向设置的细长轮廓(例如矩形覆盖区)。因此,相比于上覆的半导体芯片160,半导体芯片110可在Y方向上具有更大的延伸。TIW 150可形成在并不由半导体芯片160覆盖的接触柱115上。在一些实施例中,如图2A中所示出,半导体芯片110可在Y方向上从半导体芯片160的两个相对侧突出,且TIW 150可设置在半导体芯片160的相对侧上。因此,半导体芯片160的相对侧表面160s1、相对侧表面160s2可皆沿Y方向面向TIW 150。TIW 150可在半导体芯片160的侧面上延伸穿过密封体170,以提供形成在上部层级T2上的连接端子180与半导体芯片110之间的电连接。在一些实施例中,TIW 150可具有细长轮廓,其中沿X方向(侧表面160s1和侧表面160s2的方向)的尺寸D1大于沿Y方向的尺寸D2。在一些实施例中,尺寸D1与尺寸D2的比率介于1到5范围内。如图2B中所示出,在一些实施例中,沿Y方向上的水平高度II-II(图2A中绘示)截取的无源器件模块PDM1的横截面图可展现仅下部层级T1的半导体芯片110,以及上层TIW 150。类似地,在图2C中,沿Y方向上的水平高度III-III(图2A中绘示)截取的无源器件模块PDM1的横截面图可展现堆叠的半导体芯片110、半导体芯片160,而TIW150可能并不可见。在一些实施例中,连接端子180可用于将无源器件模块PDM1整合在较大器件(未绘示)中。在一些实施例中,通过封装如本文中所公开的半导体芯片110、半导体芯片160,有可能在无源器件模块PDM1内实现整合式无源器件的更高密度,从而减小所述无源器件模块PDM1的外观尺寸和寄生电感。
图2D是根据本公开的一些实施例的无源器件模块PDM1B的示意性横截面图。图2D的横截面图是沿图2A的横截面图的相同水平高度I-I(图1G中绘示)截取的。在一些实施例中,图2D的无源器件模块PDM1B与图2A的无源器件模块PDM1之间的区别在于TIW 150的定向。也就是说,无源器件模块PDM1B的TIW 150可具有沿X方向的尺寸D1,所述沿X方向的尺寸D1小于沿Y方向的尺寸D2。换句话说,TIW 150可具有比相邻半导体芯片160(TIW 150直接面向半导体芯片160)的面向侧表面(例如160s1)的延伸方向(例如方向X)更大的沿不同方向(例如方向Y)定向的尺寸(例如尺寸D2)。在一些实施例中,尺寸D1和尺寸D2是相同的大小。
图2E是根据本公开的一些实施例的无源器件模块PDM1C的示意性侧视图。在一些实施例中,图2E的无源器件模块PDM1C与图1G的无源器件模块PDM1之间的区别在于半导体芯片110、半导体芯片160中的一或多个已由包含有源器件的半导体管芯替换。举例来说,半导体管芯110D替代半导体芯片110B设置于下部层级T1中。半导体管芯110D包含形成在半导体衬底111D中的有源器件,且可充当逻辑管芯。在一些替代实施例中,半导体管芯110D可充当存储器管芯。也就是说,半导体管芯110D可以是有源器件或充当有源器件。在一些实施例中,无源器件模块比有源器件包含更大数目的整合式无源器件。
图3A是根据本公开的一些实施例的无源器件模块PDM2的示意性侧视图。在一些实施例中,无源器件模块PDM2与图1G的无源器件模块PDM1类似,且进一步包含形成在上部层级T2上并插入于半导体芯片160A、半导体芯片160B、TIW 150与连接端子180之间的重布线结构190。在一些实施例中,重布线结构190包含介电层192、重布线导电层194以及多个凸块下金属196。为简单起见,介电层192示出为单个介电层,且重布线导电层194示出为嵌入于介电层192中。尽管如此,从制造工艺的角度来看,介电层192由至少两个介电层构成。重布线导电层194可由多个重布线导电图案构成。重布线导电层194的重布线导电图案包夹在两个相邻介电层之间。重布线导电图案中的一些可竖直地延伸穿过介电层192,以在重布线结构190的不同金属化层级之间建立电连接。在一些实施例中,(最外)介电层192可经图案化以暴露下层重布线导电层194。凸块下金属196可任选地在暴露重布线导电层194的(最外)介电层192的开口中共形地形成,且可进一步在(最外)介电层192的暴露表面的部分上方延伸。在一些实施例中,凸块下金属196包含多个堆叠层。举例来说,凸块下金属196可包含堆叠在晶种层上的一或多个金属层。
在一些实施例中,重布线导电层194和凸块下金属196的材料包含铝、钛、铜、镍、钨或其合金。重布线导电层194和凸块下金属196可由例如电镀、沉积和/或光刻(photolithography)以及刻蚀形成。在一些实施例中,介电层192的材料包含聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene,BCB)、聚苯并恶唑(polybenzooxazole,PBO)或任何其它合适的聚合物类介电材料。介电层192可例如由合适的制作技术形成,所述合适的制作技术例如旋涂法、化学气相沉积(CVD)、等离子体增强化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)或类似物。应注意,图3A中所示出的重布线导电层194的数目和介电层192的数目仅为达成说明性目的,且本公开不限于此。在一些替代实施例中,可取决于电路设计而形成更少或更多层的重布线导电层194和更少或更多层的介电层192。在需要更多层的重布线导电层194和更多层的介电层192时,重布线导电层194的层仍与介电层192的层交替地堆叠。
在一些实施例中,可遵循上文相对于图1A到图1F针对无源器件模块PDM1所描述的类似工艺制作图3A的无源器件模块PDM2。举例来说,重布线结构190可在形成连接端子180之前形成在图1E中所示出的结构上。此后,可设置连接端子180,可分割无源器件模块PDM2,且可移除载体100。
图3B是根据本公开的一些实施例的无源器件模块PDM2B的示意性侧视图。在一些实施例中,无源器件模块PDM2B与图3A的无源器件模块PDM2类似,且进一步包含形成在下部层级T1上并插入于下部层级T1与上部层级T2之间的重布线结构144。在一些实施例中,重布线结构144可包含介电层140和嵌入于介电层140中的重布线导电层146。在一些实施例中,重布线导电层144可互连下部层级T1的半导体芯片110A、半导体芯片110B,且进一步提供半导体芯片110A、半导体芯片110B与TIW 150之间的电连接。
图4A是根据本公开的一些实施例的无源器件模块PDM3的示意性侧视图。图4B是沿Z方向上的水平高度IV-IV(图4A中绘示)截取的在XY平面中的图4A的无源器件模块PDM3的示意性横截面图。在一些实施例中,半导体芯片110、半导体芯片160以及TIW 150可沿与先前论述的无源器件模块PDM1和无源器件模块PDM2中示出的方向不同的方向定向。举例来说,在半导体器件PDM3中,下部层级T1的半导体芯片110A可相对于上部层级T2的上层半导体芯片160A沿X方向突出,且下部层级T1的另一半导体芯片110B可相对于上部层级T2的上层半导体芯片160B沿Y方向突出。在一些实施例中,半导体芯片110、半导体芯片160可具有细长形状(例如矩形覆盖区)。在一些实施例中,半导体芯片110A可具有沿X方向延伸的覆盖区的较长侧,且半导体芯片110B可具有沿Y方向延伸的较长侧。在一些实施例中,半导体芯片160A可具有沿Y方向延伸的较长侧,且半导体芯片160B可具有沿X方向延伸的较长侧。在一些实施例中,半导体芯片160B可与下部层级T1的半导体芯片110A和半导体芯片110B两者部分地交叠。在一些实施例中,形成在半导体芯片110A上的TIW 150A可具有细长形状,其中沿Y方向延伸的尺寸更长。TIW 150A中的一些可设置在上部层级T2的半导体芯片160A与半导体芯片160B之间。形成在半导体芯片110B上的TIW 150B也可具有细长形状,其中沿X方向延伸的尺寸更长。在一些实施例中,半导体芯片160B可面向形成在半导体芯片110A和半导体芯片110B中的每一个上的TIW 150A和TIW 150B。在一些实施例中,半导体芯片160B具有沿三个侧面延伸的TIW 150A和TIW 150B。在一些实施例中,半导体芯片160A具有保护层167A以及接触柱165A,半导体芯片160B具有保护层167B以及接触柱165B。
图5A到图5G是在无源器件模块PDM4的制造工艺期间产生的结构的示意性侧视图。参考图5A,设置载体200(任选地具有形成在其上的剥离层202)。在一些实施例中,载体200是玻璃衬底、金属板、塑料支撑板或类似物,但可使用其它合适的衬底材料,只要所述材料能够承受工艺的后续步骤即可。在一些实施例中,剥离层202包含光热转换(LTHC)层释放层。在一些实施例中,背侧重布线结构210形成在载体200上。背侧重布线结构210包含介电层212和嵌入于介电层212中的重布线导电层214。在一些实施例中,介电层212在载体200上方毯覆式地延伸,且包含远离载体200的表面210a的开口216。重布线导电层214的部分经由开口216暴露。在一些实施例中,可遵循如上文针对重布线结构190所描述的类似工艺制作背侧重布线结构210。在一些实施例中,TIW 220可对应于开口216形成在背侧重布线结构210上。TIW 220可填充开口216以接触重布线导电层214。简单来说,TIW 220可通过将导电材料沉积在后续移除的辅助掩模(未绘示)的开口中来制作,或可通过将预制的金属块取放在背侧重布线结构210上来形成。
参考图5B,半导体芯片230可在TIW 220之间设置在背侧重布线结构210上。在一些实施例中,每一半导体芯片230包含半导体衬底231、形成在半导体衬底231上的接触衬垫233、形成在接触衬垫233上的接触柱235以及覆盖半导体衬底231的顶部表面的保护层237。在一些实施例中,半导体芯片230以正面朝上的配置设置,具有其中接触柱235暴露的远离背侧重布线结构210的顶部表面230t(接触表面)。在一些实施例中,半导体芯片230是整合式无源器件的芯片。在一些实施例中,密封体240形成在背侧重布线结构210上以横向环绕TIW 220和半导体芯片230。在一些实施例中,密封体240的材料和制造工艺可与上文针对密封体130所论述的材料和制造工艺类似。在一些实施例中,密封体的顶部表面240t与TIW220的顶部表面220t、半导体芯片230的接触表面230t与保护层237的顶部表面237t大体上齐平。在一些实施例中,可将嵌入于密封体240中的半导体芯片230和TIW 220视为无源器件模块单元PDMU的下部层级T1。
参考图5C,在一些实施例中,介电层250形成在TIW 220、半导体芯片230以及密封体240上。介电层250经图案化以包含暴露半导体芯片230的下层接触柱235和TIW 220的顶部表面220t的开口252。介电层250可以是单层或多层结构,且可包含例如PBO的聚合物、其它合适的介电材料或其组合。介电层250可由合适的制作技术形成,所述合适的制作技术例如旋涂法、化学气相沉积(CVD)或类似物。在一些实施例中,TIW 260形成在TIW 220上方,且TIW 270形成在半导体芯片230上方。在一些实施例中,对于TIW220,TIW 260和TIW 270可分别镀覆在TIW 220和接触柱235的暴露部分上,或可以是预制的金属块。在一些实施例中,TIW 260经由TIW 220电连接到背侧重布线结构210。也就是说,TIW 260可堆叠在TIW 220上方,且TIW 270可堆叠在半导体芯片230上方。
参考图5D,在一些实施例中,半导体芯片280设置在介电层250上位于TIW 260旁侧。在一些实施例中,半导体芯片280经由取放方法放置到介电层250上。半导体芯片280可设置在介电层250上,具有远离介电层250的暴露接触柱285的顶部表面280t。半导体芯片280可与半导体芯片230竖直地堆叠且部分地交叠。也就是说,每一半导体芯片230的至少一部分可由上层半导体芯片280暴露。半导体芯片280可与半导体芯片230类似。在一些实施例中,半导体芯片280是整合式无源器件。在一些实施例中,密封体290形成在介电层250上方以横向密封TIW 260、TIW 270以及半导体芯片280。在一些实施例中,可遵循如上文针对密封体130所描述的类似工艺且利用类似材料产生密封体290。密封体290形成为使得TIW260、TIW 270的顶部表面260t、顶部表面270t以及接触柱285在半导体芯片280的顶部表面280t处保持暴露。在一些实施例中,TIW 260、TIW 270的顶部表面260t、顶部表面270t,半导体芯片280的顶部表面280t以及密封体290的顶部表面290t可相对于彼此大体上齐平。在一些实施例中,将TIW 260、TIW 270、半导体芯片280以及密封体290视为无源器件模块单元PDMU的上部层级T2的部分。
参考图5E,在一些实施例中,重布线结构300可形成在密封体290、半导体芯片280以及TIW 260、TIW 270上方。重布线结构300包含介电层302、嵌入于介电层302中的重布线导电层304以及任选地相对于半导体芯片280设置在重布线结构300的相对侧上的凸块下金属306。在一些实施例中,重布线结构300直接电连接到半导体芯片280,经由TIW 270电连接到半导体芯片230,且经由TIW 260和TIW 220电连接到背侧重布线结构210。连接端子310可设置在凸块下金属306上。重布线结构300和连接端子310的材料和制造工艺可分别与先前针对重布线结构190和连接端子180描述的材料和制造工艺类似。
参考图5E和图5F,重建构晶片可在支撑框架SF上方翻转以继续制造工艺。在一些实施例中,其中已形成连接端子310的重布线结构300的表面设置为更接近于支撑框架SF。移除载体200以暴露背侧重布线结构210以供用于进一步处理。在一些实施例中,连接端子310可嵌入于保护带(未绘示)中。在一些实施例中,开口218可例如由激光钻孔形成在背侧重布线结构210的介电层212中以暴露重布线导电层214的部分。连接端子315可对应于开口218形成以与重布线导电层214电连接。在一些实施例中,可任选地在形成连接端子315之前形成凸块下金属(未绘示)。在一些实施例中,在连接端子315的形成之后,可例如通过沿切割道SC进行切割来分割重建构晶片,以分离个别无源器件模块单元PDMU。
图5G是根据本公开的一些实施例的无源器件模块PDM4的示意性侧视图。图6是无源器件模块PDM4的示意性横截面图。图6的横截面图是沿Z方向上的水平高度V-V(图5G中绘示)在由方向X和方向Y定义的平面中截取的。在图6中,出于论述目的将半导体芯片230的覆盖区绘示为点划线,即使半导体芯片230并不在XY平面(在所述XY平面处截取图6的横截面图)内延伸。参考图5G和图6,在一些实施例中,无源器件模块PDM4包含包夹在重布线结构300与背侧重布线结构210之间的下部层级T1的半导体芯片230和上部层级T2的半导体芯片280。下部层级T1的半导体芯片230由密封体240密封,且TIW 220从背侧重布线结构210穿过密封体240朝向上部层级T2延伸。上部层级T2的半导体芯片280由密封体290密封,且TIW260从下部层级T1穿过密封体290朝向重布线结构300延伸。TIW 270也从下部层级T1穿过密封体290朝向重布线结构300延伸。连接端子310和连接端子315分别设置在重布线结构300和背侧重布线结构210上,以实现无源器件模块PDM4的双侧竖直整合。在一些实施例中,TIW260和TIW 270具有细长形状。在一些实施例中,TIW 260和TIW 270的伸长方向可能不同。举例来说,TIW 260可具有大体上沿Y方向延伸的最长尺寸,同时TIW 270可具有大体上沿X方向延伸的最长尺寸。在一些实施例中,TIW 260可设置在上部层级T2的半导体芯片280之间。在一些实施例中,相比于半导体芯片280,半导体芯片230在TIW 260的伸长方向(例如图6中的Y方向)上的延伸可能更大,且TIW 270可沿TIW 260的伸长方向形成为面向半导体芯片280的两个相对侧。也就是说,半导体芯片280在四个侧面上可由TIW 260和TIW 270包围。在一些实施例中,在下部层级T1中,TIW 220可具有大体上与上层TIW 260的覆盖区相对应的覆盖区。也就是说,TIW 220可沿半导体芯片230的侧面且在半导体芯片230之间延伸。在一些实施例中,半导体芯片230的两个相对侧表面可沿X方向面向TIW 220。在一些实施例中,TIW260和TIW 220的覆盖区(提供重布线结构300与背侧重布线结构210之间的竖直电连接)可大于TIW 270的覆盖区(提供半导体芯片230与重布线结构300之间的电连接)。在一些实施例中,分别形成在半导体芯片230A与半导体芯片230B上的TIW 270A与TIW 270B可具有细长形状,其中沿X方向延伸的尺寸更长。
图7是根据本公开的一些实施例的无源器件模块PDM5的示意性侧视图。在无源器件模块PDM5中,连接端子315可直接形成在TIW 220上。也就是说,可省略背侧重布线结构210(图5G中绘示)的形成。在一些实施例中,无源器件模块PDM5可遵循与针对无源器件模块PDM4所描述的工艺类似的工艺形成,省略背侧重布线结构210(图5A中绘示)的形成。举例来说,TIW220和半导体芯片230可直接设置在载体200(或剥离层202,皆在图5A中绘示)上。此外,在重建构晶片在支撑框架SF(如图5F中所绘示)上方翻转时,连接端子315可直接形成在TIW 220上。
图8A是根据本公开的一些实施例的无源器件模块PDM6的示意性侧视图。图8B是沿Z方向上的水平高度VI-VI(图8A中绘示)截取的在XY平面中的图8A的无源器件模块PDM6的示意性横截面图。在一些实施例中,半导体芯片230、半导体芯片280以及TIW 270可沿与先前论述的针对无源器件模块PDM4和无源器件模块PDM5所示出的方向不同的方向定向。举例来说,在半导体器件PDM6中,下部层级T1的半导体芯片230A可相对于上部层级T2的上层半导体芯片280A沿X方向突出,且下部层级T1的另一半导体芯片230B可相对于上部层级T2的上层半导体芯片280B沿Y方向突出。在一些实施例中,半导体芯片230、半导体芯片280可具有细长形状(例如矩形覆盖区)。在一些实施例中,半导体芯片230A可具有沿X方向延伸的最长侧,且半导体芯片230B可具有沿Y方向延伸的最长侧。在一些实施例中,半导体芯片280A可具有沿Y方向延伸的最长侧,且半导体芯片280B可具有沿X方向延伸的最长侧。在一些实施例中,半导体芯片280B可与下部层级T1的半导体芯片230A和半导体芯片230B两者部分地交叠。在一些实施例中,形成在半导体芯片230A上的TIW 270A可具有细长形状,其中沿Y方向延伸的尺寸更长。在一些实施例中,形成在半导体芯片230B上的TIW 270B可具有细长形状,其中沿X方向延伸的尺寸更长。TIW 270A中的一些可设置在半导体芯片280A与半导体芯片280B之间。也就是说,在无源器件模块PDM6中,TIW 270A(而非TIW 260)可插入于半导体芯片280A与半导体芯片280B之间(如针对图6中的无源器件模块PDM4所绘示)。在一些实施例中,TIW 270A可插入于半导体芯片280A与TIW 260之间,同时半导体芯片280B可直接面向TIW 260。
图9是根据本公开的一些实施例的无源器件模块PDM7的示意性侧视图。在无源器件模块PDM7中,连接端子315可直接形成在TIW 220上。也就是说,可省略背侧重布线结构210(图8A中绘示)的形成。在无源器件模块PDM7中,半导体芯片230A、半导体芯片230B、半导体芯片280A、半导体芯片280B的设置可与图8B中所示出的用于无源器件模块PDM7的设置类似。举例来说,半导体芯片230A和半导体芯片280B可具有沿方向X延伸的较长侧和沿方向Y延伸的较短侧,同时半导体芯片230B和半导体芯片280A可具有沿方向Y延伸的较长侧和沿方向X延伸的较短侧。在一些实施例中,半导体芯片280B与下部层级T1的多个半导体芯片230A、半导体芯片230B部分地交叠。在一些实施例中,重布线结构300以及TIW 260、TIW 220可在下部层级T1的半导体芯片230A、半导体芯片230B中的一或多个与连接端子315之间建立电连接。
图10A到图10G是在根据本公开的一些实施例的无源器件模块PDM8的制造方法期间产生的结构的示意性横截面图。参考图10A,在一些实施例中,设置载体320,其任选地具有形成在其上的剥离层322。介电层330可毯覆式地设置在载体320上方。此后,TIW 340可形成在介电层330上。图10A的横截面图是沿Y方向上的水平在XZ平面中截取的,其中TIW 340不可见。出于这个原因,将TIW 340在图10A的XZ平面中的投射绘示为点划线。在一些实施例中,半导体芯片350设置在介电层330上,其中接触柱352远离介电层330。在一些实施例中,半导体芯片350可由管芯贴合膜354的部分紧固到介电层。密封体360可形成在介电层330上以横向覆盖半导体芯片350和TIW 340。在一些实施例中,密封体的顶部表面360t、半导体芯片350的顶部表面350t以及TIW 340的顶部表面大体上齐平。在一些实施例中,可将密封的TIW 340和半导体芯片350视为无源器件模块单元PDMU的最低层级T1。在图10A的横截面图中,出于说明的目的绘示两个无源器件模块单元PDMU,但本公开不限于此。
参考图10B,重布线结构370可形成在最低层级T1上以使半导体芯片350与属于相同无源器件模块单元PDMU的相邻TIW 340互连。在一些实施例中,重布线结构370包含介电层372和重布线导电层374,所述重布线导电层374可经由接触柱352与半导体芯片350电接触且与TIW 340电接触。参考图10C,介电层372可经图案化以暴露重布线导电层374的部分。TIW 380可随后形成在重布线结构370上方。TIW 380填充介电层372的开口376以建立与重布线导电层374的电接触。在一些实施例中,TIW 380可形成为不与最低层级T1的TIW 340竖直地对准。举例来说,TIW 380和TIW 340可不沿Y方向竖直地对准。因此,TIW 380可在图10C的视图的XZ平面中为可见的,同时TIW 340可在视图的相同XZ平面中为不可见的。半导体芯片390可设置在TIW 380旁侧,其中顶部表面390t背对重布线结构370。半导体芯片390可与最低层级T1的半导体芯片350竖直地堆叠。
参考图10D,TIW 380和半导体芯片390可横向密封在密封体400中,且统称为无源器件模块单元PDMU的下部中间层级T2。包括介电层412和重布线导电层414的重布线结构410可设置在下部中间层级T2上方,以使半导体芯片390与相同无源器件模块单元PDMU的TIW 380电互连。在一些实施例中,TIW 380提供最低层级T1上的重布线结构370与下部中间层级T2上的重布线结构410之间的竖直电连接。也就是说,TIW 380可竖直地延伸穿过密封体400以接触重布线导电层374和重布线导电层414。
参考图10E,在一些实施例中,上部中间层级T3和最高层级T4可添加在重布线结构410上方,遵循如先前针对层级T1和层级T2所描述的类似工艺。简单来说,重布线结构410的介电层412经图案化以暴露重布线导电层414的部分。TIW 420形成在重布线结构410上,电连接到重布线导电层414。TIW 420可相对于下部中间层级T2的TIW 380竖直地不对准(在Y方向上),同时可与最低层级T1的TIW 340竖直地交叠。也就是说,在无源模块单元中,形成在每一其它层级中的TIW(例如层级T3的TIW 420和层级T1的TIW 340)可彼此竖直地对准。半导体芯片430设置在TIW 420旁侧,分别与下部层级T2和下部层级T1的半导体芯片390和半导体芯片350竖直地堆叠。半导体芯片430可相对于下层重布线结构410以正面朝上的配置设置(例如其中接触表面远离重布线结构410)。密封体440形成为横向环绕半导体芯片430和TIW 420。重布线结构450包含介电层452,且重布线导电层454形成在上部中间层级T3上。包括TIW 460、半导体芯片470以及密封体480的最高层级T4形成在上部中间层级T3上方,之后为重布线结构490。在一些实施例中,重布线结构490的上部表面490t(在Z方向上的远离半导体芯片470的表面)可保留而不经图案化。也就是说,重布线结构490的重布线导电层494可在一个侧面上与半导体芯片470和TIW 460连接,同时在相对侧上由介电层492覆盖。
在一些实施例中,可通过沿切割道SC1切割包含多个无源器件模块单元PDMU的重建构晶片来执行单一化工艺。在一些实施例中,同一无源器件模块单元PDMU的层级T1到层级T4的TIW 340、TIW 380、TIW 420以及TIW460的外边缘在X方向上进一步远离属于同一无源器件模块单元PDMU的皆大体上处于同一YZ平面内的半导体芯片350、半导体芯片390、半导体芯片430、半导体芯片470。也就是说,在TIW 340、TIW 380、TIW 420以及TIW460可由于其沿Y方向分布而不竖直地对准(当在YZ平面中查看时)时,TIW 340、TIW 380、TIW 420以及TIW 460的外边缘可沿X方向位于同一水平处。在一些实施例中,切割道SC1可沿TIW 340、TIW 380、TIW 420以及TIW 460的对准的外边缘延伸。也就是说,可通过在TIW 340、TIW380、TIW420以及TIW 460与对应密封体360、密封体400、密封体440、密封体480之间的界面处进行切割来单一化无源器件模块单元PDMU。在一些实施例中,半导体芯片350、半导体芯片390、半导体芯片430、半导体芯片470可在无源器件模块单元PDMU的一个侧面处竖直地交叠,同时TIW 340、TIW 380、TIW 420以及TIW 460可在无源器件模块单元PDMU的相对侧处交替地竖直对准。举例来说,在给定层级(例如下部层级T1)中,TIW(例如TIW 340)可设置在左手侧上,且半导体芯片(例如半导体芯片350)可设置在右手侧上。可在无源器件模块单元的所有层级(例如T2到T4)中重复类似分布。因此,即使在单一化之前,给定层级(例如层级T2)中的半导体芯片(例如半导体芯片390)可在沿X方向的两侧上具有TIW(例如TIW 380),重布线结构370、重布线结构410、重布线结构450或重布线结构490仍可使半导体芯片与仅设置在半导体芯片的一个侧面处的TIW互连。在一些实施例中,遵循单一化步骤,无源器件模块单元PDMU可大体上为平行六面体,且暴露以下各项:三个侧面上的介电层330,若干层级T1到层级T4的密封体360、密封体400、密封体440以及密封体480和重布线结构370、重布线结构410、重布线结构450、重布线结构490的介电层372、介电层412、介电层452、介电层492;第四侧上的介电层330;第五侧上的介电层492;以及第六侧上的密封体360、密封体400、密封体440以及密封体480,介电层330、介电层372、介电层412、介电层452、介电层492以及TIW340、TIW 380、TIW420、TIW 460。
参考图10E和图10F,在一些实施例中,可移除载体320,且单一化无源器件模块单元PDMU可旋转且设置在支撑框架SF上方。在一些实施例中,执行90度(或同等)旋转,以将无源模块单元PDMU设置在支撑框架SF上,其中第六侧(暴露TIW 340、TIW 380、TIW 420、TIW460的侧)暴露且可供用于进一步处理(例如具有与面向支撑框架SF的第六侧相对的侧)。在一些实施例中,连接端子510安装在TIW 340、TIW 380、TIW 420以及TIW 460的暴露的外边缘上。也就是说,层级T2到层级T4的TIW 380、TIW 420、TIW 460可包夹在相邻重布线结构370、重布线结构410、重布线结构450、重布线结构490的对之间,具有连接到所述对的一个重布线结构的一个端部和连接到所述对的其它重布线结构的另一端部,且进一步具有设置在暴露的外边缘上的连接端子510。也就是说,TIW 380可直接电连接到三个不同元件(例如两个重布线结构和一个连接端子510)。在一些实施例中,连接端子510相对于半导体芯片350、半导体芯片390、半导体芯片430以及半导体芯片470的接触表面以90度的角度安装。连接端子510可用于与更大器件(未绘示)整合。参考图10F和图10G,在一些实施例中,在移除支撑框架SF之后,获得无源器件模块PDM8。
图10G是根据本公开的一些实施例的无源器件模块PDM8的XZ平面中的示意性横截面图。图11A是根据本公开的一些实施例的无源器件模块PDM8的透视三维图。图11B是根据本公开的一些实施例的无源器件模块PDM8的ZY平面中的示意性横截面图。图11B的横截面图可沿图11A中示出的X方向在水平高度VII-VII处截取。图11C是根据本公开的一些实施例的无源器件模块PDM8的XY平面中的示意性横截面图。图11C的横截面图可沿图11A中示出的Z方向在水平高度VIII-VIII处截取。参考图10G和图11A到图11C,无源器件模块PDM8可包含多个堆叠的层级T1到层级T4,每一层级T1到层级T4包括密封的半导体芯片350、半导体芯片390、半导体芯片430、半导体芯片470以及TIW 340、TIW 380、TIW 420、TIW 460。TIW 340、TIW 380、TIW 420以及TIW 460可在无源器件模块PDM8的一个侧面处暴露,且具有设置在其上的连接端子510。在一些实施例中,TIW 340、TIW 380、TIW 420、TIW 460以及密封体360、密封体400、密封体440、密封体480可在无源器件模块PDM8的侧面上暴露以便定义棋盘形图案。也就是说,在给定层级(例如层级T2)内沿Y方向移动,密封体400和TIW 380的暴露部分可交替。类似地,贯穿不同层级T1到层级T4沿Z方向移动,密封体的部分和TIW的部分可交替地暴露。举例来说,在给定Y水平处沿Z方向继续进行,层级T1和层级T3的TIW 340和TIW 420以及层级T2和层级T4的密封体400和密封体480的部分相遇。在不同Y水平处,层级T2和层级T4的TIW 380和TIW 460以及密封体360和密封体440相遇。在相邻层级之间设置中间重布线结构370、重布线结构410、重布线结构450的介电层。如图11A和图11C中所示出,在给定Z水平处,层级(例如层级T3)的密封体(例如密封体440)可在所有侧面上暴露,同时TIW(例如TIW 420)可仅在一个侧面上暴露。
图12A是在根据本公开的一些实施例的无源器件模块PDM9(图12B中绘示)的制造方法期间产生的结构的示意性横截面图。图12B是根据本公开的一些实施例的无源器件模块PDM9的透视图。图12C是沿图12B中绘示的水平高度XII-XII截取的在XY平面中的无源器件模块PDM9的示意性横截面图。在一些实施例中,图12A的结构可遵循如相对于图10A到图10E所描述的类似工艺形成。图12A的结构与图10E的结构之间的区别在于半导体芯片350、半导体芯片390、半导体芯片430以及半导体芯片470电连接到沿X方向设置在每一侧上的TIW 340、TIW 380、TIW 420、TIW 460。也就是说,以下部中间层级T2为例,半导体芯片390电连接到在图12A中示出为在其右手侧上和在其左手侧上的TIW 380。在一些实施例中,在单一化重建构晶片之前,属于相邻无源器件模块单元PDMU的半导体芯片可连接到同一TIW(共享TIW)。在一些实施例中,通过沿延伸穿过若干层级T1到层级T4的TIW 340、TIW 380、TIW420、TIW 460的切割道SC2进行切割来单一化无源器件模块单元PDMU。因此,TIW 340、TIW380、TIW 420以及TIW 460在无源器件模块PDM9的两个相对侧处暴露。如图12B中所示出,连接端子510可安装在于一个侧面处暴露的TIW 340、TIW 380、TIW 420、TIW 460上,且连接端子520可在相对侧上安装在TIW 340、TIW 380、TIW 420、TIW460上。在一些实施例中,沿图12B的水平高度IX-IX或水平高度XI-XI的在YZ平面中截取的无源器件模块PDM9的横截面图与图11B中示出的无源器件模块PDM8的横截面图类似。如图12C中所示出,在一些实施例中,设置于给定层级(例如层级T2)的半导体芯片(例如半导体芯片390)的相对侧处的TIW(例如TIW 380)可沿X方向对准(可沿Y方向设置于同一水平处)。然而,本公开并不限于此。
在一些实施例中,本文中所公开的无源器件模块可整合在任何类型的半导体封装中。图13A到图13C绘示根据本公开的一些实施例的示范性半导体封装SP1到半导体封装SP3的示意性侧视图。然而,本公开并不受限于其中可整合无源器件模块的半导体封装的类型。应注意,虽然半导体封装SP1到半导体封装SP3示出为具有整合于其中的无源器件模块PDM1,但可在半导体封装中使用属于本公开的范围内的任何其它无源器件模块。参考图13A,半导体封装SP1包含半导体管芯530,电连接到重布线结构540。在一些实施例中,半导体管芯530中的每一个可独立地为或包含逻辑管芯或存储器管芯。在一些实施例中,重布线结构540形成在半导体管芯530的有源表面530t上。半导体管芯530可设置在重布线结构540的第一侧540a上且由密封体550密封。导电端子560可设置在重布线结构540的与第一侧540a相对的第二侧540b上。在一些实施例中,无源器件模块(例如无源器件模块PDM1)可从第二侧540b连接到重布线结构540。也就是说,无源器件模块可在导电端子560之间设置在重布线结构540的第二侧540b上。在一些实施例中,无源器件模块的连接端子(例如无源器件模块PDM1的连接端子180)可建立重布线结构540与无源器件模块之间的电连接。在一些实施例中,多个无源器件模块可连接到重布线结构540。举例来说,无源器件模块可与设置在重布线结构590上的半导体管芯530中的每一个对应地(与所述半导体管芯中的每一个竖直地交叠)设置。在一些实施例中,半导体封装SP1可以是整合的扇出型半导体器件。
在一些实施例中,半导体封装SP2可以是叠层封装半导体器件。半导体封装SP2可包含下部封装570和连接到下部封装的上部封装575。在一些实施例中,下部封装570包含连接到重布线结构590的第一侧590a的半导体管芯580。重布线结构590可形成在半导体管芯580的有源表面580t上,且被称为前侧重布线结构。在一些实施例中,半导体管芯580可由密封体600密封,且背侧重布线结构610可相对于前侧重布线结构590的相对侧上在密封体600和半导体管芯580上方延伸。绝缘体穿孔620可使前侧重布线结构590与背侧重布线结构610电连接。在一些实施例中,导电端子630设置在重布线结构590的与第一侧590a相对的第二侧590b上。在一些实施例中,下部封装570的半导体管芯580为逻辑管芯或包含逻辑管芯。在一些实施例中,上部封装575包含连接到插入件650的一或多个半导体管芯640。在一些实施例中,半导体管芯640是存储器管芯或包含存储器管芯。半导体管芯640可任选地由密封体660密封。上部封装575可经由导电端子670连接到下部封装570的背侧重布线结构610。在一些实施例中,无源器件模块(例如无源器件模块PDM1)可从第二侧590b连接到前侧重布线结构590。也就是说,无源器件模块可在导电端子630之间设置在重布线结构590的第二侧590b上。在一些实施例中,无源器件模块的连接端子(例如无源器件模块PDM1的连接端子180)可建立重布线结构590与无源器件模块之间的电连接。
根据本公开的一些实施例,半导体封装SP3可以是大型(例如晶片大小或面板大小)半导体封装。在一些实施例中,大型半导体封装SP3包含电连接到重布线结构690的第一侧690a的多个半导体管芯680。半导体管芯680可在重布线结构690上以阵列方式并排地设置。在一些实施例中,半导体管芯680的有源表面680t与重布线结构690接触。密封体700可形成在重布线结构690上以密封半导体管芯680。在一些实施例中,散热器710可相对于重布线结构690在相对侧上任选地设置在密封体700上。导电端子720可设置在重布线结构690的与第一侧690a相对的第二侧690b上,且可建立与插口730的电连接。额外模块740(例如存储器、功率模块、射频模块等)可设置在插口730上。在一些实施例中,一或多个无源器件模块从第二侧690b连接到重布线结构690。无源器件模块(例如无源器件模块PDM1、无源器件模块PDM7)可设置在导电端子720之间,且可位于插口730与重布线结构690之间。
在一些实施例中,在使用与无源器件模块PDM8(图11A中绘示)或无源器件模块PDM9(图12A中绘示)类似的无源器件模块时,包含在无源器件模块中的半导体芯片的接触表面(具有接触柱)可能处于相对于半导体管芯530、半导体管芯580或半导体管芯680的有源表面所处的平面分散(非并行)的平面中。在一些实施例中,半导体芯片的接触表面的平面和半导体管芯的有源表面的平面可相交,从而定义直角。
在一些实施例中,通过将无源器件整合在根据本公开的无源器件模块中,有可能实现整合式无源器件模块的更高密度,从而减小外观尺寸、寄生电阻以及电感。因此,可增强包含根据本公开的无源器件模块的半导体封装的性能。在一些实施例中,由于无源器件整合在无源器件模块中,可在不造成大小损失的情况下实现半导体封装的性能的增强。
根据本公开的一些实施例,提供一种无源器件模块。无源器件模块包含第一层级、第二层级以及连接端子。第一层级包含第一半导体芯片和第一密封体。第一半导体芯片具有接触柱。密封体密封第一半导体芯片。第二层级设置在第一层级上,且包含第二半导体芯片、层间贯穿壁(through interlayer wall)以及第二密封体。层间贯穿壁位于第二半导体芯片的侧壁旁侧并面向第二半导体芯片的侧壁,且电连接到接触柱。第二密封体密封第二半导体芯片和层间贯穿壁。连接端子设置在第二层级上方且经由层间贯穿壁电连接到第一半导体芯片。第一半导体芯片和第二半导体芯片包含无源器件。
在一些实施例中,进一步包括设置在所述第一半导体芯片或所述第二半导体芯片中的一个旁侧的半导体管芯,其中所述半导体管芯包含有源器件。在一些实施例中,所述第二半导体芯片跨越所述第一半导体芯片且与所述第一半导体芯片竖直地交叠。在一些实施例中,所述层间贯穿壁中的至少一个层间贯穿壁设置在两个第二半导体芯片之间。在一些实施例中,连接到所述第一半导体芯片的所述接触柱的所述层间贯穿壁是第一层间贯穿壁,所述第二层级进一步包含设置在所述第二半导体芯片和所述第一层间贯穿壁旁侧的第二层间贯穿壁,所述第一层级进一步包含设置在所述第一半导体芯片旁侧的第三层间贯穿壁。在一些实施例中,进一步包括设置在所述第二层级上方的重布线结构,其中所述连接端子经由所述重布线结构连接到所述层间贯穿壁和所述第二半导体芯片。在一些实施例中,进一步包括设置在所述第一层级与所述第二层级之间的第一重布线结构和设置在所述第二层级上的第二重布线结构,其中所述层间贯穿壁中的一个层间贯穿壁的第一端部连接到所述第一重布线结构,所述一个层间贯穿壁的第二端部连接到所述第二重布线结构,且所述连接端子中的一个连接端子位于所述一个层间贯穿壁的侧边缘上。
根据本公开的一些实施例,提供一种半导体封装。半导体封装包含第一重布线结构、半导体管芯、导电端子以及无源器件。重布线结构具有第一侧和与第一侧相对的第二侧。半导体管芯设置在重布线结构的第一侧上。导电端子电性设置在重布线结构的第二侧上。无源器件模块设置在重布线结构的第二侧上。无源器件模块包含第一半导体芯片、第一层间贯穿壁、第一密封体、第二半导体芯片、第二密封体以及连接端子。第一层间贯穿壁设置在第一半导体芯片旁侧。第一密封体横向环绕第一半导体芯片和第一层间贯穿壁。第二半导体芯片与第一半导体芯片竖直地堆叠且电连接到第一层间贯穿壁。第二密封体横向环绕第二半导体芯片。至少一个连接端子与第一层间贯穿壁中的一个层间贯穿壁接触。第一半导体芯片和第二半导体芯片包含无源器件。
在一些实施例中,所述无源器件模块进一步包含:第二重布线结构,设置在所述第二密封体和所述第二半导体芯片上方。在一些实施例中,所述无源器件模块进一步包含第二层间贯穿壁,所述第二层间贯穿壁设置在所述第二半导体芯片旁侧、由所述第二密封体密封且竖直地堆叠在所述第一层间贯穿壁上,且其中所述第一半导体芯片经由所述第二重布线结构和所述第二层间贯穿壁中的至少一个第二层间贯穿壁连接到所述第一层间贯穿壁中的至少所述一个层间贯穿壁。在一些实施例中,进一步包括设置在所述第二半导体芯片旁侧且由所述第二密封体密封的第二层间贯穿壁,其中所述第二层间贯穿壁中的一个层间贯穿壁具有沿第一方向的细长横截面,所述第二层间贯穿壁中的另一个层间贯穿壁具有沿第二方向的细长横截面,所述横截面是在同一平面中截取的,且所述第一方向与所述第二方向正交。在一些实施例中,所述第二层间贯穿壁中的一些位于所述第一半导体芯片的接触柱上。在一些实施例中,所述至少一个连接端子直接设置在所述一个层间贯穿壁上。在一些实施例中,所述第一半导体芯片的接触表面相对于所述半导体管芯的有源表面倾斜。
根据本公开的一些实施例,提供一种无源器件模块的制造方法。所述方法至少包含以下步骤。设置第一半导体芯片。第一半导体芯片密封在第一密封体中。第一层间贯穿壁形成在第一密封体上方。第一层间贯穿壁电连接到第一半导体芯片。设置第二半导体芯片。第二半导体芯片竖直地堆叠在第一半导体芯片上。形成第二密封体。第二密封体密封第一半导体芯片和第一层间贯穿壁。连接端子形成为经由第一层间贯穿壁连接到第一半导体芯片。第一半导体芯片和第二半导体芯片包含无源器件。
在一些实施例中,进一步包括:在形成所述连接端子之前在所述第二密封体上形成重布线结构,其中所述重布线结构与所述第一层间贯穿壁和所述第二半导体芯片直接连接。在一些实施例中,所述重布线结构使所述第二半导体芯片中的两个半导体芯片电连接到所述第一层间贯穿壁中的一个层间贯穿壁,且所述制造方法进一步包括切穿所述一个层间贯穿壁以便使所述两个半导体芯片彼此电隔离。在一些实施例中,进一步包括:在切穿所述一个层间贯穿壁之后在所述一个层间贯穿壁的切穿侧壁上形成所述连接端子中的一个连接端子。在一些实施例中,所述连接端子形成在所述重布线结构上,且经由所述重布线结构电连接到所述第一层间贯穿壁。在一些实施例中,进一步包括:形成第一重布线结构;在设置所述第一半导体芯片之前在所述第一重布线结构上形成第二层间贯穿壁;在所述第二密封体上形成第二重布线结构,其中所述连接端子形成在所述第二重布线结构上;以及在所述第一重布线结构上形成额外连接端子。
前文概述若干实施例的特征以使所属领域的技术人员可更好地理解本公开的各个方面。所属领域的技术人员应了解,其可很容易地将本公开用作设计或修改用于实现本文中所引入的实施例的相同目的和/或达成相同优势的其它工艺和结构的基础。所属领域的技术人员还应认识到,这类等效构造并不脱离本公开的精神和范围,且其可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代以及更改。
Claims (1)
1.一种无源器件模块,包括:
第一层级,包含:
第一半导体芯片,具有接触柱;以及
第一密封体,密封所述第一半导体芯片;
第二层级,设置在所述第一层级上且包含:
第二半导体芯片;
层间贯穿壁,位于所述第二半导体芯片的侧壁旁侧并面向所述第二半导体芯片的侧壁,且电连接到所述接触柱;以及
第二密封体,密封所述第二半导体芯片和所述层间贯穿壁;以及
连接端子,设置在所述第二层级上方且经由所述层间贯穿壁电连接到所述第一半导体芯片,
其中所述第一半导体芯片和所述第二半导体芯片包含无源器件。
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US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
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