TW202125470A - Display, display driving circuit and display driving method - Google Patents

Abstract

A display and a display driving circuit and a display driving method thereof are disclosed. The display driving circuit includes a control circuit and a gate driving circuit. The gate driving circuit is coupled to the control circuit. The control circuit receives frame signals arranged by time. Each frame signal includes an input enable signal. The control circuit outputs a first signal to the gate driving circuit corresponding to every frame signal. A period of the control circuit outputting the first signal includes a first period of time, a second period of time and a third period of time. During the second period of time, previous voltage-level of the first signal is maintained. During the third period of time, the first signal and the input enable signal are synchronized.

Description

Display device, display drive circuit and display drive method

The present invention relates to a display device, and more particularly to a display device, a display drive circuit and a display drive method that can be applied to a gate driver in panel (GIP) architecture.

Traditionally, under the in-panel gate driver (GIP) architecture, in order for the gate driver to generate the gate pulse signal at the correct time, the start signal of each image frame is usually transmitted The STV clock signal CKV and other pulse signals are sent to the gate driver, so that the gate driver can know the time to turn on and switch the gate line.

In the case where it is necessary to start outputting the correct start signal STV and clock signal CKV before the correct data (Valid data) and other pulse signals (such as dummy pulse or interlaced gate driver), the data is consistent In the data enable (DE) mode, the vertical blanking (Vertical blanking) VBK is located between every two image frames.

Although the number of vertical blanking intervals VBK can be detected each time, if this value is used directly, it is likely that the output of the wrong start will be caused by the changes of the horizontal blanking interval (Horizontal blanking) HBK or the vertical blanking interval VBK. The signal STV and the clock signal CKV cause the display screen to be abnormal, so further solutions are needed.

In view of this, the present invention provides a display device, a display driving circuit, and a display driving method to effectively solve the above-mentioned problems encountered in the prior art.

A specific embodiment according to the present invention is a display driving circuit. In this embodiment, the display driving circuit includes a gate driving circuit and a control circuit. The control circuit is coupled to the gate drive circuit for receiving a plurality of image frame signals arranged in time and corresponding to each image frame signal to output a first signal to the gate drive circuit, wherein each image frame signal includes an input enable Signal. The period during which the control circuit outputs the first signal sequentially includes a first period, a second period, and a third period. In the second period, the first signal maintains its original potential. In the third time period, the first signal is synchronized with the input enable signal.

In one embodiment, the control circuit includes a gate control circuit for outputting the first signal. The gate control circuit includes a vertical blank interval learning unit, a parameter setting unit and a gate signal generating unit. The vertical blank interval learning unit and the parameter setting unit are respectively coupled to the gate signal generating unit. The vertical blank interval learning unit provides an interval signal to the gate signal generating unit according to the time difference between the plurality of image frame signals. The parameter setting unit provides the parameter signal to the gate signal generating unit. The gate signal generating unit determines the start time of the first period according to the interval signal, and determines the time length of the second period according to the parameter signal.

In one embodiment, the gate signal generating unit includes an active area control unit for outputting an active area control signal, and the signal edge of the active area control signal determines the switching time of the first time period, the second time period, and the third time period.

In one embodiment, the first signal corresponding to each image frame signal includes a first start signal and at least one first clock signal. The gate driving circuit determines the start time for sending out a plurality of scanning signals according to the first start signal. The gate driving circuit determines the time length and the sending time of each scan signal according to the at least one first clock signal.

In one embodiment, the first start signal is issued in the first time period.

In one embodiment, the first start signal is issued in the first period and ends in the third period.

Another specific embodiment according to the present invention is a display device. In this embodiment, the display device includes a display panel, a gate driving circuit, and a control circuit. The gate drive circuit is arranged on the display panel. The control circuit is coupled to the gate drive circuit for receiving a plurality of image frame signals arranged in time and corresponding to each image frame signal to output a first signal to the gate drive circuit, wherein each image frame signal includes an input enable Signal. Among them, the period during which the control circuit outputs the first signal sequentially includes a first period, a second period, and a third period; in the second period, the first signal maintains the original potential; in the third period, the first signal and the input Can signal synchronization.

Another specific embodiment according to the present invention is a display driving method. In this embodiment, the display driving method includes the following steps:

A control circuit receives a plurality of image frame signals arranged in time, wherein each image frame signal includes an input enable signal;

The control circuit corresponding to each image frame signal to output the first signal to the gate driving circuit; and

When the period during which the control circuit outputs the first signal sequentially includes the first period, the second period, and the third period, the first signal maintains its original potential during the second period and the first signal interacts with the input enable signal during the third period Synchronize.

Compared with the prior art, the display driving circuit and the display driving method according to the present invention are applied to the source driver IC or timing controller IC of the display panel, and can be applied to the gate driver in panel (GIP) architecture. Its characteristics are: After starting to output the start signal STV and/or clock signal CKV in advance, temporarily stop changing the output start signal STV and/or clock signal CKV for a period of time until the correct data (Valid data) starts (that is, the enable signal is input After DE start), continue to output the start signal STV and/or the clock signal CKV.

Thereby, temporarily stopping changing the output start signal STV and/or clock signal CKV for this period of time can be used to overcome the influence caused by the fluctuating horizontal blanking interval HBK or vertical blanking interval VBK, so it can effectively avoid the horizontal blanking interval. The change of HBK or the vertical blank interval VBK outputs the wrong start signal STV and/or the clock signal CKV, so that the picture displayed by the display device will not appear abnormal.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

A specific embodiment according to the present invention is a display driving circuit. In this embodiment, the display driving circuit is applied to a display device and may have a gate in panel (GIP) architecture, but it is not limited to this.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of the display driving circuit in this embodiment. As shown in FIG. 1, the display driving circuit 1 may include a control circuit 10 and a gate driving circuit 12 coupled to each other. The control circuit 10 receives a plurality of image frame signals FR arranged in time. Among them, each image frame signal FR may include the input enable signal DE and the input data DAT, but is not limited to this.

Then, the control circuit 10 outputs the first signal S1 to the gate driving circuit 12 corresponding to each image frame signal FR. The first signal S1 may include the start signal STV and/or the clock signal CKV of the image frame, but is not limited to this.

It should be noted that in the DE mode, the number of vertical blanking intervals between every two image frames can be detected. However, if the detected value is used directly, the control circuit 10 is likely to output an erroneous first signal S1 (the start signal STV and/ Or the clock signal CKV), which causes the display screen to appear abnormal.

Therefore, in the data enable (DE) mode, the control circuit 10 in the display driving circuit 1 of the present invention can start outputting the first signal S1 ( The start signal STV and/or the clock signal CKV of the image frame). After the control circuit 10 has output one or more first signals S1 (the start signal STV of the image frame and/or the clock signal CKV), the control circuit 10 can stop outputting the first signal S1 (the start signal of the image frame) in advance. STV and/or clock signal CKV). After the input enable signal DE starts to be activated, the control circuit 10 continues to output the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame). Thereby, the control circuit 10 can use this Stop period to overcome the influence caused by the fluctuating horizontal blanking interval/vertical blanking interval, so it can effectively avoid outputting the wrong first signal S1 (the start signal of the image frame). STV and/or clock signal CKV) cause the display screen to be abnormal.

For example, as shown in FIG. 2, in the data enable (DE) mode, it is assumed that the control circuit 10 outputs the first signal S1 (the start signal STV of the image frame and/or the clock signal CKV) during the period T in sequence It includes a first time period T1, a second time period T2, and a third time period T3.

In the first time period T1, the vertical blank interval VBK has not yet ended, and the input enable signal DE has not been activated. The control circuit 10 can start outputting the first signal S1 (the start signal of the image frame) before the input enable signal DE has been activated. STV and/or clock signal CKV) to the gate driving circuit 12.

In the second time period T2, the vertical blank interval VBK has not yet ended, and the input enable signal DE has not been activated. Since the second time period T2 is the stop period, the first signal S1 (the start signal STV of the image frame and the / Or the clock signal CKV) will remain unchanged at the original potential. In other words, the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame) output by the control circuit 10 will not have any change in potential during the second period T2 (ie, the stop period).

In the third time period T3, when the vertical blanking interval VBK ends and the input enable signal DE is activated, the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame) will be synchronized with the input enable signal DE. For example, the rising edge of the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame) is aligned with the rising edge of the input enable signal DE, or the first signal S1 (image The falling edge of the frame start signal STV and/or the clock signal CKV) is aligned with the falling edge of the input enable signal DE, but not limited to this.

In one embodiment, as shown in FIG. 3, the control circuit 10 may include a gate control circuit 100, such as a gate driver in panel (GIP) control circuit, but it is not limited to this.

The gate control circuit 100 may include a vertical blank space (VBK) learning unit VLU, a parameter setting unit CFU, and a gate signal generating unit GSU. The vertical blank interval learning unit VLU and the parameter setting unit CFU are respectively coupled to the gate signal generating unit GSU.

The vertical blank interval learning unit VLU is used for providing the interval signal SG to the gate signal generating unit GSU according to the time difference between the plurality of image frame signals FR. The parameter setting unit CFU is used to provide the parameter signal SP to the gate signal generating unit GSU.

It should be noted that since the control circuit 10 cannot directly know the vertical blanking interval (VBK) information of the front-end system in the data enable (DE) mode, the control circuit 10 can use the learning mechanism to use the vertical blanking interval learning unit VLU. The information of the previous one or several vertical blank intervals is applied to the current screen to determine the time to start outputting the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame).

When the gate signal generating unit GSU receives the interval signal SG and the parameter signal SP, respectively, the gate signal generating unit GSU can determine the start time of the first period T1 according to the interval signal SG, and determine the second period T2 according to the parameter signal SP ( That is, the length of time during the stop period, but not limited to this.

In addition, because the present invention intends to start outputting the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame) earlier by a few lines through the circuit setting method, and output a fixed number of The output of the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame) is stopped for a period of time, and the first signal S1 (the start signal STV of the image frame) will continue to be output after the input enable signal DE starts to be activated. And/or clock signal CKV).

Therefore, as shown in FIG. 3, the gate signal generating unit GSU may include an action area control unit AAU, which is used to determine the range of the action area through the interval signal SG and the parameter signal SP and output the action area control signal SAA. Through this range, the gate signal generating unit GSU is activated to output the expected waveform of the first signal S1 (the start signal STV and/or the clock signal CKV of the image frame).

For example, as shown in FIG. 2, the actuation area control signal SAA output by the actuation area control unit AAU is maintained at a high level during the first period T1, maintained at a low level during the second period T2, and maintained at the third period T3. At a high potential, in other words, the switching time of the first time period T1, the second time period T2, and the third time period T3 can be determined by the signal edge (such as the rising edge or the falling edge) of the active area control signal SAA, but is not limited thereto.

It should be noted that when the active area control signal SAA enters the third period T3 from the second period T2, its rising edge is aligned with the rising edge of the input enable signal DE as shown in FIG. 2, in another embodiment It is also possible to align the falling edge of the input enable signal DE, and there is no specific restriction.

In one embodiment, in the data enable (DE) mode, it is assumed that the first signal S1 corresponding to the image frame signal FR includes the start signal STV and at least one clock signal CKV. When the gate driving circuit 12 receives the start signal STV and the at least one clock signal CKV, the gate driving circuit 12 will determine the start time TS at which it starts to output a plurality of scanning signals GOUT1~GOUTN according to the start signal STV and according to The at least one first clock signal CKV determines the time length and output time of each scan signal GOUT1~GOUTN. In fact, the start signal STV is started in the first time period T1 and the start signal STV can end in the first time period T1 or the third time period T3, but not limited to this.

Next, the description will be made through two embodiments operating in the data enable (DE) mode respectively.

In one embodiment, as shown in FIG. 4, in the data enable (DE) mode, it is assumed that the first signal S1 corresponding to the image frame signal FR includes the start signal STV and the clock signals CKV1 to CKV4. After the start signal STV is activated in the first time period T1, the clock signals CKV1 to CKV2 are sequentially activated in the first time period T1. In this embodiment, the start signal STV also ends in the first time period T1.

Then, in the second time period T2 (that is, the stop period), the start signal STV and the clock signals CKV1 to CKV4 maintain their original potentials. When the third period T3 starts, the clock signals CKV3~CKV4 that have not been activated will be activated in sequence, and then the recurrence clock signals CKV1~CKV2 will be activated in sequence, and so on.

It should be noted that when the stop period ends at the falling edge of the input enable signal DE, the second time period is T2; when the stop period ends at the rising edge of the input enable signal DE, the second time period is T2', But not limited to this.

In the third time period T3, the gate driving circuit 12 will determine the start time ts at which it starts to output a plurality of scanning signals GOUT1~GOUT9 according to the start signal STV. In addition, the gate driving circuit 12 also determines the time length and output time of the scan signals GOUT1 to GOUT9 according to the clock signals CKV3, CKV4, CKV1, CKV2 that are sequentially activated in the third time period T3.

For example, the scan signal GOUT1 corresponds to the clock signal CKV3; the scan signal GOUT2 corresponds to the clock signal CKV4; the scan signal GOUT3 corresponds to the clock signal CKV1; the scan signal GOUT4 corresponds to the clock signal CKV2; the scan signal GOUT5 corresponds to the clock signal CKV3; the scan signal GOUT6 corresponds to the clock signal CKV4; the scan signal GOUT7 corresponds to the clock signal CKV1; the scan signal GOUT8 corresponds to the clock signal CKV2; the scan signal GOUT9 corresponds to the clock signal Signal CKV3, and so on.

In another embodiment, as shown in FIG. 5, in the data enable (DE) mode, it is assumed that the first signal S1 corresponding to the image frame signal FR includes the start signal STV and the clock signals CKV1 to CKV4. After the start signal STV is activated in the first time period T1, the clock signals CKV1 to CKV2 are sequentially activated in the first time period T1. In this embodiment, the start signal STV continues to be activated until the third period T3 ends.

Then, in the second time period T2 (that is, the stop period), the start signal STV and the clock signals CKV1 to CKV4 maintain their original potentials. In the third period T3, when the start signal STV ends, the unactivated clock signals CKV3~CKV4 will be activated in sequence, and then the recurrence clock signals CKV1~CKV2 will be activated in sequence, and so on.

It should be noted that when the stop period ends at the falling edge of the input enable signal DE, the second time period is T2; when the stop period ends at the rising edge of the input enable signal DE, the second time period is T2', But not limited to this.

In the third time period T3, the gate driving circuit 12 will determine the start time TS at which it starts to output a plurality of scanning signals GOUT1~GOUT9 according to the start signal STV. In addition, the gate driving circuit 12 also determines the time length and output time of the scan signals GOUT1 to GOUT9 according to the clock signals CKV3, CKV4, CKV1, CKV2 that are sequentially activated in the third time period T3.

For example, the scan signal GOUT1 corresponds to the clock signal CKV3; the scan signal GOUT2 corresponds to the clock signal CKV4; the scan signal GOUT3 corresponds to the clock signal CKV1; the scan signal GOUT4 corresponds to the clock signal CKV2; the scan signal GOUT5 corresponds to the clock signal CKV3; the scan signal GOUT6 corresponds to the clock signal CKV4; the scan signal GOUT7 corresponds to the clock signal CKV1; the scan signal GOUT8 corresponds to the clock signal CKV2; the scan signal GOUT9 corresponds to the clock signal Signal CKV3, and so on.

Another specific embodiment according to the present invention is a display device. In this embodiment, the display device includes a display panel, a gate driving circuit, and a control circuit. The gate drive circuit is arranged on the display panel. The control circuit is coupled to the gate drive circuit for receiving a plurality of image frame signals arranged in time and corresponding to each image frame signal to output a first signal to the gate drive circuit, wherein each image frame signal includes an input enable Signal. Among them, the period during which the control circuit outputs the first signal sequentially includes a first period, a second period, and a third period; in the second period, the first signal maintains the original potential; in the third period, the first signal and the input Can signal synchronization.

As for the detailed description of the display device in this embodiment, please refer to the content of the foregoing embodiment and FIGS. 1 to 5, which will not be repeated here.

Another specific embodiment according to the present invention is a display driving method. In this embodiment, the display driving method is applied to a display driving circuit in a display device. The display driving circuit may include a control circuit and a gate driving circuit coupled to each other, and the display driving circuit may have an in-panel gate driver (GIP) Architecture, but not limited to this.

Please refer to FIG. 6. FIG. 6 shows a flowchart of the display driving method in this embodiment. As shown in FIG. 6, the display driving method may include the following steps:

Step S10: Use the control circuit to receive a plurality of image frame signals arranged in time, wherein each image frame signal includes an input enable signal;

Step S12: output the first signal to the gate driving circuit corresponding to each image frame signal by the control circuit; and

Step S14: When the period during which the control circuit outputs the first signal sequentially includes the first period, the second period, and the third period, the first signal maintains its original potential during the second period and the first signal interacts with the input during the third period. Enable signal synchronization.

Compared with the prior art, the display driving circuit and the display driving method according to the present invention are applied to the source driver IC or timing controller IC of the display panel, and can be applied to the gate driver in panel (GIP) architecture. Its characteristics are: After starting to output the start signal STV and/or clock signal CKV in advance, temporarily stop changing the output start signal STV and/or clock signal CKV for a period of time until the correct data (Valid data) starts (that is, the enable signal is input After DE start), continue to output the start signal STV and/or the clock signal CKV.

Thereby, temporarily stopping changing the output start signal STV and/or clock signal CKV for this period of time can be used to overcome the influence caused by the fluctuating horizontal blanking interval HBK or vertical blanking interval VBK, so it can effectively avoid the horizontal blanking interval. The change of HBK or the vertical blank interval VBK outputs the wrong start signal STV and/or the clock signal CKV, so that the picture displayed by the display device will not appear abnormal.

Through the detailed description of the above preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent for which the present invention is intended.

1: Display drive circuit 10: Control circuit 12: Gate drive circuit FR: Video frame signal DE: Input enable signal DAT: input data S1: The first signal STV: Start signal of video frame CKV, CKV1~CKV4: clock signal T1: the first period T2: second period T3: The third period VBK: vertical blank interval DE: Input enable signal 100: Gate control circuit VLU: Vertical Blank Space Learning Unit CFU: Parameter setting unit GSU: Gate signal generating unit SG: Interval signal SP: parameter signal AAU: Actuation area control unit SAA: Actuation area control signal GOUT1~GOUTN: scan signal GOUT1~GOUT9: Sweep signal T2’: The second period ts: start time

The drawings of the present invention are described as follows: FIG. 1 is a functional block diagram of a display driving circuit according to an embodiment of the present invention. FIG. 2 is a timing diagram showing the period during which the control circuit outputs the first signal sequentially includes the first period to the third period. Figure 3 shows a functional block diagram of the gate control circuit in the control circuit. FIG. 4 is a timing diagram showing the start and end of the start signal in the first period of time. FIG. 5 is a timing diagram showing that the start signal starts in the first time period and ends in the third time period. FIG. 6 is a flowchart of a display driving method according to another embodiment of the present invention.

S10~S14: steps

Claims (19)

A display drive circuit, including: A gate drive circuit; and A control circuit coupled to the gate drive circuit for receiving a plurality of image frame signals arranged in time and corresponding to each image frame signal to output a first signal to the gate drive circuit, wherein each image frame The signal includes an input enable signal; Wherein, the period during which the control circuit outputs the first signal sequentially includes a first period, a second period, and a third period; in the second period, the first signal maintains the original potential; in the third period Inside, the first signal is synchronized with the input enable signal. The display driving circuit according to claim 1, wherein the control circuit includes a gate control circuit for outputting the first signal; the gate control circuit includes a vertical blank interval learning unit, a parameter setting unit, and a gate A pole signal generating unit; the vertical blank interval learning unit and the parameter setting unit are respectively coupled to the gate signal generating unit; the vertical blank interval learning unit provides an interval signal to the gate according to the time difference between the plurality of image frame signals A pole signal generating unit, the parameter setting unit provides a parameter signal to the gate signal generating unit; the gate signal generating unit determines the start time of the first period according to the interval signal, and determines the second period according to the parameter signal The length of time. The display driving circuit according to claim 2, wherein the gate signal generating unit includes an active area control unit for outputting an active area control signal, and the signal edge of the active area control signal determines the first period, the The switching time between the second period and the third period. The display driving circuit according to claim 1, wherein the first signal corresponding to each image frame signal includes a first start signal and at least one first clock signal; the gate driving circuit is determined according to the first start signal The starting time for starting to send out a plurality of scanning signals; the gate driving circuit determines the time length and the sending time of each scanning signal according to the at least one first clock signal. The display driving circuit according to claim 4, wherein the first start signal is issued in the first time period. The display driving circuit according to claim 4, wherein the first start signal is issued in the first period and ends in the third period. A display device including: A display panel; A gate drive circuit arranged on the display panel; and A control circuit coupled to the gate drive circuit for receiving a plurality of image frame signals arranged in time and corresponding to each image frame signal to output a first signal to the gate drive circuit, wherein each image frame The signal includes an input enable signal; Wherein, the period during which the control circuit outputs the first signal sequentially includes a first period, a second period, and a third period; in the second period, the first signal maintains the original potential; in the third period Inside, the first signal is synchronized with the input enable signal. The display device according to claim 7, wherein the gate drive circuit is provided on the display panel in the form of a gate in panel (GIP). The display device according to claim 7, wherein the control circuit includes a gate control circuit for outputting the first signal; the gate control circuit includes a vertical blank interval learning unit, a parameter setting unit, and a gate A signal generating unit; the vertical blank interval learning unit and the parameter setting unit are respectively coupled to the gate signal generating unit; the vertical blank interval learning unit provides an interval signal to the gate according to the time difference between the plurality of image frame signals A signal generating unit, the parameter setting unit provides a parameter signal to the gate signal generating unit; the gate signal generating unit determines the start time of the first period according to the interval signal, and determines the second period of time according to the parameter signal length of time. The display device according to claim 9, wherein the gate signal generating unit includes an actuation area control unit for outputting an actuation area control signal, and the signal edge of the actuation area control signal determines the first period and the first period The switching time of the second period and the third period. The display device according to claim 7, wherein the first signal corresponding to each of the image frame signals includes a first start signal and at least one first clock signal; the gate driving circuit determines the start according to the first start signal The start time of sending out a plurality of scanning signals; the gate driving circuit determines the time length and sending time of each scanning signal according to the at least one first clock signal. The display device according to claim 11, wherein the first start signal is issued in the first time period. The display device according to claim 11, wherein the first start signal is issued in the first period and ends in the third period. A display driving method includes the following steps: A control circuit receives a plurality of image frame signals arranged in time, wherein each image frame signal includes an input enable signal; Using the control circuit to output a first signal to a gate driving circuit corresponding to each image frame signal; and When the period during which the control circuit outputs the first signal sequentially includes a first period, a second period, and a third period, the first signal maintains its original potential during the second period and the first signal is Synchronize with the input enable signal in the third time period. The display driving method according to claim 14, further comprising the following steps: Determine the start time of the first period according to the time difference between the plurality of image frame signals; and The time length of the second time period is determined according to a parameter signal. The display driving method according to claim 14, further comprising the following steps: According to the start time of the first period and the length of the second period, an active area control signal is output, wherein the signal edge of the active area control signal determines the switching time of the first period, the second period, and the third period . The display driving method according to claim 14, wherein the first signal corresponding to each of the image frame signals includes a first start signal and at least one first clock signal; the gate driving circuit is determined according to the first start signal The starting time for starting to send out a plurality of scanning signals; and the gate driving circuit determines the time length and the sending time of each scanning signal according to the at least one first clock signal. The display driving method according to claim 14, wherein the first start signal is issued in the first time period. The display driving method according to claim 14, wherein the first start signal is issued in the first period and ends in the third period.

Images