JP2007093695A - Display driving device and drive control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driving device and a drive control method thereof capable of suppressing burn-in and deterioration of liquid crystal by hold of a display image even when a state that timing signals such as a horizontal synchronizing signal and a vertical synchronizing signal are not supplied temporarily occurs. <P>SOLUTION: An LCD controller 40 has configuration equipped with a display switching control part 41 which outputs an internal horizontal synchronizing signal HSCKb and an internal vertical synchronizing signal VSCKb which are independently generated in place of an external horizontal synchronizing signal HSCKa and an external vertical synchronizing signal VSCKa and outputs white display data in place of external display data based on a video signal supplied from a display signal generation circuit 50 when the state that the external horizontal synchronizing signal HSCKa and the external vertical synchronizing signal VSCKa from the display signal generation circuit 50 are not input for a fixed period is detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a display drive device that is suitable for application to a display device such as a liquid crystal display device and a drive control method thereof.

  In recent years, electronic devices such as digital still cameras, mobile phones, electronic dictionaries, and personal digital assistants have been widely used. Liquid crystal displays (LCDs) are used as display devices for displaying various information on these electronic devices. ) Is generally installed. Also, in information terminals and video equipment such as computers and televisions, liquid crystal display devices are increasingly used in place of conventional cathode ray tubes (Cathode Ray Tubes; CRTs).

Hereinafter, a schematic configuration example of a conventional display device will be briefly described.
FIG. 5 is a schematic block diagram showing an example of a liquid crystal display device in the prior art. Here, a configuration when an active matrix liquid crystal display panel is provided as a liquid crystal display device will be described.

  As shown in FIG. 5, the schematic configuration of a conventional liquid crystal display device is roughly classified into a liquid crystal display panel 110, a signal driver (source driver) 120, a scanning driver (gate driver) 130, an LCD controller 140, and a display. A signal generation circuit (video interface circuit) 150. Here, the display signal generation circuit 150 generates display data (luminance gradation data) based on a video signal (video signal) supplied from the outside and supplies the display data to the signal driver 120 and various timing signals (systems). A clock SYSCK, a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, etc.) are generated and supplied to the signal driver 120 and the LCD controller 140. In addition, the LCD controller 140 generates at least a horizontal control signal and a vertical control signal based on the timing signal supplied from the display signal generation circuit 150 and supplies them to the signal driver 120 and the scan driver 130 individually.

That is, the display signal generation circuit 150 includes, for example, a digital signal processor (DSP) that generates various timing signals serving as a basis for displaying predetermined image information based on a video signal on the liquid crystal display panel 110. The LCD controller 140 also generates a horizontal control signal and a vertical synchronization signal for operating the signal driver 120 and the scan driver 130 at a predetermined timing based on the timing signal generated by the digital signal processor. TG).
The configuration of the liquid crystal display device (display device) as described above is described in detail, for example, in Patent Document 1 and the like.

JP 2001-236052 A (2nd to 4th pages, FIGS. 6 and 10)

However, in the above-described liquid crystal display device (display device) according to the prior art, for example, in a digital signal processor provided in the display signal generation circuit due to the influence of static electricity or the like from the outside of the device, a horizontal synchronization signal or a vertical synchronization signal In some cases, timing signals such as the above are not temporarily generated and are not supplied to the LCD controller. In addition to the static electricity described above, the digital signal processor may temporarily malfunction due to an error (bug) in the control program written in the digital signal processor or an abnormal operation of the liquid crystal display device. In some cases, the supply was temporarily stopped.
Even in Patent Document 1 described above, although the cause is different, when a special reproduction or the like of a video signal (video signal) is performed, an abnormality in the signal waveform or timing of the horizontal synchronization signal occurs or the signal is lost. It is described that such a phenomenon occurs.

  For this reason, the horizontal control signal and vertical control signal generated by the LCD controller are not normally output to the signal driver or the scanning driver, so that the image information (display image) displayed on the liquid crystal display panel is held and an afterimage is generated. As a result, a DC voltage is applied to the liquid crystal constituting the display pixel, causing screen burn-in or deterioration of the liquid crystal.

  Therefore, in view of the above-described problems, the present invention is a case where a liquid crystal is burned or deteriorated by holding a display image even when a timing signal such as a horizontal synchronization signal or a vertical synchronization signal is temporarily not supplied. It is an object of the present invention to provide a display drive device and a drive control method thereof that can suppress the above-described problem.

  According to the first aspect of the present invention, in the display drive device that generates a drive control signal for displaying desired image information on the display panel based on the timing signal, the supply state of the external timing signal supplied from the outside of the device is changed. An external signal detecting means for detecting, an internal timing signal independent of the external timing signal, an internal signal generating means for generating internal display data for setting the display panel in a predetermined display state, and the external signal A signal output switching means for outputting the internal timing signal and the internal display data generated by the internal signal generating means when the lack of the external timing signal is detected by a detecting means; and the external timing signal or the internal Control signal generating means for generating the drive control signal based on a timing signal. And features.

  According to a second aspect of the present invention, in the display driving device according to the first aspect, the external signal detecting means counts a reference clock number for each period of the external timing signal, and the count value is a full count value in the counter. A counter that outputs a full count output when the signal reaches the value, and a switching signal generator that detects the full count output output from the counter and outputs a switching signal, and the signal output switching means includes the switching Based on the signal, the signal path is switched so as to output the internal timing signal and the internal display data.

According to a third aspect of the present invention, in the display driving device according to the first or second aspect, the external timing signal whose supply state is detected by the external signal detecting means is at least one of a horizontal synchronizing signal and a vertical synchronizing signal. It is characterized by being either.
According to a fourth aspect of the present invention, in the display driving device according to any one of the first to third aspects, the internal display data generated by the internal signal generating means displays a white display image on the display panel. Luminance gradation data.

According to a fifth aspect of the present invention, in the drive control method for a display drive device for generating a drive control signal for displaying desired image information on the display panel based on the timing signal, the external timing signal supplied from the outside of the device Detecting the supply state, and when the external timing signal is normally supplied, generating the drive control signal based on the external timing signal, and detecting the absence of the external timing signal And generating the drive control signal based on an internal timing signal independent of the external timing signal generated inside the display driving device and displaying the desired image information. The step of switching the external display data supplied from the outside to the internal display data for displaying the white display image. Characterized in that it comprises a and.
According to a sixth aspect of the present invention, in the drive control method for a display driving device according to the fifth aspect, the external timing signal is at least one of a horizontal synchronizing signal and a vertical synchronizing signal.

  The present invention relates to a display drive device and a drive control method thereof applied to a liquid crystal display device, and includes an external timing signal (external horizontal synchronization signal, external vertical synchronization signal) supplied from outside the device (display signal generation circuit). It is configured to always detect the supply state (count value for each cycle), the external timing signal is missing (count value reaches full count), and there is an abnormal state that is not input to the display drive device (LCD controller) If it occurs, use internal timing signals (internal horizontal sync signal, internal vertical sync signal) generated by internal signal generation means (switch data generator) provided inside the device instead of the external timing signal Then, a drive control signal (horizontal control signal, vertical control signal) to be supplied to the signal driver or scanning driver is generated, Instead of the external display data (luminance gradation data) supplied from the display signal generation circuit), a white display image based on the internal display data (white display data) generated by the internal signal generation means (switching data generation unit) is generated. It is displayed on the display panel (liquid crystal display panel).

  As a result, when the external timing signal is normally supplied (normal state), desired image information corresponding to the external display data is displayed based on the external timing signal, and the lack of the external timing signal is detected. In the case (abnormal state), the drive control signal is generated based on the internal timing signal independent of the external timing signal, and white according to the internal display data (white display data) prepared in advance. Since a display image is displayed, it is possible to prevent a phenomenon in which image information displayed in a normal display state is held and an afterimage is generated, and application of a DC voltage to each display pixel (liquid crystal) is suppressed. , Screen burn-in and deterioration of the liquid crystal can be suppressed.

Hereinafter, a display drive device and a drive control method thereof according to the present invention will be described in detail with reference to embodiments.
First, a display device to which the display driving device according to the present invention is applied will be briefly described.
FIG. 1 is a schematic block diagram showing a configuration example of a display device to which a display driving device according to the present invention is applied. Here, components equivalent to those of the above-described prior art (see FIG. 5) will be described with the same reference numerals. FIG. 2 is a main part configuration diagram showing an embodiment of a display driving device (LCD controller) according to the present invention.

  A display device to which the display driving device according to the present invention can be applied is, for example, as shown in FIG. 1, a liquid crystal display panel 10 in which a plurality of display pixels are two-dimensionally arranged, and a video signal (display data) in the display pixels. A signal driver 20 that applies a corresponding signal voltage, a scanning driver 30 that applies a scanning signal that sets a display pixel to a selected state for each row of the liquid crystal display panel 10, and external display data (luminance gradation) based on the video signal. Data) and an external timing signal (system clock, horizontal synchronization signal, vertical synchronization signal, etc., which will be described later), and a drive control signal to be supplied to the signal driver 20 and the scan driver 30 based on the timing signal. An LCD controller 40 for generating (a horizontal control signal, a vertical control signal, etc., which will be described later). Depending on the state of supply of the horizontal and vertical synchronization signals from 示信 No. generating circuit 50 has a configuration having a display switching control section 41 for switching the image display in the liquid crystal display panel 10.

  The liquid crystal display panel 10 is roughly configured to connect a plurality of display pixels arranged in a matrix, scanning lines arranged to connect the display pixels in the row direction, and the display pixels in the column direction. The display pixel is arranged in a selected state by sequentially applying a scanning signal from the scanning driver 30 to the scanning line of each row and setting the display pixel to the selected state. By applying a signal voltage corresponding to the display data, the alignment state of the liquid crystal sealed in the display pixel (between the pixel electrode and the common electrode) is controlled to display desired image information on the liquid crystal display panel 10. Display drive control is executed.

  The display signal generation circuit 50 extracts a luminance gradation component from a video signal supplied from the outside of the display device and supplies it to the LCD controller 40 as external display data. Further, for example, the system clock SYSCK is extracted from the video signal and supplied to the signal driver 20 and the LCD controller 40, and the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa that are synchronized with the system clock SYSCK are generated. This is supplied to the LCD controller 40.

  For example, as shown in FIG. 1, the LCD controller 40 detects external horizontal synchronization when at least the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa from the display signal generation circuit 50 are not input for a certain period of time. A display switching control unit that outputs the internal horizontal synchronization signal HSCKb and the internal vertical synchronization signal VSCKb instead of the signal HSCKa and the external vertical synchronization signal VSCKa, and outputs specific internal display data different from the external display data to the signal driver 20 (External signal detection means, internal signal generation means, signal output switching means) 41 and timing signals (external horizontal synchronization signal HSCKa and external vertical synchronization signal VSCKa or internal horizontal synchronization signal) output from the display switching control unit 41 HSCKb and internal vertical synchronization signal VSCKb) It has a configuration which includes a timing generator (control signal generating means) 42 for generating a horizontal control signal and a vertical control signals supplied to the driver 20 and the scan driver 30, a.

  Specifically, as shown in FIG. 2, the display switching control unit 41 receives, for example, an external horizontal synchronization signal HSCKa supplied from the display signal generation circuit 50 and inputs the system clock SYSCK to the reset terminal RST. The first counter 411 input to the terminal CK and the external vertical synchronization signal VSCKa are input to the reset terminal RST, the system clock SYSCK is input to the clock terminal CK, and the external horizontal synchronization signal HSCKa is input to the enable terminal ENB. Second counter 412 and a select signal generation unit (switching signal generation unit) 413 for detecting a full count output from each of first counter 411 and second counter 412 and outputting a select signal. 414 and the external horizontal signal supplied from the display signal generation circuit 50. A switching data generation unit (internal signal generation) for generating and outputting the signal HSCKa, the external vertical synchronization signal VSCKa, the internal horizontal synchronization signal HSCKb and the internal vertical synchronization signal VSCKb independent of the external display data, and the white display data (internal display data) Means) 415 and the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa supplied from the display signal generation circuit 50 based on the select signal, the external display data, or the internal horizontal output from the switching data generation unit 415. A signal output changeover switch (SEL-SW; signal output changeover means) 416 for individually outputting any one of the synchronization signal HSCKb, the internal vertical synchronization signal VSCKb, and the white display data to the timing generator 42 and the signal driver 20 in the LCD controller 40; 417, 418 It has been.

  Here, the first counter 411 starts the operation of counting the system clock SYSCK at the input timing (rising timing) of the external horizontal synchronization signal HSCKa, and at the input timing of the next external horizontal synchronization signal HSCKa, For example, when the number of system clocks in one horizontal period (1H) is 1716 CK, 4096 counts that are approximately two horizontal periods (2H) or more are set as full count values, and the count number is the full count value. Is set so that a full count output is output from the output terminal Q to the select signal generation unit 413.

The second counter 412 starts an operation of counting the external horizontal synchronization signal HSCKa input to the enable terminal ENB at the input timing (rising timing) of the external vertical synchronization signal VSCKa, and the next external vertical synchronization signal VSCKa. The count value is reset at the input timing of, for example, when one vertical period (1 V; 1 frame) is set to 240 horizontal periods, 512 counts that are approximately two vertical periods (2 V) or more are fully counted. The value is set so that the full count output is output from the output terminal Q to the select signal generation unit 414 when the count number reaches the full count value.
That is, the first and second counters 411 and 412 and the select signal generators 413 and 414 constitute an external signal detection unit according to the present invention.

  Further, the switching data generation unit 415 detects the full count output output from the first counter 411 and the second counter 422, and outputs a signal based on the selection signal output from the selection signal generation units 413 and 414. Then, the internal horizontal synchronization signal HSCKb is output to the signal output changeover switch 416, the internal vertical synchronization signal HSCKb is output to the signal output changeover switch 417, and the white display data is output to the signal output changeover switch 418.

  Here, in the display switching control unit 41 shown in FIG. 2, the select signal output from the select signal generation units 413 and 414 is transmitted via the single signal line to the switching data generation unit 415 and the signal output changeover switch 416. 417, 418. That is, in such a configuration, all the functions of the switching data generation unit 415 are activated all at once based on the selection signal output by detecting the full count output in any of the selection signal generation units 413 and 414. Then, a transition is made to a signal output state in which all of the internal horizontal synchronization signal HSCKb and internal vertical synchronization signal VSCKb and white display data are output, and all of the signal output changeover switches 416, 417, 418 are switched by the select signal, The external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa supplied from the display signal generation circuit 50 and the external display data are cut off, and the internal horizontal synchronization signal HSCKb and the internal vertical synchronization signal output from the switching data generation unit 415 are cut off. Capture and output VSCKb and white display data It is controlled to so that.

  In addition, the timing generator 42 is supplied with timing signals (external horizontal synchronization signal HSCKa and external vertical synchronization signal VSCKa supplied from the display signal generation circuit 50, system clock SYSCK, or A horizontal control signal and a vertical control signal are generated on the basis of the internal horizontal synchronization signal HSCKb, the internal vertical synchronization signal VSCKb, and the system clock SYSYCK, and are output to the signal driver 20 and the scan driver 30, respectively.

Next, a drive control operation in the display drive device (LCD controller) having the above-described configuration will be specifically described.
FIG. 3 is a timing chart showing an example of a drive control operation in a normal state of the drive control method for the display drive device according to the present embodiment, and FIG. 4 shows an abnormality in the drive control method for the display drive device according to the present embodiment. 6 is a timing chart illustrating an example of a drive control operation in a state. Here, description will be made with reference to the configuration of the display driving device shown in FIG.

  First, in the normal state (normal state) in which the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa are normally output from the display signal generation circuit 50, the drive control operation (drive control method) of the display drive device according to the present embodiment. 2), as shown in FIGS. 2 and 3, in the first counter 411, the reset operation is executed by the input timing (rise timing) of the external horizontal synchronization signal HSCKa supplied from the display signal generation circuit 50, and then the system Count values are sequentially added according to the input timing (rise timing) of the clock SYSCK. That is, the count operation of the system clock SYSCK is executed for each period (1H) of the external horizontal synchronization signal HSCKa.

  On the other hand, in the second counter 412, the reset operation is executed by the input timing (rise timing) of the external vertical synchronization signal VSCKa supplied from the display signal generation circuit 50, and then the input timing (rise timing) of the external horizontal synchronization signal HSCKa. ), The count value is sequentially added. That is, the count operation of the external horizontal synchronization signal HSCKa is executed for each period (1 V) of the external vertical synchronization signal VSCKa.

  Here, in the normal state, the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa having a normal signal waveform at a normal timing are supplied from the display signal generation circuit 50. Therefore, the first counter 411 and the second counter 411 In the counter 412, before reaching the full count (4096 count, 512 count), the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa of the next timing are input, so that they are periodically reset. . That is, the counters 411 and 412 are not counted until the full count.

  Accordingly, the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa supplied from the display signal generation circuit 50 are passed through (through) the signal output changeover switches 416 and 417 of the display changeover control unit 41 to the timing generator 42 as they are. In addition to the output, the external display data is output to the signal driver 20 as it is via the signal output changeover switch 418 (through). The system clock SYSCK is also supplied to the timing generator 42 as it is.

  Accordingly, the timing generator 42 generates a horizontal control signal and a vertical control signal based on the external horizontal synchronization signal HSCKa, the external vertical synchronization signal VSCKa, and the system clock SYSCK supplied from the display signal generation circuit 50, and each of the signal drivers 20 Then, the desired image information based on the video signal (external display data supplied from the display signal generation circuit 50) is displayed on the liquid crystal display panel by being supplied to the scanning driver 30.

  On the other hand, in an abnormal state in which the external horizontal synchronization signal HSYNC and the external vertical synchronization signal VSYNC supplied from the display signal generation circuit 50 are missing, the drive control operation (drive control method) of the display drive device is as shown in FIG. As shown in FIG. 4, first, similarly to the above-described normal state, the first counter 411 performs a reset operation at the input timing of the external horizontal synchronization signal HSCKa, and then the count value at the input timing of the system clock SYSCK. A count operation for sequentially adding is started. Also in the second counter 412, the reset operation is executed at the input timing of the external vertical synchronization signal VSCKa, and the count operation in which the count values are sequentially added at the input timing of the external horizontal synchronization signal HSCKa is started.

  Here, in an abnormal state in which the external horizontal synchronization signal HSYNC or the external vertical synchronization signal VSYNC is missing, the count value is not reset periodically in the first counter 411 or the second counter 412 and counts up to the full count. In other words, for example, when the first counter 411 counts 4096 system clocks, and when the second counter 412 counts 512 external horizontal synchronization signals VSCKa, the counters 411 and 412 output full counts. Is output to the select signal generators 413 and 414. In FIG. 4, the case where the external horizontal synchronization signal HSCKa and the external vertical synchronization signal VSCKa are missing is shown in the same drawing, but only one of these synchronization signals may be missing.

  As a result, at least one of the select signal generation units 413 and 414 generates a select signal and inputs it to the switching data generation unit 415, whereby the switching data generation unit 415 shifts to a signal output state, The horizontal synchronization signal HSCKb, the internal vertical synchronization signal VSCKb, and white display data are output, and the signal paths of the signal output changeover switches 416, 417, and 418 are switched.

  Therefore, in the signal output changeover switch 416, the external horizontal synchronization signal HSCKa from the display signal generation circuit 50 is blocked, and the internal horizontal synchronization signal HSCKb from the switch data generation unit 415 is captured and output to the timing generator 42. Further, in the signal output changeover switch 417, the external vertical synchronization signal VSCKa from the display signal generation circuit 50 is cut off, and the internal vertical synchronization signal VSCKb from the switching data generation unit 415 is taken in and output to the timing generator 42. Further, in the signal output changeover switch 418, the external display data (based on the video signal) from the display signal generation circuit 50 is blocked, and the white display data from the switching data generation unit 415 is captured and the signal driver. 20 is output. The system clock SYSCK is supplied to the timing generator 42 as it is as described above.

  Thereby, in the timing generator 42, the internal horizontal synchronizing signal HSCKb and the internal vertical synchronizing signal VSCKb supplied from the display switching control unit 41 (switching data generating unit 415), and the system clock SYSCK supplied from the display signal generating unit 50 are displayed. The horizontal control signal and the vertical control signal are generated based on the signal, and are supplied to the signal driver 20 and the scanning driver 30, respectively, and the white display data supplied from the display switching control unit 41 (switching data generation unit 415) is the signal driver. 20, a preset white display image is displayed on the liquid crystal display panel 10.

  As described above, according to the display drive device and the drive control method thereof according to the present embodiment, the external horizontal synchronization signal and the external vertical synchronization signal supplied from the display signal generation circuit are lost, and the LCD controller (display switching control unit) When an abnormal state that is not input to the external controller occurs, an external signal based on the video signal is generated based on the internal horizontal synchronization signal, the internal vertical synchronization signal, and the white display data supplied from the switching data generation unit provided in the LCD controller. Since a white display image is displayed instead of the display data (luminance gradation data), it is possible to prevent a phenomenon in which image information displayed in a normal display state is held and an afterimage is generated. Application of a DC voltage to the (liquid crystal) can be suppressed to suppress screen burn-in and deterioration of the liquid crystal.

  The internal horizontal synchronization signal and the internal vertical synchronization signal generated and output by the display switching control unit (switching data generation unit) described above are based on, for example, a video signal and a system clock, as in the display signal generation circuit described above. It may be generated based on a basic clock independent of the video signal or the system clock.

  In the abnormal state described above, when the display signal generation circuit returns to a state in which an external horizontal synchronization signal or an external vertical synchronization signal is normally supplied (normal state), the first and second counters are reset. Since the operation is executed and the full count output is not detected, the select signal is not output, the signal path of the signal output changeover switch is switched, and the internal horizontal synchronization signal and internal vertical synchronization signal supplied from the switching data generation unit are white. The display data capture is interrupted, and the external horizontal synchronization signal, the external vertical synchronization signal, and the external display data supplied from the display signal generation circuit are output to the timing generator and the signal driver.

It is a schematic block diagram which shows the example of 1 structure of the display apparatus to which the display drive device which concerns on this invention is applied. It is a principal part block diagram which shows one Embodiment of the display drive device (LCD controller) which concerns on this invention. 6 is a timing chart illustrating an example of a drive control operation in a normal state of the drive control method for the display drive device according to the embodiment. 6 is a timing chart showing an example of a drive control operation in an abnormal state of the drive control method for the display drive device according to the embodiment. It is a schematic block diagram which shows an example of the liquid crystal display device in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Liquid crystal display panel 20 Signal driver 30 Scan driver 40 LCD control 41 Display switching control part 42 Timing generator 50 Display signal generation circuit 411, 412 Counter 413, 414 Select signal generation part 415 Switching data generation part 416-418 Data output switching part

Claims (6)

In a display drive device that generates a drive control signal for displaying desired image information on a display panel based on a timing signal,
An external signal detecting means for detecting a supply state of an external timing signal supplied from the outside of the device;
An internal timing signal independent of the external timing signal, and an internal signal generating means for generating internal display data for setting the display panel to a predetermined display state;
A signal output switching means for outputting the internal timing signal and the internal display data generated by the internal signal generating means when the external signal detecting means detects the absence of the external timing signal;
Control signal generating means for generating the drive control signal based on the external timing signal or the internal timing signal;
A display driving device comprising: The external signal detection means counts the reference clock number for each cycle of the external timing signal, and outputs a full count output when the count value reaches the full count value in the counter, and is output from the counter A switching signal generation unit that detects the full count output and outputs a switching signal,
2. The display driving device according to claim 1, wherein the signal output switching means switches a signal path so as to output the internal timing signal and the internal display data based on the switching signal. 3. The display driving device according to claim 1, wherein the external timing signal whose supply state is detected by the external signal detecting means is at least one of a horizontal synchronizing signal and a vertical synchronizing signal. 4. The display according to claim 1, wherein the internal display data generated by the internal signal generation means is luminance gradation data for displaying a white display image on the display panel. Drive device. In a drive control method for a display drive device that generates a drive control signal for displaying desired image information on a display panel based on a timing signal,
Detecting a supply state of an external timing signal supplied from outside the apparatus;
When the external timing signal is normally supplied, generating the drive control signal based on the external timing signal;
When the lack of the external timing signal is detected, the drive control signal is generated based on an internal timing signal that is generated inside the display driving device and independent of the external timing signal, and Switching external display data supplied from the outside of the apparatus to display desired image information to internal display data for displaying a white display image;
A drive control method for a display drive device, comprising: 6. The display drive apparatus drive control method according to claim 5, wherein the external timing signal is at least one of a horizontal synchronization signal and a vertical synchronization signal.

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