JP2011048031A - Display signal output device and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain the insufficiency of gradation and resolution and an increase in processing load. <P>SOLUTION: Clock signals are generated on a cycle higher than a cycle corresponding to the horizontal resolution of image signals until a horizontal synchronization signal changes to a first horizontal synchronization signal level after the horizontal synchronization signal changes to a second horizontal synchronization signal level from the first horizontal synchronization signal level. A data enable signal is generated in a period combining a first period of generating clock signals corresponding to the horizontal resolution of the image signals and a second period before or after the first period. The image signals are output in the first period, and attribute information is output in the second period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display signal output device and a display device.

  In recent years, a display signal display device has received a display signal expressed in gradations of 8 bits for each RGB, such as 10 bits and 12 bits, and a display signal transmitted at 60 Hz, such as 120 Hz and 240 Hz. It has become possible to display various images such as high-frequency driving technology and 3D video display technology.

  As a result of such various displays being possible, there is a need for a means for the display signal output device to transmit a set value such as the type of the display signal to the display signal display device that can display it. In order to transmit the set value to the display signal display device, a dedicated line for transmitting the set value can be provided in a connection cable connecting the display signal output device and the display signal display device. However, in such a case, for example, it deviates from a widely spread connector standard such as DVI (Digital Visual Interface) formulated by DDWG (Digital Display Working Group). Deviation from the connector standard physically loses versatility for connection between the output device and the display device, and is not convenient.

  In order to solve such a problem, a partial area of a 1920 × 1080 pixel video is set as a header area, and a 10-byte length setting value is superimposed on the MSB (Most Significant Bit) of the video signal in this area, and the header area There is a technique for setting a video as a non-display area (Non-Patent Document 1). Deviation from the connector standard can be avoided because the set value is superimposed on a partial area of the video.

Philips 3D Solutions, “3D INTERFACE SPECIFCATIONS WHITE PAPER”, FIG. 10, [online], February 15, 2008, Konlinkijke Philips Electronics N. V. [Search on March 26, 2008], Internet <URL: http://www.business-sites.philips.com/shared/assets/global/Downloadablefile/Philips-3D-Interface-White-Paper-13725. pdf>

  As described above, when the set value is superimposed on 1 bit of the MSB in the 8-bit video signal, the video signal is expressed by the remaining 7-bit gradation in the pixel corresponding to the header area where the set value is superimposed. That is, the other area is expressed by 256 gradations (8 bits), while the header area is expressed by 128 gradations (7 bits), resulting in insufficient gradation.

  In addition, as in Non-Patent Document 1, it is possible to display only a horizontal pixel corresponding to the Header area as a non-display area and stretch other areas to display on the display device. May increase.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a display signal output device and a display signal display device in which insufficient gradation and resolution and increase in processing load are suppressed.

  A display signal output device according to an embodiment of the present invention includes a clock signal generation unit that generates a clock signal according to a resolution and a refresh rate of a display signal, and a vertical synchronization signal that corresponds to the vertical resolution of the display signal. A vertical synchronization signal generator, a horizontal synchronization signal generator for generating a horizontal synchronization signal according to the horizontal resolution of the display signal, a video signal output unit for generating a video signal, and a first signal according to the resolution of the display signal. A data enable signal generator for generating a data enable signal having a first period for outputting one data enable signal level and a second period for outputting a second data enable signal level; The signal level of the period is changed from the second data enable signal level to the first data enable. A data enable signal changing unit for changing to a video signal level, and a video signal changing unit for changing the video signal so as to have a video signal in the first period and attribute information in the second period. And

  In addition, a display device according to an embodiment of the present invention includes a clock signal receiving unit that receives a clock signal corresponding to the resolution and refresh rate of a display signal, and a vertical synchronization signal that corresponds to the vertical resolution of the display signal. A vertical synchronizing signal receiving unit, a horizontal synchronizing signal receiving unit that receives a horizontal synchronizing signal according to the horizontal resolution of the display signal, and a first data enable signal level that is output according to the resolution of the display signal. The signal level of the second period of the data enable signal having a period and a second period of outputting the second data enable signal level is changed from the second data enable signal level to the first data enable signal level. A data enable signal changing unit, the vertical synchronization signal, the horizontal synchronization signal, and the data Based on at least one of the enable signals and the clock signal, the first period video signal and the second period attribute information included in the display signal are discriminated, and the attribute information is separated from the display signal. And a video signal changing unit for changing in such a manner.

  According to the present invention, it is possible to provide a display signal output device and a display signal display device in which insufficient gradation and resolution and an increase in processing load are suppressed.

The display signal output apparatus and display signal display apparatus which concern on embodiment of this invention. A display signal generation unit and an attribute information addition unit. The schematic diagram of the relationship with the time-axis of a display signal. Attribute information separation unit and display controller. An example of a video signal, a clock signal, attribute information, and a data enable signal DE1. An example of connector pin assignment. Setting value holding unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a video signal is transmitted and received between a display signal output device and a display signal display device using DVI (Digital Visual Interface), HDMI (High-Definition Multimedia Interface), etc. In the description of the embodiment, a parallel signal before serializing a control signal and a video signal or a parallel signal after receiving the serialized control signal and video signal will be described as an example. A description of the portion encoded in the DVI or HDMI format and the portion decoded from the DVI or HDMI format will be omitted.

  FIG. 1 is a diagram showing a display signal output device 101 and a display signal display device 102 according to the present embodiment. In FIG. 1, the flow of data between the blocks of the display signal output device 101 and the display signal display device 102 is indicated by arrows. The display signal output device 101 according to the present embodiment includes a storage device unit 11, a display signal generation unit 12, an attribute information addition unit 13, and a display signal transmission unit 14. The display signal display apparatus 102 according to the present embodiment includes a display signal receiving unit 15, an attribute information separating unit 16, a display controller 17, and a display 18.

  The storage unit 11 stores video data that is a source of video to be displayed on the display 18. The video data is input to the storage device 11 from a storage disk or computer network in which broadcast waves and video content are stored. The video data input to the storage unit 11 is not only the entire video data, but also the entire video data such as video data input from a broadcast wave or a computer network, for example, is input in time series. May be stored in the storage device unit 11.

  The display signal generation unit 12 includes a video signal generation unit 135 that generates a video signal for each frame based on the video data stored in the storage unit 11, and a clock signal generation unit that generates a clock signal (Clock). 131, a data enable generator 132 that generates a data enable signal (DE0), a vertical synchronization signal generator 133 that generates a vertical synchronization signal (Vsync), and a horizontal synchronization signal generator 134 that generates a horizontal synchronization signal (Hsync). .

  The attribute information adding unit 13 is arranged before or after the effective period (first period) of the data enable (DE) signal, or before and after (second period), before or after the video signal and the video signal, or video. Add attribute information before and after the signal. The attribute information is, for example, a flag indicating whether the video data is 2D video or 3D video, viewing area information of a stereoscopic display, coordinate information indicating a region of 2D video or 3D video in the video data, etc. is there.

  The display signal transmission unit 14 converts the display signal generated by the display signal generation unit 12 and the attribute information addition unit 13 into a video signal and transmits the video signal to the display signal display device 102.

  The display signal receiving unit 15 receives the video signal transmitted by the display signal transmitting unit 14 and converts it into a display signal.

  The attribute information separation unit 16 determines and separates the attribute information added by the attribute information addition unit 13 and transmits a display signal to the display controller 17.

  The display controller 17 controls the display 18 based on the received video signal, synchronization signal, clock signal, DE signal, and attribute information.

  FIG. 2 is a diagram illustrating the display signal generation unit 12 and the attribute information addition unit 13. The display signal generation unit 12 includes a clock signal generation unit 131, a data enable signal generation unit 132, a vertical synchronization signal generation unit 133, a horizontal synchronization signal generation unit 134, and a video signal output unit 135. The attribute information adding unit 13 includes a VA counter (vertical direction counter) 136, an HA counter (horizontal direction counter) 137, an attribute information holding unit 138, a data enable signal changing unit 139, and a video signal changing unit 140.

  The clock signal generation unit 131 generates a clock signal Clock based on a system clock signal supplied from outside (not shown). Clock is a signal for transmitting a video signal and a control signal and obtaining synchronization. The frequency of the clock is determined by the product of the horizontal period (HP), the vertical period (VP), and the frame frequency.

  The data enable signal generation unit 132 generates DE0 based on the resolution of the video signal to be transmitted (for example, the resolution of the display 18 input separately). The DE signal is a signal for discriminating between a valid period and a non-valid period of the video signal. Depending on the resolution of the video signal, it is High (high level) during the effective period and Low (low level) during the non-effective period.

  The vertical synchronization signal generation unit 133 generates a vertical synchronization signal Vsync indicating a break in the video signal in the vertical direction based on the vertical resolution of the video signal to be transmitted.

  The horizontal synchronization signal generation unit 134 generates a horizontal synchronization signal Hsync indicating a break in the horizontal video signal based on the horizontal resolution of the video signal to be transmitted.

  The video signal output unit 135 generates a video signal based on the video data and Clock.

  FIG. 3 is a diagram schematically allocating Clock, DE signals (DE0 and DE1), Vsync, Hsync, and time axis among the display signals generated by the display signal generation unit 12 to the display surface coordinates of the display 18. .

  DE0 is a signal that defines an effective period and an ineffective period of the video signal. For example, in DE0, a high level (first data enable signal level) period (H period) is an effective period, and a low level (second data enable signal level) period (L period) is an ineffective period. In FIG. 3, DE0 is schematically shown by separating it into a horizontal period (DE0h) and a vertical period (DE0v) for convenience of explanation, but it is a single DE signal having a horizontal period and a vertical period. In DE0h schematically showing the DE signal in the horizontal period, the H period is an effective display period and the L period is an ineffective display period, as in the case of the DE signal. Further, in DE0v schematically showing the DE signal in the vertical period, the H period is an effective display period and the L period is an ineffective display period, like the DE signal.

  DE0 is from the start of the H period corresponding to the screen coordinates (Rx + 1, 1) from the start of the H period corresponding to the screen coordinates (Rx + 1, 1) from the start of the H period corresponding to the screen coordinates (1, 1) to the end of the H period corresponding to the screen coordinates (Rx, 1). Until the end of the H period corresponding to the screen coordinates (1-1, 2), from the start of the H period corresponding to the L period, the screen coordinates (1, 2) to the end of the H period corresponding to the screen coordinates (Rx, 2). , H period. From the start of the H period corresponding to the screen coordinates (1, 1) to the end of the H period corresponding to the screen coordinates (Rx, Ry), the H period repeats VA (times) when converted into the number of clocks.

  Vsync has an L period and an H period. The L period has a vertical sync pulse period (VSPW). The H period includes a vertical back porch period (VBP) from the end of the L period of the VSPW to the start of the effective period, an effective display period (VA), and a vertical front porch period from the end of the VA period to the start of the next VSPW period ( VFP).

  Hsync has an L period and an H period. The L period has a horizontal sync pulse period (HSPW). The H period includes a horizontal back porch period (HBP) from the end of the HSPW L period to the start of the effective period, an effective display period (HA), and a horizontal front porch period (from the end of the HA period to the start of the next HSPW period) ( HFP).

The addition periods α1 to α4 are periods during which attribute information is added (transmitted). The additional period α1 is immediately before the effective period of DE0h, and the additional period α2 is a period immediately after the effective period of DE0h. The additional period α3 is a period obtained by adding the HA period and the additional periods α1 and α2 in the period immediately before the screen coordinates (1, 1). The additional period α4 is a period obtained by adding the HA period and the additional periods α1 and α2 among the period immediately after the screen coordinates (Rx, Ry). The additional periods α3 and α4 are not necessarily continuous periods, and may include a period obtained by adding the additional periods α1 and α2 to a plurality of consecutive HA periods. The additional periods α1 to α4 depend on the amount of attribute information.
α1: 0 ≦ α1 ≦ HBP
α2: 0 ≦ α2 ≦ HFP
α3: 0 ≦ α3 ≦ VBP
α4: 0 ≦ α4 ≦ VFP
Can be set between. For example, maximum {(α1 + HA + α2) * (α3 + VA + α4) − (HA * VA)} * number of gradations (bit)
The attribute information can be arbitrarily set by the user.

  The video signal 201 includes, for example, 6-bit data and 8-bit data of RED, BLUE, and GREEN. When DE0 is in the H period, the video signal 201 is treated as a valid video signal 202 and displayed on the display 18. On the other hand, when DE0 is in the L period, the video signal 201 is treated as an invalid signal and is not displayed on the display 18.

  The video signal 201 further has attribute information. When DE0 is in the L period and DE1 is in the H period, the video signal 201 is treated as valid attribute information 203. The display signal with the attribute information added by the attribute information adding unit 13 is transmitted from the display signal transmitting unit 14 and received by the display signal receiving unit 15. The attribute information separation unit 16 separates the attribute information 203, the effective video signal 202 is transmitted to the display controller 17, and the video is displayed on the display 18.

  The attribute information adding unit 13 will be described in detail with reference to FIG. The display signal generation unit 12 generates Clock, DE0, Vsync, Hsync, and video signal DATA0 based on the resolution of the video signal to be transmitted (for example, the resolution of the display 18 that is input separately).

  The attribute information adding unit 13 receives Clock, DE0, Vsync, Hsync, and DATA0. Based on the attribute information held in the attribute information holding unit 138, DE0 to DE1 and video signal DATA1 from DATA0 are generated.

  DE1 is a signal that defines a period obtained by adding at least one of the additional periods α1, α2, α3, or α4 to the H period of DE0. For example, DE1 is a period obtained by adding an additional period to an effective period, and an L period is a period obtained by removing the additional period from an ineffective period.

  The VA counter 136 counts the vertical resolution (VA) using Clock, DE0, Vsync, and Hsync. As the VA counter 136, an up counter having a D-type flip-flop (DFF) circuit can be used.

  The HA counter 137 counts the horizontal resolution (HA) using Clock, DE0, Vsync, and Hsync. As the HA counter 137, an up counter having a D-type flip-flop (DFF) circuit can be used.

  The attribute information holding unit 138 stores a threshold value of the number of clocks in the HA period according to the horizontal resolution Rx. Further, a threshold value for the number of lines in the VA period corresponding to the vertical resolution Ry is stored. Moreover, the setting value is preserve | saved about the length of addition period (alpha) 1-4.

  The data enable signal changing unit 139 changes DE0 to DE1 based on the attribute information stored in the attribute information holding unit 138.

  The video signal changing unit 140 changes DATA0 to DATA1 based on the attribute information stored in the attribute information holding unit 138.

  The attribute information addition unit 13 compares the count number of the VA counter 136 with this threshold value, and the count number of the HA counter 137 with this threshold value, and determines the boundary between the addition periods α1 to α4 and the VA period and HA period. Further, based on the counts of the VA counter 136 and the HA counter 137 and the set value, the boundary between the additional periods α1 to α4 and the ineffective period is determined.

  Further, the attribute information adding unit 13 determines the transmission timing of Hsync, Vsync, display signal DATA, and DE1 according to the processing time of the attribute information adding unit 13 based on the counts and clocks of the VA counter 136 and the HA counter 137. Delay. For example, a shift register having a D-type flip-flop (DFF) can be used as the delay circuit.

  The display signal transmission unit 14 and the display signal reception unit 15 can use a transmitter IC and a receiver IC that are compatible with a format (for example, DVI, HDMI, analog, etc.) used for data transmission / reception.

  FIG. 4 is a diagram for explaining the attribute information separation unit 16 and the display controller 17. The attribute information separation unit 16 includes a VA counter 151, an HA counter 152, an attribute information holding unit 153, a data enable signal changing unit 154, and a video signal changing unit 155. The display controller 17 includes a clock signal reception unit 156, a data enable signal reception unit 157, a vertical synchronization signal reception unit 158, a horizontal synchronization signal reception unit 159, a video signal reception unit 160, and a setting value holding unit 161.

  The VA counter 151 counts vertical resolution (VA) and attribute information α3, attribute information α4, or both using Clock, DE1, Vsync, and Hsync. As the VA counter 151, an up counter having a D-type flip-flop (DFF) circuit can be used.

  The HA counter 152 counts the horizontal resolution (HA) and the attribute information α1, the attribute information α2, or both using Clock, DE0, Vsync, and Hsync. As the HA counter 152, an up counter having a D-type flip-flop (DFF) circuit can be used.

  The attribute information holding unit 153 stores a threshold value for the number of lines in the VA period corresponding to the vertical resolution Ry. A threshold value of the number of clock signals Clock in the HA period corresponding to the horizontal resolution Rx is stored. Moreover, the setting value is preserve | saved about the length of addition period (alpha) 1-4.

  The data enable signal changing unit 154 reads the threshold value for the number of lines and the threshold value for the number of clocks from the attribute information holding unit 153. The count number of the VA counter 151 is compared with the threshold value of the number of lines in the VA period. Further, the count value of the HA counter 152 is compared with the threshold value of the Clock number. By this comparison, the boundary between the additional periods α1 to 4 and the VA period and HA period is determined, and DE1 is returned to DE0.

  The video signal changing unit 155 receives DATA1. The count number of the VA counter 151 is compared with the threshold value of the number of lines in the VA period. Further, the count number of the HA counter 152 is compared with the threshold value of the clock signal Clock number. By this comparison, the boundary between the additional periods α1 to 4 and the VA period and the HA period is determined, and DATA1 is restored to DATA0. The attribute information α1 to 4 is determined according to the count numbers of the VA counter 151 and the HA counter 152. Moreover, the attribute information of DATA1 is received based on the attribute information α1-4. The received attribute information is stored in the set value holding unit 161. Note that the step of returning DATA1 to DATA0 can be omitted.

  The attribute information separation unit 16 delays the transmission timing of DE0, Vsync, Hsync, and DATA0 according to the processing time of the attribute information separation unit 16 based on the counts of the VA counter 151 and the HA counter 152 and Clock. For example, a shift register having a D-type flip-flop (DFF) can be used as the delay circuit.

  The clock signal receiving unit 156 receives the Clock. The data enable signal receiving unit 157 receives DE0. The vertical synchronization signal receiving unit 158 receives Vsync based on a period (VA) corresponding to the vertical resolution Ry of the display 18. The horizontal synchronization signal receiving unit 159 receives Hsync based on a period (HA) corresponding to the horizontal resolution Rx of the display 18. The video signal receiving unit 160 receives DATA0. The set value holding unit 161 stores the transmitted attribute information. Based on these signals, an image and timing to be displayed on the display 18 are generated.

  FIG. 5 shows an example of Clock, DE1, video signal, and attribute information. The video signal is RED, GREEN, BLUE, each 8 bits wide. [7] of each color is an MSB (Most Significant Bit) and [0] is an LSB (Least Significant Bit). In FIG. 5, RED [7: 1], GREEN [7: 0], and BLUE [7: 0] represent buses. RED [7: 1] is a 7-bit bus arranged in descending order from the 7th bit to the 1st bit of RED, and GREEN [7: 0] and BLUE [7: 0] are in descending order from the 7th bit to the 0th bit. These are 8-bit wide buses lined up. In the example of FIG. 5, attribute information is assigned to RED [0].

  FIG. 5A shows an example of transmitting a video signal for 2D video. FIG. 5B is an example when transmitting a video signal for 3D video. When DE1 is in the H period, if 1 clock portion immediately before the effective portion of RED [0] of the video signal is set to 0, it is for 2D video display, and if it is set to 1, it is for 3D video display. it can.

  The video signal output device and the display device thus made can suppress a lack of gradation and resolution and an increase in processing load. That is, it is not necessary to superimpose attribute information on the effective portion of the video signal, and lack of gradation and resolution can be suppressed. In addition, when attribute information is added / separated from DATA0, a counter having a small circuit scale can be used, and an increase in processing load can be suppressed. In addition, since a new control signal line is not required, there is no need to change the general-purpose connector specification (for example, DVI standard). Further, since the video signal after the attribute information is separated can be made the same as the video signal when the attribute information is not added, the versatility is high.

  An example in which the video signal output device according to the present embodiment is applied to a video signal of XGA (Rx = 1024, Ry = 768) is shown below (FIG. 3). The number of gradations is 256 gradations (8 bits) for each of RED, GREEN, and BLUE. The connector pin assignment is an example of the DVI connector pin assignment defined by the DDWG (FIG. 6).

  The frequency of Clock is 65.2 MHz, HP is 1344 pixels, and VP is 806 pixels. HSPW is set to 136 pixels, HBP is set to 160 pixels, and HFP is set to 24 pixels. VSPW is 6 lines, VBP is 29 lines, and VFP is 3 lines. Here, the unit pixels is the number of clocks, and lines is the number of HPs. For example, 1344 pixels of HP are 1344 × 15.38 nsec, and 806 lines of VP are 806 × 20.67 μsec.

  The attribute information is transmitted using the RED LSB in the α1 period. α1 is set to 1, α2 to 4 are set to 0, and the HA of the display signal DATA transmitted from the video signal output device is incremented by 1 pixel and is changed from 1024 pixels to 1025 pixels. Also, HBP is incremented by 1 pixel and changed from 160 pixels to 159 pixels.

  FIG. 7 shows an example of the attribute information holding unit 138. The HA holding unit 301 stores a threshold value for the number of clocks in the HA period, which is 1024 in this example. The VA holding unit 302 stores a threshold value for the number of clocks in the VA period, in this example, 768. The α1 holding unit 303 stores a set value for the length of the additional period α1, which is 1 in this example. Similarly, in the α2 holding unit 304, the α3 holding unit 305, and the α4 holding unit 306, a set value for the length of the additional periods α2 to 4, which is 0 in this example, is stored. Information on which bit of the video signal the attribute information is assigned to is stored in 307. Note that the set value holding unit 161 holds the set value in the same manner as the attribute information holding unit 138.

  The data enable signal changing unit 139 refers to the set value of the attribute information holding unit 138. Based on the setting value referred to in the present example, the data enable signal changing unit 139 changes DE0 to DE1 in the forward direction by a length of one clock. The data enable signal changing unit 154 refers to the set value of the set value holding unit 161. Based on the setting value referred to in this example, the data enable signal changing unit 154 changes DE1 to DE0 by temporally shortening by one clock from the forward direction.

  Although the attribute information holding unit 138 has been described with respect to the case where the setting values for the length of the additional periods α1 to α4 are stored in the α1 to 4 holding units 303 to 306, the count numbers of the VA counter 151 and the HA counter 152 are described. And DE1 can separate the video signal and the attribute information from the display signal DATA. In this case, holding of the set values for the lengths α2 and α4 can be omitted.

DESCRIPTION OF SYMBOLS 101 ... Display signal output device, 102 ... Display signal display device, 11 ... Memory | storage device part, 12 ... Display signal generation part, 13 ... Attribute information addition part, 14 ... Display signal Transmitter, 15 ... display signal receiver, 16 ... attribute information separator, 17 ... display controller, 18 ... display, 131 ... clock signal generator, 132 ... data enable signal Generation unit, 133 ... vertical synchronization signal generation unit, 134 ... horizontal synchronization signal generation unit, 135 ... video signal output unit, 136 ... VA counter, 137 ... HA counter, 138 ... Attribute information holding unit, 139 ... Data enable signal changing unit, 140 ... Video signal changing unit, 151 ... VA counter, 152 ... HA 153... Attribute information holding unit, 154... Data enable signal changing unit, 155... Video signal changing unit, 156... Clock signal receiving unit, 157. ... vertical sync signal receiver, 159 ... horizontal sync signal receiver, 160 ... video signal receiver, 161 ... set value holding unit, 201 ... video signal, 202 ... valid Video signal 203... Valid attribute information 301... HA holding unit 302... VA holding unit 303... Α1 holding unit 304... Α2 holding unit 305. 306... Α4 holding unit, 307... Video signal allocation position holding unit

Claims (5)

A clock signal generator that generates a clock signal according to the resolution and refresh rate of the display signal;
A vertical synchronization signal generator for generating a vertical synchronization signal according to the vertical resolution of the display signal;
A horizontal synchronization signal generating unit that generates a horizontal synchronization signal according to a horizontal resolution of the display signal;
A video signal output unit for generating a video signal;
A data enable signal generator for generating a data enable signal having a first period for outputting a first data enable signal level according to the resolution of the display signal and a second period for outputting a second data enable signal level When,
A data enable signal changing section for changing the signal level of the data enable signal from the second data enable signal level to the first data enable signal level;
A video signal changing unit that changes the video signal to have the video signal in the first period and the attribute information in the second period;
A display signal output device comprising: 2. The video signal output device according to claim 1, further comprising a counter that counts a clock signal during at least one of the first period and the second period. The counter is
A vertical direction counter that counts clock signals at a period according to the vertical resolution of the display signal;
A horizontal counter that counts the clock signal at a period according to the horizontal resolution of the display signal;
The video signal output apparatus according to claim 2, wherein: The display signal output apparatus according to claim 3, further comprising a shift register that delays the video signal. A clock signal receiver for receiving a clock signal according to the resolution and refresh rate of the display signal;
A vertical synchronization signal receiver that receives a vertical synchronization signal according to the vertical resolution of the display signal;
A horizontal synchronization signal receiving unit that receives a horizontal synchronization signal according to a horizontal resolution of the display signal;
The signal level of the second period of the data enable signal having a first period for outputting the first data enable signal level according to the resolution of the display signal and a second period for outputting the second data enable signal level. A data enable signal changing unit for changing from the second data enable signal level to the first data enable signal level;
Based on at least one of the vertical synchronization signal, the horizontal synchronization signal, and the data enable signal, and the clock signal, the first period video signal and the second period attribute information included in the display signal are determined. And a video signal changing unit for changing the attribute information to separate from the display signal,
A display device comprising:

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