CN100543831C - Multi-scan LCD with and driving method - Google Patents
Multi-scan LCD with and driving method Download PDFInfo
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- CN100543831C CN100543831C CNB2007100846833A CN200710084683A CN100543831C CN 100543831 C CN100543831 C CN 100543831C CN B2007100846833 A CNB2007100846833 A CN B2007100846833A CN 200710084683 A CN200710084683 A CN 200710084683A CN 100543831 C CN100543831 C CN 100543831C
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Abstract
The invention provides a kind of multi-scan LCD with and driving method.Wherein, this LCD comprises circuit system, is used for producing first scan line clock, second scan line clock, the first sweep trace control signal and the second sweep trace control signal.Gate drivers comprises first shift register, second shift register and logical circuit.First shift register is used for producing the first grid switching signal according to the first sweep trace control signal when this first scan line clock triggers.Second shift register is used for producing the second grid switching signal according to the second sweep trace control signal when this second scan line clock triggers.Logic circuits coupled is used from selecting the output scanning signal among first grid switching signal and the second grid switching signal in first shift register and this second shift register.The voltage data signal that each pixel basis source electrode driver produces is adjusted the arrangement of liquid crystal molecule in the liquid crystal capacitance.
Description
Technical field
The gate drivers that the present invention relates to a kind of LCD and be used for this LCD relates in particular to a kind of gate drivers that is used for multi-scan LCD and is used for this multi-scan LCD.
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has become the display that various electronic equipments such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the widespread use of notebook computer screen institute have the high-resolution color screen gradually.
See also Fig. 1, Fig. 1 is the functional block diagram of the LCD 10 of prior art.LCD 10 comprises display panels 12, a plurality of gate drivers (gate driver) 14a, 14b, 14c and multiple source driver (source driver) 16.Display panels 12 comprises a plurality of pixels (pixel) 20.With a display panels 12 with 1024 * 768 resolution and 60Hz renewal frequency is example, and display panels 12 has 1024 * 768 pixels 20, and the demonstration time of each picture is about 1/60=16.67ms.For display panels 12, need 768 sweep traces to connect all pixels 20 altogether.With a gate drivers chip with 256 passage pins, display panels 12 needs three gate drivers 14a, 14b, 14c to control 768 sweep traces.Can be considered shift register (shift register) on gate drivers 14a, 14b, the 14c function, its purpose promptly makes the transistor 22 of each row pixel 20 open in regular turn every fixed intervals (16.67ms/768=21.7 μ s) output scanning signal, the liquid crystal capacitance 24 of 16 pixels 20 of voltage data signal to a full line of output correspondence in the time of this 21.7 μ s of source electrode driver makes it be charged to required separately voltage simultaneously, to show different GTGs.After pixel 20 chargings with delegation finish, just the sweep signal of this row is closed, the output scanning signal is opened the transistor 22 of the pixel 20 of next line again, and the pixel 20 by 16 pairs of next lines of source electrode driver discharges and recharges again.Carry out so in regular turn after 768 sweep traces all are scanned once, rescan by first horizontal scanning line again.
In order to increase display quality, develop a kind of LCD that is referred to as the multiple scaaning technology now, just in the demonstration time of a picture (16.67ms), gate drivers 14a, 14b, 14c produce above sweep signal twice to the sweep trace of each row, thus, the transistor 22 of the pixel 20 on this row is opened more than twice, makes liquid crystal capacitance 24 be received above voltage data signal twice.See also Fig. 2, Fig. 2 be the LCD 10 of Fig. 1 when multiple scaaning, part scans the sequential chart of online signal.In Fig. 2, be scanned the pulse C triggering of line clock signal YDIO as gate drivers 14a after, can produce the sweep signal pulsed D is positioned at the pixel 20 on first row with unlatching to the sweep trace G1 of first row transistor according to scan line driving signal YOED, and source electrode driver 16 is opened the transistorized while of the pixel 20 on first row at the sweep signal pulsed D, then the corresponding voltage data signal of output makes it be charged to required separately voltage to first pixel 20 of going, to show different GTGs.Because each gate drivers 14a-14c all can be considered a shift register, so gate drivers 14a-14c is every the cycle of a scan line clock YCLK (cycle), can be in regular turn according to scan line driving signal YOED output scanning signal pulse D give second row after sweep trace G2 ..., G768 and open the transistor 22 of the pixel 20 of correspondence.After gate drivers 14a output scanning signal pulse D gives sweep trace G256, gate drivers 14b can produce the sweep signal pulsed D according to scan line driving signal YOED and give sweep trace G257, at the same time, the pulse E that gate drivers 14a also can be scanned line horizontal-drive signal YDIO triggers, make gate drivers 14a begin to produce sweep trace G1 that sweep signal pulse B gives first row and be positioned at first the transistor 22 of pixel 20 on capable to open once more according to scan line driving signal YOEB, and source electrode driver 16 is when sweep signal pulse B opens the transistor 22 of the pixel 20 on first row, then the corresponding voltage data signal of output makes it be charged to required voltage to first pixel 20 of going once more, to show different GTGs.Sweep trace G2...G256 then can open the transistor 22 of corresponding pixel 20 in regular turn once more according to sweep signal pulse B afterwards, to show different GTGs.
For fear of pixel 20 have charge into simultaneously two kinds of different pieces of information signal voltages may, gate drivers 14a, a 14b, 14c can only received scanline drive signal YOED in a period or YOEB one of them.With gate drivers 14b is example, if gate drivers 14b just according to scan line driving signal YOED in regular turn output scanning signal pulse D give sweep trace G257 ..., G512, then gate drivers 14b must wait until that the sweep signal pulsed D exports to after the sweep trace G512, could receive another scan line driving signal YOEB output scanning signal pulse B give sweep trace G257 ..., G512.
Yet in the trend now, for the usage quantity of the gate drivers that reduces LCD, passage pin (channel) number of single gate drivers increases gradually.A gate drivers had 256 passage pins in the past, yet the gate drivers with 512 even 1024 passage pins develops successively.To have 512 or more the gate drivers of hyperchannel pin is because of the mode that can't receive different scanning line drive signal YOED or YOEB simultaneously and cause using multiple scaaning drives the problem of display panels in order solving, to be necessary that configuration circuit is with head it off in gate drivers.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of gate drivers that is used for multi-scan LCD and is used for LCD, can allow the LCD of using gate drivers can receive a plurality of scan line driving signals to produce sweep signal repeatedly.
One embodiment of the present of invention provide a kind of gate drivers, are used for driving display panels, and this gate drivers comprises first shift register, second shift register and a plurality of logical circuit.This first shift register produces the first grid switching signal according to the first sweep trace control signal after triggered by first scan line clock.This second shift register produces the second grid switching signal according to the second sweep trace control signal after triggered by second scan line clock.Described a plurality of logic circuits coupled is used from selecting the output scanning signal to drive this display panels among this first grid switching signal and this second grid switching signal in this first shift register and this second shift register.
Aforesaid gate drivers, wherein said a plurality of logical circuits are used for this first grid switching signal and this second grid switching signal are carried out the OR logical operation to export this sweep signal.
Aforesaid gate drivers, wherein this first shift register and this second shift register are used for respectively producing this first grid switching signal and this second grid switching signal every the cycle of a clock signal respectively according to this first sweep trace control signal and this second sweep trace control signal after this first scan line clock and the triggering of this second scan line clock.
Aforesaid gate drivers, wherein the triggering period of this first sweep trace control signal is different from the triggering period of this second sweep trace control signal.
Aforesaid gate drivers wherein also comprises the current potential adjustment unit, is coupled to described a plurality of logical circuit, is used for adjusting the voltage potential of this sweep signal.
Another embodiment of the present invention also provides a kind of LCD, and it comprises circuit system, source electrode driver, gate drivers and a plurality of pixel.This circuit system is used for according to vertical synchronizing signal and horizontal-drive signal, produces first scan line clock, second scan line clock, the first sweep trace control signal and the second sweep trace control signal.This source electrode driver is used for producing voltage data signal.This gate drivers comprises first shift register, second shift register and a plurality of logical circuit.This first shift register is used for producing the first grid switching signal according to this first sweep trace control signal when this first scan line clock triggers.This second shift register is used for producing the second grid switching signal according to this second sweep trace control signal when this second scan line clock triggers.Described a plurality of logic circuits coupled is used from selecting the output scanning signal among this first grid switching signal and this second grid switching signal in this first shift register and this second shift register.Each pixel comprises transistor and liquid crystal capacitance, is used for when this sweep signal is opened this transistor, and the voltage data signal that this liquid crystal capacitance produces according to this source electrode driver is adjusted the arrangement of liquid crystal molecule in this liquid crystal capacitance.
Aforesaid LCD, wherein said a plurality of logical circuits are used for this first grid switching signal and this second grid switching signal are carried out the OR logical operation to export this sweep signal.
Aforesaid LCD, wherein this gate drivers comprises the current potential adjustment unit in addition, is coupled to described a plurality of logical circuit, is used for adjusting the voltage potential of this sweep signal.
Aforesaid LCD, wherein the pulsewidth of this first sweep trace control signal is substantially equal to the pulsewidth of this first grid switching signal.
Aforesaid LCD, wherein the pulsewidth of this second sweep trace control signal is substantially equal to the pulsewidth of this second grid switching signal.
Aforesaid LCD, wherein also comprise clock generator, be used for clocking, wherein this first shift register and this second shift register are used for respectively producing this first grid switching signal and this second grid switching signal every the cycle of this clock signal respectively according to this first sweep trace control signal and this second sweep trace control signal after this first scan line clock and the triggering of this second scan line clock.
Aforesaid LCD, wherein the triggering period of this first sweep trace control signal is different from the triggering period of this second sweep trace control signal.
Another embodiment of the present invention also provides a kind of multiple scaaning method of LCD, it comprises the following step: (a) according to vertical synchronizing signal and horizontal-drive signal, produce first scan line clock, second scan line clock, the first sweep trace control signal and the second sweep trace control signal; (b) after this first scan line clock triggers, produce the first grid switching signal according to this first sweep trace control signal; (c) after this second scan line clock triggers, produce the second grid switching signal according to this second sweep trace control signal; (d) select the output scanning signal among this first grid switching signal and this second grid switching signal certainly; And (e) when this sweep signal triggers, according to this voltage data signal display image.
Aforesaid multiple scaaning method, wherein step (d) comprises: this first grid switching signal and this second grid switching signal are carried out the OR logical operation to export this sweep signal.
Aforesaid multiple scaaning method, wherein the pulsewidth of this first sweep trace control signal is substantially equal to the pulsewidth of this first grid switching signal.
Aforesaid multiple scaaning method, wherein the pulsewidth of this second sweep trace control signal is substantially equal to the pulsewidth of this second grid switching signal.
Aforesaid multiple scaaning method, wherein step (b) comprises: after this first scan line clock triggers, produce this first grid switching signal every the cycle of a clock signal according to this first sweep trace control signal.
Aforesaid multiple scaaning method, wherein step (c) comprises: after this second scan line clock triggers, produce this second grid switching signal every the cycle of a clock signal according to this second sweep trace control signal.
Aforesaid multiple scaaning method, wherein the triggering period of this first sweep trace control signal is different from the triggering period of this second sweep trace control signal.
Another embodiment of the present invention provides a kind of LCD, and it comprises circuit system, source electrode driver, gate drivers and a plurality of pixel.This circuit system is used for according to vertical synchronizing signal and horizontal-drive signal, produces a plurality of scan line clock and a plurality of sweep trace control signal.This source electrode driver is used for outputting data signals voltage.This gate drivers comprises a plurality of shift registers and a plurality of logical circuit.Each shift register is coupled to a scan line clock of described a plurality of scan line clock and a sweep trace control signal of described a plurality of sweep trace control signals, be used for when this scan line clock voltage triggered, produce the gate switch signal according to this sweep trace control signal.Each logic circuits coupled is used from selection output scanning signal among the gate switch signal of described a plurality of shift registers generations in described a plurality of shift registers.Described a plurality of pixel, each pixel comprises transistor and liquid crystal capacitance, is used for when this sweep signal is opened this transistor, and the voltage data signal that this liquid crystal capacitance produces according to this source electrode driver is adjusted the arrangement of liquid crystal molecule in this liquid crystal capacitance.
Aforesaid LCD, wherein said a plurality of logical circuits are used for described a plurality of gate switch signals are carried out the OR logical operation to export this sweep signal.
Aforesaid LCD, wherein this gate drivers also comprises the current potential adjustment unit, is coupled to described a plurality of logical circuit, is used for adjusting the voltage potential of this sweep signal.
Aforesaid LCD, wherein the pulsewidth of each sweep trace control signal is substantially equal to the pulsewidth of the pairing gate switch signal of described each sweep trace control signal.
Aforesaid LCD, it also comprises clock generator, be used for clocking, wherein each shift register is used for producing this gate switch signal every the cycle of this clock signal according to this sweep trace control signal after this scan line clock triggers.
Aforesaid LCD, the triggering period difference of any two sweep trace control signals of wherein said a plurality of sweep trace control signals.
The present invention can make the transistor of the pixel of each bar sweep trace that the above opening time is arranged twice, to reach the purpose of multiple scaaning.
Description of drawings
Fig. 1 is the functional block diagram of the LCD of prior art.
Fig. 2 be the LCD of Fig. 1 when multiple scaaning, the sequential chart of the signal that gate drivers produces.
Fig. 3 is the synoptic diagram of LCD of the present invention.
Fig. 4 is the functional block diagram of the gate drivers of Fig. 3.
Fig. 5 is the sequential chart of each signal of Fig. 4.
Wherein, description of reference numerals is as follows:
10,100 LCD, 12,102 display panels
14a-14c gate drivers 16 source electrode drivers
20 pixels, 22 transistors
24 liquid crystal capacitance G1-G768 sweep traces
104 gate drivers 106a-h source electrode drivers
108 circuit systems, 110 clock circuits
120 data lines, 121,122 shift registers
124 current potential adjustment units, 200 pixels
202 transistors, 204 liquid crystal capacitances
130-1～130-768 logical circuit
Embodiment
See also Fig. 3, Fig. 3 is the synoptic diagram of LCD 100 of the present invention.LCD 100 comprises display panels 102, gate drivers 104, multiple source driver 106 and circuit system 108.Comprise a plurality of pixels 200 on the display panels 102, each pixel 200 includes switching transistor 202 and liquid crystal capacitance 204, be distributed with liquid crystal molecule between the liquid crystal capacitance 204, liquid crystal molecule can be adjusted rotation direction according to the cross-pressure size that is applied to liquid crystal capacitance 204.Circuit system 108 can according to horizontal-drive signal H-Sync and vertical synchronizing signal V-Sync or data enable signal DE produces the first scan line clock YDIOD, the second scan line clock YDIOB, the first sweep trace control signal YOED and the second sweep trace control signal YOEB to gate drivers 104.In addition, comprise clock circuit 110 in the circuit system 108 in addition, be used for clocking YCLK to gate drivers 104.For ease of the explanation, in the present embodiment, the resolution of display panels 102 be 1024 * 768 and renewal frequency be 60Hz, so the demonstration time of each picture is about 1/60=16.67ms.Gate drivers 104 has 768 passage pins, and each passage pin is connected to sweep trace G1-G768.Multiple source driver 106 1 has 1024 passage pins, and each passage pin is connected to data line 120.In the utilization of reality, the usage quantity of gate drivers 104 can be according to the resolution of the number of the passage pin of gate drivers 104 and display panels and is adjusted.For instance, if display panels resolution is 1200 * 800, then need 2 gate drivers just to be enough to connect 800 sweep traces with 512 passage pins.
See also Fig. 3, Fig. 4 and Fig. 5, Fig. 4 is the functional block diagram of the gate drivers 104 of Fig. 3, and Fig. 5 is the sequential chart that respectively transmits online signal of Fig. 4.Gate drivers 104 comprise first shift register (shift register), 121, second shift register 122, a plurality of logical circuit 130-1,130-2 ... 130-768 and current potential adjustment unit 124.Behind the pulsed D A of first scan line clock YDIOD feed-in, first shift register 121, the first grid switching signal (that is pulse E) that first shift register 121 can be exported and the first sweep trace control signal YOED is synchronous is to transmission line R1, so the pulsewidth of the first grid switching signal and the first sweep trace control signal YOED is roughly the same.Next, first shift register 121 can be every the cycle of clock signal YCLK (16.67ms/768=21.7 μ s), in regular turn at the pulse C synchronous pulse E of transmission line R2, R3...R768 output with the first sweep trace control signal YOED.Between a display frame 16.67ms (that is the pulsed D A (or DB) of two scan line clock YDIOD (or YDIOB) be triggered during), suppose the 5.56ms (256 * 21.7 μ s) after transmission line R1 produces pulse E, the pulsed D B of the second scan line clock YDIOB is feed-in second shift register 122 also, at this moment, can produce the second grid switching signal of exporting synchronously with the second sweep trace control signal YOEB (pulse A) (pulse F) on the transmission line B1, so the pulsewidth of the second grid switching signal and the second sweep trace control signal YOEB is roughly the same.And second shift register 122 also can be every the cycle of clock signal YCLK (16.67ms/768=21.7 μ s), in regular turn at the pulse F of the synchronous second grid switching signal of transmission line B2, B3...B768 output and the pulse A of the second sweep trace control signal YOEB.
Logical circuit 130-1 is coupled to transmission line R1, B1 receiving first grid switching signal and second grid switching signal respectively, and selects one as sweep signal and export sweep trace G1 to.Similarly, logical circuit 130-2 is coupled to transmission line R2, B2 to receive first grid switching signal and second grid switching signal respectively, and select the output scanning signal to sweep trace G2, by that analogy, logical circuit 130-768 is coupled to transmission line R768, B768 receiving first grid switching signal and second grid switching signal respectively, and selects the output scanning signal to sweep trace G768.Logical circuit 130-1,130-2..., 130-768 can be OR logic lock or other can carry out the equivalent electrical circuit of OR logical operation.Can notice by Fig. 5, because it is not overlapping that transmission line R1, B1 produce the time of pulse E and pulse F, so after the OR logical operation via logical circuit 130-1, when appearing at transmission line R1 and transmit pulse E, when pulse B appears at transmission line B1 and transmits pulse F by the sweep signal pulsed D of logical circuit 130-1 output.Last sweep signal can be sent to sweep trace G1 after adjusting its current potential sizes via current potential adjustment unit 124 again, makes that the transistor 202 of the pixel 200 on the sweep trace G1 is opened.And liquid crystal capacitance 204 all can be adjusted the arrangement of liquid crystal molecule in this liquid crystal capacitance 204 according to the voltage data signal that source electrode driver 106 sends in the time that this twice pulsed D, B occur, to show different GTGs.Similarly, the function mode of other logical circuit 130-2,130-3..., 130-768 is consistent with logical circuit 130-1, does not repeat them here.
In Fig. 4 and Fig. 5, gate drivers 104 only utilizes two scan line clock YDIOD, YDIOB to control the generation of two sweep trace control signal YOED, YOEB, and each sweep trace can be scanned twice in the demonstration time of same picture to reach.That is to say, each bar sweep trace G1-G768 the pulsed D A of two scan line clock YDIOD (or YDIOB) (or DB) be triggered during in (that is a picture show during) all can export twice sweep signal pulsed D, B.In practical application, gate drivers can also utilize the scan line clock more than three to control three generations with the upper tracer control signal, that is to say, each sweep trace can be scanned more than three times in the demonstration time of same picture.
Compared to prior art, LCD of the present invention is provided with a plurality of logical circuits in gate drivers, make single gate drivers in the demonstration time of same picture, can receive the pulse of different sweep trace control signals simultaneously and export repeatedly sweep signal pulse, make the transistor of pixel of each bar sweep trace that the above opening time be arranged twice, to reach the purpose of multiple scaaning.
Though the present invention with preferred embodiment openly as above; right its is not in order to restriction the present invention; any one of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can doing various changes and modification, so protection scope of the present invention is as the criterion when looking the scope that accompanying Claim defines.
Claims (21)
1. a gate drivers is used for driving display panels, and this gate drivers comprises:
First shift register after triggered by first scan line clock, produces the first grid switching signal according to the first sweep trace control signal;
Second shift register after triggered by second scan line clock, produces the second grid switching signal according to the second sweep trace control signal; And
A plurality of logical circuits are coupled to this first shift register and this second shift register, use from selecting the output scanning signal to drive this display panels among this first grid switching signal and this second grid switching signal;
Wherein, the triggering period of this first sweep trace control signal is different from the triggering period of this second sweep trace control signal.
2. gate drivers as claimed in claim 1, wherein said a plurality of logical circuits are used for this first grid switching signal and this second grid switching signal are carried out the OR logical operation to export this sweep signal.
3. gate drivers as claimed in claim 1, wherein this first shift register and this second shift register are used for respectively producing this first grid switching signal and this second grid switching signal every the cycle of a clock signal respectively according to this first sweep trace control signal and this second sweep trace control signal after this first scan line clock and the triggering of this second scan line clock.
4. gate drivers as claimed in claim 1, it also comprises the current potential adjustment unit, is coupled to described a plurality of logical circuit, is used for adjusting the voltage potential of this sweep signal.
5. LCD, it comprises:
Circuit system, be used for according to vertical synchronizing signal and horizontal-drive signal, produce first scan line clock, second scan line clock, the first sweep trace control signal and the second sweep trace control signal, wherein the triggering period of this first sweep trace control signal is different from the triggering period of this second sweep trace control signal;
Source electrode driver is used for producing voltage data signal;
Gate drivers, it comprises:
First shift register after triggered by this first scan line clock, produces the first grid switching signal according to this first sweep trace control signal;
Second shift register after triggered by this second scan line clock, produces the second grid switching signal according to this second sweep trace control signal; And
A plurality of logical circuits are coupled to this first shift register and this second shift register, use from selecting the output scanning signal among this first grid switching signal and this second grid switching signal; And
A plurality of pixels, each pixel comprises transistor and liquid crystal capacitance, is used for when this sweep signal is opened this transistor, and the voltage data signal that this liquid crystal capacitance produces according to this source electrode driver is adjusted the arrangement of liquid crystal molecule in this liquid crystal capacitance.
6. LCD as claimed in claim 5, wherein said a plurality of logical circuits are used for this first grid switching signal and this second grid switching signal are carried out the OR logical operation to export this sweep signal.
7. LCD as claimed in claim 5, wherein this gate drivers comprises the current potential adjustment unit in addition, is coupled to described a plurality of logical circuit, is used for adjusting the voltage potential of this sweep signal.
8. LCD as claimed in claim 5, wherein the pulsewidth of this first sweep trace control signal is substantially equal to the pulsewidth of this first grid switching signal.
9. LCD as claimed in claim 5, wherein the pulsewidth of this second sweep trace control signal is substantially equal to the pulsewidth of this second grid switching signal.
10. LCD as claimed in claim 5, it also comprises clock generator, be used for clocking, wherein this first shift register and this second shift register are used for respectively producing this first grid switching signal and this second grid switching signal every the cycle of this clock signal respectively according to this first sweep trace control signal and this second sweep trace control signal after this first scan line clock and the triggering of this second scan line clock.
11. the multiple scaaning method of a LCD, it comprises the following step:
(a) according to vertical synchronizing signal and horizontal-drive signal, produce first scan line clock, second scan line clock, the first sweep trace control signal and the second sweep trace control signal, wherein the triggering period of this first sweep trace control signal is different from the triggering period of this second sweep trace control signal;
(b) after this first scan line clock triggers, produce the first grid switching signal according to this first sweep trace control signal;
(c) after this second scan line clock triggers, produce the second grid switching signal according to this second sweep trace control signal;
(d) select the output scanning signal among this first grid switching signal and this second grid switching signal certainly; And
(e) when this sweep signal triggers, according to this voltage data signal display image.
12. multiple scaaning method as claimed in claim 11, wherein step (d) comprises: this first grid switching signal and this second grid switching signal are carried out the OR logical operation to export this sweep signal.
13. multiple scaaning method as claimed in claim 11, wherein the pulsewidth of this first sweep trace control signal is substantially equal to the pulsewidth of this first grid switching signal.
14. multiple scaaning method as claimed in claim 11, wherein the pulsewidth of this second sweep trace control signal is substantially equal to the pulsewidth of this second grid switching signal.
15. multiple scaaning method as claimed in claim 11, wherein step (b) comprises: after this first scan line clock triggers, produce this first grid switching signal every the cycle of a clock signal according to this first sweep trace control signal.
16. multiple scaaning method as claimed in claim 11, wherein step (c) comprises: after this second scan line clock triggers, produce this second grid switching signal every the cycle of a clock signal according to this second sweep trace control signal.
17. a LCD, it comprises:
Circuit system is used for according to vertical synchronizing signal and horizontal-drive signal, produces a plurality of scan line clock and a plurality of sweep trace control signal, the triggering period difference of any two sweep trace control signals of wherein said a plurality of sweep trace control signals;
Source electrode driver is used for outputting data signals voltage;
Gate drivers, it comprises:
A plurality of shift registers, each shift register is coupled to a scan line clock of described a plurality of scan line clock and a sweep trace control signal of described a plurality of sweep trace control signals, be used for when this scan line clock voltage triggered, produce the gate switch signal according to this sweep trace control signal;
A plurality of logical circuits, each logic circuits coupled are used from selection output scanning signal among the gate switch signal of described a plurality of shift registers generations in described a plurality of shift registers; And
A plurality of pixels, each pixel comprises transistor and liquid crystal capacitance, is used for when this sweep signal is opened this transistor, and the voltage data signal that this liquid crystal capacitance produces according to this source electrode driver is adjusted the arrangement of liquid crystal molecule in this liquid crystal capacitance.
18. LCD as claimed in claim 17, wherein said a plurality of logical circuits are used for described a plurality of gate switch signals are carried out the OR logical operation to export this sweep signal.
19. LCD as claimed in claim 17, wherein this gate drivers also comprises the current potential adjustment unit, is coupled to described a plurality of logical circuit, is used for adjusting the voltage potential of this sweep signal.
20. LCD as claimed in claim 17, wherein the pulsewidth of each sweep trace control signal is substantially equal to the pulsewidth of the pairing gate switch signal of described each sweep trace control signal.
21. LCD as claimed in claim 17, it also comprises clock generator, be used for clocking, wherein each shift register is used for producing this gate switch signal every the cycle of this clock signal according to this sweep trace control signal after this scan line clock triggers.
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