CN101334978A - Display device, driving method of the same and electronic equipment incorporating the same - Google Patents
Display device, driving method of the same and electronic equipment incorporating the same Download PDFInfo
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- CN101334978A CN101334978A CNA200810127408XA CN200810127408A CN101334978A CN 101334978 A CN101334978 A CN 101334978A CN A200810127408X A CNA200810127408X A CN A200810127408XA CN 200810127408 A CN200810127408 A CN 200810127408A CN 101334978 A CN101334978 A CN 101334978A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Disclosed herein is a display device including: a pixel section having pixel circuits arranged to form a matrix with at least a plurality of columns, pixel data being written to each of the pixel circuits via a switching element; at least one scan line disposed to be associated with rows of the pixel circuits and adapted to control the conduction of the switching elements; a plurality of signal lines disposed to be associated with columns of the pixel circuits and adapted to convey the pixel data; and a horizontal driving circuit having a plurality of signal drivers, the plurality of signal drivers being associated with a plurality of groups into which the signal lines are divided, and being adapted to convey the image data supplied to the signal lines.
Description
Technical field
The present invention relates to have display device, and relate to its driving method and merged the electronic installation of this display device, and relate to the improvement of signal wire Driving technique particularly as the thin film transistor (TFT) of the on-off element that on the transparent insulation substrate, forms.
Background technology
Using liquid crystal cells is the active matrix image display as the display device of the liquid crystal display (as LCD) of pixel display unit (electrooptic cell).This class display device is designed to show output image via the liquid crystal display surface.
Because having had been found that, their very thin and low-power consumption, liquid crystal display comprising personal digital assistant device (personal digital assistant: PDA), application in the various electronic installations of mobile phone, digital camera, video camera and computer display apparatus.
Incidentally, if the image frame per second is 60Hz or higher, then human eye typically can not the perception screen flicker.
But, in this frequency, but people's perception bluring in moving image and rest image.
For the improvement to this problem is provided, promptly eliminate bluring in the moving image, disclosed as for example opening among the No.2006-78505 (after this being called patent documentation 1) the Jap.P. spy, expect frame rate for four times the 240Hz of 60Hz.
As for the writing mechanism that uses thin film transistor (TFT) (TFT), disclosed display packing uses the pixel that shows in proper order from a left side to write two field picture in 1/240 second in patent documentation 1.Alternatively, display packing writes liquid crystal by shift time and with 1/60 second, carries out with 1/240 second on the surface and refreshes (Figure 21 in the patent documentation 1).
On the other hand, open among the No.Hei 11-338438 (after this being called patent documentation 2) the Jap.P. spy and to disclose a kind of technology, it allows to write video data with the message transmission rate of about 200MHz.
This liquid crystal display is via switch shown in Figure 11 storing one row data in memory circuitry 2.Then, in next line interim, same equipment is selected redness (R) video data from red (R), green (G) and blue (B) video data, and uses switch 4-1 to 4-3 stored video data in memory circuitry 3 simultaneously.
Then, same equipment reads the R data of single driver IC from memory circuitry via switch 5-1 (or 5-2 or 5-3).Switch 5-1 switches with switch 1 to 5-3.Same equipment writes data to driver IC 6-1 (or 6-2 or 6-3), and simultaneously another driver IC is write data.Same equipment writes green (G) and blue (B) video data in the same manner.This permission writes different video-data fragment to each driver IC simultaneously.Display panels 7 comes display video based on the video data that is written into driver IC.
But, the input timing (input method) of image signal data to data line drive circuit do not described in aforementioned patent document 1.Also do not set up concrete data writing system for the picture frame frequency of 240Hz.
On the other hand, in patent documentation 2 disclosed technology with view data synchronously with one another write driver IC 6-1 to 6-3.In addition, it is synchronized with each other to be supplied to the data segment of three driver ICs.
This situation causes the noise of the increase at the front end of view data between adjacent writing and clock or tail end edge, causes the voltage fluctuation of view data and clock signal itself, and makes data and clock instability.
The input of the view data of distortion causes the mistake in the driver IC view data, has reduced picture quality significantly.The wave shaping of being undertaken by buffer circuits produces the waveform that tends to error in data.
Particularly, in the frequency that surpasses 100MHz, the noise in cable or printed panel between the adjacent wiring is almost inevitable.
Nowadays, VGA (800 * 600 pixel) expectation 27MHz and be the clock frequency of 108MHz of four times high frame per second on speed.
In addition, with UVGA (1600 * 1400 pixel), minimum clock frequency is 135MHz.Four times the frequency of 135MHz is 540MHz, and this is that common printed plate is uncontrollable.
This is that the reason that drives is divided in expectation.But, drive the restriction that the scale aspect that is considered to be in panel system is divided in four times or five times.
In this case, owing to the high fdrequency component that causes from the stray capacitance that is suitable between the adjacent wiring of driver IC suppling signal, electromotive force rising (develop).This electromotive force itself shows as the noise in clock and the view data, causes the mistake in clock signal and view data, and finally reduces panel picture quality.
The purpose of embodiments of the invention provides a kind of display device that allows to load the high frequency imaging data and do not reduce picture quality, and its driving method and the electronic installation that has merged this display device are provided.
Summary of the invention
The display device of first pattern comprises pixel portion according to an embodiment of the invention, and this pixel portion has and is arranged the image element circuit that has the matrix of a plurality of at least row with formation.Via on-off element pixel data is write each image element circuit.This display device also comprises at least one sweep trace, and this at least one sweep trace is arranged with the line correlation with described image element circuit and joins, and is suitable for controlling the conducting of described on-off element.Display device also comprises a plurality of signal wires, and these a plurality of signal wires are arranged being associated with the row of described image element circuit, and are suitable for transmitting described pixel data.Display device also comprises the horizontal drive circuit with a plurality of signal drivers.A plurality of groups of being divided into of signal driver and described signal wire are associated, and are suitable for transmitting the view data that is supplied to described signal wire.Each of described a plurality of signal drivers passes to described view data the signal wire that is associated in response to the driving pulse that separates.Be supplied to driving pulse skew mutually on phase place of described signal driver.
Preferably, the adjacent towards each other described signal driver data feed of mode to divide.Also preferably, to present described view data to described signal driver with the synchronous sequential of described driving pulse.
Preferably, display device comprises the multiphase clock Data Generator.Also preferably, this maker is divided the described driving pulse than high usually frequency on frequency, so that to described signal driver supply mutual driving pulse that is offset on phase place.Also preferably, this maker is divided described view data, and the data segment of being divided is rearranged for the data ordering that is suitable for inputing to described signal driver, and supplies these data segments.
Preferably, described multiphase clock Data Generator is respectively to described signal driver supply mutual independently driving pulse that is offset on phase place.Also preferably, described driving pulse each comprise time clock and the beginning pulse.
Preferably, described driving pulse on phase place mutually the time interval Φ of skew be provided so that to satisfy and concern Φ≤(T/2)/N that wherein (T/2) is the half period (period) of image clock, and N is the quantity of frequency division.
Preferably, this display device comprises selector switch, is disposed between each of signal driver and the signal wire that it is associated.Also preferably, described selector switch is suitable for selecting view data with time division way.
The driving method of the display device of second pattern is the driving method of following display device according to an embodiment of the invention, and described display device comprises having and is arranged the pixel portion of image element circuit that has the matrix of a plurality of at least row with formation.Via on-off element pixel data is write each image element circuit.This display device also comprises at least one sweep trace, and this at least one sweep trace is arranged with the line correlation with described image element circuit and joins, and is suitable for controlling the conducting of described on-off element.Display device also comprises a plurality of signal wires, and these a plurality of signal wires are arranged being associated with the row of described image element circuit, and are suitable for transmitting described pixel data.Display device also comprises the horizontal drive circuit with a plurality of signal drivers.A plurality of groups of being divided into of signal driver and described signal wire are associated, and are suitable for transmitting the view data that is supplied to described signal wire.Described driving method makes each signal driver described view data be passed to the signal wire that is associated in response to the driving pulse that is received to the driving pulse of a plurality of signal driver supplies separation of mutual skew on phase place.
The three-mode of embodiments of the invention is electronic installations of having incorporated display device into.Display device comprises pixel portion, and this pixel portion has and is arranged the image element circuit that has the matrix of a plurality of at least row with formation.Via on-off element pixel data is write each image element circuit.This display device also comprises at least one sweep trace, and this at least one sweep trace is arranged with the line correlation with described image element circuit and joins, and is suitable for controlling the conducting of described on-off element.Display device also comprises a plurality of signal wires, and these a plurality of signal wires are arranged being associated with the row of described image element circuit, and are suitable for transmitting described pixel data.Display device also comprises the horizontal drive circuit with a plurality of signal drivers.A plurality of groups of being divided into of signal driver and described signal wire are associated, and are suitable for transmitting the view data that is supplied to described signal wire.Each of described a plurality of signal drivers passes to described view data the signal wire that is associated in response to the driving pulse that separates.Be supplied to driving pulse skew mutually on phase place of described signal driver.
Embodiments of the invention are to the driving pulse of a plurality of signal driver supplies separation of mutual skew on phase place.
Each of signal driver transmitted view data in response to the driving pulse that is received to signal wire.
Description of drawings
Fig. 1 has described the figure that allows to write with the message transmission rate of about 200MHz the prior art of video data;
Fig. 2 is the figure of diagram as the example of the driving pulse of signal driver comparative example of the present invention, that be supplied to typical horizontal drive circuit;
Fig. 3 is the figure that has described the problem of the driving pulse among Fig. 2;
Fig. 4 illustrates the calcspar of the configuration example of liquid crystal display according to an embodiment of the invention;
Fig. 5 is the oscillogram that is shown in the relation between output enable signal and the strobe pulse;
Fig. 6 is the figure of example of the driving pulse of the diagram signal driver that is supplied to horizontal drive circuit;
Fig. 7 is the figure of diagram according to the concrete configuration example of the multiphase clock Data Generator of present embodiment;
Fig. 8 is the figure that describes the example that writes according to present embodiment, the data of being undertaken by the multiphase clock Data Generator after sequential control and frequency partition;
Fig. 9 is the figure that describes the effect of present embodiment;
Figure 10 is the calcspar of diagram according to the configuration example of the liquid crystal display of the embodiments of the invention of dividing switch service time; And
Figure 11 A is the view of diagram use according to the example of the electronic installation of the display device of present embodiment to 11G.
Embodiment
The multiplexing control clock of embodiments of the invention, as the beginning pulse and the view data of synchronizing signal, and generate the leggy pulse, therefore allow to load the high frequency imaging data in the mode that does not reduce picture quality.
To before describing embodiments of the invention, typical horizontal drive circuit be described.
Fig. 2 is the figure of diagram as the example of the driving pulse of signal driver comparative example of the present invention, that be supplied to typical horizontal drive circuit 130.In this case, signal driver is divided into four horizontal viewing areas, presents view data with the frequency of four times (four-fold).
In this embodiment, as shown in Figure 2, come the load image signal data by single control clock.As a result, signal driver must the processing controls clock, as with the input pulse of the data frequency of moving image clock synchronization.
Show that to realize high frame per second view data can not be fed to liquid crystal display with quadruple rate input image data even attempt in this case.Its reason is, the impedance that the responding ability of signal driver IC and being suitable for is transmitted the cable of view data is not suitable for high frequency.
In addition, as shown in Figure 3, the noise that is caused by the interference that obtains from the stray capacitance between the signal wire of high frequency influences time clock itself and view data unfriendly, may make display image correctly.
That is, the data segment that is supplied to driver IC is a homophase each other.This situation has caused the noise NTS of the increase of the front end of view data between adjacent writing and clock or tail end edge, causes the voltage fluctuation of view data and clock signal itself, and makes data and jitter.In the example depicted in fig. 3, the electromotive force of the noise NIS in horizontal time clock HCK1, HCK2, HCK3 and HCK4 increases jointly, shown in the Reference numeral X among Fig. 3 for example.From synchronizing signal, derive time clock HCK1, HCK2, HCK3 and HCK4.Should be noted that by the normal waveform that is shown in dotted line view data IMD among Fig. 3, and error section is shown by the solid line among Fig. 3.
As solution, need to reduce being supplied to the frequency of signal driver and the phase place of offset clocks pulse HCK1, HCK2, HCK3 and HCK4, so that prevent noise rise to this problem.Mention that along band in VGA, at the frame rate of 60Hz, clock frequency is 27MHz, and when four frame doubling frequencies of 240Hz, clock frequency is 108MHz.
In order to address the above problem, the multiplexing control clock of present embodiment, as the beginning pulse and the view data of synchronizing signal, and generate the leggy pulse, therefore allow to load above-mentioned high frequency imaging data.
Describe present embodiment in detail below with reference to accompanying drawing.
Fig. 4 illustrates the calcspar of the configuration example of liquid crystal display according to an embodiment of the invention.
Each of image element circuit 111 comprises thin film transistor (TFT) (TFT) 112, the liquid crystal cells 113 as on-off element and keeps electric capacity (memory capacitance) 114.Liquid crystal cells 113 has its pixel electrode of drain electrode (or source electrode) electrode that is connected in TFT 112.Keep electric capacity 114 to have one of its electrode of the drain electrode that is connected in TFT 112.
For every row of image element circuit 111, arrange that along same circuits 111 gating (gate) (scanning) line 115-1 is to one of 115-m.For every row of image element circuit 111, arrange that along same circuits 111 signal wire 116-1 is to one of 116-n.
The TFT 112 of the image element circuit 111 in every row has its gate electrode that is connected in same gating (scanning) line (115-1 is to one of 115-m).The TFT 112 of the image element circuit 111 in every row has its source electrode (or drain electrode) electrode that is connected in same signal wire (116-1 is to one of 116-n).
In addition, liquid crystal cells 113 has its pixel electrode and its reverse electrode that is connected in bridging line 117 of the drain electrode that is connected in TFT 112.Keep electric capacity 114 to be connected between the drain electrode and bridging line 117 of TFT 112.
Apply given AC voltage as common voltage Vcom from unshowned VCOM circuit to bridging line 117, this VCOM circuit is formed integrally as on glass substrate with driving and other circuit.
Each of image element circuit 111 writes pixel data via the TFT 112 as on-off element to maintenance electric capacity 114.By modulating liquid crystal cells 113 based on the voltage that is written into the pixel data that keeps electric capacity 114.Liquid crystal display 100 comes display image by the visibility (transmittance) that the light of a pair of unshowned polarizer is passed in control, should be to front that is disposed in liquid crystal cells 113 of unshowned polarizer, another is disposed in the back side of liquid crystal cells 113.
Select lines 115-1 is driven by vertical drive circuit 120 to 115-m.Signal wire 116-1 is driven by horizontal drive circuit 130A to 116-n.
In response to vertical commencing signal VST, vertical clock VCK and enable signal ENAB, vertical drive circuit 120 vertically scans at each interval and is connected in the image element circuit 111 of sweep trace 115-1 to 115-m, sequentially selects same circuit 111 based on coming line by line.
That is, when by vertical drive circuit 120 when select lines 115-1 applies strobe pulse GP1, be chosen in first the row in pixel.When select lines 115-2 applies scanning impulse GP2, be chosen in the pixel in second row.Similarly, apply strobe pulse GP3 to GPm to select lines 115-3 to 115-m respectively.
Should be noted that by unshowned second time schedule controller different with the time schedule controller of multiphase clock Data Generator 140, that separate and generate vertical commencing signal VST, vertical clock VCK and enable signal ENAB.
Second time schedule controller be supplied to multiphase clock Data Generator 140, synchronously operate as the horizontal signal of hst, hck1, hck2, hck3, hck4 and data d0.
Fig. 6 illustrates the example of the driving pulse of the signal driver 131 to 134 that is supplied to horizontal drive circuit 130A.
In the present embodiment, discretely to signal driver 131 to 134 supply driving pulses.Each driving pulse comprises that level begins pulse HST and horizontal time clock HCK.Level begins the beginning that pulse HST is used to commanded level scanning.Horizontal time clock HCK is as the reference of horizontal scanning.
The level that is supplied to signal driver 132 begins pulse HST2, begins pulse HST1 from the level that is supplied to signal driver 131, the clock period of skew (delay) 1/4 on phase place.
Similarly, the level that is supplied to signal driver 133 begins pulse HST3, begins pulse HST2 from the level that is supplied to signal driver 132, the clock period of skew (delay) 1/4 on phase place.
The level that is supplied to signal driver 134 begins pulse HST4, begins pulse HST3 from the level that is supplied to signal driver 133, the clock period of skew (delay) 1/4 on phase place.
Be supplied to the horizontal time clock HCK2 of signal driver 132, from being supplied to the horizontal time clock HCK1 of signal driver 131, the clock period of skew (delay) 1/4 on phase place.
Similarly, be supplied to the horizontal time clock HCK3 of signal driver 133, from being supplied to the horizontal time clock HCK2 of signal driver 132, the clock period of skew (delay) 1/4 on phase place.
Be supplied to the horizontal time clock HCK4 of signal driver 134, from being supplied to the horizontal time clock HCK3 of signal driver 133, the clock period of skew (delay) 1/4 on phase place.
In the example shown in Fig. 4 and 6, signal driver 131 begins pulse HST1 and as the horizontal time clock HCK1 of the reference of horizontal scanning, generates sampling pulse in response to the level of the beginning that is suitable for commanded level scanning.Begin pulse HST1 and horizontal time clock HCK1 from multiphase clock Data Generator 140 levels of supply.
As mentioned above, present embodiment is divided in horizontal drive circuit 130A a plurality of groups with a plurality of signal wires.One of a plurality of (in the present embodiment four) signal driver 131 to 134 is provided for each group of signal wire, to transmit view data.
Offset level begins pulse HST1, HST2, HST3 and HST4 and horizontal time clock HCK1, HCK2, HCK3 and HCK4 mutually on phase place.These pulses are as the driving pulse of the driving that is suitable for controlling a plurality of signal drivers 131 to 134.
More specifically, adjacent towards each other signal driver 131 to 134 data feeds of mode to divide.
Begin pulse HST1 by level and come control signal drivers 131 to 134 to HCK4 to HST4 and horizontal time clock HCK1 with phase place independent of each other.To present view data with the sequential of clock independently and beginning impulsive synchronization.
That is, shown in Fig. 4 and 6, by on phase place at random offset level begin pulse HST and horizontal time clock HCK (be offset in the present embodiment 1/4 clock period) and come operation signal driver 131 to 134.OTEN synchronously exports the final image signal with the output enable signal.
This makes and may come the drive device with the frequency that is lower than original frequency with time clock, beginning pulse and view data.
To be described as driving as described above in the present embodiment where the reason of horizontal drive circuit 130A below.
If the image frame per second is 60Hz or higher, then typically can not be by the flicker of human eye perception screen.
But, in this frequency, but bluring in people's perceive motion image and the rest image.
For the improvement to this problem is provided, the frame rate of expectation 240Hz is eliminated bluring in moving image.
Therefore, if nowadays active matrix display device has the problem relevant with its moving image characteristic, then, improve this specific character by using than the number of frames of four times high usually per second demonstration and to come display image than common four times high frame rate.Common frame rate is 60Hz.Therefore, four frame doubling frequencies are 240Hz.
Usually, clock frequency is 135MHz in UXGA (1600 * RGB * 1200).Common silicon IC can be in this frequencies operations.
But if frame rate is four times big, then clock frequency is 540MHz.Silicon IC is difficult in this high frequencies of operation.
In addition, the picture signal that generates in this frequency may be owing to the interference between signal wiring is not easy to pass to liquid crystal apparatus via cable.Must reduce frequency and overcome the problems referred to above.
Present embodiment can keep the view data clock, and the frequency of minimizing is provided simultaneously.
Below multiphase clock Data Generator 140 will be described.
Multiphase clock Data Generator 140 reception levels begin pulse hst and horizontal time clock hck1 to hck4, and these pulses are divided into 1/4 frequency.For example to begin pulse hst and horizontal time clock hck1 to hck4 from unshowned pattern I C level of supply than usually high quadruple rate.
Multiphase clock Data Generator 140 is supplied the level that produces to the signal driver 131 of horizontal drive circuit 130A and is begun pulse HST1 and horizontal time clock HCK1 from frequency partition.Begin pulse HST1 from level, on phase place, horizontal time clock HCK1 is offset the clock period of (delay) 1/4.
In addition, 140 generations of multiphase clock Data Generator begin the level of pulse HST1 in the clock period of phase place skew (delay) 1/4 from level and begin pulse HST2.Same maker 140 is supplied the level that produces to the signal driver 132 of horizontal drive circuit 130A and is begun pulse HST2 and horizontal time clock HCK2 from frequency partition.Begin pulse HST2 from level, on phase place, horizontal time clock HCK2 is offset the clock period of (delay) 1/4.
In addition, 140 generations of multiphase clock Data Generator begin the level of pulse HST2 in the clock period of phase place skew (delay) 1/4 from level and begin pulse HST3.Same maker 140 is supplied the level that produces to the signal driver 133 of horizontal drive circuit 130A and is begun pulse HST3 and horizontal time clock HCK3 from frequency partition.Begin pulse HST3 from level, on phase place, horizontal time clock HCK3 is offset the clock period of (delay) 1/4.
In addition, 140 generations of multiphase clock Data Generator begin the level of pulse HST3 in the clock period of phase place skew (delay) 1/4 from level and begin pulse HST4.Same maker 140 is supplied the level that produces to the signal driver 134 of horizontal drive circuit 130A and is begun pulse HST4 and horizontal time clock HCK4 from frequency partition.Begin pulse HST4 from level, on phase place, horizontal time clock HCK4 is offset the clock period of (delay) 1/4.
Should be noted that time clock on phase place mutually the time interval Φ of skew be provided so that to satisfy and concern Φ≤(T/2)/N, wherein (T/2) is the half period of image clock, N is the quantity of frequency partition.
In addition, multiphase clock Data Generator 140 is aligned to the view data d0 that is supplied in the line buffer.Then, same maker 140 will be through frequency partition and be arranged on view data in the line storage impact damper and rearrange in a plurality of (in the present embodiment four) independent of each other line storage impact damper, then from each line storage buffer circuits to the signal driver supply data.
Fig. 7 is the figure of diagram according to the concrete configuration example of the multiphase clock Data Generator 140 of present embodiment.
Fig. 8 is the figure that describes according to example present embodiment, that write in sequential control and the data after the frequency partition by the multiphase clock Data Generator.
Multiphase clock Data Generator 140 comprises time schedule controller (TC) 141, data-carrier store buffer count device 142, the first counter triggers device (CNT/FF) 143, the 2nd CNT/FF 144, the 3rd CNT/FF 145 and the 4th CNT/FF 146.
Begin pulse hst1 and horizontal time clock hck1 to hck4 in response to the level than usually high quadruple rate of being in, time schedule controller 141 is supplied trigger point signal a1 to a4 to first to the 4th CNT/FF 143 to 146.Trigger point signal a1 is offset Φ mutually to a4 on phase place.
More specifically, time schedule controller 141 is to a CNT/FF 143 supply trigger point signal a1.Same controller 141 plays the trigger point signal a2 that has been offset Φ on phase place to the 2nd CNT/FF 144 supply slave flipflop point signal a1.
In addition, same controller 141 plays the trigger point signal a3 that has been offset Φ on phase place to the 3rd CNT/FF 145 supply slave flipflop point signal a2.Same controller 141 plays the trigger point signal a4 that has been offset Φ on phase place to the 4th CNT/FF 146 supply slave flipflop point signal a3.
In addition, begin pulse hst1 and horizontal time clock hck1 to hck4 in response to the level than usually high quadruple rate of being in, time schedule controller 141 is supplied trigger point signal b1 to b4 to data-carrier store buffer count device 142.Trigger point signal b1 is offset Φ mutually to b4 on phase place.
More specifically, time schedule controller 141 is to data-carrier store buffer count device 142 supply trigger point signal b1 and b2.With trigger point signal b2 slave flipflop point signal b1 skew Φ on phase place.
In addition, same controller 141 is to data-carrier store buffer count device 142 supply trigger point signal b3 and b4.With trigger point signal b3 slave flipflop point signal b2 skew Φ on phase place.With trigger point signal b4 slave flipflop point signal b3 skew Φ on phase place.
Should be noted that time schedule controller 141 generate trigger point signal a1 to a4 and b1 to b4, feasible each signal of synchronously keeping mutually.
The output enable signal OTEN that time schedule controller 141 generates as the horizontal interval control signal, and to horizontal drive circuit 130A and vertical drive circuit output signal.
In response to input data d0, synchronously the cycle of growth data d0 is four times to data-carrier store buffer count device 142 to b4 with trigger point signal b1 from time schedule controller 141.Same counter 142 is rearranged for data segment D1, D2, D3, D4 or the like with data d0, and exports these data segments.These data segments D1, D2, D3, D4 or the like are offset on phase place mutually.Data segment D1, the D2 that rearranges, D3, D4 or the like are made up of R (redness), G (green) and B (blueness) data.
The one CNT/FF 143 begins pulse hst and horizontal time clock hck1 in response to trigger point signal a1 division level on frequency.
The one CNT/FF 143 begins pulse HST1 and horizontal time clock HCK1 to signal driver 131 supplies of horizontal drive circuit 130A by the level that frequency partition produces.Horizontal time clock HCK1 is begun the clock period of pulse HST1 skew (delay) 1/4 from level on phase place.
The 2nd CNT/FF 144 begins pulse hst and horizontal time clock hck2 in response to trigger point signal a2 division level on frequency.The 2nd CNT/FF 144 also is created on the phase place and begins the level of the clock period of pulse HST1 skew (delay) 1/4 from level and begin pulse HST2.
The 2nd CNT/FF 144 begins pulse HST2 and horizontal time clock HCK2 to signal driver 132 levels of supply of horizontal drive circuit 130A.The clock period that will on phase place, begin pulse HST2 skew (delay) 1/4 by the horizontal time clock HCK2 that frequency partition produces from level.
The 3rd CNT/FF 145 begins pulse hst and horizontal time clock hck3 in response to trigger point signal a3 division level on frequency.The 3rd CNT/FF 145 also is created on the phase place and begins the level of the clock period of pulse HST2 skew (delay) 1/4 from level and begin pulse HST3.
The 3rd CNT/FF 145 begins pulse HST3 and horizontal time clock HCK3 to signal driver 133 levels of supply of horizontal drive circuit 130A.The clock period that will on phase place, begin pulse HST3 skew (delay) 1/4 by the horizontal time clock HCK3 that frequency partition produces from level.
The 4th CNT/FF 146 begins pulse hst and horizontal time clock hck4 in response to trigger point signal a4 division level on frequency.The 4th CNT/FF 146 also is created on the phase place and begins the level of the clock period of pulse HST3 skew (delay) 1/4 from level and begin pulse HST4.
The 4th CNT/FF 146 begins pulse HST4 and horizontal time clock HCK4 to signal driver 134 levels of supply of horizontal drive circuit 130A.The clock period that will on phase place, begin pulse HST4 skew (delay) 1/4 by the horizontal time clock HCK4 that frequency partition produces from level.
As mentioned above, for the high frame per second with four times is come display image, multiphase clock Data Generator 140 receives the horizontal time clock hck1 that is in than high usually quadruple rate and begins pulse hst to hck4 with horizontal time clock hck1 to the synchronous horizontal drive of hck4, as shown in Figure 8.
At this, show output and input data break in a horizontal interval.These allow the processing of data at interval.
At this, T represents the cycle as the horizontal time clock HCK of the control clock of signal driver (IC), T1 is the data break in a horizontal interval after frequency partition is 1/4 frequency, and T2 is the data break in a horizontal interval, and T3 is a horizontal interval.
Following relationship is present between the above-mentioned interval.
T3≥T1≥T2
That is, the data break T1 after frequency partition is 1/4 frequency in a horizontal interval is longer than the raw data interval T 2 in a high-frequency horizontal interval before frequency partition is 1/4 frequency, but is shorter than horizontal interval T3.
This relation must be satisfied to satisfy the sequential chart of the distinctiveness function that present embodiment is provided.
In addition, shown in Fig. 7 and 8, the level that CNT/FF independent of each other 143 to 146 generates mutually on phase place skew and is supplied to the signal driver 131 to 134 of present embodiment begin pulse HST1 to HST4 and horizontal time clock HCK1 to HCK4.
As the beginning pulse hst of synchronizing signal and image clock pulse hck is fed to CNT/FF 143 to 146 from original video source each.
These pulses are divided on frequency under the control of time schedule controller 141.In addition, the view data d0 that is fed simultaneously also is divided on frequency, and is arranged in the data-carrier store buffer count device 142.Then, view data d0 be rearranged four independently data segment D1 in D4.
As a result, CNT/FF 143 to 146, and storage buffer 143 to 146 at once, can independently export to the signal driver supply.
In addition, can use frequency-dividing clock offset data on phase place according to the frequency of being divided.
As mentioned above and shown in the reference marker Y among Fig. 9, horizontal time clock HCK1 on phase place from horizontal time clock HCK2 skew.As a result, horizontal time clock HCK1 only is subjected to the noise NIS influence of horizontal time clock HCK2.
Similarly, horizontal time clock HCK2 is influenced by the noise NIS of horizontal time clock HCK3 only.
That is, the noise still less that obtains from the stack of the electromotive force of horizontal time clock HCK1, the HCK2, HCK3 and the HCK4 that cause by synchronizing signal will be had.
Therefore, by the view data IMD after the unshowned buffer circuits shaping of signal driver 131 to 134, present and the irrelevant normal square waveform of error section shown in the reference marker Z among Fig. 9.
The half period that the time interval Φ that time clock is offset on phase place mutually equals image clock divided by divider ratio N (for integer) or still less.
This relation can be represented as Φ≤(T/2)/N.
Below with reference to Fig. 4 and 8 operation of the liquid crystal display 100 of configuration is as mentioned above described.
As shown in Figure 4, vertical drive circuit 120 is in response to vertical commencing signal VST, vertical clock VCK and enable signal ENAB shown in Figure 4, based on sequentially selecting image element circuit 111 line by line.In response to each signal, vertical drive circuit 120 vertically scans at each interval and is connected to the image element circuit 111 of sweep trace 115-1 to 115-m, based on sequentially selecting same circuit 111 line by line.
Multiphase clock Data Generator 140 reception levels begin pulse hst and horizontal time clock hck1 to hck4, and these pulses are divided into 1/4 frequency.From unshowned pattern I C, for example to come level of supply to begin pulse hst and horizontal time clock hck1 to hck4 than common high quadruple rate.
Multiphase clock Data Generator 140 begins pulse HST1 and horizontal time clock HCK1 to signal driver 131 supplies of horizontal drive circuit 130A by the level that frequency partition produces.Horizontal time clock HCK1 is begun the clock period of pulse HST1 skew (delay) 1/4 from level on phase place.
Similarly, multiphase clock Data Generator 140 is created on the phase place and begins the level of the clock period of pulse HST1 skew (delay) 1/4 from level and begin pulse HST2.
In addition, multiphase clock Data Generator 140 is created on the phase place and begins the level of the clock period of pulse HST2 skew (delay) 1/4 from level and begin pulse HST3.
In addition, multiphase clock Data Generator 140 is created on the phase place and begins the level of the clock period of pulse HST3 skew (delay) 1/4 from level and begin pulse HST4.
In addition, multiphase clock Data Generator 140 is aligned to the view data d0 that is supplied in the line buffer.Then, same maker 140 will pass through frequency partition and the view data that is arranged in the line storage impact damper rearranges in separate a plurality of (being four in the present embodiment) line storage impact damper, then from each line storage buffer circuits (Fig. 8) to the signal driver supply data.
In addition, signal driver 131 is in response to the sampling pulse that is generated sequentially sample input image data R (redness), G (green) and B (blueness).
Similarly, signal driver 132 begins pulse HST2 and generates sampling pulse as the horizontal time clock HCK2 of the reference of horizontal scanning in response to the level of the beginning that is suitable for commanded level scanning.Begin pulse HST1 and horizontal time clock HCK1 offset level on phase place begins pulse HST2 and horizontal time clock HCK2 from level respectively.
In addition, signal driver 132 is in response to the sampling pulse that is generated sequentially sample input image data R (redness), G (green) and B (blueness).
In addition, signal driver 133 is in response to the sampling pulse that is generated sequentially sample input image data R (redness), G (green) and B (blueness).
In addition, signal driver 134 is in response to the sampling pulse that is generated sequentially sample input image data R (redness), G (green) and B (blueness).
Should be noted that vertical drive circuit 120 can change into passive low level falling edge output strobe at same signal OTEN from active high level in response to output enable signal OTEN.Same signal OTEN makes that horizontal drive circuit 130A can be to signal wire 116-1 to the 116-n output data.
As mentioned above, present embodiment is divided into a plurality of groups with a plurality of signal wires.For each group, provide one of a plurality of signal drivers 131 to 134 that are suitable for transmitting the view data that is supplied to signal wire
Offset level begins pulse HST1, HST2, HST3 and HST4 and horizontal time clock HCK1, HCK2, HCK3 and HCK4 mutually on phase place.These pulses are as the driving pulse of the driving that is suitable for controlling a plurality of signal drivers 131 to 134.
Begin pulse HST1 by horizontal time clock HCK1 to HCK4 and level and come control signal drivers 131 to 134 to HST4 with phase place independent of each other.To present view data with the sequential of clock independently and beginning impulsive synchronization.
In the present embodiment, by on phase place at random offset level begin pulse HST and horizontal time clock HCK comes operation signal driver 131 to 134.OTEN synchronously exports the final image signal with the output enable signal.
This makes and may come the drive device with the frequency that is lower than original frequency with time clock, beginning pulse and view data.
Therefore, can transmit high-definition picture with high speed, and without any image quality degradation.
In addition, than the image of existing frame rate, high frame rate image provides the significantly improved moving image characteristic of display device, has therefore eliminated picture roll (rolling).
In addition, can use picture signal driver, therefore allow to make display device with low cost in common clock frequency operation.Do not need to use custom-designed high speed image signal driver.
Should be noted that when with time division way when panel writes view data, embodiments of the invention are also effective.When using time-division switching as shown in figure 10, particularly can not sufficiently satisfy under the electronics and the situation of picture characteristics of level in selecting at interval in the quantity of time-division, the embodiment of the invention also can be used.
In this case, as mentioned above, signal driver is divided the incoming frequency of time clock (gating pulse), beginning pulse and view data.
In Figure 10, send signal SV to signal wire 116 (116-1 is to 116-12) from signal driver 131 to 134 via each selector switch SEL with a plurality of transmission gates (gate) TMG.
By selecting signal S1, its reverse signal XS1, select signal S2, its reverse signal XS2, selecting signal S3, its reverse signal XS3 or the like control transmission gate TMG (analog switch) conducting.
As mentioned above, high resolving power (UXGA) and high frame per second active matrix display device can use the selector switch time-division to drive, and it guarantees the quantity of minimizing of link and the improved reliability on mechanical connection.
Should be noted that CMOS signaling, LVDS (low voltage difference signaling (Low Voltage DifferentialSignaling)) or TMDS (transformation minimizes difference signaling (Transition Minimized DifferentialSignaling)) can be used to transmit the numerical data of using in the present embodiment.These transfer mechanisms are used in the input and output side of multiphase clock Data Generator 140.
Active matrix display device and typical active matrix liquid crystal display device are used as the display as the OA device of personal computer and word processor and televisor.In addition, this display device be especially suitable for use as its main body become more and more littler and compact, as the display part of the electronic installation of mobile phone and PDA.
That is, the liquid crystal display 100 according to present embodiment can be applicable to Figure 11 A to the various electronic installations shown in the 11G.
For example, same equipment 100 can be used as the display device of the electronic installation (comprising digital camera, laptop PC, mobile phone and portable video recorder) of crossing over all spectra.The device of these classes is designed to show the image or the video of the vision signal that is fed to electronic installation or generates in electronic installation inside.
The example of the applied above-mentioned electronic installation of embodiments of the invention will be shown below.
The applied televisor 300 of Figure 11 A diagram embodiments of the invention as an example.Televisor 300 comprises the video display screen curtain of being made up of for example front panel 301, filter glass 302 and other parts 303.Make televisor by using according to an embodiment of the invention display device as video display screen curtain 303.
Figure 11 B and the applied digital camera 310 of 11C diagram embodiments of the invention are as an example.Digital camera 310 comprises imaging lens 311, flash of light part 312, display part 313, gauge tap 314 and other parts.Make digital camera by using according to an embodiment of the invention display device as display part 313.
The applied portable video recorder 320 of Figure 11 D diagram embodiments of the invention.Portable video recorder 320 comprises that main part 321, being used for of providing on the side surface in front carry out imaging to object camera lens 322, imaging begins/shutdown switch 323, display part 324 and other parts.Make portable video recorder by using according to an embodiment of the invention display device as display part 324.
Figure 11 E and the applied mobile terminal device 330 of 11F diagram embodiments of the invention.Mobile terminal device 330 comprises upper case 331, lower case 332, coupling part (hinge fraction in this embodiment) 333, display 334, sub-display 335, picture lamp 336, camera 337 and other parts.Make mobile terminal device by using according to an embodiment of the invention display device as display 334 and sub-display 335.
The applied laptop PC 340 of Figure 11 G diagram embodiments of the invention.Laptop PC 340 comprises main body 341, is suitable for being handled the keyboard 342 with input text or other information, the display part 343 that is suitable for display image and other parts.Make laptop PC by using according to an embodiment of the invention display device as display part 343.
Should be noted that by the situation that adopts embodiments of the invention to be applied to active liquid crystal display and described the foregoing description as an example.But embodiments of the invention are not limited thereto, and can be applied to similarly as using EL element other active matrix display devices as electroluminescence (EL) display device of the electrooptic cell of each pixel.
It should be appreciated by those skilled in the art that in the scope of claim or its equivalent, can need to carry out various modifications, combination, sub-portfolio and change based on design with other factors.
The cross reference of related application
The present invention comprises the theme that is involved in the Japanese patent application JP2008-119201 that submits to Jap.P. office in the Japanese patent application JP 2007-171691 that submitted to Jap.P. office on June 29th, 2007 and on April 30th, 2008, and its full content is incorporated at this by reference.
Claims (11)
1. display device comprises:
Pixel portion has and is arranged the image element circuit that has the matrix of a plurality of at least row with formation, via on-off element pixel data is write each image element circuit;
At least one sweep trace, be arranged with each line correlation connection of described image element circuit, and be suitable for controlling the conducting of described on-off element;
A plurality of signal wires are arranged to be associated with each row of described image element circuit, and are suitable for transmitting described pixel data; And
A plurality of groups of being divided into of horizontal drive circuit with a plurality of signal drivers, described a plurality of signal drivers and described signal wire are associated, and are suitable for transmitting the view data that is supplied to described signal wire, wherein
Each of described a plurality of signal drivers in response to the driving pulse that separates with described view data
Pass to the signal wire that is associated, and
Be supplied to driving pulse skew mutually on phase place of described signal driver.
2. display device according to claim 1, wherein
With the adjacent towards each other described signal driver data feed of dividing of mode, and
To present described view data to described signal driver with the synchronous sequential of described driving pulse.
3. display device according to claim 1 comprises:
The multiphase clock Data Generator, be suitable on frequency, dividing described driving pulse than high usually frequency, so that driving pulse to described signal driver supply mutual skew on phase place, described multiphase clock Data Generator also is suitable for dividing described view data, the data segment of being divided is rearranged for the data ordering that is suitable for inputing to described signal driver, and supplies these data segments.
4. display device according to claim 2 comprises:
The multiphase clock Data Generator, be suitable on frequency, dividing described driving pulse than high usually frequency, so that driving pulse to described signal driver supply mutual skew on phase place, described multiphase clock Data Generator also is suitable for dividing described view data, the data segment of being divided is rearranged for the data ordering that is suitable for inputing to described signal driver, and supplies these data segments.
5. display device according to claim 3, wherein
The independently driving pulse that described multiphase clock Data Generator is offset on phase place mutually to described signal driver supply respectively, and
Each comprises time clock and beginning pulse described driving pulse.
6. display device according to claim 4, wherein
The independently driving pulse that the multiphase clock Data Generator is offset on phase place mutually to described signal driver supply respectively, and
Each comprises time clock and beginning pulse described driving pulse.
7. display device according to claim 4, wherein
Described driving pulse on phase place mutually the time interval Φ of skew be provided so that to satisfy and concern Φ≤(T/2)/N that wherein (T/2) is the half period of image clock, and N is the quantity of frequency partition.
8. display device according to claim 6, wherein
Described driving pulse on phase place mutually the time interval Φ of skew be provided so that to satisfy and concern Φ≤(T/2)/N that wherein (T/2) is the half period of image clock, and N is the quantity of frequency partition.
9. according to each described display device of claim 1, comprising:
Selector switch is disposed between each of signal driver and the signal wire that it is associated, and described selector switch is suitable for selecting view data with time division way.
10. the driving method of a display device comprises step:
Layout has and is arranged the pixel portion of image element circuit that has the matrix of a plurality of at least row with formation, via on-off element pixel data is write each image element circuit;
Arrange that at least one sweep trace joins with each line correlation with described image element circuit, and be suitable for controlling the conducting of described on-off element;
Arrange that a plurality of signal wires to be associated with each row of described image element circuit, and are suitable for transmitting described pixel data;
Layout has the horizontal drive circuit of a plurality of signal drivers, and a plurality of groups of being divided into of described a plurality of signal drivers and described signal wire are associated, and are suitable for transmitting the view data that is supplied to described signal wire;
Respectively to described signal driver supply mutual independently driving pulse that is offset on phase place; And
Make each signal driver described view data be passed to the signal wire that is associated in response to the driving pulse that is received.
11. the electronic installation with display device, described display device comprises:
Pixel portion has and is arranged the image element circuit that has the matrix of a plurality of at least row with formation, via on-off element pixel data is write each image element circuit;
At least one sweep trace, be arranged with each line correlation connection of described image element circuit, and be suitable for controlling the conducting of described on-off element;
A plurality of signal wires are arranged to be associated with each row of described image element circuit, and are suitable for transmitting described pixel data; And
Horizontal drive circuit has a plurality of signal drivers, and a plurality of groups of being divided into of described a plurality of signal drivers and described signal wire are associated, and are suitable for transmitting the view data that is supplied to described signal wire, wherein
Each of described a plurality of signal drivers passes to the signal wire that is associated in response to the driving pulse that separates with described view data, and
Be supplied to driving pulse skew mutually on phase place of described signal driver.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007171691 | 2007-06-29 | ||
| JP171691/07 | 2007-06-29 | ||
| JP119201/08 | 2008-04-30 |
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| CN101334978A true CN101334978A (en) | 2008-12-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA200810127408XA Pending CN101334978A (en) | 2007-06-29 | 2008-06-30 | Display device, driving method of the same and electronic equipment incorporating the same |
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| JP (2) | JP2009031751A (en) |
| KR (1) | KR101475389B1 (en) |
| CN (1) | CN101334978A (en) |
| TW (1) | TWI396167B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034416A (en) * | 2009-10-06 | 2011-04-27 | 三星电子株式会社 | Electronic device, display device and method of controlling the display device |
| US9922598B2 (en) | 2014-12-24 | 2018-03-20 | Lg Display Co., Ltd. | Organic light emitting diode display and method for sensing characteristic thereof |
| CN108335674A (en) * | 2013-02-04 | 2018-07-27 | 索尼半导体解决方案公司 | Display device |
| CN114339100A (en) * | 2020-09-29 | 2022-04-12 | 豪威科技股份有限公司 | Switching technique for fast voltage stabilization in image sensors |
| CN115428064A (en) * | 2020-04-24 | 2022-12-02 | 京瓷株式会社 | Dot matrix display device and timepiece device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105976778B (en) * | 2016-07-04 | 2019-01-11 | 深圳市华星光电技术有限公司 | The data-driven system of liquid crystal display panel |
| TWI675363B (en) * | 2018-09-04 | 2019-10-21 | 友達光電股份有限公司 | Display, display driving device and the driving method thereof |
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| JP2007102219A (en) * | 1997-11-26 | 2007-04-19 | Seiko Epson Corp | Integrated circuit for image processor |
| JP4152699B2 (en) * | 2001-11-30 | 2008-09-17 | シャープ株式会社 | Signal line driving circuit and display device using the same |
| TWI259432B (en) * | 2004-05-27 | 2006-08-01 | Novatek Microelectronics Corp | Source driver, source driver array, and driver with the source driver array and display with the driver |
| JP4749687B2 (en) * | 2004-07-30 | 2011-08-17 | シャープ株式会社 | Display device |
| JP4666456B2 (en) * | 2004-09-16 | 2011-04-06 | 富士通セミコンダクター株式会社 | Multi-phase clock generation circuit |
| KR101152119B1 (en) * | 2005-02-07 | 2012-06-15 | 삼성전자주식회사 | Display device and driving method thereof |
| KR101197057B1 (en) * | 2005-12-12 | 2012-11-06 | 삼성디스플레이 주식회사 | Display device |
-
2008
- 2008-04-30 JP JP2008119201A patent/JP2009031751A/en active Pending
- 2008-06-16 TW TW097122456A patent/TWI396167B/en active
- 2008-06-18 KR KR1020080057222A patent/KR101475389B1/en active IP Right Grant
- 2008-06-30 CN CNA200810127408XA patent/CN101334978A/en active Pending
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034416A (en) * | 2009-10-06 | 2011-04-27 | 三星电子株式会社 | Electronic device, display device and method of controlling the display device |
| CN108335674A (en) * | 2013-02-04 | 2018-07-27 | 索尼半导体解决方案公司 | Display device |
| US9922598B2 (en) | 2014-12-24 | 2018-03-20 | Lg Display Co., Ltd. | Organic light emitting diode display and method for sensing characteristic thereof |
| CN105741776B (en) * | 2014-12-24 | 2018-09-04 | 乐金显示有限公司 | Organic light emitting diode display and method for sensing its characteristic |
| CN115428064A (en) * | 2020-04-24 | 2022-12-02 | 京瓷株式会社 | Dot matrix display device and timepiece device |
| CN114339100A (en) * | 2020-09-29 | 2022-04-12 | 豪威科技股份有限公司 | Switching technique for fast voltage stabilization in image sensors |
| CN114339100B (en) * | 2020-09-29 | 2022-12-09 | 豪威科技股份有限公司 | Switching technique for fast voltage stabilization in image sensors |
Also Published As
| Publication number | Publication date |
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| KR20090004518A (en) | 2009-01-12 |
| JP2009031751A (en) | 2009-02-12 |
| TW200912876A (en) | 2009-03-16 |
| KR101475389B1 (en) | 2014-12-22 |
| JP5191509B2 (en) | 2013-05-08 |
| TWI396167B (en) | 2013-05-11 |
| JP2010256921A (en) | 2010-11-11 |
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