TW202109889A - 積體電路 - Google Patents

積體電路 Download PDF

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TW202109889A
TW202109889A TW109107163A TW109107163A TW202109889A TW 202109889 A TW202109889 A TW 202109889A TW 109107163 A TW109107163 A TW 109107163A TW 109107163 A TW109107163 A TW 109107163A TW 202109889 A TW202109889 A TW 202109889A
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gate
ferroelectric
region
oxide
layer
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TW109107163A
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莊其毅
蔡慶威
程冠倫
王志豪
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例關於混合的積體電路。在一實施方式中，積體電路可包含第一區，其包括：第一閘極結構，具有鐵電閘極介電層；與第一區的第一閘極結構相關的至少一源極；以及與第一區的第一閘極結構相關的至少一汲極。此外，積體電路可包含第二區，其包括：第二閘極結構，具有高介電常數的閘極介電層；與第二區的第二閘極結構相關的至少一源極；以及與第二區的第二閘極結構相關的至少一汲極。積體電路亦可包括至少一溝槽隔離於第一區與第二區之間。

Description

積體電路
本發明實施例關於積體電路，更特別關於鐵電閘極與高介電常數閘極的混合結構。
電晶體技術(如互補式金氧半結構、鰭狀場效電晶體結構、或類似物)通常施加電壓至閘極末端以控制源極區與汲極區之間的電流。電晶體可為依據閘極電壓的開關。
採用鐵電材料的閘極可降低次臨界擺幅，因此可增加電源效率。然而鐵電材料在高頻時會產生磁滯，因此可能影響效率或效能如交流電應用中的效能。
本發明一實施例提供之積體電路，包括：第一區，包括：第一閘極結構，具有鐵電閘極介電層；與第一區的第一閘極結構相關的至少一源極；以及與第一區的第一閘極結構相關的至少一汲極；第二區，包括：第二閘極結構，具有高介電常數的閘極介電層；與第二區的第二閘極結構相關的至少一源極；以及與第二區的第二閘極結構相關的至少一汲極；以及至少溝槽隔離，位於第一區與第二區之間。
本發明一實施例提供之製作積體電路的方法，包括：提供結構，其包括具有一或多個源極區與一或多個汲極區的半導體裝置；形成界面層於半導體裝置、源極區、與汲極區上；形成鐵電膜於界面層對應半導體裝置的第一部分的部分上；形成介電膜於界面層對應半導體裝置的第二部分的部分上；形成金屬於鐵電膜與介電膜上；以及蝕刻源極區與汲極區上的界面層、鐵電膜、介電膜、與金屬的部分。
本發明一實施例提供之半導體裝置，包括:半導體基板，具有第一區、第二區、以及第一區與第二區之間的一或多個隔離區，其中第一區包括具有鐵電閘極介電材料的一或多個第一閘極結構，第二區包括具有高介電常數的閘極介電材料的一或多個第二閘極結構，且第一區與第二區形成相同半導體基板的部分，以及其中第一區設置為由直流電啟動，第二區設置為由交流電啟動，且第一區與第二區以線路分別啟動。
下述內容提供的不同實施例或例子可實施本發明實施例的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。
此外，空間性的相對用語如「之下」、「下方」、「下側」、「上方」、「上側」、「上」、「之上」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
如圖1所示，互補式金氧半結構100可包含一或多個n型金氧半結構102與一或多個p型金氧半結構104。舉例來說，p型基板106可包含一或多個n型井(如井108)。在其他實施例中，互補式金氧半結構100可包含n型基板，其包含一或多個p型井。
如圖1所示，n型金氧半結構102可包含對應的源極井110與汲極井112。類似地，p型金氧半結構104可包含對應的源極井114與汲極井116。n型金氧半結構102可包括對應的主體末端118，而p型金氧半結構104可包含對應的主體末端120。在一些實施例中，主體末端118可耦接至源極井110 (比如經由線路連接端點BN 至端點SN )及/或耦接至汲極井112 (比如經由線路連接端點BN 至端點DN )，以消除n型金氧半結構102中的主體偏置。在額外或其他實施例中，主體末端120可耦接至源極井114 (比如經由線路連接端點BP 至端點SP )及/或耦接至汲極井116 (比如經由線路連接端點BP 至端點DP )，以消除p型金氧半結構104中的主體偏置。
雖然圖式中的主體末端118位於相同的基板側上(如源極井110與汲極井112的一側)，且主體末端120位於相同的基板側上(如源極井114與汲極井116的一側)，主體末端118及/或主體末端120可改為形成於基板106的相反兩側上。在這些實施例中，主體末端118及/或主體末端120可分別配置為比圖1所示的實施例更靠近閘極122及/或閘極124。
閘極122 (GN )與閘極124 (GP )可包含互補式金氧半結構100的氧化物閘極。閘極122與124可包含介電層與金屬層。閘極122與124可用於互補式金氧半結構，其可分別施加電壓以控制或改變源極井110與汲極井112之間的電流以及源極井114與汲極井116之間的電流。閘極122與124所用的介電材料可控制閘極的一或多種特性，其將搭配圖2進一步說明如下。
如圖2所示，鰭狀場效電晶體200可包含源極與汲極如隆起的區域202與204於基板206上。隆起的源極與汲極可經由一或多個鰭狀物耦接至閘極(如閘極208)，比如鰭狀物210連接源極的區域204至閘極208。鰭狀場效電晶體可包含n型金氧半結構、p型金氧半結構、或具有多閘極的結構(如n型金氧半閘極的陣列、p型金氧半閘極的陣列、或互補式金氧半結構)。
如圖3A所示，鐵電閘極300可包含圖1的閘極122或閘極124，或圖2的閘極208。綜上所述，閘極208可形成於基板302上並控制源極區304與汲極區306之間的電流。鐵電閘極300的名稱來自鐵電材料的鐵電膜308。舉例來說，鐵電膜308可包含鈣鈦礦、氧化鉿為主的材料、有機聚合物、或類似物。鐵電膜308亦可包含鋯鈦酸鉛、鉭酸鍶鉍、鈦酸鋇、鈦酸鉍鑭、氧化鉿鋯、氧化鉿鍺、氧化鉿鑭、氧化鉿矽、氧化鉿釓、氧化鉿釔、氧化鉿鈧、氧化鉿鈮、氧化鉿鋁、聚偏二氟乙烯、三氟乙烯、或類似物。金屬層310可包含適用於金氧半閘極的任何層狀物。舉例來說，金屬層310可包含鈦、銀、鋁、氮化鈦鋁、碳化鉭、碳氮化鉭、氮化鉭矽、錳、鋯、氮化鈦、氮化鈦矽、氮化鉭、釕、鉬、鋁、氮化鎢、銅、鎢、或類似物。
在一些實施例中，鐵電閘極300的形成方法可採用一或多道微影技術。界面層312可形成鐵電膜308所用的表面。舉例來說，界面層312可包含氧化物、氮氧化物如氮氧化矽、氧化鉿矽、或類似物。在一些實施例中，界面層312可促進沉積或形成的層狀物(如鐵電膜308)黏著至基板302，或提供較佳的界面性質至相鄰的材料或層狀物。依據與其相接的材料或所需提供的特性，可採用其他材料。
如圖3B所示，高介電常數閘極320 (其可包含圖1的閘極122或124或者圖2的閘極208)。高介電常數閘極320可形成於基板322上，並控制源極區324與汲極區326之間的電流。高介電常數閘極320的介電膜328包含高介電常數值的介電材料。高介電常數的材料可視作高介電常數的任何材料，比如介電常數大於氧化矽的介電常數(約3.9)的材料。舉例來說，介電膜328可包含氧化鉿、氧化鑭、氧化鋁、氧化鋯、氧化鈦、氧化鉭、氧化釔、鈦酸鍶、鈦酸鋇、氧化鋇鋯、氧化鉿鋯、氧化鉿鑭、氧化鉿矽、氧化鑭矽、氧化鋁矽、氧化鉿鉭、氧化鉿鈦、鈦酸鋇鍶、氧化鋁、氮化矽、氮氧化矽、或類似物。金屬層330可包含適用於金氧半閘極的任何層狀物。舉例來說，金屬層330與圖3A的金屬層310類似，可包含鈦、銀、鋁、氮化鈦鋁、碳化鉭、碳氮化鉭、氮化鉭矽、錳、鋯、氮化鈦、氮化鈦矽、氮化鉭、釕、鉬、鋁、氮化鎢、銅、鎢、或類似物。
在一些實施例中，高介電常數閘極320與鐵電閘極300類似，其形成方法可採用一或多種微影技術。綜上所述，界面層332可形成介電膜328所用的表面。舉例來說，界面層332與界面層312類似，可包含氧化物、氮氧化物(如氮氧化矽)、氧化鉿矽、或類似物。
如圖3C所示的本發明實施例，設置的混合結構340可包含不同種類的閘極結構於單一基板上。混合結構340的基板302與322上包含的一些閘極(如鐵電閘極)可特別用於直流電應用，而混合結構340的基板302與322上包含的其他閘極(如高介電常數閘極)可特別用於交流電應用。這些閘極種類的組合可讓單一裝置藉由直流電應用中的鐵電閘極減少臨界擺幅以增加電源效率。然而藉由在交流電應用中採用高介電常數閘極，這些閘極在高頻下的磁滯可避免相同裝置在交流電應用中與鐵電閘極相關的缺點。
在混合結構340中，圖3A的鐵電閘極300與圖3B的高介電常數閘極320形成於相同的基板302與322上，且兩者之間隔有淺溝槽隔離342。雖然圖式中為單一溝槽，但可改用多個淺溝槽於基板302與322中，以分隔鐵電閘極300與高介電常數閘極320。此外，一些實施例可採用深溝槽隔離、局部氧化矽、或其他隔離技術以附加或取代淺溝槽隔離。藉由結合鐵電閘極300與高介電常數閘極320於單一的基板302與322上，混合結構340可提供混合晶片，其具有一閘極(如鐵電閘極300)用於直流電應用，以及另一閘極(如高介電常數閘極320)用於交流電應用。因此混合結構340可改善直流電應用的電源效率(藉由採用鐵電閘極300)，並避免交流電應用時的磁滯效應(藉由採用高介電常數閘極320)。混合結構340亦可包含不同線路以分開啟動鐵電閘極(如鐵電閘極300)與高介電常數閘極(如高介電常數閘極320)。除了分別連線以外，混合結構340可採用淺溝槽隔離342以在啟動高介電常數閘極(如高介電常數閘極320)時，避免鐵電閘極(如鐵電閘極300)的磁滯。
如圖4A所示，可結合多個鐵電閘極(如鐵電閘極402a、402b、402c、與402d)以及多個高介電常數閘極(如高介電常數閘極404a、404b、404c、與404d)於單一基板上(因此形成晶片400)，其採用圖3C的混合結構340。
綜上所述，可啟動晶片400的部分410以用於直流電應用，並可啟動晶片400的另一部分420以用於交流電應用(又稱作射頻應用)，端視鐵電閘極402a、402b、402c、與402d以及高介電常數閘極404a、404b、404c、與404d的空間配置而定。在圖4A的例子中，部分410與420的尺寸近似相同，比如晶片400上相同數目的邏輯閘極及/或近似相同的面積。然而在其他實施例中，晶片400可客製化為特定比例以適用於不同用途，比如部分410與部分420的比例為2:1、3:1、1:2、1:3、或類似比例。在額外或其他實施例中，可採用任何數目的鐵電閘極與高介電常數閘極，雖然圖4A的例子只顯示4個鐵電閘極與4個高介電常數閘極。
此外，雖然部分410與420在圖式中相連，但可包含晶片400的不連續部分。舉例來說，如圖4B的晶片400'所示，部分410可包含晶片400的兩個區域，且兩個區域隔有部分420。在圖4C的晶片400"之另一例中，部分420可包含晶片400的兩個區域，且兩個區域隔有部分410。綜上所述，這些部分適用於不同用途。
圖5顯示形成鐵電閘極300與高介電常數閘極320於單一基板302與322上的製程500。如圖5所示，製程500一開始採用的基板302與322已包含溝槽(如淺溝槽隔離342)。在一些實施例中，溝槽可將基板302與322分隔成閘極如鐵電閘極300與高介電常數閘極320所用的部分。可採用任何合適的微影技術形成溝槽。以上述解釋內容為例，溝槽的形成方法可採用淺溝槽隔離、深溝槽隔離、局部氧化矽、或其他隔離技術。
如圖5所示的一些實施例中，用於製程500的基板302與322已包含源極區與汲極區。可採用任何合適技術形成源極/汲極區。舉例來說，可採用離子束、退火、或上述之組合佈植p型雜質(如硼或類似物)至基板302與322中，以形成p型源極及/或汲極。在額外或其他實施例中，可採用離子束、退火、或上述之組合佈植n型雜質(如砷、磷、或類似物)至基板302與322中，以形成n型源極及/或汲極。
製程500一開始的基板302與322已包含界面層312與332，如圖5所示的例子。舉例來說，界面層312與332的形成方法可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術。如上述說明，界面層312與332可包含氧化物、氮氧化物如氮氧化矽、氧化鉿矽、或類似物。
一些實施例在步驟510之前，提供的基板302與322可具有源極區與汲極區，以及形成其上的界面層312與332。在步驟510中，可形成保護層504於基板302與322將形成高介電常數閘極(如高介電常數閘極320)的部分上。與界面層312與332類似，保護層504的形成方法可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術。保護層504可包含一或多種光阻材料。舉例來說，保護層504可包含正型光阻及/或負型光阻。
在圖5所示的一些實施例中，步驟510可包含在形成保護層504之前形成犧牲層502。可形成犧牲層502以在後續製作步驟時保護界面層312與332。舉例來說，犧牲層502在後續蝕刻步驟時，可用於保護高介電常數閘極320的區域上的界面層312與332。在這些實施例中，保護層504可形成於犧牲層502上。舉例來說，可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術形成犧牲層502於基板302與322上。舉例來說，在形成保護層504之前與形成界面層312與332之後，可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術形成犧牲層502於基板302與322上。在一些實施例中，犧牲層502的組成可為介電材料如氧化矽、氮化矽、或類似物。在其他或額外實施例中，犧牲層502的材料依據蝕刻速率差異。舉例來說，犧牲層502的材料與鐵電膜相較，可具有較低的蝕刻速率。
在步驟520中，可形成鐵電膜308於基板302與322將形成鐵電閘極(如鐵電閘極300)的部分上。舉例來說，鐵電膜308可形成於保護層504 (及/或犧牲層502)未覆蓋的基板302與322的部分上。鐵電膜308的形成方法可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術。
在一些實施例中，可選擇性地沉積鐵電膜308於對應鐵電閘極300的區域上，且沉積方法可採用蔭罩微影及/或直接微影技術。在其他或額外實施例中，鐵電膜308的形成方法可採用減法微加工技術。舉例來說，可形成鐵電膜308於基板302與322的所有或主要部分上，接著可自未對應鐵電閘極300的區域蝕刻鐵電膜308。在這些實施例中，在步驟520時可圖案化保護層506於鐵電膜308上。綜上所述，保護層506在蝕刻鐵電膜308的步驟時，可保護鐵電閘極300的區域上的鐵電膜308。
如圖5所示，步驟520亦可在圖案化鐵電膜308之前或之後蝕刻保護層504 (來自步驟510)，因此步驟520中未顯示保護層504。舉例來說，在圖案化鐵電膜308之前，可暴露基板302與322至有機溶劑以移除保護層504。此外，在形成犧牲層502的實施例中，步驟520中亦可蝕刻犧牲層502，因此圖5中的步驟520未顯示犧牲層502。舉例來說，基板302與322可暴露至蝕刻劑如氟化氫、四氟化碳、及/或三氟化氮以移除氮化矽。
在一些實施例中，步驟520中可移除不在鐵電閘極300上的任何殘留鐵電材料。舉例來說，步驟520中亦可蝕刻高介電常數閘極區(如高介電常數閘極320)上的鐵電膜308。舉例來說，步驟520中可暴露基板302與322的鐵電膜308至蝕刻劑如氯氣/氬氣。在這些實施例中，可移除露出的任何鐵電膜308 (比如保護層506未覆蓋的鐵電膜308)。自高介電常數閘極320的區域移除鐵電膜308，可避免高介電常數閘極320故障並改善高介電常數閘極320的效能。
雖然圖5未顯示，但可形成其他犧牲層於鐵電膜308與保護層506之間。在形成保護層506之前與形成鐵電膜308之後，可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術形成其他犧牲層。
在步驟530中，可形成介電膜328於基板302與322將形成高介電常數閘極(如高介電常數閘極320)的部分上。舉例來說，介電膜328可形成於鐵電膜308及/或保護層506未覆蓋的基板302與322的部分上。介電膜328的形成方法可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術。
在一些實施例中，可選擇性地形成介電膜328於對應高介電常數閘極320的區域上，且形成方法可採用蔭罩微影及/或直接微影技術。在其他或額外實施例中，介電膜328的形成方法可採用減法微加工技術。舉例來說，介電膜328可形成於基板302與322的所有或主要部份上，接著自未對應高介電常數閘極320 (與其他高介電常數閘極)的部分蝕刻介電膜328。在這些實施例中，步驟530時可圖案化介電膜328上的保護層508。綜上所述，在蝕刻介電膜328的步驟時，保護層508可保護高介電常數閘極320之區域上的介電膜328。
如圖5所示，步驟530可在形成介電膜328之前或之後蝕刻保護層506，因此圖5未顯示步驟530中的保護層506。在含有另一犧牲層(未圖示)的實施例中，可一起蝕刻保護層506與犧牲層。
在一些實施例中，步驟530中可移除不在高介電常數閘極320上的任何殘留介電膜328。舉例來說，步驟520中亦可蝕刻基板302與322將形成鐵電閘極(如鐵電閘極300)的部分上的介電膜328。舉例來說，在步驟520中可暴露基板302與322的介電膜328至蝕刻劑如四氟化碳。在這些實施例中，可移除露出(比如保護層508未保護)的任何介電膜328。自鐵電閘極300的區域移除鐵電膜308可避免鐵電閘極故障並改善鐵電閘極300的效能。
在步驟540中，可蝕刻保護層508並形成金屬層310於鐵電閘極區(如鐵電閘極300)與高介電常數閘極區(如高介電常數閘極320)上。舉例來說，金屬層310可形成於基板302與322上，且形成方法可採用電子束沉積、化學氣相沉積、及/或物理氣相沉積。在其他或額外實施例中，金屬層310的形成方法可採用旋轉塗佈、電子束沉積、或任何其他的形成技術。在圖5所示的一些實施例中，金屬層310可形成於基板302與322的所有部分(或主要部分)上。
如圖5所示，可分別形成保護層512與514於鐵電閘極區(如鐵電閘極300)與高介電常數閘極區(如高介電常數閘極320)上。舉例來說，可採用光罩或直接微影技術選擇性地形成保護層512與514。在額外或其他實施例中，保護層512與514的形成方法可採用旋轉塗佈、氣相沉積、電子束沉積、或任何其他形成技術。保護層512與514可讓步驟550蝕刻所有多餘的鐵電膜308、介電膜328、與金屬層310，而不蝕刻鐵電閘極(如鐵電閘極300)的鐵電材料與金屬，且不蝕刻高介電常數閘極(如高介電常數閘極320)的介電材料與金屬，如搭配步驟550說明的下述內容。
在步驟550中，可蝕刻不在鐵電閘極區(如鐵電閘極300)或高介電常數閘極區(如高介電常數閘極320)上多餘的鐵電膜308、介電膜328、金屬層310、以及界面層312與332。舉例來說，一些實施例的步驟550可露出任何源極區與汲極區。綜上所述，可蝕刻不在保護層512與514下的多餘鐵電膜308、介電膜328、與金屬層310。此外，亦可蝕刻保護層512與514，不論採用相同或不同的蝕刻步驟。在一些實施例中，基板302與322的相同部分上的界面層312與332的部分，可與多餘的鐵電材料、介電材料、與金屬層一起移除。
如上述說明內容，前述的任何步驟可採用光罩已選擇性地形成犧牲層與保護層於整片基板302與322上，接著採用微影、選擇性紫外線、及/或其他射線曝光以選擇性地移除犧牲層與保護層。在其他或額外實施例中，可直接沉積犧牲層。此外，上述的任何步驟中的任何蝕刻可採用一或多種濕式蝕刻技術(比如採用只選擇性移除所需層狀物的濕蝕刻劑)、及/或一或多種乾蝕刻技術(比如採用電漿移除保護層未保護的層狀物)。
在一些實施例中，製程500可形成鐵電閘極(如鐵電閘極300)後再形成高介電常數閘極(如高介電常數閘極320)。然而在其他實施例中，可在形成鐵電閘極之前先形成高介電常數閘極。舉例來說，步驟510中可形成保護層504於鐵電閘極300的區域上。接著可一起形成介電膜328與保護層508。綜上所述，可在沉積鐵電層308與保護層506之前或之後蝕刻保護層508，接著可在蝕刻保護層506 (而非保護層508)之後形成金屬層310。接著可進行製程500的其餘部分，如上述說明。
雖然圖5未顯示，但亦可形成一或多個通道於基板302與322上，已與鐵電閘極300及/或高介電常數閘極320的區域重疊。通道可包含矽、矽鍺、鍺、或類似物。在額外或其他實施例中，通道可包含二為材料如石墨烯、二硫化鉬、二硒化鎢、二碲化鉿、或類似物。可採用直接圖案化技術或上述微影製程的一部分，以形成通道於基板上。在其他實施例中，通道可包含基板302與322的摻雜部分，而不包含額外材料形成其上。
通道可連接鐵電閘極300至相同基板上的其他鐵電閘極，並可連接高介電常數閘極320至相同基板上的其他高介電常數閘極。如搭配圖4說明的上述內容，鐵電閘極與高介電常數閘極通常不相連，以在交流電下使用晶片時避免磁滯。
圖6顯示形成混合晶片(如晶片400)的方法600，且混合晶片具有鐵電閘極(如鐵電閘極300)與高介電常數閘極(如高介電常數閘極320)。雖然方法600搭配圖5的部分說明，但方法600不限於圖5所示的實施例。
如圖6所示，方法600的步驟602可包含提供結構，其半導體晶片(如半導體晶片的基板302與322)具有一或多個源極區(如源極區304與324)以及一或多個汲極區(如汲極區306與326)。舉例來說，半導體晶片的基板302與322可包含矽或其他半導體材料。在一些實施例中，半導體晶片的基板302與322可包含複合的多種導體。
在一些實施例中，方法600可進一步包含在半導體晶片的基板302與322中擴散至少一n型井或p型井，以形成一或多個源極區304與324以及一或多個汲極區306與326。舉例來說，摻雜半導體晶片的基板302與322的特定區域可能擴散n型井及/或p型井。因此這些井區可能形成一或多個源極區304與324以及一或多個汲極區306與326。在半導體晶片的基板302與322包含鰭狀場效電晶體結構的實施例中，可沉積或形成(而非擴散)一或多個源極區304與324以及一或多個汲極區306與326。
在額外或其他實施例中，方法600可包含形成隔離溝槽(如淺溝槽隔離342)於半導體晶片的基板302與322之第一部分與第二部分之間。舉例來說，本技術領域中具有通常知識者應理解可採用微影技術，形成淺溝槽及/或深溝槽於半導體晶片用於鐵電閘極的部分與用於高介電常數閘極的部分之間。
如圖6所示，方法600可包含沉積或形成界面層(如界面層312與332)於半導體晶片的基板302與322、一或多個源極區304與324、與一或多個汲極區306上(步驟604)。以上述解釋內容為例，界面層312與332可包含氧化物、氮氧化物、氧化鉿矽、或類似物。
如圖6所示，方法600可包含沉積或形成鐵電膜(如鐵電膜308)於界面層312與332對應半導體晶片的基板302與322的第一部分之部分上(步驟606)。以上述解釋內容為例，鐵電膜可包含鈣鈦礦(如鋯鈦酸鉛、鉭酸鍶鉍、鈦酸鋇、鈦酸鉍鑭、或類似物)、氧化鉿為主的材料(如氧化鉿鋯、氧化鉿鍺、氧化鉿鑭、氧化鉿矽、氧化鉿釓、氧化鉿釔、氧化鉿鈧、氧化鉿鈮、氧化鉿鋁、或類似物)、有機聚合物(如聚偏二氟乙烯、三氟乙烯、或類似物)、或任何其他鐵電材料。
如圖6所示，方法600可包含沉積或形成介電膜(如介電膜328)於界面層312與332對應半導體晶片的基板302與322之第二部分的部分上(步驟608)。以上述解釋內容為例，介電膜328可包含氧化鉿、氧化鑭、氧化鋁、氧化鋯、氧化鈦、氧化鉭、氧化釔、鈦酸鍶、鈦酸鋇、氧化鋇鋯、氧化鉿鋯、氧化鉿鑭、氧化鉿矽、氧化鑭矽、氧化鋁矽、氧化鉿鉭、鈦酸鋇鍶、氧化鋁、氮化矽、氮氧化矽、或類似物。
如圖6所示，方法600可包含沉積或形成金屬層(如金屬層310)於鐵電膜308與介電膜328上(步驟610)。以上述解釋內容為例，金屬層310可包含鈦、銀、鋁、氮化鈦鋁、碳化鉭、碳氮化鉭、氮化鉭矽、錳、鋯、氮化鈦、氮化鈦矽、氮化鉭、釕、鉬、鋁、氮化鎢、銅、鎢、或類似物。
如圖6所示，方法600的步驟612可包含蝕刻一或多個源極區304與324以及一或多個汲極區306與326之上的界面層312與332、鐵電膜308、介電膜328、與金屬層310的部分。一些實施例如上述說明內容，可蝕刻基板302與322的所有部分上的界面層312與332、鐵電膜308、介電膜328、與金屬層310，但不蝕刻鐵電閘極(如鐵電閘極300)與高介電常數閘極(如高介電常數閘極320)上的界面層312與332、鐵電膜308、介電膜328、與金屬層310。
方法600亦可包含額外步驟。舉例來說，方法600在形成鐵電膜308或介電膜328之前，亦可包含沉積或形成犧牲層502於界面層312與332上。
在這些實施例中，方法600在形成鐵電膜308之前，可進一步包含沉積或形成保護層504於半導體晶片的第二部分上的犧牲層502上，並自半導體晶片的第一部分蝕刻犧牲層502。在額外或其他實施例中，方法600可進一步包含沉積或形成保護層於半導體晶片的第一部分上的犧牲層上，並在形成介電膜328之前自半導體晶片的第二部分蝕刻犧牲層。
在上述的任何實施例中，方法600在形成金屬層310之前可更包含沉積或形成保護層508於介電膜328上、自半導體晶片的第一部分蝕刻介電膜328、並蝕刻保護層508。在額外或其他實施例中，方法600在形成金屬層310之前，可進一步包含沉積或形成保護層506於鐵電膜308上、自半導體晶片的第二部分蝕刻鐵電膜308、並蝕刻保護層506。
在上述的任何實施例中，方法600可更包含沉積或形成保護層512與514於不含一或多個源極區與一或多個汲極區的半導體晶片的部分上的金屬層310上，並在蝕刻界面層、鐵電膜、介電膜、與金屬層的部分之後蝕刻保護層512與514。
本發明實施例可提供鐵電閘極與高介電常數閘極於單一半導體基板上。舉例來說，具有鐵電閘極與高介電常數閘極的半導體晶片可形成互補式金氧半結構、鰭狀場效電晶體結構、或任何其他電晶體結構。藉由採用含有鐵電閘極與高介電常數閘極的混合結構，本發明實施例在直流電應用時可改善電源效率，且不會在交流電應用時故障。
在一實施例中，積體電路包括：第一區，其包括第一閘極結構，具有鐵電閘極介電層；與第一區的第一閘極結構相關的至少一源極；以及與第一區的第一閘極結構相關的至少一汲極；以及第二區，其包括：第二閘極結構，具有高介電常數的閘極介電層；與第二區的第二閘極結構相關的至少一源極；以及與第二區的第二閘極結構相關的至少一汲極。積體電路亦可包括至少一溝槽隔離，位於第一區與第二區之間。
在一實施例中，鐵電閘極介電層的厚度介於約0.5nm至約20nm之間。
在一實施例中，第一區或第二區的至少一者為半導體基板上的連續區域。
在一實施例中，第一區或第二區的至少一者包括半導體基板上的不連續區域。
在一實施例中，第一閘極結構包括界面層、鐵電膜、與金屬層。
在一實施例中，金屬層包括鈦、銀、鋁、氮化鈦鋁、碳化鉭、碳氮化鉭、
在一實施例中，氮化鉭矽、錳、鋯、氮化鈦、氮化鈦矽、氮化鉭、釕、鉬、氮化鎢、銅、或鎢的至少一者。
在一實施例中，鐵電膜包括鈣鈦礦、氧化鉿為主的化合物、與有機聚合物之一者。
在一實施例中，鐵電膜包括鋯鈦酸鉛、鉭酸鍶鉍、鈦酸鋇、鈦酸鉍鑭、氧化鉿鋯、氧化鉿鍺、氧化鉿鑭、氮氧化鉿、氧化鉿矽、氧化鉿釓、氧化鉿釔、氧化鉿鈧、氧化鉿鈮、氧化鉿鋁、聚偏二氟乙烯、或三氟乙烯的至少一者。
在一實施例中，第二閘極結構包括界面層、介電膜、與金屬層。
在一實施例中，介電膜包括氧化鉿、氧化鑭、氧化鋁、氧化鋯、氧化鈦、氧化鉭、氧化釔、鈦酸鍶、鈦酸鋇、氧化鋇鋯、氧化鉿鋯、氧化鉿鑭、氧化鉿矽、氧化鑭矽、氧化鋁矽、氧化鉿鉭、氧化鉿鈦、鈦酸鋇鍶、氧化鋁、氮化矽、或氮氧化矽的至少一者。
在一實施例中，金屬層包括鈦、銀、鋁、氮化鈦鋁、碳化鉭、碳氮化鉭、氮化鉭矽、錳、鋯、氮化鈦、氮化鈦矽、氮化鉭、釕、鉬、鋁、氮化鎢、銅、或鎢的至少一者。
在一實施例中，製作積體電路的方法可包括提供結構，其包括具有一或多個源極區與一或多個汲極區的半導體裝置；以及形成界面層於半導體裝置、源極區、與汲極區上。方法亦可包括形成鐵電膜於界面層對應半導體裝置的第一部分的部分上；並形成介電膜於界面層對應半導體裝置的第二部分的部分上。方法亦可包括形成金屬於鐵電膜與介電膜上；以及蝕刻源極區與汲極區上的界面層、鐵電膜、介電膜、與金屬的部分。綜上所述，第一部分可包含鐵電閘極，而第二部分可包含高介電常數閘極。
在一實施例中，方法更包括：在形成鐵電膜或形成介電膜之前，形成犧牲層於界面層上。
在一實施例中，方法更包括：形成保護層於半導體裝置的第二部分上的犧牲層上；以及在形成鐵電膜之前，自半導體裝置的第一部分蝕刻犧牲層。
在一實施例中，方法更包括：形成保護層於半導體裝置的第一部分上的犧牲層上；以及在形成介電膜之前，自半導體裝置的第二部分蝕刻犧牲層。
在一實施例中，方法更包括：形成保護層於介電膜上；以及自半導體裝置的第一部分蝕刻介電膜；以及在形成金屬之前蝕刻保護層。
在一實施例中，方法更包括：形成保護層於鐵電膜上；自半導體裝置的第二部分蝕刻鐵電膜；以及在形成金屬之前蝕刻保護層。
在一實施例中，方法更包括：形成保護層於半導體裝置不含源極區與汲極區的部分上的金屬上；以及在蝕刻界面層、鐵電膜、介電膜、與金屬的部分之後，蝕刻保護層。
在一實施例中，方法更包括：形成隔離溝槽於第一部分與第二部分之間。
在一實施例中，半導體裝置，包括:半導體基板，其具有第一區與第二區。半導體基板可更包含第一區與第二區之間的一或多個隔離區。在本發明實施例中，第一區包括具有鐵電閘極介電材料的一或多個第一閘極結構，且第二區包括具有高介電常數的閘極介電材料的一或多個第二閘極結構。第一區與第二區形成相同半導體基板的部分。綜上所述，第一區設置為由直流電啟動，第二區設置為由交流電啟動，且第一區與第二區以線路分別啟動。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明實施例。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
BN ,BP ,DN ,DP ,SN ,SP :端點 GN ,GP ,122,124,208:閘極 100:互補式金氧半結構 102:n型金氧半結構 104:p型金氧半結構 106,206,302,322:基板 108:井 110,114:源極井 112,116:汲極井 118,120:主體末端 200:鰭狀場效電晶體 202,204:區域 210:鰭狀物 300,402a,402b,402c,402d:鐵電閘極 304,324:源極區 306,326:汲極區 308:鐵電膜 310,330:金屬層 312,332:界面層 320,404a,404b,404c,404d:高介電常數閘極 328:介電膜 340:混合結構 342:淺溝槽隔離 400,400',400":晶片 410,420:部分 500:製程 502:犧牲層 504,506,508,512,514:保護層 600:方法 510,520,530,540,550,602,604,606,608,610,612:步驟
圖1係一些實施例中，互補式金氧半結構的圖式。 圖2係一些實施例中，鰭狀場效電晶體的圖式。 圖3A係一些實施例中，鐵電閘極的圖式。 圖3B係一些實施例中，高介電常數閘極的圖式。 圖3C係一些實施例中，混合鐵電-高介電常數閘極配置的圖式。 圖4A係一些實施例中，具有直流電區與射頻區的半導體晶片，直流電區具有鐵電閘極，且射頻區具有高介電常數閘極。 圖4B係一些實施例中，具有直流電區與射頻區的另一半導體晶片，直流電區具有鐵電閘極，且射頻區具有高介電常數閘極。 圖4C係一些實施例中，具有直流電區與射頻區的另一半導體晶片，直流電區具有鐵電閘極，且射頻區具有高介電常數閘極。 圖5係一些實施例中，形成混合鐵電-高介電常數閘極的製程。 圖6係一些實施例中，形成混合鐵電-高介電常數閘極的製程之流程圖。
300:鐵電閘極
302,322:基板
304,324:源極區
306,326:汲極區
308:鐵電膜
310,330:金屬層
312,332:界面層
320:高介電常數閘極
328:介電膜
340:混合結構
342:淺溝槽隔離

Claims (1)

  1. 積體電路，包括： 一第一區，包括： 一第一閘極結構，具有一鐵電閘極介電層； 與該第一區的該第一閘極結構相關的至少一源極；以及 與該第一區的該第一閘極結構相關的至少一汲極； 一第二區，包括： 一第二閘極結構，具有一高介電常數的閘極介電層； 與該第二區的該第二閘極結構相關的至少一源極；以及 與該第二區的該第二閘極結構相關的至少一汲極；以及 至少一溝槽隔離，位於該第一區與該第二區之間。
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