TW202103236A - 製造半導體裝置之方法及半導體裝置 - Google Patents

製造半導體裝置之方法及半導體裝置 Download PDF

Info

Publication number
TW202103236A
TW202103236A TW109106590A TW109106590A TW202103236A TW 202103236 A TW202103236 A TW 202103236A TW 109106590 A TW109106590 A TW 109106590A TW 109106590 A TW109106590 A TW 109106590A TW 202103236 A TW202103236 A TW 202103236A
Authority
TW
Taiwan
Prior art keywords
insulating layer
organic insulating
base film
semiconductor device
bump base
Prior art date
Application number
TW109106590A
Other languages
English (en)
Other versions
TWI822967B (zh
Inventor
松田慶太
Original Assignee
日商住友電工器件創新股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商住友電工器件創新股份有限公司 filed Critical 日商住友電工器件創新股份有限公司
Publication of TW202103236A publication Critical patent/TW202103236A/zh
Application granted granted Critical
Publication of TWI822967B publication Critical patent/TWI822967B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • H01L2224/03614Physical or chemical etching by chemical means only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03618Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
    • H01L2224/0362Photolithography
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622Manufacturing methods by patterning a pre-deposited material using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/03828Applying flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/0383Reworking, e.g. shaping
    • H01L2224/0384Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/03848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391Forming a passivation layer after forming the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05016Shape in side view
    • H01L2224/05018Shape in side view being a conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05024Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05558Shape in side view conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13026Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1415Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10344Aluminium gallium nitride [AlGaN]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13064High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking
    • H01L2924/35121Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

本發明提供一種用於製造一半導體裝置之方法,該方法包含:在一半導體區域上形成一第一有機絕緣層;形成一凸塊基膜,該凸塊基膜包括與該第一有機絕緣層接觸之一邊緣部分;對該凸塊基膜執行熱處理;及形成一第二有機絕緣層以便覆蓋該凸塊基膜之該邊緣部分及該凸塊基膜周圍之該第一有機絕緣層,同時與該第一有機絕緣層接觸,該第二有機絕緣層具備曝露該凸塊基膜之一表面之一第一開口。

Description

製造半導體裝置之方法及半導體裝置
本發明係關於一種用於製造半導體裝置之方法及一種半導體裝置。
JP2005-150578A及JP2017-228583A揭示了與用於製造半導體裝置之方法相關之技術。在JP2005-150578A中所揭示之方法中,由用作Au凸塊之基膜(凸塊下金屬(UBM)膜)之導電膜(自底層起之Ti膜及Pd膜)形成重新佈線。使用濺鍍方法來形成Ti膜及Pd膜。當重新佈線中之電阻成為問題時,在Pd膜上形成Au膜,藉此實現自底層起具有Ti膜、Pd膜及Au膜之重新佈線結構。
JP2017-228583A中所揭示之方法包括形成第一金屬層之步驟、形成覆蓋膜之步驟,及形成第二金屬層之步驟。在形成覆蓋膜之步驟中,在第一金屬層之外圓周之區域中形成由Cu、Ti、Al、Mg及Cr中之任一者形成之覆蓋膜。在形成以第一金屬層作為種子金屬之第二金屬層之步驟中,相對於與構成覆蓋膜之材料不同並選自Ni、Pd及Al之金屬執行無電極電鍍處理。第二金屬層定位於第一金屬層之上表面上,且不會延伸至覆蓋膜之外側。
本發明提供一種用於製造一半導體裝置之方法。此方法包含:在一半導體區域上形成一第一有機絕緣層;形成一凸塊基膜,該凸塊基膜包括與該第一有機絕緣層接觸之一邊緣部分;對該凸塊基膜執行熱處理;及形成一第二有機絕緣層以便覆蓋該凸塊基膜之該邊緣部分及該凸塊基膜周圍之該第一有機絕緣層,同時與該第一有機絕緣層接觸。該第二有機絕緣層具備曝露該凸塊基膜之一表面之一第一開口。
本發明提供一種半導體裝置。該半導體裝置包含一半導體區域、一第一有機絕緣層、一凸塊基膜、一第二有機絕緣層及一焊料凸塊。該第一有機絕緣層設置於該半導體區域上。該凸塊基膜包括定位於該第一有機絕緣層上之一邊緣部分。該第二有機絕緣層被設置為覆蓋該凸塊基膜之該邊緣部分及該凸塊基膜周圍之該第一有機絕緣層,同時與該第一有機絕緣層接觸。該第二有機絕緣層具備曝露該凸塊基膜之一表面之一第一開口。該焊料凸塊覆蓋該第一開口並與該凸塊基膜接觸。
[本發明欲解決之問題] 球狀柵格陣列(BGA)之封裝可用於在基板或其類似者上執行半導體裝置之覆晶安裝。在此類半導體裝置之佈線層上形成焊料凸塊(例如參考JP2005-150578A、JP2017-228583A)。為了抑制金屬材料在焊料與佈線層之間的相互擴散,在佈線層與焊料凸塊之間設置凸塊基膜(UBM膜)。舉例而言,諸如聚醯亞胺膜之有機絕緣層作為佈線層之層間膜設置於半導體區域上。
歸因於諸如聚醯亞胺之有機絕緣材料之熱膨脹係數與金屬材料之熱膨脹係數之間的差異,凸塊基膜可能由於在焊球安裝時產生之熱應力或其類似者而易於自有機絕緣層剝離。當在凸塊基膜與有機絕緣層之間產生間隙時,焊料可能滲入至該間隙中。若焊料滲入,則很可能在凸塊基膜與佈線層之間的邊界表面上發生破裂,使得半導體裝置之可靠性劣化。
[本發明之效果] 本發明提供一種用於製造半導體裝置之方法及一種半導體裝置,其中可藉由減少焊料滲入至凸塊基膜與有機絕緣層之間的間隙中來改良可靠性。
[本發明之實施例之描述] 下文將參考圖式描述本發明之用於製造半導體裝置之方法及該半導體裝置之特定實例。本發明不限於此等實例。本發明係由申請專利範圍指示,且本發明意欲包括與申請專利範圍等效之含義及範圍內之所有變化。在以下描述中,相同的附圖標記應用於圖式描述中之相同的元件,且將省略重複的描述。
圖1係繪示根據實施例之半導體裝置1A的平面圖。如圖1中所繪示,為BGA半導體裝置之半導體裝置1A包含半導體區域10及設置於半導體區域10之表面上之複數個焊料凸塊17。複數個焊料凸塊17以平面分散之方式安置於半導體區域10之表面上。舉例而言,焊料凸塊17係由諸如錫及銀之合金(Sn-Ag)之金屬構成之實質上球形結構。
舉例而言,當半導體裝置1A係由基於氮化鎵(GaN)之半導體構成之高電子遷移率電晶體(HEMT)時,半導體區域10包括GaN通道層及AlGaN障壁層(或InAlN障壁層)。半導體區域10可包括除HEMT以外之場效電晶體(FET)或用於除彼等裝置以外之半導體運行裝置之半導體層。
接地佈線區域11及信號佈線區域12設置於半導體區域10之表面上。接地佈線區域11實質上設置於半導體區域10之整個表面上。在一實例中,接地佈線區域11之平面形狀與半導體裝置1A之平面形狀實質上相似,並為實質上矩形形狀。在接地佈線區域11之在某一方向上彼此面對之一對側11a及11b中形成N個(在圖1中所繪示之實例中為五個)半圓形切口11c,且該等信號佈線區域12中之每一者設置於該等切口11c中之每一者之內側上。舉例而言,該等信號佈線區域12中之每一者之平面形狀為圓形形狀。接地佈線區域11及每一信號佈線區域12彼此隔離,且半環形間隙區域13設置於接地佈線區域11與信號佈線區域12之間。在圖1中所繪示之實例中,兩個信號佈線區域12沿著接地佈線區域11之一個側11a並排地安置,且三個信號佈線區域12沿著接地佈線區域11之另一側11b並排地安置。
多個焊料凸塊17包括M個(在圖1中所繪示之實例中為12個)接地焊料凸塊17a及N個信號焊料凸塊17b。M個接地焊料凸塊17a在接地佈線區域11中在彼此正交之列方向及行方向上以二維形狀配置。N個信號焊料凸塊17b分別設置於信號佈線區域12上。N個信號焊料凸塊17b中之一些(在圖1中所繪示之實例中為兩個)沿著接地佈線區域11之側11a配置,且其他(在圖1所繪示之實例中為三個)沿著接地佈線區域11之側11b配置。
圖2係繪示沿著圖1中所繪示之線II-II之焊料凸塊17之基礎結構之橫截面的放大圖。如圖2中所繪示,半導體裝置1A包括設置於半導體區域10之表面上之金屬佈線21及設置於半導體區域10之表面上之有機絕緣層31。此外,半導體裝置1A包括金屬膜22及23、凸塊基膜26,及有機絕緣層32。在圖2中,圖1中所繪示之半導體區域10及焊料凸塊17之繪示被省略。
金屬佈線21係設置於半導體區域10上之無機絕緣層(例如SiN層或SiO2 層)上之信號佈線。金屬佈線21連接至與半導體區域10進行歐姆接觸之電極(例如源極電極及汲極電極),或與半導體區域10進行肖特基接觸之電極(例如閘極電極)。舉例而言,金屬佈線21由諸如金(Au)之金屬構成。該等金屬佈線21中之每一者之厚度可在0.5 μm至3.0 μm之範圍內,並在一實例中為1 μm。
有機絕緣層31係設置於佈線層之間的介電物質之層間膜。在一實例中,有機絕緣層31主要由樹脂形成並由聚醯亞胺形成。有機絕緣層31設置於半導體區域10之整個表面上並覆蓋無機絕緣層及金屬佈線21。有機絕緣層31在金屬佈線21上具有用於曝露金屬佈線21之一部分之開口31a。當在半導體區域10之厚度方向上檢視時,開口31a與信號焊料凸塊17b重疊(參考圖1)。有機絕緣層31之厚度可在1 μm至6 μm之範圍內。
金屬膜22用作接地佈線。金屬膜23用作信號佈線。舉例而言,金屬膜22及23設置於有機絕緣層31上並由諸如金(Au)之金屬形成。金屬膜22設置於圖1中所繪示之接地佈線區域11上,且金屬膜22之平面形狀與接地佈線區域11之平面形狀一致。具體言之,金屬膜22實質上設置於半導體區域10之整個表面上。在一實例中,金屬膜22之平面形狀與半導體裝置1A之平面形狀實質上相似,並為實質上矩形形狀。在金屬膜22之在某一方向上彼此面對之一對側中,形成對應於圖1中所繪示之切口11c之半圓形切口,且該等金屬膜23中之每一者設置於該等切口中之每一者之內側上。該等金屬膜23中之每一者設置於圖1中所繪示之信號佈線區域12中之每一者上,且該等金屬膜23中之每一者之平面形狀與該等信號佈線區域12中之每一者之平面形狀一致。舉例而言,金屬膜22及金屬膜23彼此分離,且金屬膜22與金屬膜23之間的距離d1在50 μm至300 μm之範圍內。金屬膜23填充形成於有機絕緣層31中之開口31a,完全覆蓋開口31a,並通過開口31a連接至金屬佈線21。金屬膜22及23中之每一者之厚度可在0.5 μm至5.0 μm之範圍內,並在一實例中為2 μm。
凸塊基膜26被構成為包括設置於金屬膜22上並覆蓋金屬膜22之部分26a,及設置於金屬膜23上並覆蓋金屬膜23之部分26b。在本實施例中,部分26a覆蓋金屬膜22之上表面及側表面,且部分26a之邊緣部分26c定位於金屬膜22周圍之有機絕緣層31上並與有機絕緣層31接觸。該等部分26b中之每一者覆蓋該等金屬膜23中之每一者之上表面及側表面,且該等部分26b中之每一者之邊緣部分26d定位於金屬膜23周圍之有機絕緣層31上並與有機絕緣層31接觸。部分26a及各別部分26b彼此分離,其中間隙區域13 (參考圖1)包夾於部分26a與各別部分26b之間。
凸塊基膜26主要被構成為包括種子金屬膜24及設置於種子金屬膜24上之主膜25。舉例而言,種子金屬膜24主要包括諸如鈦(Ti)及鈀(Pd)之金屬。在一實例中,種子金屬膜24包括分別設置於金屬膜22及23上之Ti層,及設置於Ti層上之Pd層。在此情況下,Ti層之厚度可在5 nm至100 nm之範圍內,並在一實例中為5 nm。Pd層之厚度可在10 nm至500 nm之範圍內,並在一實例中為10 nm。當經由無電極電鍍處理形成主膜25時,種子金屬膜24用作種子金屬。當主膜25包括Ni (或NiCr)且金屬佈線21包括Au時,種子金屬膜24阻礙Ni (或NiCr)及Au形成合金。
主膜25係設置於種子金屬膜24上之金屬膜,並與種子金屬膜24接觸。舉例而言,主膜25主要包括諸如鎳(Ni)或鎳鉻合金(NiCr)之金屬。設置主膜25以防止構成焊料凸塊17之焊料及構成金屬佈線21之金(Au)的相互擴散。當主膜25係Ni層時,舉例而言,Ni層之厚度在3 μm至6 μm之範圍內。主膜25之邊緣部分25c自種子金屬膜24突出。邊緣部分25c可在相對於有機絕緣層31之厚度方向上具備間隙或可與有機絕緣層31接觸。
舉例而言,有機絕緣層32主要包括感光樹脂。舉例而言,感光樹脂係感光聚醯亞胺。在一實例中,有機絕緣層32由與有機絕緣層31相同的材料形成。有機絕緣層32至少自凸塊基膜26之邊緣部分26c及26d上方設置至凸塊基膜26周圍之有機絕緣層31上方,並與有機絕緣層31接觸。在本實施例中,有機絕緣層32設置於半導體區域10之整個表面上,並覆蓋自凸塊基膜26曝露之有機絕緣層31。有機絕緣層32具有用於曝露凸塊基膜26之部分26a之開口32a及用於曝露凸塊基膜26之部分26b之開口32b。當在半導體區域10之厚度方向上檢視時,開口32a與接地焊料凸塊17a重疊(參考圖1),且開口32b與信號焊料凸塊17b重疊(參考圖1)。接地焊料凸塊17a覆蓋開口32a,並通過開口32a與凸塊基膜26之部分26a之主膜25接觸。信號焊料凸塊17b覆蓋開口32b,並通過開口32b與凸塊基膜26之部分26b之主膜25接觸。舉例而言,有機絕緣層32之厚度在1.0 μm至10.0 μm之範圍內。
隨後,將描述用於製造上述半導體裝置1A之方法。首先,在基板上磊晶生長半導體區域10。舉例而言,此係使用金屬有機化學氣相沈積(MOCVD)方法來生長。接下來,在半導體區域10上形成電極(例如閘極電極、源極電極及汲極電極)。舉例而言,電極係藉由如下方式來形成:在半導體區域10上形成具有開口之抗蝕劑遮罩,在抗蝕劑遮罩之開口內部並在抗蝕劑遮罩上執行成為電極材料之金屬之氣相沈積,及移除抗蝕劑遮罩上之金屬以及抗蝕劑遮罩(亦即,執行起離)。隨後,在半導體區域10上形成無機絕緣層(例如SiN層)。舉例而言,可藉由電漿CVD方法來形成無機絕緣層。
圖3A至圖3C、圖4A至圖4C及圖5A及圖5B係繪示用於製造半導體裝置1A之方法中在形成無機絕緣層之後的每一步驟的橫截面圖。舉例而言,繼上述步驟後,如圖3A中所繪示,藉由電鍍方法在無機絕緣層上形成各自具有預定平面圖案之金屬佈線21。此時,金屬佈線21及電極經由插入於其間之無機絕緣層中形成之開口彼此連接。
隨後,在半導體區域10之設置有金屬佈線21之表面上形成有機絕緣層31。舉例而言,藉由在半導體區域10上執行有機絕緣層31之材料(例如聚醯亞胺)之旋塗來形成有機絕緣層31。另外,藉由在有機絕緣層31上形成具有對應於開口31a之開口圖案之遮罩並在此遮罩插入於有機絕緣層31之情況下蝕刻有機絕緣層31,形成開口31a以曝露金屬佈線21。舉例而言,遮罩之材料係SiN或SiO2 。舉例而言,使用光微影技術或電子束微影技術來形成遮罩之開口。可藉由使用電漿進行乾式蝕刻來形成開口31a。
隨後,如圖3B中所繪示,舉例而言,藉由電鍍方法在有機絕緣層31上形成各自具有預定平面圖案之金屬膜22及23。在此步驟中,在圖1中所繪示之接地佈線區域11中形成金屬膜22,且在該等信號佈線區域12中之每一者中形成該等金屬膜23中之每一者。此時,金屬膜23連接至金屬佈線21,其中有機絕緣層31之開口31a插入於金屬膜23與金屬佈線21之間。
隨後,如圖3C中所繪示,在半導體區域10之整個表面上形成種子金屬膜24,且金屬膜22之上表面及側表面、每一金屬膜23之上表面及側表面以及有機絕緣層31之自金屬膜22及23曝露之表面由種子金屬膜24覆蓋。舉例而言,種子金屬膜24係藉由濺鍍方法而形成。在一實例中,藉由濺鍍方法形成厚度為5 nm之Ti層。此後,藉由濺鍍方法在Ti層上形成厚度為10 nm之Pd層。以此方式形成之種子金屬膜24包括覆蓋金屬膜22之部分24a、覆蓋金屬膜23之部分24b,及定位於有機絕緣層31上之部分24c。
隨後,如圖4A中所繪示,在種子金屬膜24上形成光阻R。光阻R在部分24c上具有開口Ra,並通過開口Ra僅曝露部分24c。舉例而言,光阻R係負性抗蝕劑。在此類情況下,在種子金屬膜24上施加負性抗蝕劑,且使排除對應於開口Ra之區域之其他區域經受曝光及顯影,使得可僅移除對應於開口Ra之尚未經受曝光之區域。光阻R覆蓋種子金屬膜24之部分24a及24b,並覆蓋部分24c之鄰近於部分24a及24b中之每一者之圓周邊緣部分的部分。另外,經由蝕刻來移除種子金屬膜24之自光阻R之開口Ra曝露之部分24c。蝕刻係例如使用碘蝕刻劑(由關東化學株式會社(KANTO CHEMICAL CO., INC.)製造之產品名「AURUM」系列)之濕式蝕刻或諸如反應性離子蝕刻(RIE)之乾式蝕刻。因此,種子金屬膜24之部分24a及部分24b彼此分離。種子金屬膜24之定位於有機絕緣層31上並與有機絕緣層31接觸之邊緣部分保留於部分24a及24b周圍。此後,移除光阻R。
隨後,如圖4B中所繪示,藉由在種子金屬膜24上形成主膜25來形成凸塊基膜26之部分26a及26b。在此步驟中,主膜25係藉由用於使種子金屬膜24成為種子金屬之無電極電鍍方法而形成。舉例而言,主膜25係藉由將用於自催化電鍍之次磷酸鹽作為催化劑之無電極電鍍處理(例如自催化無電極電鍍處理)而形成。使用無電極電鍍之原因係它與電鍍相比具有更優良的可靠性。由於種子金屬膜24以限制性方式設置於部分24a及24b中,故此無電極電鍍成為選擇性電鍍,使得主膜25在部分24a上及在部分24b上以限制性方式生長。由於主膜25亦在橫向方向上生長,故自種子金屬膜24突出之邊緣部分25c形成於主膜25中。
無電極電鍍係用於在不使用外部電源之情況下執行電鍍的方法,且存在使用離子化傾向之置換電鍍、使用還原劑之自催化無電極電鍍(還原電鍍)、組合此等者之置換還原電鍍,及其類似者。此處,使用自催化無電極電鍍,但可使用其他類型之無電極電鍍。另一方面,電鍍係用於執行藉由使用外部電源來使電流在電極之間流動而自陰極施加電子之電鍍的方法。
隨後,在主膜25上形成Au膜。舉例而言,使用無電極電鍍處理、電鍍處理、氣相沈積起離方法或濺鍍方法來形成Au膜。舉例而言,Au膜之厚度係10 μm。
隨後,如圖4C中所繪示,將包括凸塊基膜26之產品安裝於熱處理爐Q內部,且對凸塊基膜26執行熱處理。舉例而言,熱處理溫度係比在後續構造中形成之焊料凸塊17之回焊溫度高的溫度,且該熱處理溫度在260℃至350℃之範圍內。熱處理時間可為5分鐘至60分鐘,並在一實例中為30分鐘。舉例而言,用於熱處理之氛圍係大氣(氮氣(N2 )及氧氣(O2 )之混合氛圍)、真空氛圍,或氬氣(Ar)或氦氣(He)之惰性氣體氛圍。
隨後,如圖5A中所繪示,在半導體區域10之形成有凸塊基膜26之表面上形成有機絕緣層32。如上文所描述,有機絕緣層32至少自凸塊基膜26之邊緣部分26c及26d上方設置至凸塊基膜26周圍之有機絕緣層31上方,並與有機絕緣層31接觸。與有機絕緣層31相似,舉例而言,有機絕緣層32係藉由在凸塊基膜26上及在自該凸塊基膜26曝露之有機絕緣層31上執行有機絕緣層32之材料(例如感光聚醯亞胺)之旋塗而形成。另外,有機絕緣層32使用具有對應於開口32a及32b之開口圖案之光遮罩來經受曝光及顯影,使得形成開口32a及32b且曝露凸塊基膜26之部分26a及26b之表面。
隨後,如圖5B中所繪示,形成焊料凸塊17。亦即,形成覆蓋開口32a並與凸塊基膜26之部分26a接觸之接地焊料凸塊17a,及覆蓋開口32b並與凸塊基膜26之部分26b接觸之信號焊料凸塊17b。在此步驟中,在施加助熔劑之後,舉例而言,藉由在250℃之溫度下之回焊(亦即,熱處理)來形成例如具有諸如直徑為160 μm之大小之焊料凸塊17。在此步驟中,形成於種子金屬膜24上之Au膜實質上在焊料凸塊17內部擴散。此後,清潔助熔劑。經由上述步驟,產生了圖1及圖2中所繪示之本實施例之半導體裝置1A。
將與相關技術中之製造方法之問題一起描述由上述用於製造根據本實施例之半導體裝置1A之方法達成的效果。圖10A係繪示JP2017-228583A中所揭示之半導體裝置之比較實例之結構之一部分的放大橫截面圖。例如由Au構成之金屬佈線120設置於主要包括氮化物半導體之半導體區域110上,且該金屬佈線120由保護半導體區域110之無機絕緣層141覆蓋。舉例而言,無機絕緣層141係SiN或其類似者之矽化合物膜。例如由諸如聚醯亞胺之樹脂形成之有機絕緣層133設置於無機絕緣層141上。在厚度方向上穿透無機絕緣層141及有機絕緣層133之開口141a及133a形成於無機絕緣層141及有機絕緣層133中,且此等開口141a及133a填充有例如由Au構成之金屬佈線121。金屬佈線121通過開口141a及133a連接至金屬佈線120。無機絕緣層142及有機絕緣層131層壓於有機絕緣層133上。舉例而言,無機絕緣層142係由SiN或其類似者之矽化合物膜。有機絕緣層131由諸如聚醯亞胺之樹脂形成。無機絕緣層142及有機絕緣層131之開口142a及131a形成於金屬佈線121上,且種子金屬膜124設置於開口142a及131a中之每一者之側表面及金屬佈線121之自開口142a及131a曝露之表面上。舉例而言,種子金屬膜124由Ti及Pd構成。主膜125設置於種子金屬膜124上,在該主膜125中,種子金屬膜124被電鍍形成為種子金屬。舉例而言,主膜125由Ni及Au構成。種子金屬膜124及主膜125構成凸塊基膜126。凸塊基膜126之圓周邊緣部分與有機絕緣層131之表面接觸。焊料凸塊形成於凸塊基膜126上。
當在以上結構中經由回焊形成焊料凸塊時,或當經由回焊在佈線基板上安裝在形成焊料凸塊之後的以上半導體裝置時,存在歸因於諸如聚醯亞胺之有機絕緣材料之熱膨脹係數與金屬材料之熱膨脹係數之間的差異而導致凸塊基膜126之圓周邊緣部分自有機絕緣層131剝離的情況,如圖10B中所繪示。當在凸塊基膜126與有機絕緣層131之間產生間隙G時,焊料可能滲入至此間隙G中,且此焊料可能使凸塊基膜126與金屬佈線121之間的邊界表面破裂。
關於此問題,用於製造本實施例之半導體裝置1A之方法包括在半導體區域10上形成有機絕緣層31之步驟、形成凸塊基膜26之步驟、對凸塊基膜26執行熱處理之步驟,及形成有機絕緣層32之步驟。在形成凸塊基膜26之步驟中,形成包括定位於有機絕緣層31上之邊緣部分26c及26d之凸塊基膜26。在形成有機絕緣層32之步驟中,形成有機絕緣層32,該有機絕緣層32至少自凸塊基膜26之邊緣部分26c及26d上方設置至凸塊基膜26周圍之有機絕緣層31上方,與有機絕緣層31接觸,並具有用於曝露凸塊基膜26之表面之開口32a及32b。
本實施例之半導體裝置1A包括半導體區域10、設置於半導體區域10上之有機絕緣層31、包括定位於有機絕緣層31上之邊緣部分26c及26d之凸塊基膜26、有機絕緣層32,及與凸塊基膜26接觸之焊料凸塊17。有機絕緣層32至少自凸塊基膜26之邊緣部分26c及26d上方設置至凸塊基膜26周圍之有機絕緣層31上方,並與有機絕緣層31接觸。有機絕緣層32具有用於曝露凸塊基膜26之表面之開口32a及32b。接地焊料凸塊17a覆蓋開口32a並與凸塊基膜26接觸,且信號焊料凸塊17b覆蓋開口32b並與凸塊基膜26接觸。
圖6係用於描述由根據本實施例之半導體裝置1A及用於製造該半導體裝置之方法達成之效果的視圖。在本實施例中,在形成凸塊基膜26之後對凸塊基膜26執行熱處理。此時,歸因於由熱膨脹係數之間的差異所導致之應力,凸塊基膜26在凸塊基膜26與有機絕緣層31之間的接合強度低的部分中自有機絕緣層31剝離(圖6中之部分A)。當凸塊基膜26及經曝露之有機絕緣層31在此後之步驟中由有機絕緣層32覆蓋時,有機絕緣層32之材料進入凸塊基膜26與有機絕緣層31之間的間隙。
以此方式,本實施例在焊料凸塊17之回焊之前提前剝離凸塊基膜26與有機絕緣層31之間的接合強度低的部分。作為其結果而產生之間隙提前被有機絕緣層32之材料所填充。因此,凸塊基膜26之內部應力被釋放,且可減少歸因於焊料凸塊17之回焊期間之熱而導致的凸塊基膜26與有機絕緣層31之間的間隙之產生。因此,減少了焊料滲入至凸塊基膜26與有機絕緣層31之間的間隙中,使得可改良半導體裝置1A之可靠性。
在本實施例中,有機絕緣層32可主要包括感光樹脂,且形成有機絕緣層32之步驟可包括藉由對有機絕緣層32執行曝光及顯影來形成開口32a及32b之步驟。關於有機絕緣層32,通常經由蝕刻來形成開口32a及32b。然而,當使用感光樹脂時,在曝光及顯影之步驟中形成開口32a及32b,使得可省略蝕刻步驟。
在本實施例中,用於製造半導體裝置1A之方法可包括以下步驟:藉由回焊程序來形成焊料凸塊17,以覆蓋開口32a及32b並與凸塊基膜26接觸。如上文所描述,根據本實施例之製造方法,可減少歸因於焊料凸塊17之回焊程序期間之熱而導致的凸塊基膜26與有機絕緣層31之間的間隙之產生。因此,可改良當藉由回焊程序形成焊料凸塊17時的半導體裝置1A之可靠性。
在本實施例中,在凸塊基膜26之熱處理步驟中,可在比焊料凸塊17之回焊溫度高的溫度下執行熱處理。因此,在回焊之前可以可靠地剝離可在焊料凸塊17之回焊溫度下發生凸塊基膜26及有機絕緣層31之剝離的地方。因此,可進一步改良半導體裝置1A之可靠性。
在本實施例中,金屬膜22及23整體上可由凸塊基膜26覆蓋。因此,凸塊基膜26之面積增加,且可進一步減少焊料與金屬膜22及23之間的接觸。
(修改實例) 圖7係繪示根據上述實施例之修改實例之步驟的橫截面圖。在執行圖4C中所繪示之凸塊基膜26之熱處理之後並在形成圖5A中所繪示之有機絕緣層32之前執行此步驟。在此步驟中,有機絕緣層31之自凸塊基膜26曝露之一部分被蝕刻(圖7中之箭頭E),以在該部分中形成自有機絕緣層31之表面下凹之凹入部分31b。舉例而言,蝕刻係使用O2 電漿之反應性離子蝕刻(RIE)。凹入部分31b距有機絕緣層31之表面的深度可為有機絕緣層31之厚度的一半或小於該厚度。舉例而言,當有機絕緣層31之厚度為2 μm時,凹入部分31b之深度為1 μm或更小。圖8係繪示在上述步驟之後形成有機絕緣層32之狀態的橫截面圖。如圖8中所繪示,有機絕緣層32填充凹入部分31b。
當對凸塊基膜26執行熱處理且在凸塊基膜26與有機絕緣層31之間產生微小間隙時,取決於該間隙之大小,擔心歸因於有機絕緣層32之構成材料之黏度而導致該構成材料可能不進入間隙。在此類情況下,若如在本修改實例中一樣蝕刻有機絕緣層31,則可如圖9A之部分B中所繪示而擴大凸塊基膜26與有機絕緣層31之間的間隙。另外,如圖9B之部分C中所繪示,當形成有機絕緣層32時,有機絕緣層32之構成材料容易進入間隙。因此,間隙可容易被有機絕緣層32之構成材料所填充,使得可更有效地減少焊料滲入至間隙中,且可進一步改良半導體裝置1A之可靠性。
本發明之用於製造半導體裝置之方法及該半導體裝置不限於上述實施例,且可執行各種其他修改。舉例而言,在上述實施例中,HEMT已作為半導體區域之實例被描述。然而,本發明不限於HEMT,並可應用於包括金屬佈線及焊料凸塊之各種半導體裝置。相關申請 之交叉 參考
本申請案係基於並主張2019年2月28日申請之日本專利申請案第2019-035719號的優先權益,該專利申請案之全部內容以引用之方式併入本文中。
1A:半導體裝置 10:半導體區域 11:接地佈線區域 11a:側 11b:側 11c:半圓形切口 12:信號佈線區域 13:半環形間隙區域 17:焊料凸塊 17a:接地焊料凸塊 17b:信號焊料凸塊 21:金屬佈線 22:金屬膜 23:金屬膜 24:種子金屬膜 24a:部分 24b:部分 24c:部分 25:主膜 25c:邊緣部分 26:凸塊基膜 26a:部分 26b:部分 26c:邊緣部分 26d:邊緣部分 31:有機絕緣層 31a:開口 31b:凹入部分 32:有機絕緣層 32a:開口 32b:開口 110:半導體區域 120:金屬佈線 121:金屬佈線 124:種子金屬膜 125:主膜 126:凸塊基膜 131:有機絕緣層 131a:開口 133:有機絕緣層 133a:開口 141:無機絕緣層 141a:開口 142:無機絕緣層 142a:開口 A:部分 B:部分 C:部分 d1:距離 E:箭頭 G:間隙 Q:熱處理爐 R:光阻 Ra:開口 II-II:線
圖1係繪示根據實施例之半導體裝置的平面圖。
圖2係繪示沿著圖1中所繪示之線II-II之焊料凸塊之基礎結構之橫截面的放大圖。
圖3A、圖3B及圖3C係繪示用於製造圖1中所繪示之半導體裝置之方法中之每一步驟的橫截面圖。
圖4A、圖4B及圖4C係繪示用於製造半導體裝置之方法中之每一步驟的橫截面圖。
圖5A及圖5B係繪示用於製造半導體裝置之方法中之每一步驟的橫截面圖。
圖6係用於描述由根據實施例之半導體裝置及用於製造該半導體裝置之方法達成之效果的視圖。
圖7係繪示根據修改實例之步驟的橫截面圖。
圖8係繪示在修改實例中形成有機絕緣層之狀態的橫截面圖。
圖9A及圖9B係用於描述由根據修改實例之製造方法達成之效果的視圖。
圖10A係繪示JP2017-228583A中所揭示之半導體裝置之比較實例之結構之一部分的放大橫截面圖。圖10B係繪示圖10A中之一部分的放大橫截面圖。
21:金屬佈線
22:金屬膜
23:金屬膜
24:種子金屬膜
25:主膜
25c:邊緣部分
26:凸塊基膜
26a:部分
26b:部分
26c:邊緣部分
26d:邊緣部分
31:有機絕緣層
31a:開口
32:有機絕緣層
32a:開口
32b:開口
d1:距離

Claims (20)

  1. 一種用於製造一半導體裝置之方法,其包含: 在一半導體區域上形成一第一有機絕緣層; 形成一凸塊基膜,該凸塊基膜包括與該第一有機絕緣層接觸之一邊緣部分; 對該凸塊基膜執行熱處理;及 形成一第二有機絕緣層以便覆蓋該凸塊基膜之該邊緣部分及該凸塊基膜周圍之該第一有機絕緣層,同時與該第一有機絕緣層接觸,該第二有機絕緣層具備曝露該凸塊基膜之一表面之一第一開口。
  2. 如請求項1之用於製造一半導體裝置之方法,其中在該形成該第二有機絕緣層之前對該凸塊基膜執行該熱處理。
  3. 如請求項1之用於製造一半導體裝置之方法,其進一步包含: 在該執行該熱處理之後並在該形成該第二有機絕緣層之前蝕刻該第一有機絕緣層。
  4. 如請求項3之用於製造一半導體裝置之方法,其中藉由該蝕刻該第一有機絕緣層而形成自該第一有機絕緣層之一表面下凹之一凹入部分。
  5. 如請求項4之用於製造一半導體裝置之方法,其中該凹入部分距該第一有機絕緣層之該表面的一深度為該第一有機絕緣層之一厚度的一半或小於該厚度。
  6. 如請求項1至5中任一項之用於製造一半導體裝置之方法,其中該形成該第二有機絕緣層包括藉由對主要包括一感光樹脂之該第二有機絕緣層進行曝光及顯影來形成該第一開口。
  7. 如請求項1至6中任一項之用於製造一半導體裝置之方法,其進一步包含: 藉由一回焊程序來形成一焊料凸塊,以便覆蓋該第一開口並與該凸塊基膜接觸。
  8. 如請求項7之用於製造一半導體裝置之方法,其中在比該焊料凸塊之該回焊程序之一溫度高的一溫度下執行該熱處理。
  9. 如請求項7或8之用於製造一半導體裝置之方法,其中在260℃至350℃之一範圍之一溫度下執行該熱處理。
  10. 如請求項1至9中任一項之用於製造一半導體裝置之方法,其中該凸塊基膜之該熱處理繼續5分鐘至60分鐘。
  11. 如請求項1至10中任一項之用於製造一半導體裝置之方法,其中在一大氣、一真空氛圍或一惰性氣體氛圍中對該凸塊基膜執行該熱處理。
  12. 如請求項1至11中任一項之用於製造一半導體裝置之方法,其進一步包含: 在該半導體區域上形成用作一信號佈線之一金屬佈線, 其中在該形成該第一有機絕緣層時,該第一有機絕緣層被形成為具有曝露該金屬佈線之一表面之一第二開口。
  13. 如請求項12之用於製造一半導體裝置之方法,其進一步包含: 在該第一有機絕緣層上之一接地佈線區域中形成用作一接地佈線之一第一金屬膜;及 在與該接地佈線區域隔離之一信號佈線區域中形成用作該信號佈線之一第二金屬膜,以便通過該第二開口與該金屬佈線連接。
  14. 如請求項13之用於製造一半導體裝置之方法,其中在該形成該凸塊基膜時,單獨地形成該凸塊基膜之覆蓋該第一金屬膜之一第一部分及該凸塊基膜之覆蓋該第二金屬膜之一第二部分。
  15. 如請求項13或14之用於製造一半導體裝置之方法,其中在該形成該凸塊基膜時,該第一金屬膜及該第二金屬膜整體上由該凸塊基膜覆蓋。
  16. 一種半導體裝置,其包含: 一半導體區域; 一第一有機絕緣層,其設置於該半導體區域上; 一凸塊基膜,其包括定位於該第一有機絕緣層上之一邊緣部分; 一第二有機絕緣層,其被設置為覆蓋該凸塊基膜之該邊緣部分及該凸塊基膜周圍之該第一有機絕緣層,同時與該第一有機絕緣層接觸,該第二有機絕緣層具備曝露該凸塊基膜之一表面之一第一開口;及 一焊料凸塊,其覆蓋該第一開口並與該凸塊基膜接觸。
  17. 如請求項16之半導體裝置,其中構成該第二有機絕緣層之一材料進入該第一有機絕緣層與該凸塊基膜之間的一間隙。
  18. 如請求項16或17之半導體裝置,其進一步包含: 用作一信號佈線之一金屬佈線,其設置於該半導體區域上,其中該第一有機絕緣層具有自其曝露該金屬佈線之一第二開口。
  19. 如請求項18之半導體裝置,其進一步包含: 用作一接地佈線之一第一金屬膜,其設置於該第一有機絕緣層上之一接地佈線區域中;及 用作該信號佈線之一第二金屬膜,其設置於與該接地佈線區域隔離之一信號佈線區域中,並通過該第二開口連接至該金屬佈線。
  20. 如請求項19之半導體裝置,其中該凸塊基膜包括覆蓋該第一金屬膜之一第一部分,及與該第一部分分離並覆蓋該第二金屬膜之一第二部分。
TW109106590A 2019-02-28 2020-02-27 製造半導體裝置之方法及半導體裝置 TWI822967B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019035719A JP7176169B2 (ja) 2019-02-28 2019-02-28 半導体装置の製造方法及び半導体装置
JP2019-035719 2019-02-28

Publications (2)

Publication Number Publication Date
TW202103236A true TW202103236A (zh) 2021-01-16
TWI822967B TWI822967B (zh) 2023-11-21

Family

ID=72237179

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109106590A TWI822967B (zh) 2019-02-28 2020-02-27 製造半導體裝置之方法及半導體裝置

Country Status (4)

Country Link
US (1) US11270967B2 (zh)
JP (1) JP7176169B2 (zh)
CN (1) CN111627825A (zh)
TW (1) TWI822967B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210126310A (ko) * 2020-04-10 2021-10-20 삼성전자주식회사 씨드 구조체를 갖는 반도체 소자 및 그 형성 방법
WO2022249526A1 (ja) * 2021-05-25 2022-12-01 ソニーセミコンダクタソリューションズ株式会社 半導体パッケージおよび電子機器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6519842B2 (en) * 1999-12-10 2003-02-18 Ebara Corporation Method for mounting semiconductor device
JP2005150578A (ja) 2003-11-19 2005-06-09 Renesas Technology Corp 半導体装置及びその製造方法
JP6425532B2 (ja) * 2014-12-17 2018-11-21 ルネサスエレクトロニクス株式会社 半導体装置
JP6705592B2 (ja) * 2016-06-20 2020-06-03 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP2018006391A (ja) * 2016-06-28 2018-01-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2020141054A (ja) 2020-09-03
CN111627825A (zh) 2020-09-04
US11270967B2 (en) 2022-03-08
TWI822967B (zh) 2023-11-21
JP7176169B2 (ja) 2022-11-22
US20200279822A1 (en) 2020-09-03

Similar Documents

Publication Publication Date Title
US9653592B2 (en) Method for fabricating semiconductor device and semiconductor device
US10283472B2 (en) Electrode for a semiconductor device of a ball grid array (BGA) type
TWI705570B (zh) 半導體裝置及其製造方法
US8907407B2 (en) Semiconductor device covered by front electrode layer and back electrode layer
TWI822967B (zh) 製造半導體裝置之方法及半導體裝置
JP5952998B2 (ja) 半導体装置の製造方法
JP2019102756A (ja) 半導体装置
JP2020017647A (ja) 半導体装置の製造方法
EP2996155B1 (en) Semiconductor device and method for manufacturing a semiconductor device
JP6874928B2 (ja) 半導体装置
JP5096675B2 (ja) 半導体装置の製造方法および半導体装置
TWI802705B (zh) 半導體裝置之製造方法
US20210091023A1 (en) Semiconductor device
US11594507B2 (en) Method for manufacturing semiconductor device
JP6029060B2 (ja) 半導体装置
JP6776501B2 (ja) 半導体装置の製造方法
JP2020136459A (ja) 半導体装置の製造方法および半導体装置
JPS62156878A (ja) 半導体装置