TW202101720A - 封裝結構 - Google Patents

封裝結構 Download PDF

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TW202101720A
TW202101720A TW109115947A TW109115947A TW202101720A TW 202101720 A TW202101720 A TW 202101720A TW 109115947 A TW109115947 A TW 109115947A TW 109115947 A TW109115947 A TW 109115947A TW 202101720 A TW202101720 A TW 202101720A
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Taiwan
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conductive
layer
substrate
hole portion
opening
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TW109115947A
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TWI853931B (zh
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鄭志楷
林宗澍
陳琮瑜
胡憲斌
魏文信
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台灣積體電路製造股份有限公司
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Abstract

本揭露之一些實施例提供一種封裝結構及其形成方法。封裝結構包括一第一通孔結構以及一半導體晶粒。第一通孔結構形成在一基板中。半導體晶粒形成在第一通孔結構下方。封裝結構更包括一導電結構。導電結構形成在基板上方的一護層中。導電結構包括一第一導孔部分以及一第二導孔部分，第一導孔部分係直接地在第一通孔結構上方，且沒有導電材料係直接地在第二導孔部分下方並直接接觸第二導孔部分。

Description

封裝結構
本揭露之一些實施例係有關於一種封裝結構。
半導體裝置在各種電子應用中被使用，例如，個人電腦、手機、數位相機以及其他電子設備。通常藉由在半導體基板上方依序地沉積絕緣層或介電層、導電層以及半導體材料層以及使用微影製程圖案化各種材料層以形成其上的電路組件以及元件來製造半導體裝置。通常在單一半導體晶圓上製造出許多積體電路，並且透過沿著在積體電路之間劃定的線切割而分隔出晶圓上個別的晶粒。個別的晶粒通常分開地封裝，例如，在多晶圓模組中或在其他封裝類型中。
已經開始發產新穎的封裝技術，例如，層疊封裝（package on package, PoP），其中具有裝置晶粒的頂部封裝接合至具有另一裝置晶粒的底部封裝。透過採用新穎的封裝技術，具有不同或相似功能的各種封裝可被整合在一起。
儘管現有的封裝結構以及製造封裝結構之方法已經一般地適用於所欲達成的目的，但是並非在所有方面都全然地令人滿意。
本揭露之一些實施例提供一種封裝結構。封裝結構包括一第一通孔結構以及一半導體晶粒。第一通孔結構形成在一基板中。半導體晶粒形成在第一通孔結構下方。封裝結構更包括一導電結構。導電結構形成在基板上方的一護層中。導電結構包括一第一導孔部分以及一第二導孔部分，第一導孔部分係直接地在第一通孔結構上方，且沒有導電材料係直接地在第二導孔部分下方並直接接觸第二導孔部分。
本揭露之一些實施例提供一種封裝結構。封裝結構包括一通孔結構以及一第一半導體晶粒。通孔結構形成在一封裝層中。第一半導體晶粒形成鄰近於通孔結構。封裝結構包括一第一導孔部分以及一第二導孔部分。第一導孔部分直接地在通孔結構上。第二導孔部分鄰近於第一導孔部分。第二導孔部分在一鉛直方向上具有一第一端以及一第二端，且第一端直接接觸封裝層。封裝結構亦包括一第一線部分以及一第二線部分。第一線部分形成在第一導孔部分上。第二線部分形成在第二導孔部分上。第一線部分連接至第二線部分，且第二導孔部分之第二端直接接觸第二線部分。封裝結構更包括一連接器。連接器形成在第二導孔部分上。連接器包括一突出部，且第二導孔部分係直接地在連接器之突出部下方。
本揭露之一些實施例提供一種形成封裝結構之方法。方法包括在一基板中形成一通孔結構，並在基板下方形成一半導體晶粒。方法更包括在基板上方形成一第一護層，並在第一護層中形成一第一開口以及一第二開口。第一開口暴露通孔結構，第二開口暴露基板，第一開口俯視時具有一圓形形狀，且第二開口俯視時具有一圓形形狀。方法亦包括在第一開口以及第二開口中形成一導電材料，且導電材料亦在第一護層上方形成，以形成一導電結構。導電結構包括在第一開口中的一第一導孔部分以及在第二開口中的一第二導孔部分。第一導孔部分係直接地在通孔結構上方，且第二導孔部分之底表面直接接觸基板。
以下的揭露內容提供許多不同的實施例或範例以實施本揭露之不同特徵。以下敘述各個構件以及排列方式之特定範例，以簡化本揭露。當然，範例僅供說明用且意欲不限於此。例如，若說明書敘述了第一特徵形成於第二特徵上方，即表示可包括上述第一特徵與上述第二特徵係直接接觸的實施例，亦可包括有額外特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可未直接接觸的實施例。除此之外，在各種範例中，本揭露可能使用重複的參考符號及/或字母。這樣的重複係為了簡化以及清楚之目的，並不表示所討論的各種實施例及/或配置之間的關聯。
描述了一些變異的實施例。在本揭露之各方面的圖式以及示例性的實施例中，類似的參考符號係用於表示類似的元件。應理解的是，可在方法之前、期間以及之後提供額外的操作，而且，在方法之其他實施例中，可取代或省略一些所描述的操作。
亦可包括其他特徵以及製程。例如，可包括測試結構，以幫助三維封裝或三維積體電路裝置之驗證測試。測試結構可包括，例如，形成在重分布層中或在基板上的測試墊，其允許測試三維封裝或三維積體電路、使用探測針及/或探測卡等。可在中間結構以及最終結構上執行驗證測試。額外地，在此揭露的結構以及方法可與合併了現有良好晶粒之中間驗證的測試方法結合使用，以增加良率並降低成本。
本揭露之一些實施例提供了封裝結構以及其形成方法。第1A圖至第1I圖示出根據本揭露之一些實施例來形成一封裝結構100a之各個階段之剖面圖。封裝結構100a可為基板上的晶圓上的晶片（CoWoS）或其它合適的封裝。封裝結構100a包括形成在一半導體晶粒上方的一通孔結構以及在通孔結構上方的一導電結構。導電結構包括一第一導孔部分以及第二導孔部分。第一導孔部分的兩端可用於連接，但是第二導孔部分僅有一端可用於連接。形成第二導孔部分係用於降低應力並防止形成裂痕以及空隙。
如第1A圖所示，提供一基板102。基板102包括一前表面102a以及一後表面102b。基板102可由矽或其它半導體材料製成。可選地或額外地，基板102可包括其他元素半導體材料，例如：鍺。在一些實施例中，基板102由化合物半導體製成，例如：碳化矽、砷化鎵、砷化銦或磷化銦。在一些實施例中，基板102由合金半導體製成，例如：矽鍺、碳化矽鍺、磷化鎵砷，或磷化銦鎵。在一些實施例中，基板102包括磊晶層。例如，基板102具有磊晶層，覆蓋一塊體（bulk）半導體。
在基板102中形成數個導電結構104。導電結構104從基板102之前表面102a朝著基板102之後表面102b延伸。在一些實施例中，透過形成從基板102之前表面102a延伸的數個溝槽（未示出）來形成導電結構104。之後，將一阻障層103填充至每一溝槽中，並將導電結構104形成在阻障層103上以及每個溝槽中。
在導電結構104以及基板102上方形成一內連線結構110。內連線結構110可作為用於佈線的重分布（redistribution, RDL）結構。內連線結構110包括形成在多個介電層112中的多個導電層114以及多個導電墊116。在一些實施例中，為了作為接合墊，導電墊116暴露於最頂部的介電層112之頂表面，或者，導電墊116從最頂部的介電層112之頂表面突出。
介電層112可由一種或多種的聚合物材料製成或包括一種或多種的聚合物材料。一種或多種的聚合物材料可包括聚苯并㗁唑（polybenzoxazole, PBO）、聚醯亞胺（PI）、一種或多種其他合適的聚合物材料或前述材料之組合。在一些實施例中，一些或全部的介電層112由聚合物材料以外的介電材料製成或包括介電材料。介電材料可包括氧化矽、碳化矽、氮化矽、氧氮化矽、一種或多種其他合適的材料或前述材料之組合。
導電層114以及導電墊116可由銅（Cu）、銅合金、鋁（Al）、鋁合金、鎢（W）、鎢合金、鈦（Ti）、鈦合金、鉭（Ta）或鉭合金製成。在一些實施例中，透過電鍍、無電電鍍、印製（printing）、化學氣相沉積（chemical vapor deposition, CVD）製程或物理氣相沉積（physical vapor deposition, PVD）製程來形成導電層114以及導電墊116。
之後，如第1B圖所示，根據本揭露之一些實施例，在導電層116上方形成一半導體晶粒120。半導體晶粒120包括一基板121以及基板121上方的一內連線結構122。半導體晶粒120之內連線結構122包括數個導電層124。
在一些實施例中，從一晶圓切割出半導體晶粒120，且半導體晶粒120可為一「已知良好晶粒（known-good-die）」。半導體晶粒120可為晶片上系統（system-on-chip, SoC）晶片或記憶體晶粒。在一些其它實施例中，半導體晶粒120係一積體電路上系統（system on integrated circuit, SoIC）裝置，其包括二個或更多具有整合功能的晶片。在一些實施例中，記憶體晶粒包括一靜態隨機存取記憶體（static random access memory, SRAM）裝置、一動態隨機存取記憶體（dynamic random access memory, DRAM）裝置、一高頻寬記憶體（high bandwidth memory, HBM）或另一記憶體晶粒。半導體晶粒120之數量不限於二個，且可根據實際應用調整數量。
在一些實施例中，在半導體晶粒120之導電層124下方形成數個導電墊126，且每一個導電墊126透過數個導電連接器128接合至每一個導電墊116。
導電墊126由金屬材料製成，例如，銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭或鉭合金。在一些實施例中，透過電鍍、無電電鍍、印製、化學氣相沉積製程或物理氣相沉積製程來形成導電墊126。
導電連接器128由焊料材料製成，例如，錫（Sn），錫-銀（SnAg）、錫-鉛（SnPb）、錫-銅（SnCu）、錫-銀-銅（SnAgCu）、錫-銀-鋅（SnAgZn）、錫-鋅（SnZn）、錫-鉍-銦（SnBiIn）、錫-銦（SnIn）、錫-金（SnAu）、錫-鋅-銦（SnZnIn）、錫-銀-銻（SnAgSb）或其他適用的材料。在一些實施例中，透過電鍍、無電電鍍、印製、化學氣相沉積製程或物理氣相沉積製程來形成導電連接器128。
接下來，如第1C圖所示，根據本揭露之一些實施例，在半導體晶粒120與內連線結構110之間形成一底部充填層130。底部充填層130圍繞並保護導電連接器128。在一些實施例中，底部充填層130直接接觸導電連接器128。
在一些實施例中，底部充填層130由聚合物材料製成或包括聚合物材料。底部充填層130可包括環氧基樹脂。在一些實施例中，底部充填層130包括分散在環氧基樹脂中的填料（fillers）。
在一些實施例中，形成底部充填層130涉及注入製程、旋塗製程、分配製程、膜層壓製程、施加製程、一或多個其他可應用的製程或前述製程之組合。在一些實施例中，在形成底部充填層130的期間使用熱固化製程。
之後，在底部充填層130上方形成一封裝層136。在底部充填層130與封裝層136之間具有一界面，且此界面較半導體晶粒之頂表面低。封裝層136圍繞並保護半導體晶粒120。在一些實施例中，封裝層136直接接觸半導體晶粒120之部分。
封裝層136由一可成形化合物材料製成。可成形化合物材料可包括一聚合物材料，例如，有分散的填料的環氧基樹脂。在一些實施例中，在半導體晶粒120上方施加液體可成形化合物材料。液體可成形化合物材料可流入半導體晶粒120之間的空間。之後，使用熱製程，以固化液體可成形化合物材料並將其轉換至封裝層136內。
之後，如第1D圖所示，根據本揭露之一些實施例，移除封裝層136之一部分。因此，暴露了半導體晶粒120之頂表面。半導體晶粒120之頂表面實質上與封裝層136之頂表面齊平。在合適的情形下，用語「實質上」亦可與90%或更高相符，例如：95%或更高，特別是99%或更高，包括100%。
在一些實施例中，使用平坦化製程來使得封裝層136變薄。平坦化製程可包括化學機械研磨（chemical mechanical polishing, CMP）製程、研磨（grinding）製程、蝕刻製程、其他適用的製程或前述製程之組合。
接下來，如第1E圖所示，根據一些實施例，基板102被倒置並被放置在一承載基板139上方。在一些實施例中，承載基板139係作為一暫時基板。在後續製程步驟的期間（例如，後續將更詳細描述的製程），暫時基板提供機械以及結構支撐。承載基板139由半導體材料、陶瓷材料、聚合物材料、金屬材料、其它合適的材料或前述材料之組合製成。在一些實施例中，承載基板139係玻璃基板。在一些其他實施例中，承載基板139係半導體基板，例如：矽晶圓。
之後，以承載基板139作為支撐，將基板102變薄。在一些實施例中，基板102從後表面102b變薄直到暴露導電結構104。在一些實施例中，導電結構104以及阻障層103成為暴露的並穿過變薄的基板102。因此，在基板102中形成一通孔結構108。在一些實施例中，通孔結構108係基板通孔（through substrate via, TSV）結構。在一些其它實施例中，通孔結構108可被稱為矽通孔。
之後，如第1F圖所示，根據本揭露之一些實施例，移除承載基板139，且在基板102之後表面102b形成一第一護層（passivation layer）140。在第一護層140中形成一第一開口141以暴露通孔結構108，並在第一護層140中形成一第二開口145以暴露基板102。第一開口141具有傾斜的側壁表面，且第二開口145亦具有傾斜的側壁表面。
第一護層140由聚苯并㗁唑、苯並環丁烯（benzocyclobutene, BCB）、矽氧樹脂（silicone）、丙烯酸酯、矽氧烷、其它合適的材料或前述材料之組合。在一些其他實施例中，第一護層140由非有機的材料製成。非有機材料包括氧化矽、未經摻雜的矽玻璃、氧氮化矽、氮化矽、碳化矽、其他合適的材料或前述材料之組合。在一些實施例中，透過沉積製程，例如，物理氣相沉積製程、化學氣相沉積製程或其他適用的製程來形成第一護層140。
第一開口141以及第二開口145係透過圖案化製程形成。圖案化製程包括光微影製程以及蝕刻製程。光微影製程包括光阻塗佈（例如：旋塗）、軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、清洗以及乾燥（例如：硬烘烤）。蝕刻製程可包括乾蝕刻製程或濕蝕刻製程。
第2A圖示出根據本揭露之一些實施例的第一開口141以及第二開口145沿著第1F圖之A-A’線之俯視圖。
第一開口141俯視時具有一圓形形狀，且第二開口145俯視時具有一圓形形狀。第一開口141之一直徑從頂部朝向底部逐漸縮減，且第二開口145之一直徑從頂部朝向底部逐漸縮減。在一些實施例中，第一開口141之底表面具有一第一直徑D1 ，而第二開口145之底表面具有一第二直徑D2 。第二直徑D2 大於第一直徑D1 。在一些實施例中，第一開口141之底表面之第一直徑D1 係在約15微米至約20微米的範圍內。在一些實施例中，第二開口145之底表面之第二直徑D2 係在約40微米至約50微米的範圍內。
接下來，如第1G圖所示，根據本揭露之一些實施例，在第一開口141以及第二開口145中形成一導電材料，以形成一導電結構148。因此，導電結構148包括一第一部分1481 以及一第二部分1482 。第一部分1481 包括在第一開口141中的一第一導孔部分148a以及在第一導孔部分148a上的一第一金屬部分148b。第二部分1482 包括在第二開口145中的一第二導孔部分148c以及在第二導孔部分148c上的一第二金屬部分148d。第一導孔部分148a之底表面與第二導孔部分148c之底表面齊平。第1G圖中所繪示的虛線係為了提供更方便理解的結構，但是，在第一導孔部分148a與第一金屬部分148b之間沒有實際的分界，而且，在第二導孔部分148c與第二金屬部分148d之間也沒有實際的分界。
應注意的是，第一導孔部分148a在鉛直方向上具有一第一端以及一第二端，第一端直接接觸通孔結構108，而第二端直接接觸第一金屬部分148b。第二導孔部分148c在鉛直方向上具有一第一端以及一第二端，第一端直接接觸基板102，且第二端直接接觸第二金屬部分148d。第一金屬部分148b實體地連接至第二金屬部分148d並電性連接至第二金屬部分148d。第二導孔部分148c透過第二金屬部分148d、第一金屬部分148b以及第一導孔部分148a電性連接至通孔結構108。
應注意的是，第一導孔部分148a的兩端可用於電性連接至其他導電材料，但是第二導孔部分148c僅有一端可用於電性連接至其他導電材料。第二導孔部分148c之底表面之整體直接接觸基板102。因此，沒有導電層或導電材料係直接地在第二導孔部分148c下方，而且，沒有導電層或導電材料直接接觸第二導孔部分148c。第二導孔部分148c之底表面並未直接接觸導電材料或導電層。第一金屬部分148b具有凹入的頂表面，且第二金屬部分148d亦具有凹入的頂表面。第二導孔部分148c係介於二個相鄰的通孔結構108之間。
在第一開口141以及第二開口145中以及基板102上方形成導電材料之後，透過諸如乾蝕刻製程或濕蝕刻的蝕刻製程移除一部分的導電材料，以形成導電結構148。
導電材料可由銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭或鉭合金製成。在一些實施例中，透過電鍍、無電電鍍、印製、化學氣相沉積製程或物理氣相沉積製程來形成導電材料。
第2B圖示出根據本揭露之一些實施例的第一導孔部分148a以及第二導孔部分148c沿著第1G圖之B-B’線之俯視圖。
如第2B圖所示，該第二導孔部分148c在水平方向上沿著B-B’線藉由第一護層140與第一導孔部分148a分隔。第二導孔部分148c之寬度或直徑大於第一導孔部分148a之寬度或直徑。
第2C圖示出根據本揭露之一些實施例的第一導孔部分148a以及第二導孔部分148c之俯視圖。第1G圖示出根據本揭露之一些實施例沿著第2C圖之C-C’線之剖面圖。第2B圖係第2C圖之一部分，且第2C圖示出了第二導孔部分148c與半導體晶粒120之間的位置關係。
如第2C圖所示，在一些實施例中，第二導孔部分148c係位於外圍區域，其在半導體晶粒120之外。第二導孔部分148c係位於半導體晶粒120之角落。在一些實施例中，第二導孔部分148c係位於二個相鄰半導體晶粒120之間的中間部分。在一些其他實施例中，第二導孔部分148c係直接地位於半導體晶粒120上。
第2D圖示出根據本揭露之一些實施例的第一導孔部分148a以及第二導孔部分148c沿著第1G圖之D-D’線之俯視圖。
如第2D圖所示，第一金屬部分148b以及第二金屬部分148d俯視時形成多邊形形狀，例如，八邊形形狀。第一金屬部分148b重疊於通孔結構108。第一金屬部分148b以及第二金屬部分148d覆蓋第一導孔部分148a以及第二導孔部分148c。更具體地，第一導孔部分148a（以虛線示出）以及第二導孔部分148c（以虛線示出）係直接地在第一金屬部分148b以及第二金屬部148d下方。
第3圖示出根據本揭露之一些實施例的第1G圖中的區域A之放大圖。第一導孔部分148a之底表面具有一第一直徑Da，且第一金屬部分148b之底表面具有一第二直徑Db。第二導孔部分148c之底表面具有一第三直徑Dc，且第二金屬部分148d之底表面具有一第四直徑Dd。第一直徑Da小於第三直徑Dc，且第二直徑Db小於第四直徑Dd。第二直徑Db小於第三直徑Dc。在一些實施例中，第一直徑Da係在約15微米至約20微米的範圍內，且第二直徑Db係在約18微米至約23微米的範圍內。在一些實施例中，第三直徑Dc係在約40微米至約50微米的範圍內，且第四直徑Dd係在約45微米至約55微米的範圍內。
在第一導孔部分148a之邊緣與第二導孔部分148c之邊緣之間的距離為一第一距離S1 。在一些實施例中，第一距離S1 小於導電結構148之第二導孔部分148c之直徑。在一些實施例中，第一距離S1 係在約10微米至約15微米的範圍內。若第一距離S1 小於10微米，在第一導孔部分148a以及第二導孔部分148c中產生的應力可能無法達到平衡並造成不想要的裂痕。若第一距離S1 大於15微米，導電結構148之尺寸可能太大而佔用過多的佈線面積。
之後，如第1H圖所示，根據本揭露之一些實施例，在第一護層140上方以及導電結構148上形成一第二護層150。之後，移除第二護層150之一部分以形成一第三開口151。第三開口151係直接地在第二金屬部分148d上方。
接下來，如第1I圖所示，根據本揭露之一些實施例，在第三開口151中形成一凸塊下金屬（under bump metallurgy, UBM）層155，並在凸塊下金屬層155上方形成一導電連接器156。凸塊下金屬層155係直接地在導電結構148之第二導孔部分148c上方。導電連接器156透過凸塊下金屬層155電性連接至導電結構148。導電連接器156重疊於通孔結構108之一部分。
凸塊下金屬層155可由導電材料製成，例如：銅、銅合金、鋁、鋁合金、鎢、鎢合金、鈦、鈦合金、鉭或鉭合金。除此之外，凸塊下金屬層155可含有黏著層及/或濕潤層（wetting layer）。在一些實施例中，凸塊下金屬層155進一步包括一銅晶種層。在一些實施例中，凸塊下金屬層155包括由Ti/Cu製成的黏著層以及由Cu製成的濕潤層。在一些實施例中，凸塊下金屬層155透過電鍍製程形成，例如，電化學電鍍製程或無電製程。
在一些實施例中，導電連接器156由一金屬層製成，例如，銅、銅合金、鎳、鎳合金、鋁、鋁合金、錫、錫合金、鉛、鉛合金、銀、銀合金或前述金屬或合金之組合。在一些實施例中，導電連接器156透過電鍍製程形成，例如，電化學電鍍製程或無電製程。
導電連接器156包括一突出部156a以及一頂部156b。突出部156a形成在第三開口151中，且頂部156b形成在突出部156a上方。突出部156a朝向內連線結構110以及通孔結構108延伸。突出部156a埋入在第一護層140中。第1I圖中所繪示的虛線係為了提供更方便理解的結構，但是，在突出部156a與頂部156b之間沒有實際的分界或邊界。
由於導電結構148以及第一護層140由不同的材料製成，導電結構148之熱膨脹係數（coefficient of thermal expansion, CTE）與第一護層140之熱膨脹係數失配。隨著封裝結構100a微縮化，結構（例如，護層以及導電材料（重分布層））之材料之間的熱膨脹係數的差異，導致應力累積在導電結構/護層的界面。除此之外，由於導電連接器156相對於通孔結構108偏移，第一區上的應力（通孔結構108正上方）以及第二區上的應力（導電連接器156正下方）彼此不同且並未達到平衡。這樣不平衡的應力可能導致在封裝製程的期間導電結構產生裂痕或護層中生成空隙。
應注意的是，由於通孔結構108並未與導電連接器156對齊，第二導孔部分148c係直接地在導電連接器156下方，以作為支撐並平衡應力。更具體地，第二導孔部分148c係直接地在導電連接器156之突出部156a下方，以降低應力。因此，可防止裂痕並提高封裝結構100a之可靠性。
第1I’圖示出根據本揭露之一些實施例的一封裝結構100b之剖面圖。除了在基板102與第一護層140之間所形成的一絕緣層109，封裝結構100b類似於或等同於第1I圖中的第一封裝結構100a。用於形成封裝結構100b的製程以及材料可類似於或等同於形成封裝結構100b的製程以及材料，且在此不再贅述。
如第1I'圖所示，絕緣層109提供絕緣效果。應理解的是，沒有導電材料或導電層係直接地在導電結構148之第二導孔部分148c下方或直接接觸導電結構148之第二導孔部分148c。第二導孔部分148c之底表面直接接觸絕緣層109。在一些實施例中，絕緣層109由氮化矽或氧化矽製成。
第4A圖至第4B圖示出根據本揭露之一些實施例來形成一封裝結構100c之導電結構148之第一部分1481 以及第二部分1482 之各個階段之剖面圖。除了第二導孔部分148c之俯視形狀具有一環形形狀，封裝結構100c類似於或等同於第1I圖中的第一封裝結構100a。
如第4A圖所示，第一護層140中形成第一開口141以及第二開口145。第二開口145具有一第一部分145a以及一第二部分145b，且第一部分145a連接至第二部分145b，以形成俯視時的一環形形狀。
之後，如第4B圖所示，根據本揭露之一些實施例，在第一開口141以及第二開口145中形成導電材料，以形成導電結構148。
導電結構148包括一第一部分1481 以及一第二部分1482 。第一部分1481 包括在第一開口141中的一第一導孔部分148a以及在第一導孔部分148a上的一第一金屬部分148b。第二部分1482 包括在第二開口145中的一第二導孔部分148c以及在第二導孔部分148c上的一第二金屬部分148d。第1G圖中所繪示的虛線係為了提供更方便理解的結構，但是，在第一導孔部分148a與第一金屬部分148b之間沒有實際的分界，而且，在第二導孔部分148c與第二金屬部分148d之間也沒有實際的分界。
第4C圖示出根據本揭露之一些實施例的第一導孔部分148a以及第二導孔部分148c沿著第4B圖之C-C’線之俯視圖。如第4C圖所示，第二導孔部分148c俯視時具有環形形狀。
第5A圖示出根據本揭露之一些實施例的導電結構148之俯視圖。第1G圖示出根據本揭露之一些實施例的封裝結構100a沿著第5A圖之E-E’線之剖面圖。
如第5A圖所示，俯視時，通孔結構108（虛線）具有一圓形形狀，第一導孔部分148a（虛線）具有一圓形形狀，且第二導孔部分148c（虛線）具有一圓形形狀。在第一導孔部分148a與第二導孔部分148c之間的距離為一第一距離S1 。第一導孔部分148a之底表面直接接觸通孔結構108，而第二導孔部分148c之底表面直接接觸基板102。
第5B圖示出根據本揭露之一些實施例在導電結構148與導電連接器156之間的位置關係之俯視圖。第1I圖示出根據本揭露之一些實施例的封裝結構100a沿著第5B圖之F-F’線之剖面圖。
如第5B圖所示，導電連接器156形成在導電結構148上方。導電結構148具有一八邊形形狀，而導電連接器156具有一橢圓形形狀。第二導孔部分148c大致位於導電連接器156中央的位置。第一導孔部分148a位於導電連接器156邊緣的位置。第二導孔部分148c之尺寸大於第一導孔部分148a之尺寸。形成第二導孔部分148c係避免應力在一些區域上累積並因此降低了應力。
在一些實施例中，在導電結構148下方有二個第一導孔部分148a。導電連接器156完全地覆蓋第一導孔部分148a之其中一者，且導電連接器156部分地覆蓋第一導孔部分148a之另外一者。在一些實施例中，導電結構148覆蓋二個第一導孔部分148a以及一個第二導孔部分148c。第一導孔部分148a之數量可大於二個，且可根據實際應用調整數量。
第二導孔部分148c之面積與導電連接器156之面積之比例在約30%至約70%的範圍內。當比例落入上述範圍內時，應力可被降低，以有效地防止裂痕以及空隙之形成。除此之外，由於較大的導電連接器156將從基板102轉移更多的應力，第二導孔部分148c之面積與導電連接器156之面積的比例應設計成落入上述範圍內，以在不影響佈線的情形下降低應力。
第6A圖至第6E圖示出根據本揭露之一些實施例來形成一封裝結構100d之各個階段之剖面圖。
如第6A圖所示，在一基板602上方形成一護層604。在一些實施例中，基板602係作為一暫時基板。在後續製程步驟的期間（例如，後續將更詳細描述的製程），暫時基板提供機械以及結構支撐。基板602由半導體材料、陶瓷材料、聚合物材料、金屬材料、其它合適的材料或前述材料之組合製成。在一些實施例中，基板602係玻璃基板。在一些其他實施例中，基板602係半導體基板，例如：矽晶圓。
護層604係透過一黏著層（未示出）沉積或層壓在基板602上。護層604提供用於接合積體電路晶粒的結構支撐並幫助降低晶粒偏移的問題，這將在以下內容進一步詳細地描述。在一些實施例中，護層604係聚合物層或含有聚合物的層。護層604係聚苯并㗁唑層、聚醯亞胺層、防焊（solder resist, SR）層、Ajinomoto公司的buildup film（ABF）層、晶粒黏著層、其他合適的層或前述層之組合。
在第一護層604上方形成一內連線結構610。內連線結構610可作為用於佈線的重分布結構。內連線結構610包括形成在多個護層612中的多個導電層614。在多個護層612中形成一導電結構648。導電結構648包括一第一部分6481 以及一第二部分6482 。第一部分6481 包括一第一導孔部分648a以及一第一金屬部分648b。第二部分6482 包括一第二導孔部分648c以及一第二金屬部分648d。
之後，一通孔結構608實體地連接至導電結構648之第一導孔部分648a並電性連接至導電結構648之第一導孔部分648a。在一些實施例中，通孔結構608被稱為載板通孔（through interposer vias, TIVS）。
在一些實施例中，通孔結構608由銅、鋁、鎳、鉑、其他合適的導電材料或前述材料之組合製成。在一些實施例中，透過電鍍製程、物理氣相沉積、化學氣相沉積、電化學沉積（electrochemical deposition）製程、分子束磊晶（molecular beam epitaxy, MBE）製程、原子層沉積（atomic layer deposition, ALD）製程或其他適用的製程來形成通孔結構608。
如第6B圖所示，根據一些實施例，透過一黏著膜619將一半導體晶粒620設置在內連線結構610上。在一些實施例中，半導體晶粒620之前側（主動面）遠離內連線結構610。半導體晶粒620之後側（非主動面）面朝內連線結構610。之後，在內連線結構610上方沉積一封裝層650。因此，通孔結構608以及半導體晶粒620透過封裝層650被封裝。
半導體晶粒620包括一基板621、一護層622以及複數個導電墊624。可在基板621中或上方形成各種裝置元件。裝置元件包括主動裝置及/或被動裝置。在一些其它實施例中，裝置元件包括圖像感測器裝置、邏輯裝置、記憶體裝置、其他適用類型的裝置或前述裝置之組合。
黏著膜619係用於將半導體晶粒620接合或附接至內連線結構610。黏著膜619包括一晶粒附接膜（die attach film, DAF）、其它合適的層或晶粒附接膜或其他合適的層之組合。在一些實施例中，封裝層650包括聚合物材料。在一些實施例中，封裝層650包括成形化合物。
之後，如第6C圖所示，根據一些實施例，在封裝層650上方形成一護層660。一導電層664形成並埋入在護層660中。導電層664電性連接至通孔結構608以及半導體晶粒620。護層660由一種或多種的介電材料製成，且護層660在隨後的接合製程的期間帶來的接合應力提供應力消除的效果。
接下來，如第6D圖所示，根據一些實施例，第6C圖中示出的結構被翻轉且附接至一承載基板667。之後，移除基板102以暴露護層604。
之後，如第6E圖所示，根據一些實施例，在護層604中形成一凸塊下金屬層675，並在凸塊下金屬層675上方形成一導電連接器676。除此之外，透過一導電連接器682在護層604上方形成一半導體晶粒680。在一些實施例中，導電連接器676的高度高於導電連接器682的高度。
導電連接器676包括一突出部676a以及形成在突出部676a上方的一頂部676b。突出部676a朝向通孔結構608延伸，且突出部676a埋入在護層604中。第6E圖中所繪示的虛線係為了提供更方便理解的結構，但是，在突出部676a與頂部676b之間沒有實際的分界或邊界。
導電連接器676透過導電層614以及第二金屬部分648d電性連接至第二導孔部分648c。第二導孔部分648c透過第二金屬部分648d、第一金屬部分648b以及第一導孔部分648a電性連接至通孔結構608。第二導孔部分648c具有連接至第二金屬部分648d的一端，且另一端直接接觸封裝層650。沒有導電材料或導電層直接地在第二導孔部分648c下方或直接接觸第二導孔部分648c。
應理解的是，形成第二導孔部分648c係用於防止應力累積在一些區域並因此降低了應力。第二導孔部分648c提供可靠的支撐。因此，可避免形成裂痕以及空隙，且提高了封裝裝置100d之可靠度。
本揭露之一些實施例提供一種封裝結構及其形成方法。封裝結構包括形成在一基板中的一第一通孔結構。一半導體晶粒形成在第一通孔結構下方，且一導電結構形成在基板上方。導電結構包括一第一部分以及一第二部分。第一部分包括一第一導孔部分以及一第一金屬部分。第二部分包括一第二導孔部分以及一第二金屬部分。導電連接器形成在導電結構上。第一導孔部分係直接地形成在第一通孔結構上，且第二導孔部分之底表面直接接觸基板。第二導孔部分係作為支撐，以降低應力。可降低產生裂痕以及空隙。因此，改善了封裝結構之品質、良率以及可靠性。
在一些實施例中，提供了一種封裝結構。封裝結構包括一第一通孔結構以及一半導體晶粒。第一通孔結構形成在一基板中。半導體晶粒形成在第一通孔結構下方。封裝結構更包括一導電結構。導電結構形成在基板上方的一護層中。導電結構包括一第一導孔部分以及一第二導孔部分，第一導孔部分係直接地在第一通孔結構上方，且沒有導電材料係直接地在第二導孔部分下方並直接接觸第二導孔部分。
在一些實施例中，導電結構更包括在第一導孔部分上方的一第一線部分以及在第二導孔部分上方的一第二線部分，且第一線部分直接接觸第二線部分。在一些實施例中，第一導孔部分之一底表面與第二導孔部分之一底表面齊平。在一些實施例中，第二導孔部分之一底表面之整體直接接觸基板。在一些實施例中，在同一水平面基準上，第二導孔部分藉由護層與第一導孔部分分隔。在一些實施例中，封裝結構更包括一凸塊下金屬層以及一連接器。凸塊下金屬層直接地在第二導孔部分上方。連接器形成在凸塊下金屬層上方。連接器包括在護層中的一突出部，且第二導孔部分係直接地在連接器之突出部下方。在一些實施例中，連接器重疊於通孔結構。
在一些實施例中，封裝結構更包括一內連線結構。內連線結構形成在第一通孔結構下方。內連線結構係介於第一通孔結構與半導體晶粒之間。在一些實施例中，第一導孔部分俯視時具有一圓形形狀，第二導孔部分俯視時具有一圓形形狀，第一導孔部分具有一第一直徑，第二導孔部分具有一第二直徑，且第二直徑大於第一直徑。在一些實施例中，封裝結構更包括一第二通孔結構。第二通孔結構形成在基板中。第二導孔部分係介於第一通孔結構與第二通孔結構之間。在一些實施例中，第二導孔部分俯視時具有一環形形狀。
在一些實施例中，提供了一種封裝結構。封裝結構包括一通孔結構以及一第一半導體晶粒。通孔結構形成在一封裝層中。第一半導體晶粒形成鄰近於通孔結構。封裝結構包括一第一導孔部分以及一第二導孔部分。第一導孔部分直接地在通孔結構上。第二導孔部分鄰近於第一導孔部分。第二導孔部分在一鉛直方向上具有一第一端以及一第二端，且第一端直接接觸封裝層。封裝結構亦包括一第一線部分以及一第二線部分。第一線部分形成在第一導孔部分上。第二線部分形成在第二導孔部分上。第一線部分連接至第二線部分，且第二導孔部分之第二端直接接觸第二線部分。封裝結構更包括一連接器。連接器形成在第二導孔部分上。連接器包括一突出部，且第二導孔部分係直接地在連接器之突出部下方。
在一些實施例中，封裝結構更包括一內連線結構。內連線結構形成在第一半導體晶粒下方。第一導孔部分透過通孔結構電性連接至內連線結構。在一些實施例中，第一導孔部分與第二導孔部分之間的一距離小於第二導孔部分之一直徑。在一些實施例中，封裝結構更包括一第二半導體晶粒。第二半導體晶粒形成在第一半導體晶粒上方。第二半導體晶粒係鄰近於連接器。在一些實施例中，第二導孔部分俯視時具有一圓形形狀，且第二導孔部分之一直徑從第二端朝向第一端逐漸縮減。
在一些實施例中，提供了一種形成封裝結構之方法。方法包括在一基板中形成一通孔結構，並在基板下方形成一半導體晶粒。方法更包括在基板上方形成一第一護層，並在第一護層中形成一第一開口以及一第二開口。第一開口暴露通孔結構，第二開口暴露基板，第一開口俯視時具有一圓形形狀，且第二開口俯視時具有一圓形形狀。方法亦包括在第一開口以及第二開口中形成一導電材料，且導電材料亦在第一護層上方形成，以形成一導電結構。導電結構包括在第一開口中的一第一導孔部分以及在第二開口中的一第二導孔部分。第一導孔部分係直接地在通孔結構上方，且第二導孔部分之底表面直接接觸基板。
在一些實施例中，方法更包括在第一護層上方形成一第二護層，在第二護層中形成一第三開口，以暴露導電結構之一部分，並在第三開口中形成一連接器。第二導孔部分係直接地在連接器下方。在一些實施例中，方法更包括形成覆蓋半導體晶粒的一底部充填層，並形成覆蓋底部充填層的一封裝層。在一些實施例中，第二導孔部分俯視時具有一環形形狀。
前面概述數個實施例之特徵，使得本技術領域中具有通常知識者可更好地理解本揭露之各方面。本技術領域中具有通常知識者應理解的是，可輕易地使用本揭露作為設計或修改其他製程以及結構的基礎，以實現在此介紹的實施例之相同目的及/或達到相同優點。本技術領域中具有通常知識者亦應理解的是，這樣的等效配置並不背離本揭露之精神以及範疇，且在不背離本揭露之精神以及範疇的情形下，可對本揭露進行各種改變、替換以及更改。
100a,100b,100c,100d:封裝結構 102,602,621:基板 102a:前表面 102b:後表面 103:阻障層 104:導電結構 108,608:通孔結構 109:絕緣層 110,122,610:內連線結構 112:介電層 114,124,614,664:導電層 116,126,624:導電墊 120,620,680:半導體晶粒 121:基板 128,156,676,682:導電連接器 130:底部充填層 136,650:封裝層 139,667:承載基板 140:第一護層 141:第一開口 145:第二開口 145a:第二開口之第一部分 145b:第二開口之第二部分 148,648:導電結構 1481, 6481:導電結構之第一部分 1482, 6482:導電結構之第二部分 148a,648a:第一導孔部分 148b,648b:第一金屬部分 148c,648c:第二導孔部分 148d,648d:第二金屬部分 150:第二護層 151:第三開口 155:凸塊下金屬層 156a,676a:突出部 156b,676b:頂部 604,612,622,660:護層 619:黏著膜 D1, Da:第一直徑 D2, Db:第二直徑 Dc:第三直徑 Dd:第四直徑 S1:第一距離
當閱讀所附圖式時，從以下的詳細描述能最佳理解本揭露之各方面。應注意的是，各種特徵並不一定按照比例繪製。事實上，可能任意地放大或縮小各種特徵之尺寸，以做清楚的說明。 第1A圖至第1I圖示出根據本揭露之一些實施例來形成封裝結構之各個階段之剖面圖。 第1I’圖示出根據本揭露之一些實施例的封裝結構之剖面圖。 第2A圖示出根據本揭露之一些實施例的第一開口以及第二開口沿著第1F圖之A-A’線之俯視圖。 第2B圖示出根據本揭露之一些實施例的第一導孔部分以及第二導孔部分沿著第1G圖之B-B’線之俯視圖。 第2C圖示出根據本揭露之一些實施例的第一導孔部分以及第二導孔部分之俯視圖。 第2D圖示出根據本揭露之一些實施例的第一導孔部分以及第二導孔部分沿著第1G圖之D-D’線之俯視圖。 第3圖示出根據本揭露之一些實施例的第1G圖中的區域A之放大圖。 第4A圖至第4B圖示出根據本揭露之一些實施例來形成封裝結構之導電結構之第一部份以及第二部分之各個階段之剖面圖。 第4C圖示出根據本揭露之一些實施例的第一導孔部分以及第二導孔部分沿著第4B圖之C-C’線之俯視圖。 第5A圖示出根據本揭露之一些實施例的導電結構之俯視圖。 第5B圖示出根據本揭露之一些實施例在導電結構與導電連接器之間的位置關係之俯視圖。 第6A圖至第6E圖示出根據本揭露之一些實施例來形成封裝結構之各個階段之剖面圖。
無
100a:封裝結構
102:基板
102a:前表面
108:通孔結構
110:內連線結構
112:介電層
114:導電層
120:半導體晶粒
140:第一護層
148:導電結構
150:第二護層
155:凸塊下金屬層
156:導電連接器
156a:突出部
156b:頂部

Claims (1)

  1. 一種封裝結構，包括： 一第一通孔結構，形成在一基板中； 一半導體晶粒，形成在該第一通孔結構下方；以及 一導電結構，形成在該基板上方的一護層中； 其中該導電結構包括一第一導孔部分以及一第二導孔部分，該第一導孔部分係直接地在該第一通孔結構上方，且沒有導電材料係直接地在該第二導孔部分下方並直接接觸該第二導孔部分。
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TWI805229B (zh) * 2021-07-30 2023-06-11 力晶積成電子製造股份有限公司 晶圓結構及其製造方法
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* Cited by examiner, † Cited by third party
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TWI807719B (zh) * 2021-04-08 2023-07-01 聯發科技股份有限公司 半導體封裝及其製造方法
TWI805229B (zh) * 2021-07-30 2023-06-11 力晶積成電子製造股份有限公司 晶圓結構及其製造方法

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