TWI807719B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TWI807719B
TWI807719B TW111111090A TW111111090A TWI807719B TW I807719 B TWI807719 B TW I807719B TW 111111090 A TW111111090 A TW 111111090A TW 111111090 A TW111111090 A TW 111111090A TW I807719 B TWI807719 B TW I807719B
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Taiwan
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conductive
conductive via
hole
substrate
layer
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TW111111090A
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TW202303877A (zh
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季彥良
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聯發科技股份有限公司
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Abstract

一種半導體封裝，包括基板、第一絕緣層、導電過孔以及導電線路。 基板包括導電體。第一絕緣層形成於基板上且具有暴露出導電體的第一通孔。導電過孔形成于第一通孔內。導電線路直接連接導電過孔，且導電線路的至少一部分位於導電過孔的正上方。該半導體封裝能夠減少/降低寄生電阻。

Description

半導體封裝及其製造方法
本發明涉及一種半導體封裝及其製造方法，特別是涉及一種包括導電過孔(conductive via)的半導體封裝及其製造方法。
傳統的半導體封裝包括導電過孔(conductive via)、導電線路(conductive trace)和包括導電體的基板，其中導電過孔電連接導電線路和導電體。然而，導電過孔和導電線路之間的導電路徑導致寄生電阻(parasitic resistance)。因此，如何降低寄生電阻成為業界的一項突出任務。
在本發明的一個實施例中，提供了一種半導體封裝。半導體封裝包括基板、第一絕緣層、導電過孔以及導電線路。基板包括導電體。第一絕緣層形成於基板上且具有暴露出導電體的第一通孔。導電過孔形成于第一通孔內。導電線路直接連接至導電過孔，且所述導電線路的至少一部分位於所述導電過孔的正上方。其中，基板的導電體可以包括至少一個金屬層或至少一個導電線路。
在本發明的另一個實施例中，提供了一種半導體封裝的製造方法。該製造方法包括以下步驟：提供包含導電體的基板；在基板上形成第一絕緣層，其中第一絕緣層具有暴露出導電體的第一通孔；在第一通孔內形成導電過孔；形成與導電過孔直接連接的導電線路，且所述導電線路的至少一部分位於所述導電過孔的正上方。
當結合附圖閱讀以下對本發明實施例的詳細描述時，本發明的許多目的、特徵和優點將是顯而易見的。然而，這裡使用的附圖是為了描述的目的而不應被認為是限制性的。
本發明實施例提供的半導體封裝中的導電線路與導電過孔直接連接，使得導電線路與導電過孔之間的導電路徑較短或最短，因此可減少/降低寄生電阻。
100:半導體封裝
110:基板
120:第一絕緣層
121:第一層
122:第二層
120a:第一通孔
120u:第一絕緣層的上表面
125:第二絕緣層
1251:第三層
1252:第四層
130:導電墊
131:導電過孔
132:突出層
132s:導電過孔的上表面的一側面
132a:開口
140:導電線路
141:連接部
142:延伸部
150:第一封裝體
150a:第二通孔
160:第二封裝體
160a:開口
170:導電部
111:導電體
1311:暴露部分
131u:導電過孔的上表面
131s:導電過孔的側面
P1:導電路徑
W1:導電過孔的寬度
W2:連接部的寬度
125a:開口
在閱讀了以下詳細描述和附圖之後，本發明的上述目的和優點對於所屬領域具有通常知識者將變得更加明顯，其中：第1圖為根據本發明一實施例的半導體封裝的示意圖。
第2A圖到第2F圖示出了第1圖的半導體封裝的製造工藝。
參考第1圖，第1圖示出了根據本發明實施例的半導體封裝100的示意圖。半導體封裝100包括基板110、第一絕緣層120、第二絕緣層125、至少一個導電過孔(conductive via)131、突出層(protrusion layer)132、至少一個導電 線路140、第一封裝體(encapsulation)150、第二封裝體160和至少一個導電部170。半導體封裝100例如是晶圓級晶片規模封裝(Wafer Level Chip Scale Packaging,WLCSP)。
基板110包括至少一個導電體111。第一絕緣層120形成在基板110上並且具有暴露導電體111的至少一個第一通孔120a。導電過孔131形成在第一通孔120a內，其中，在第一通孔120a內填充導電材料形成導電過孔131。導電線路140直接連接至導電過孔131，且所述導電線路140的至少一部分位於導電過孔131的正上方。作為結果，導電線路140與導電過孔131之間的導電路徑較短或最短(垂直距離)，導電線路140與導電體111之間的導電路徑P1較短或最短(垂直距離)，因此可減少/降低寄生電阻。
如第1圖所示，基板110例如可以是晶圓(wafer)。基板110的導電體111可以包括例如至少一個金屬層、至少一個導電線路、至少一個導電過孔和/或至少一個電連接至金屬層、導電線路和/或導電過孔的電晶體。
如第1圖所示，第一絕緣層120包括第一層121和第二層122。第一層121形成在基板110上，第二層122形成在第一層121上。第一通孔120a穿過第一層121和第二層122。另外，第一層121可以由包括例如氮化矽(silicon nitride,SiN)的材料製成，第二層122可以由包括例如氧化物(oxide)的材料製成。
如第1圖所示，第二絕緣層125覆蓋第一絕緣層120和突出層132的一部分。第二絕緣層125包括第三層1251和第四層1252。第三層1251覆蓋第一絕緣層120和突出層132的一部分，並且第四層1252形成在第三層1251上。第三層1251可以由包括例如氧化物的材料製成，並且第四層1252由包括例如氮化 矽(SiN)的材料製成。此外，第二絕緣層125具有至少一開口125a，暴露出部分的導電過孔131和/或部分的突出層132。
如第1圖所示，導電過孔131通過第一通孔120a直接形成於基板110的導電體111上。換言之，導電體111與導電過孔131之間不存在非導電的物理材料。導電過孔131的至少一部分可以形成于第一通孔120a內。導電過孔131具有相對於第一絕緣層120的上表面120u突出的上表面131u。在另一實施例中，上表面131u可以相對於第一絕緣層120的上表面120u凹陷，或與第一絕緣層120的上表面120u齊平。
如第1圖所示，導電過孔131的寬度W1介於20微米(micrometer,um)和800um之間，甚至介於比這個範圍更小或更大的範圍內。寬度W1大於導電線路140的寬度W2，因此可以防止導電過孔131形成/產生凹陷(recess)、空洞(cavity)、凹處(concave)和/或裂紋(crack)。因此，本實施例的導電過孔131具有足夠的強度。此外，從頂部看，導電過孔131可以是圓形、多邊形(polygon)、橢圓形(ellipse)等。
如第1圖所示，突出層132與導電過孔131連接，相對于導電過孔131的上表面131u突出並延伸超出導電過孔131的側面131s。突出層132與導電過孔131形成導電墊130，並且半導體封裝100包括至少一個導電墊130。
在一個實施例中，導電過孔131和突出層132可以在相同的製造工藝中形成，例如濺射(sputter)。因此，導電過孔131與突出層132可形成一體結構。此外，由於濺射，突出層132形成連接導電過孔131的上表面131u的一彎曲(curved)側面132s。此外，突出層132具有暴露出導電過孔131的開口132a，其中導電線路140通過開口132a連接到導電過孔131。在材料上，導電過孔131與 突出層132的材料可以包括例如鋁、銅或其組合。此外，從頂部觀察，突出層132可以為一閉環或開環，暴露出導電過孔131的上表面131u。
如第1圖所示，至少一個導電線路140例如可以是重分佈層(RDL)的一部分。導電線路140包括一連接部141及一連接於連接部141的延伸部142，其中連接部141直接連接至導電過孔131，例如暴露部分(exposed portion)1311，且延伸部142延伸于第一封裝體150上。連接部141具有前述寬度W2。導電線路140與導電過孔131上下重疊，即導電線路140的至少一部分在基板的投影與導電過孔131在該基板的投影重疊。例如，導電線路140的連接部141與導電過孔131上下重疊，即連接部141在基板的投影與導電過孔131在該基板的投影重疊。而且，第一通孔120a、連接部141與導電過孔131上下重疊。在材料方面，導電線路140可以由包括例如鋁、銅或其組合的材料製成。
如第1圖所示，第一封裝體150覆蓋第一絕緣層120、第二絕緣層125、部分的導電過孔131和/或部分的突出層132。第一封裝體150具有至少一個暴露出的導電過孔131的暴露部分1311的第二通孔150a。導電線路140通過第二通孔150a直接連接到暴露部分1311。在實施例中，第一封裝體150可以由包括例如PBO(Polybenzoxazole，聚苯並惡唑)或模塑膠(molding compound)材料的材料製成。
第二封裝體160覆蓋導電線路140和第一封裝體150。第二封裝體160具有至少一個開口160a，該開口160a暴露出連接部141的一部分和/或導電線路140的延伸部142的至少一部分。而且，第二封裝體160的材料例如與第一封裝體150的材料相似或相同。通過相應的開口160a，每一導電部170與導電線路 140物理連接或電連接。在一實施例中，導電部170例如可以是錫球、導電柱等。
第2A圖到第2F圖示出了第1圖的半導體封裝100的製造工藝。
如第2A圖所示，提供基板110，其中基板110例如可以為晶圓，且基板110包括至少一個導電元件、至少一個金屬層、至少一個導電線路、至少一個導電過孔(未示出)和/或電性連接至金屬層、導電線路和/或導電過孔的至少一個電晶體(未示出)。
如第2A圖所示，在基板110上形成包括第一層121和第二層122的第一絕緣層120。第一絕緣層120具有至少一個第一通孔120a，暴露對應的導電體111。可以通過使用例如蝕刻形成第一通孔120a。
如第2B圖所示，在對應的第一通孔120a內形成至少一個導電過孔131和至少一個突出層132。至少一突出層132與至少一導電過孔131形成至少一個導電墊130。在本實施例中，導電過孔131與突出層132可在同一制程(manufacture process)中形成，例如濺射(sputter)，因此導電過孔131與突出層132可形成一體結構。由於濺射，突出層132形成與導電過孔131的上表面131u連接的彎曲側面132s。此外，突出層132具有暴露出導電過孔131的開口132a，並且導電線路140通過開口132a連接到導電過孔131。在材料上，導電過孔131與突出層132的材料例如可以包括鋁、銅或其組合。此外，從頂部看，突出層132可為一閉環或開環，暴露出導電過孔131的上表面131u。突出層132與導電過孔131連接，相對于導電過孔131的上表面突出，並延伸超出導電過孔131的側表面131s。
如第2C圖所示，包括第三層1251和第四層1252的第二絕緣層125形成在第一絕緣層120的一部分和突出層132的一部分上。第二絕緣層125具有至少一個開口125a，開口125a暴露出導電過孔131的一部分和突出層132的一部分。開口125a例如是通過使用蝕刻形成的。
如第2D圖所示，通過使用例如塗布(coat)、塗敷(apply)等方式將封裝體150形成於第二絕緣層125與第一絕緣層120上，其中封裝體150具有至少一個第二通孔150a，暴露出導電過孔131的暴露部分，例如暴露部分1311。第二通孔150a例如可以是使用蝕刻等方法形成。
請參照第2E圖，通過例如濺射、電鍍(plate)等方式在封裝體150上形成至少一個導電線路140。導電線路140包括連接部141以及連接至連接部141的延伸部142，其中連接部141通過第二通孔150a直接連接到導電過孔131。導電線路140與導電過孔131上下重疊，即導電線路140的至少一部分在基板的投影與導電過孔131在該基板的投影重疊。例如，導電線路140的連接部141與導電過孔131上下重疊，即連接部141在基板的投影與導電過孔131在該基板的投影重疊。此外，第一通孔120a、連接部141與導電過孔131上下重疊。在材料方面，導電線路140可以由例如包括鋁、銅或其組合的材料製成。
如第2F圖所示，覆蓋導電線路140的第二封裝體160可以例如通過塗布、塗敷等方式形成。第二封裝體160具有至少一開口160a，暴露連接部141的一部分和/或導電線路140的延伸部142的至少一部分。此外，第二封裝體160的材料例如與第一封裝體150的材料相似或相同。
然後，通過對應的開口160a形成至少一個與導電線路140物理連接或電連接的導電部170，如第1圖所示。在一實施例中，導電部170例如是錫球、導電柱等。
雖然已經根據目前認為是最實用和優選的實施例描述了本發明，但是應當理解，本發明不必限於所公開的實施例。相反，它旨在涵蓋包括在應符合最廣泛的解釋的所附請求項的精神和範圍內的各種修改和類似佈置，從而涵蓋所有這些修改和類似結構。
100:半導體封裝
110:基板
120:第一絕緣層
121:第一層
122:第二層
120a:第一通孔
120u:第一絕緣層的上表面
125:第二絕緣層
1251:第三層
1252:第四層
130:導電墊
131:導電過孔
132:突出層
132s:導電過孔的上表面的一側面
132a:開口
140:導電線路
141:連接部
142:延伸部
150:第一封裝體
150a:第二通孔
160:第二封裝體
160a:開口
170:導電部
111:導電體
1311:暴露部分
131u:導電過孔的上表面
131s:導電過孔的側面
P1:導電路徑
W1:導電過孔的寬度
W2:連接部的寬度
125a:開口

Claims (16)

  1. 一種半導體封裝，包括：基板，包括導電體；第一絕緣層，形成於所述基板上，並具有暴露出所述導電體的第一通孔；導電過孔，形成於所述第一通孔內；以及導電線路，直接連接至所述導電過孔，且所述導電線路的至少一部分位於所述導電過孔的正上方；其中，所述導電線路包括連接部和與所述連接部連接的延伸部；第一封裝體，覆蓋所述第一絕緣層，並具有第二通孔，所述第二通孔暴露出所述導電過孔的暴露部分，所述導電線路的連接部通過所述第二通孔直接連接到所述導電過孔；第二封裝體，覆蓋所述導電線路的所述第二封裝體具有至少一開口，暴露所述導電線路的連接部，其中，通過所述開口導電部與所述導電線路的連接部電連接。
  2. 如請求項1所述的半導體封裝，其中，所述導電過孔通過所述第一通孔直接形成於所述基板的導電體上。
  3. 如請求項1所述的半導體封裝，其中，所述導電過孔與所述導電體之間不存在非導電的物理材料。
  4. 如請求項1所述的半導體封裝，還包括：突出層，與所述導電過孔連接，相對於所述導電過孔的上表面突出並延伸超出所述導電過孔的側面。
  5. 如請求項4所述的半導體封裝，其中，所述突出層具有暴露出所述導電過孔的開口，所述導電線路通過所述暴露出所述導電過孔的開口連接至所述導電過孔。
  6. 如請求項1所述的半導體封裝，其中，所述導電線路的至少一部分在所述基板的投影與所述導電過孔在所述基板的投影重疊。
  7. 如請求項6所述的半導體封裝，所述連接部在所述基板的投影與所述導電過孔在所述基板的投影重疊。
  8. 如請求項4所述的半導體封裝，其中，所述突出層具有連接到所述導電過孔的上表面的彎曲側表面。
  9. 一種半導體封裝的製造方法，包括：提供包含導電體的基板；在所述基板上形成第一絕緣層，其中所述第一絕緣層具有暴露出所述導電體的第一通孔；在所述第一通孔內形成導電過孔；以及形成與所述導電過孔直接連接的導電線路，所述導電線路的至少一部分位於所述導電過孔的正上方；其中，所述導電線路包括連接部和與所述連接部連接的延伸部；在所述第一絕緣層上形成第一封裝體，其中所述第一封裝體具有暴露出所述導電過孔的暴露部分的第二通孔；所述導電線路的連接部通過所述第二通孔直接連接到所述導電過孔，形成覆蓋所述導電線路的第二封裝體，所述第二封裝體具有至少一開口，暴露所述導電線路的連接部，通過所述開口導電部與所述導電線路的連接部電連接。
  10. 如請求項9所述的製造方法，其中，在所述第一通孔內形成導電過孔的步驟中，所述導電過孔是通過所述第一通孔直接形成於所述基板的導電體上。
  11. 如請求項9所述的製造方法，其中，在所述第一通孔內形成所述導電過孔的步驟中，所述導電過孔與所述導電體之間不存在非導電的物理材料。
  12. 如請求項9所述的製造方法，還包括：形成突出層，所述突出層與所述導電過孔連接，且相對於所述導電過孔的上表面突出，並延伸超出所述導電過孔的側面。
  13. 如請求項12所述的製造方法，其中，在形成與所述導電過孔連接、相對於所述導電過孔的上表面突出並延伸超出所述導電過孔的側面的所述突出層的步驟中，所述突出層具有暴露出所述導電過孔的開口，所述導電線路通過所述暴露出所述導電過孔的開口與所述導電過孔連接。
  14. 如請求項9所述的製造方法，其中，在形成與所述導電過孔直接連接的導電線路的步驟中，所述導電線路的至少一部分在所述基板的投影與所述導電過孔在所述基板的投影重疊。
  15. 如請求項14所述的製造方法，其中，所述連接部在所述基板的投影與所述導電過孔在所述基板的投影重疊。
  16. 如請求項12所述的製造方法，其中，在形成與所述導電過孔連接、相對於所述導電過孔的上表面突出並延伸超出所述導電過孔的側面的所述突出層的步驟中，所述突出層具有連接到所述導電過孔的上表面的彎曲的側表面。
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