TW202033963A - Chip carrier - Google Patents

Chip carrier Download PDF

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TW202033963A
TW202033963A TW108107879A TW108107879A TW202033963A TW 202033963 A TW202033963 A TW 202033963A TW 108107879 A TW108107879 A TW 108107879A TW 108107879 A TW108107879 A TW 108107879A TW 202033963 A TW202033963 A TW 202033963A
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Taiwan
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wafer
placement areas
chip
grooves
carrier
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TW108107879A
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Chinese (zh)
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TWI737967B (en
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蔡秋籐
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復格企業股份有限公司
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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A chip carrier is provided, and includes a bearing surface, a plurality of grooves, a plurality of vacuum suction holes, and a plurality of blocks. The grooves are recessed on the bearing surface and disposed along a lateral direction and a longitudinal direction respectively, so that the bearing surface defines a plurality of chip placement areas. The vacuum suction holes are disposed on the bearing surface, and located in each of the chip placement areas. The blocks are disposed in the grooves respectively corresponding to the chip placement areas, and protrude from the bearing surface. Therefore, the chip carrier can carry a plurality of chips to be tested, thereby improving the testing efficiency.

Description

晶片承載座 Wafer carrier

本發明是關於一種承載座,特別是關於一種晶片承載座。 The present invention relates to a bearing seat, in particular to a wafer bearing seat.

晶片承載座普遍裝載於晶片測試裝置中,供一待測晶片放置於其上,然後晶片測試裝置的探針接觸該晶片的接點,以測試該晶片的電氣特性等。 The wafer carrier is generally loaded in a wafer testing device, on which a wafer to be tested is placed, and then the probe of the wafer testing device contacts the contact of the wafer to test the electrical characteristics of the wafer.

目前業界的作法是,一台晶片測試裝置具有一個晶片承載座,其僅能承載及測試一個晶片;當一個晶片測試完後,將該晶片從晶片承載座上移除,然後下一個待測晶片再放置於晶片承載座上。因此,若有複數個晶片欲同時測試時,需準備複數台晶片測試裝置來分別為之。然而,因為需要多台的晶片測試裝置,測試成本將會增加,且還需較多的空間來擺動這些晶片的測試裝置;另外,這些晶片測試裝置的保養及維修之時間及花費亦會增加。 The current industry practice is that a wafer testing device has a wafer carrier, which can only carry and test one wafer; when a wafer is tested, remove the wafer from the wafer carrier, and then the next wafer to be tested Place it on the wafer carrier. Therefore, if there are multiple wafers to be tested at the same time, multiple wafer testing devices need to be prepared for each. However, because multiple wafer test devices are required, the test cost will increase, and more space is needed to swing the wafer test devices; in addition, the maintenance and repair time and cost of these wafer test devices will also increase.

因此,在晶片測試之技術領域中,尚有若干問題待改善。 Therefore, in the technical field of wafer testing, there are still several problems to be improved.

本發明之一目的在於提供一種晶片承載座,其可同時地承載複數個晶片,以供晶片測試裝置同時地測試該些晶片,以節省測試時間、成本等。 One objective of the present invention is to provide a wafer carrier that can simultaneously carry a plurality of wafers, so that the wafer testing device can test the wafers at the same time, so as to save testing time and cost.

為達上述目的,本發明所揭露的晶片承載座包含:一承載面;複數個溝槽,凹設於該承載面上,且分別地以橫向與縱向來配置,以使該承載面定義出複數個晶片放置區、複數個真空吸孔,設置於該承載面上,且位於該些晶片放置區之每一者中;以及,複數個擋塊,分別對應著該些晶片放置區而設置於該些溝槽中、且突出於該承載面。 To achieve the above objective, the chip carrier disclosed in the present invention includes: a carrier surface; a plurality of grooves are recessed on the carrier surface, and are respectively arranged in the horizontal and vertical directions, so that the carrier surface defines a plurality of grooves. A wafer placement area and a plurality of vacuum suction holes are arranged on the carrying surface and located in each of the wafer placement areas; and, a plurality of stoppers are respectively provided in the wafer placement areas corresponding to the wafer placement areas These grooves protrude from the bearing surface.

較佳地,該些晶片放置區為二個晶片放置區,且該些溝槽之其中一個係位於該二個晶片放置區之間。 Preferably, the wafer placement areas are two wafer placement areas, and one of the grooves is located between the two wafer placement areas.

較佳地,該些晶片放置區為二個晶片放置區,且該二個晶片放置區位於該些溝槽之其中二個之間。 Preferably, the wafer placement areas are two wafer placement areas, and the two wafer placement areas are located between two of the trenches.

較佳地,該些晶片放置區為四個晶片放置區,且該些溝槽之其中一個係位於該四個晶片放置區之其中二個之間。 Preferably, the wafer placement areas are four wafer placement areas, and one of the grooves is located between two of the four wafer placement areas.

較佳地,該些晶片放置區為四個晶片放置區,且該四個晶片放置區被該些溝槽圍繞。 Preferably, the wafer placement areas are four wafer placement areas, and the four wafer placement areas are surrounded by the grooves.

較佳地,該些擋塊之數目係等於或大於該些晶片放置區之數目。 Preferably, the number of the stoppers is equal to or greater than the number of the chip placement areas.

本發明之另一目的在於提供一種晶片測試裝置,其可同時地測試複數個晶片,以節省測試時間、成本等。 Another object of the present invention is to provide a wafer testing device, which can test multiple wafers at the same time, so as to save testing time, cost, etc.

為達上述目的,本發明所揭露的一種晶片測試裝置包含:上述之晶片承載座及一測試頭,該測試頭係可垂直移動地設置於該晶片承載座之該承載面上方。 In order to achieve the above objective, a wafer testing device disclosed in the present invention includes: the above-mentioned wafer carrier and a test head, and the test head is vertically movably arranged above the carrier surface of the wafer carrier.

較佳地,該晶片測試裝置,更包含一位置調整器,而該晶片承載座設置於該位置調整器上。 Preferably, the wafer testing device further includes a position adjuster, and the wafer carrier is disposed on the position adjuster.

較佳地,該晶片測試裝置,更包含一晶片推移器,該晶片推移器可水平移動地設置於該承載面之上方。 Preferably, the wafer testing device further includes a wafer pusher, and the wafer pusher is horizontally movable and disposed above the carrying surface.

較佳地,該測試頭包含複數個探針,該些探針係為水平式或垂直式。 Preferably, the test head includes a plurality of probes, and the probes are horizontal or vertical.

為讓上述目的、技術特徵及優點能更明顯易懂,下文以較佳的實施例配合所附圖式進行詳細說明。 In order to make the above objectives, technical features, and advantages more obvious and understandable, a detailed description will be given below with preferred embodiments in conjunction with the accompanying drawings.

為讓上述目的、技術特徵及優點能更明顯易懂,下文以較佳的實施例配合所附圖式進行詳細說明。 In order to make the above objectives, technical features, and advantages more obvious and understandable, a detailed description will be given below with preferred embodiments in conjunction with the accompanying drawings.

10A‧‧‧晶片承載座 10A‧‧‧Chip Carrier

100‧‧‧承載面 100‧‧‧Loading surface

101‧‧‧溝槽 101‧‧‧Groove

102‧‧‧真空吸孔 102‧‧‧Vacuum suction hole

103‧‧‧擋塊 103‧‧‧Block

104‧‧‧晶片放置區 104‧‧‧Chip placement area

105‧‧‧晶片 105‧‧‧chip

20A‧‧‧晶片測試裝置 20A‧‧‧Chip Test Device

201‧‧‧測試頭 201‧‧‧Test head

201A‧‧‧探針 201A‧‧‧Probe

202‧‧‧位置調整器 202‧‧‧Position adjuster

203‧‧‧升降裝置 203‧‧‧Lifting device

204‧‧‧晶片推移器 204‧‧‧chip shifter

第1A圖係依據本發明第一較佳實施例之晶片承載座之立體分解圖;第1B圖係第1A圖所示之晶片承載座之立體組合圖;第2A圖係第1A圖所示之晶片承載座之俯視圖;第2B圖係依據本發明第二較佳實施態樣之晶片承載座之俯視圖;第2C圖及第2D圖係依據本發明第三較佳實施態樣之晶片承載座之俯視圖;第3A圖係依據本發明第四較佳實施態樣之晶片承載座之俯視圖;第3B圖係依據本發明第五較佳實施態樣之晶片承載座之俯視圖;第4A圖及第4B圖係依據本發明之第六實施例之晶片測試裝置之側視圖;以及第5A圖及第5B圖係為第4A圖所示之晶片測試裝置中,晶片推移器與晶片之示意圖。 Fig. 1A is a perspective exploded view of the chip carrier according to the first preferred embodiment of the present invention; Fig. 1B is a three-dimensional assembly view of the chip carrier shown in Fig. 1A; Fig. 2A is the one shown in Fig. 1A A top view of a chip carrier; Fig. 2B is a top view of a chip carrier according to the second preferred embodiment of the present invention; Fig. 2C and Fig. 2D are of a chip carrier according to the third preferred embodiment of the present invention Top view; Figure 3A is a top view of the chip carrier according to the fourth preferred embodiment of the present invention; Figure 3B is a top view of the chip carrier according to the fifth preferred embodiment of the present invention; Figures 4A and 4B Figures are a side view of a wafer testing device according to the sixth embodiment of the present invention; and Figures 5A and 5B are schematic diagrams of a wafer stepper and a wafer in the wafer testing device shown in Figure 4A.

以下將具體地描述根據本發明之部分具體實施例;惟,在不背離本發明之精神下,本發明尚可以多種不同形式之實施例來實踐,不應將本發明保護範圍解釋為限於說明書所陳述者。另,上述發明內容中的各技術內容亦可作為實施例的技術內容,或是作為實施例的可能變化態樣。此外,以下所述之方位(如前、後、上、下、兩側等)係為相對方位,可依據晶片測試座的使用狀態(例如水平擺放)而定義。而所稱之晶片可包含尚未封裝之晶粒(die)或是經封裝之晶粒。 The following will specifically describe some specific embodiments according to the present invention; however, without departing from the spirit of the present invention, the present invention can still be practiced in various forms of embodiments, and the protection scope of the present invention should not be construed as being limited to the specification. Presenter. In addition, each technical content in the foregoing invention content can also be used as the technical content of the embodiment or as a possible variation of the embodiment. In addition, the following orientations (such as front, back, top, bottom, sides, etc.) are relative orientations, which can be defined according to the usage state of the chip test stand (such as horizontal placement). The so-called chip may include unpackaged die or packaged die.

請參閱第1A圖、第1B圖及第2A圖所示,其為依據本發明的第一較佳實施例的晶片承載座10A的立體分解圖、組合圖及俯視圖。晶片承載座10A(下稱承載座10A)係由絕緣材料來製成,其大至呈塊狀或板狀,可安裝至後述的一晶片測試裝置20A中(如第5A圖所示)。結構上,承載座10A可包含一承載面100、複數個溝槽101、複數個真空吸孔102以及複數個擋塊103,以下依序進一步說明這些結構特徵。 Please refer to FIG. 1A, FIG. 1B, and FIG. 2A, which are a three-dimensional exploded view, an assembled view, and a top view of the chip carrier 10A according to the first preferred embodiment of the present invention. The wafer carrier 10A (hereinafter referred to as the carrier 10A) is made of an insulating material, which is as large as a block or plate, and can be installed in a wafer testing device 20A described later (as shown in FIG. 5A). Structurally, the bearing base 10A may include a bearing surface 100, a plurality of grooves 101, a plurality of vacuum suction holes 102, and a plurality of stoppers 103. These structural features are further described in order below.

承載面100可為承載座10A的上表面,且可為一平面。該些溝槽101則凹設於該承載面100上,換言之,溝槽101係開口於承載面100;該些溝槽101還分別地以橫向與縱向來配置,其中一者為橫向配置,而另一者為縱向配置,不會全部都為橫向與縱向配置。所述之橫向或縱向係與承載面100之法線方向相交錯。本實施例中,該些溝槽101可相連通,從而整體上構成一T型溝槽,但該些溝槽101亦能相分隔(圖未示)。 The bearing surface 100 may be the upper surface of the bearing seat 10A, and may be a flat surface. The grooves 101 are recessed on the bearing surface 100. In other words, the grooves 101 are open on the bearing surface 100; the grooves 101 are also arranged in the horizontal and vertical directions, one of which is arranged in the horizontal direction, and The other is vertical configuration, not all horizontal and vertical configurations. The horizontal or vertical direction is staggered with the normal direction of the bearing surface 100. In this embodiment, the trenches 101 can be connected to each other to form a T-shaped trench as a whole, but the trenches 101 can also be separated (not shown).

該些溝槽101用以使承載面100定義出複數個晶片放置區 104,該些晶片放置區104的邊界為該些溝槽101之其中之一;本實施例中,承載面100係被區分出二個晶片放置區104,而其中一個溝槽101位於二個晶片放置區104之間,另一個溝槽101則位於二個晶片放置區104之同一側,使得兩個晶片放置區104完全被該些溝槽101相分隔。 The grooves 101 are used to define a plurality of chip placement areas on the bearing surface 100 104. The boundary of the wafer placement areas 104 is one of the grooves 101; in this embodiment, the carrying surface 100 is divided into two wafer placement areas 104, and one of the grooves 101 is located on the two wafers Between the placement areas 104, another trench 101 is located on the same side of the two wafer placement areas 104, so that the two wafer placement areas 104 are completely separated by the trenches 101.

該些複數個真空吸孔102亦設置於該承載面100上,且可貫通至承載座10A的另一面(如下表面或側面);此外,每一個晶片放置區104中都有一或複數個真空吸孔102。該些真空吸孔102可連接至一真空泵(圖未示),以於承載面100上提供吸力來吸附放置於承載面100上的晶片105(第2A圖所示),避免晶片105移動而造成量測誤差、或探針損壞等。 The plurality of vacuum suction holes 102 are also provided on the carrying surface 100, and can penetrate to the other surface (the lower surface or side) of the carrier 10A; in addition, each wafer placement area 104 has one or more vacuum suction holes.孔102. The vacuum suction holes 102 can be connected to a vacuum pump (not shown) to provide suction on the carrying surface 100 to suck the wafer 105 (shown in Figure 2A) placed on the carrying surface 100 to prevent the wafer 105 from moving. Measurement error, or probe damage, etc.

該些擋塊103分別對應著該些晶片放置區104而設置於該些溝槽101中、且突出於該承載面100。具體而言,該些擋塊103係作為晶片放置區104的邊界的一部分,而放置於溝槽101中的一特定處。由於突出於承載面100,擋塊103可供於承載面100上的晶片105抵靠,從而使晶片105於承載面100上定位;因此,若晶片105之尺寸較大時,擋塊103的位置或長度可對應地調整,從而使晶片105能穩固地抵靠。另外,擋塊103可採用金屬、橡膠、塑料等各種材料,且擋塊103可藉由螺栓而鎖固於溝槽101中,或其他適當的方式來固定。 The stoppers 103 are respectively disposed in the grooves 101 corresponding to the wafer placement regions 104 and protrude from the carrying surface 100. Specifically, the stoppers 103 are placed at a specific position in the trench 101 as a part of the boundary of the wafer placement area 104. Because it protrudes from the carrying surface 100, the stopper 103 can be pressed against the wafer 105 on the carrying surface 100, so that the wafer 105 is positioned on the carrying surface 100; therefore, if the size of the wafer 105 is large, the position of the stopper 103 Or the length can be adjusted accordingly, so that the wafer 105 can be firmly pressed against. In addition, the stopper 103 can be made of various materials such as metal, rubber, plastic, etc., and the stopper 103 can be locked in the groove 101 by bolts, or fixed in other appropriate ways.

本實施例中,擋塊103係為三個,分別設置於三個溝槽101的中間處,彼此相分隔(擋塊103之數目與溝槽101之數目相等);於其他實施例中,該些擋塊103可一體相連而呈一T型結構(圖未式)。或者,其中兩個擋塊103一體相連而呈一長條擋塊,另一擋塊103則相對地較短、 且與長條擋塊相分隔(圖未式)。透過上述長條擋塊或T型擋塊之設計,可減少安裝擋塊103時為了對應晶片105之尺寸所耗費的調整時間。 In this embodiment, there are three stoppers 103, which are arranged in the middle of the three grooves 101 and are separated from each other (the number of stoppers 103 is equal to the number of grooves 101); in other embodiments, the The stoppers 103 can be integrally connected to form a T-shaped structure (not shown). Or, two of the stoppers 103 are integrally connected to form a long stopper, and the other stopper 103 is relatively short, And separated from the long block (not shown). Through the design of the above-mentioned long block or T-shaped block, the adjustment time for the size of the chip 105 when the block 103 is installed can be reduced.

上述溝槽101配置及對應的擋塊配置可有其他實施方式,將依序說明如下之第二實施例至第五實施例中。 The above groove 101 configuration and the corresponding stop configuration can have other implementations, which will be described in the following second embodiment to fifth embodiment in sequence.

請參閱第2B圖所示,於第二實施例中,該些晶片放置區104亦為二個,供二個晶片105放置,且該二個晶片放置區104位於該些溝槽101之其中二個之間。更具體地說明,該些溝槽101係從二個晶片放置區104的同一側延伸至二個晶片放置區104的左右兩側,整體構成一U型溝槽,將二個晶片放置區104圍繞其中;二個晶片放置區104並沒有被溝槽101完全分隔開。而在擋塊103方面,可設置四個擋塊103於三個溝槽101中(擋塊103之數目大於溝槽101之數目相等),兩個擋塊103對應著一個晶片放置區104。 Please refer to FIG. 2B. In the second embodiment, there are also two wafer placement areas 104 for two wafers 105 to be placed, and the two wafer placement areas 104 are located in two of the trenches 101 Between. More specifically, the grooves 101 extend from the same side of the two wafer placement areas 104 to the left and right sides of the two wafer placement areas 104, forming a U-shaped groove as a whole, surrounding the two wafer placement areas 104 Among them; the two wafer placement areas 104 are not completely separated by the trench 101. As for the stoppers 103, four stoppers 103 can be arranged in the three grooves 101 (the number of stoppers 103 is greater than the number of grooves 101 by the same amount), and the two stoppers 103 correspond to one wafer placement area 104.

於其他實施中(圖未示),兩個擋塊103亦可一體成形,構成一L形擋塊,同時抵靠晶片105的兩側邊;或者四個擋塊103為一體成形,構成一U形擋塊;或者,左右兩側的溝槽101各放置一個擋塊103,而前側的溝槽101則放置一較長的擋塊103,同時地抵靠二個晶片105之前側。 In other implementations (not shown in the figure), the two stop blocks 103 can also be integrally formed to form an L-shaped stop block, which abuts both sides of the wafer 105 at the same time; or the four stop blocks 103 are integrally formed to form a U Or, the grooves 101 on the left and right sides each place a stop 103, and the groove 101 on the front side places a longer stop 103, and simultaneously abuts the front side of the two wafers 105.

請參閱第2C圖及第2D圖所示,於第三實施例中,該些晶片放置區104為二個,且其中一個晶片放置區104位於兩個縱向排列的溝槽101之間,而另一個晶片放置區104位於一個縱向排列的溝槽101之一側。或可說,其中一個縱向排列的溝槽101位於兩個晶片放置區104之間。 Please refer to FIG. 2C and FIG. 2D. In the third embodiment, there are two wafer placement areas 104, and one of the wafer placement areas 104 is located between the two longitudinally arranged trenches 101, and the other A wafer placement area 104 is located on one side of a trench 101 arranged longitudinally. In other words, one of the longitudinally arranged trenches 101 is located between the two wafer placement areas 104.

請參閱第3A圖所示,於第四實施例中,該些晶片放置區 104為更多的四個,可供四個晶片105放置其中;該些溝槽101之其中一個係位於該四個晶片放置區104之其中二個之間。更具體地說明,該些溝槽101交錯而成的十字形溝槽,將承載面100劃分出四個相分隔的晶片放置區104,而四個晶片105分別設置於該些晶片放置區104中。接著,四個擋塊103分別地對應晶片105而設置於溝槽101中;此外,該些擋塊103亦可如上所述,一體相連而呈長型擋塊、或十字形擋塊(圖未式)等。 Please refer to FIG. 3A. In the fourth embodiment, the wafer placement areas There are four more 104, which can accommodate four wafers 105; one of the grooves 101 is located between two of the four wafer placement areas 104. More specifically, the cross-shaped grooves formed by the staggered grooves 101 divide the carrying surface 100 into four separate wafer placement areas 104, and the four wafers 105 are respectively disposed in the wafer placement areas 104 . Then, the four stoppers 103 are respectively corresponding to the chip 105 and are arranged in the groove 101; in addition, the stoppers 103 can also be connected as described above to form an elongated stopper or a cross-shaped stopper (not shown in the figure).式) etc.

請參閱第3B圖所示,於第五實施例中,該些晶片放置區104亦為四個,但該四個晶片放置區104被該些溝槽101圍繞而未分隔。因此,四個晶片105放置於四個晶片放置區104時,會被該些溝槽101圍繞。該些擋塊103對應四個晶片放置區104而設置於該些溝槽101中,且如上所述般,可一體相連而呈長型擋塊、L形擋塊、或口字形擋塊(圖未式)。 Please refer to FIG. 3B. In the fifth embodiment, the number of wafer placement areas 104 is also four, but the four wafer placement areas 104 are surrounded by the trenches 101 without being separated. Therefore, when the four wafers 105 are placed in the four wafer placement areas 104, they will be surrounded by the grooves 101. The stoppers 103 are arranged in the grooves 101 corresponding to the four chip placement areas 104, and as described above, can be integrally connected to form a long stopper, an L-shaped stopper, or a square-shaped stopper (Figure Unstyled).

另說明的是,於第四或第五實施例中,亦可僅放置二或三個晶片105於該些晶片放置區104中。 It is also noted that in the fourth or fifth embodiment, only two or three wafers 105 may be placed in the wafer placement areas 104.

藉此,上述各承載座10A之承載面100具有複數個晶片放置區104,以供複數晶片105放置其中(而非單一個晶片),且每個晶片105能抵靠至少兩個擋塊103而定位,然後再由真空吸孔102之吸力而固定。上述各承載座10A係以包含二或四個晶片放置區104為例,而藉由增加溝槽101之數目及/或調整溝槽101排列方式,承載座10A可包含更多晶片放置區104(如六、八、十二、十六、三十二個等),以承載更多的晶片105供一次性的測試。 Thereby, the bearing surface 100 of each bearing seat 10A has a plurality of chip placement areas 104 for placement of a plurality of chips 105 (instead of a single chip), and each chip 105 can abut at least two stoppers 103. It is positioned and then fixed by the suction of the vacuum suction hole 102. Each carrier 10A described above includes two or four chip placement areas 104 as an example. By increasing the number of grooves 101 and/or adjusting the arrangement of the grooves 101, the carrier 10A can include more chip placement areas 104 ( Such as six, eight, twelve, sixteen, thirty-two, etc.) to carry more chips 105 for one-time testing.

上述各承載座10A可應用於例如以下所述之的晶片測試裝置20A(下稱測試裝置20A)中,以使得測試裝置20A可同時測試複數個 晶片105。 Each of the above-mentioned carriers 10A can be applied to, for example, the wafer test device 20A (hereinafter referred to as the test device 20A) described below, so that the test device 20A can simultaneously test a plurality of Wafer 105.

請參閱第4A圖及第4B圖所示,其為依據本發明的第六較佳實施例的測試裝置20A之示意圖,測試裝置20A可包含上述實施例之承載座10A、以及一測試頭201,該測試頭201可垂直移動地設置於承載座10A之承載面100上方。具體而言,測試裝置20A可包含一升降裝置203,其設置於承載座10A旁,並且升降裝置203上搭載了該測試頭201,以使測試頭201相對於承載座10A垂直地移動。 Please refer to FIGS. 4A and 4B, which are schematic diagrams of a testing device 20A according to a sixth preferred embodiment of the present invention. The testing device 20A may include the carrier 10A of the above-mentioned embodiment and a testing head 201, The test head 201 is vertically movably arranged above the bearing surface 100 of the bearing base 10A. Specifically, the testing device 20A may include a lifting device 203, which is arranged beside the bearing base 10A, and the lifting device 203 is equipped with the test head 201 so that the test head 201 can move vertically relative to the bearing base 10A.

此外,測試頭201包含複數個探針201A,該些探針201A可為水平式(如第4A圖所示)或垂直式(如第4B圖所示),其數量及位置可因應待測試的晶片105的接點。當測試頭201下降,其探針201A可接觸到晶片105的接點,並給予接點適當地壓力,開始晶片測試作業。 In addition, the test head 201 includes a plurality of probes 201A. The probes 201A can be horizontal (as shown in Figure 4A) or vertical (as shown in Figure 4B). The number and position of the probes can be adapted to the test The contact of the chip 105. When the test head 201 is lowered, the probe 201A can contact the contact of the wafer 105 and give proper pressure to the contact to start the wafer test operation.

另外,測試裝置20A可更包含一位置調整器202,而該承載座10A設置於該位置調整器202上。易言之,承載座10A的下方設有可調整XYZ三軸或角度的位置調整器202,承載座10A可藉此進行XYZ三軸的位置或角度之調整,進而使其上的晶片105的接點可準確地對應到測試頭201之探針201A。 In addition, the testing device 20A may further include a position adjuster 202, and the carrier 10A is disposed on the position adjuster 202. In other words, under the carrier 10A is provided with a position adjuster 202 that can adjust the XYZ three-axis or angle. The carrier 10A can adjust the position or angle of the XYZ three-axis so that the chip 105 on it can be connected. The point can accurately correspond to the probe 201A of the test head 201.

接著請參閱第5A圖及第5B圖,測試裝置20A尚可更包含一晶片推移器204(下稱推移器204),推移器204可水平移動地設置於承載座10A的承載面100之上方,以推移承載面100上的晶片105至抵靠擋塊103。具體而言,推移器204之數目可因應晶片承載區104(晶片105)之數目;以二個晶片放置區104為例,可設有四個推移器240,分別以二個為一組對應一個晶片放置區104。當晶片105擺設至承載面100之後,該 些推移器204個別地水平移動至晶片105旁,然後推動晶片105至抵靠擋塊103。因一個晶片105對應設置了二個推移器204,晶片105可同時橫向及縱向地被推移。推移後,可啟動真空泵而使真空吸孔102吸附住晶片105,推移器204則移回至初始位置。 Next, referring to FIGS. 5A and 5B, the testing device 20A may further include a wafer pusher 204 (hereinafter referred to as the pusher 204). The pusher 204 is horizontally movably disposed above the carrying surface 100 of the carrying base 10A. The wafer 105 on the supporting surface 100 is pushed to the stopper 103. Specifically, the number of pushers 204 can correspond to the number of wafer carrying areas 104 (wafers 105); taking two wafer placement areas 104 as an example, four pushers 240 can be provided, with two as a group corresponding to one Wafer placement area 104. After the chip 105 is placed on the carrying surface 100, the The pushers 204 horizontally move to the side of the wafer 105 individually, and then push the wafer 105 to abut the stopper 103. Since one wafer 105 is provided with two pushers 204 corresponding to each other, the wafer 105 can be pushed horizontally and vertically at the same time. After moving, the vacuum pump can be activated to make the vacuum suction hole 102 adsorb the wafer 105, and the mover 204 moves back to the initial position.

另,推移器204亦可僅為一個,依序地推移晶片105至抵靠擋塊103。此外,如第5B圖所示,推移器204所的包含推桿或針可相對於晶片105為傾斜,推桿或針之末端接觸晶片105之一側而推動晶片105;推桿或針亦可相對晶片105為水平而推動晶片105。 In addition, there may be only one pusher 204, which pushes the wafer 105 to the stopper 103 in sequence. In addition, as shown in Fig. 5B, the push rod or needle included in the pusher 204 can be inclined with respect to the wafer 105, and the end of the push rod or needle contacts one side of the wafer 105 to push the wafer 105; the push rod or needle can also be The wafer 105 is pushed against the wafer 105 to be horizontal.

綜上所述,本發明所提出之晶片承載座可承載複數個晶片,而非單一個待測晶片,因此一個晶片測試裝置即可測試複數個晶片,從而減少晶片的測試時間及花費,並且可減少晶片測試裝置的數目及佔用的空間。 To sum up, the chip carrier proposed by the present invention can carry multiple chips instead of a single chip to be tested. Therefore, one chip testing device can test multiple chips, thereby reducing the time and cost of chip testing, and can Reduce the number of wafer test devices and the space occupied.

上述的實施例僅用來例舉本發明的實施態樣,以及闡釋本發明的技術特徵,並非用來限制本發明的保護範疇。任何熟悉此技術者可輕易完成的改變或均等性的安排均屬於本發明所主張的範圍,本發明的權利保護範圍應以申請專利範圍為準。 The above-mentioned embodiments are only used to illustrate the implementation aspects of the present invention and explain the technical features of the present invention, and are not used to limit the protection scope of the present invention. Any changes or equivalence arrangements that can be easily completed by those familiar with this technology belong to the scope of the present invention, and the scope of protection of the present invention should be subject to the scope of the patent application.

10A‧‧‧晶片承載座 10A‧‧‧Chip Carrier

100‧‧‧承載面 100‧‧‧Loading surface

101‧‧‧溝槽 101‧‧‧Groove

102‧‧‧真空吸孔 102‧‧‧Vacuum suction hole

103‧‧‧擋塊 103‧‧‧Block

104‧‧‧晶片放置區 104‧‧‧Chip placement area

Claims (10)

一種晶片承載座,包含:一承載面;複數個溝槽,凹設於該承載面上,且分別地以橫向與縱向來配置,以使該承載面定義出複數個晶片放置區;複數個真空吸孔,設置於該承載面上,且位於該些晶片放置區之每一者中,以及複數個擋塊,分別對應著該些晶片放置區而設置於該些溝槽中、且突出於該承載面。 A wafer bearing seat, comprising: a bearing surface; a plurality of grooves, recessed on the bearing surface, and arranged horizontally and longitudinally respectively, so that the bearing surface defines a plurality of wafer placement areas; and a plurality of vacuums Suction holes are provided on the carrying surface and located in each of the wafer placement areas, and a plurality of stoppers are respectively corresponding to the wafer placement areas and are provided in the grooves and protrude from the Bearing surface. 如請求項1所述之晶片承載座,其中,該些晶片放置區為二個晶片放置區,且該些溝槽之其中一個係位於該二個晶片放置區之間。 The wafer carrier according to claim 1, wherein the wafer placement areas are two wafer placement areas, and one of the grooves is located between the two wafer placement areas. 如請求項1所述之晶片承載座,其中,該些晶片放置區為二個晶片放置區,且該二個晶片放置區位於該些溝槽之其中二個之間。 The chip carrier according to claim 1, wherein the chip placement areas are two chip placement areas, and the two chip placement areas are located between two of the grooves. 如請求項1所述之晶片承載座,其中,該些晶片放置區為四個晶片放置區,且該些溝槽之其中一個係位於該四個晶片放置區之其中二個之間。 The chip carrier according to claim 1, wherein the chip placement areas are four chip placement areas, and one of the grooves is located between two of the four chip placement areas. 如請求項1所述之晶片承載座,其中,該些晶片放置區為四個晶片放置區,且該四個晶片放置區被該些溝槽圍繞。 The wafer carrier according to claim 1, wherein the wafer placement areas are four wafer placement areas, and the four wafer placement areas are surrounded by the grooves. 如請求項1至5任一項所述之晶片承載座,其中,該些擋塊之數目係等於或大於該些晶片放置區之數目。 The chip carrier according to any one of claims 1 to 5, wherein the number of the stoppers is equal to or greater than the number of the chip placement areas. 一種晶片測試裝置,包含:一如請求項1至5任一項所述之晶片承載座;以及一測試頭,係可垂直移動地設置於該晶片承載座之該承載面上方。 A wafer testing device, comprising: a wafer carrier according to any one of claims 1 to 5; and a test head, which is vertically movably arranged above the carrier surface of the wafer carrier. 如請求項7所述之晶片測試裝置,更包含一位置調整器,而該晶片承載 座設置於該位置調整器上。 The chip testing device according to claim 7, further comprising a position adjuster, and the chip carrying The seat is arranged on the position adjuster. 如請求項7所述之晶片測試裝置,更包含一晶片推移器,該晶片推移器可水平移動地設置於該承載面之上方。 The wafer testing device according to claim 7, further comprising a wafer pusher, and the wafer pusher is horizontally movably arranged above the carrying surface. 如請求項7所述之晶片測試裝置,其中,該測試頭包含複數個探針,該些探針係為水平式或垂直式。 The wafer testing device according to claim 7, wherein the test head includes a plurality of probes, and the probes are of a horizontal type or a vertical type.
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