TW202027218A - 積體電路的製造方法 - Google Patents
積體電路的製造方法 Download PDFInfo
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- TW202027218A TW202027218A TW108134744A TW108134744A TW202027218A TW 202027218 A TW202027218 A TW 202027218A TW 108134744 A TW108134744 A TW 108134744A TW 108134744 A TW108134744 A TW 108134744A TW 202027218 A TW202027218 A TW 202027218A
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
一種積體電路的製造方法,包含露出複數個通道區,所述通道區包含p型通道區和n型通道區;形成閘極介電層於露出的通道區上方;以及形成功函數金屬結構於閘極介電層上方。功函數金屬結構包含形成於p型通道區上方的p型功函數金屬部分和形成於n型通道區上方的n型功函數金屬部分,且p型功函數金屬部分比n型功函數金屬部分薄。此方法更包含形成填充金屬層於功函數金屬結構上方,使得填充金屬層直接接觸p型功函數金屬部分和n型功函數金屬部分兩者。
Description
本發明實施例是關於半導體製造技術,特別是有關於半導體裝置及積體電路的製造方法。
半導體積體電路(integrated circuit,IC)產業已經歷了指數型(exponential)成長。積體電路材料和設計上的技術進展已經產生了數個世代的積體電路,每一世代皆較前一世代具有更小且更複雜的電路。在積體電路演進的歷程中,當幾何尺寸(亦即使用生產製程可以產生的最小元件(或線))縮減時,功能密度(亦即單位晶片面積的內連接裝置數量)通常也增加。這種尺寸微縮的製程通常藉由提高生產效率及降低相關成本而提供一些效益。
這樣的尺寸微縮也增加了積體電路在加工和製造上的複雜度,並且為了實現這些進展,需要積體電路在加工和製造上的類似進展。舉例來說,已經實現了閘極取代製程,其通常包含以金屬閘極電極取代多晶矽閘極電極以改善裝置效能,其中金屬閘極電極的功函數值被設計成提供具有不同臨界電壓的不同鰭式場效電晶體。雖然提供多臨界電壓的現有鰭式場效電晶體通常已滿足其預期目的,但隨著積體電路技術縮減,它們並非在所有面向皆完全令人滿意。
根據本發明實施例中的一些實施例,提供積體電路的製造方法。此方法包含:露出複數個通道區,包含p型通道區和n型通道區;在露出的通道區上方形成閘極介電層;在閘極介電層上方形成功函數金屬結構,其中功函數金屬結構包含形成於p型通道區上方的p型功函數金屬部分和形成於n型通道區上方的n型功函數金屬部分,且其中p型功函數金屬部分比n型功函數金屬部分薄;以及在功函數金屬結構上方形成填充金屬層,使得填充金屬層直接接觸p型功函數金屬部分和n型功函數金屬部分兩者。
根據本發明實施例中的另一些實施例,提供積體電路的製造方法。此方法包含提供半導體裝置結構,其包含:基底;複數個鰭片設置於基底上方並沿著第一方向延伸;以及閘極溝槽設置於基底上方並沿著與第一方向交叉的第二方向延伸,閘極溝槽露出所述鰭片中的每一個的一部分;在所述鰭片的所述露出部分上方沉積界面層;在界面層上方沉積高介電常數介電層;在高介電常數介電層上方沉積n型功函數金屬層;基於n型功函數金屬層和高介電常數介電層之間的蝕刻選擇性而將n型功函數金屬層圖案化以露出高介電常數介電層的一部分;以及在圖案化的n型功函數金屬層和高介電常數介電層的露出部分上方沉積p型功函數金屬層。
根據本發明實施例中的又另一些實施例,提供半導體裝置。此半導體裝置包含半導體基底;複數個通道區,包含p型通道區和n型通道區,設置於半導體基底上方;以及閘極結構,包含:閘極介電層,設置於所述通道區上方;功函數金屬結構,設置於閘極介電層上方,其中功函數金屬結構包含分別設置在p型通道區和n型通道區上方的p型功函數金屬部分和n型功函數金屬部分,且其中p型功函數金屬部分比n型功函數金屬部分薄;以及填充金屬層,設置於n型功函數金屬部分和p型功函數金屬部分兩者上方。
以下內容提供了許多不同的實施例或範例,用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件上或上方,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。此外,本發明實施例在不同範例中可重複使用參考數字及/或字母。此重複是為了簡化和清楚之目的,並非代表所討論的不同實施例及/或組態之間有特定的關係。
另外,在隨後的本發明實施例中,一部件形成於另一部件上、一部件連接至及/或耦合至另一部件,可能包含形成這些部件直接接觸的實施例,也可能包含額外的部件形成於這些部件之間,使得這些部件不直接接觸的實施例。此外,空間相對用語,例如「低」、「高」、「水平」、「垂直」、「上」、「上方」、「下」、「下方」、「向上」、「向下」、「頂部」、「底部」等及前述之衍生物(例如「水平地」、「向下地」、「向上地」等)係用於簡化本發明實施例的一部件與另一部件的關係。空間相對用語是為了涵蓋包含這些部件的裝置的不同取向。另外,當以「約」、「近似」和類似的用語描述數字或數字範圍時,此用語是為了涵蓋在包含所述數字之合理範圍內的數字,例如在所述數字的+/−10%內或發明所屬技術領域中具有通常知識者理解的其他數值。舉例來說,用語「約5奈米」涵蓋4.5奈米至5.5奈米的尺寸範圍。
在製造鰭式場效電晶體裝置期間,可以實施閘極取代製程以調整與製造步驟有關的臨界電壓(threshold voltage,Vt)。舉例來說,在「閘極後製(gate-last)」製程期間,在形成例如源極/汲極部件的其他組件之前,先在基底上方形成虛設閘極結構作為佔位元件。一旦形成其他組件,就移除虛設閘極結構,並在虛設閘極結構的位置形成金屬閘極結構。可以實施多個圖案化製程以在金屬閘極結構中形成各種材料層,以提供特定裝置能力,例如多臨界電壓。多臨界電壓裝置實現了場效電晶體(field effect transistors,FET)的彈性且多樣的應用。
藉由在金屬閘極結構中堆疊多個功函數金屬(work function metal,WFM)層,已經實現了鰭式場效電晶體裝置的多臨界電壓。在一範例中,較厚的功函數金屬堆疊導致較高的功函數和較高的臨界電壓。然而,隨著裝置部件尺寸縮減,堆疊功函數金屬層時會出現許多挑戰。舉例來說,由於鰭片至鰭片節距(fin-to-fin pitches)縮減,堆疊功函數金屬層的能力變得有限,因為跨過多個鰭片的這種功函數金屬層易於合併。
本發明實施例預期使用較少功函數金屬層來實現多臨界電壓的金屬閘極結構。根據一些面向,本發明實施例揭示的功函數金屬結構包含p型功函數金屬部分,其比n型功函數金屬部分更薄但仍提供更高的功函數。在一些實施例中,基於n型功函數金屬層與高介電常數介電層之間的蝕刻選擇性,這種功函數金屬結構的製造藉由直接在高介電常數介電層上將n型功函數金屬層圖案化(在其間沒有任何高介電常數蓋層),然後在圖案化的n型功函數金屬層上方形成膠合(glue)金屬層。p型功函數金屬部分包含膠合金屬層(也作為p型功函數金屬層)但不含n型功函數金屬層,而n型部分包含膠合金屬和n型功函數金屬層兩者。因此,使p型功函數金屬部分比n型功函數金屬部分薄。這種功函數金屬結構允許極高的功函數(例如等於或大於4.8電子伏特(electron volts,eV))及/或極低的功函數(例如等於或小於4.4 eV),而無須堆疊多層功函數金屬材料。相較於具有多臨界電壓的其他功函數金屬結構,總厚度減少。因此,可以在具有較小的鰭片至鰭片節距的鰭式場效電晶體裝置中實現多臨界電壓。
現在參照第1圖,根據本發明實施例的各個面向繪示用於形成半導體裝置(又稱為裝置)200的方法100的流程圖。方法100僅是範例,並非用於將本發明實施例限制於方法100中明確描述的內容。可以在方法100之前、期間和之後提供額外的步驟,並且可以為了此方法的其他實施例而取代、消除或移動所描述的一些操作。以下結合第2A~2B圖和第3A~3L圖描述方法100,其繪示在方法100期間的半導體裝置200的一部分。第2A圖是裝置200的局部上視示意圖,而第2B圖是處於相同階段的裝置200的局部Y切割剖面示意圖。第3A~3L圖是在方法100的中間步驟中裝置200的局部Y切割剖面示意圖(與第2B圖相同的示意圖)。在鰭式場效電晶體裝置中,鰭片可以在稱為X切割方向的第一方向上延伸,且金屬閘極可以在稱為Y切割方向的第二方向上延伸。因此,第2B圖和第3A~3L圖中的Y切割剖面示意圖平行於金屬閘極的長度方向且垂直於鰭片的長度方向。
裝置200可以是在積體電路的製程期間所製造的中間裝置(或積體電路結構),其可以包含靜態隨機存取記憶體(static random-access memory,SRAM)及/或其他邏輯電路、被動組件,例如電阻器、電容器和電感器、以及主動元件,例如p型場效電晶體(p-type FETs,PFET)、n型場效電晶體(n-type FETs,NFET)、鰭式場效電晶體、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistors,MOSFET)、互補式金屬氧化物半導體(complementary metal-oxide semiconductor,CMOS)電晶體、雙極性電晶體(bipolar transistors)、高壓電晶體、高頻電晶體及/或其他儲存單元。本發明實施例不限於任何特定數量的裝置或裝置區,或限於任何特定裝置配置。舉例來說,雖然繪示的裝置200是三維鰭式場效電晶體裝置,但本發明實施例還可以提供用於製造平面場效電晶體裝置的實施例。
參照第1圖和第2A~2B圖,在方法100的開始,提供起始半導體裝置200,其包含具有第一區203和第二區205的基底202、在基底202上方形成的隔離結構208隔開裝置200的各個組件、在隔離結構208上形成的閘極間隔物212和層間介電層218。在一實施例中,第一區203包含鰭片207a,而第二區205包含兩個鰭片,鰭片207b和鰭片207c。鰭片207a~207c可以各自包含電晶體部件,例如通道區230a、230b和230c。雖然未繪示於圖式中,但是源極和汲極部件也形成於每個鰭片207a~207c上(並且由通道區230a~230c隔開)。如第2B圖所示,鰭片207a~207c從右到左對齊,但本發明實施例可以採用鰭片207a~207c的任何順序來運作,鰭片207a~207c可以彼此直接相鄰或可以不彼此直接相鄰。
在步驟102,形成閘極溝槽220和222以露出鰭片207a~207c的通道區230a~230c。如第2B圖所示,閘極間隔物212和層間介電層218界定兩個閘極溝槽220和222,將以金屬材料填充閘極溝槽220和222。從第2A圖的頂視圖,鰭片207a~207c總體而言被層間介電層218覆蓋,但閘極溝槽220和222各自露出相應的一組通道區230a~230c。為了簡化的目的,對閘極溝槽220繪示方法100的步驟(而不是閘極溝槽222,閘極溝槽222經歷相同的生產製程)。
在一些實施例中,藉由移除與鰭片207a~207c接合的虛設閘極結構來形成閘極溝槽220,藉此露出鰭片207a~207c的通道區230a~230c。在步驟102移除的虛設閘極結構可以包含一或多個材料層,例如氧化物層(即虛設閘極介電層)、多晶矽層(即虛設閘極電極)、硬遮罩層、蓋層及/或其他合適的膜層。在一實施例中,形成閘極溝槽220包含進行蝕刻製程來選擇性地移除虛設閘極結構,此蝕刻製程使用乾式蝕刻製程、濕式蝕刻製程、反應離子蝕刻(reactive ion etching,RIE)、其他合適的方法或前述之組合。乾式蝕刻製程可以使用含氯氣體、含氟氣體及/或其他蝕刻氣體。濕式蝕刻溶液可以包含氫氧化銨(NH4
OH)、氫氟酸(HF)或稀釋的氫氟酸、去離子水、四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)及/或其他合適的濕式蝕刻溶液。
如第2A和2B圖所示,基底202可以包含元素(單一元素)半導體,例如矽、鍺及/或其他合適的材料;化合物半導體,例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦及/或其他合適的材料;合金半導體,例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP及/或其他合適的材料。基底202可以是具有均勻組成的單層材料。或者,基底202可以包含具有適用於積體電路裝置製造的相似或不同組成的多個材料層。在一範例中,基底202可以是絕緣體上覆矽(silicon-on-insulator,SOI)基底,其具有矽層形成於氧化矽層上。在另一範例中,基底202可以包含導電層、半導體層、介電層、其他膜層或前述之組合。
在基底202包含場效電晶體的一些實施例中,在基底202中或基底202上形成各種摻雜區,例如源極/汲極區。取決於設計規範,可以使用例如磷或砷的p型摻質及/或例如硼或BF2
的n型摻質對摻雜區進行摻雜。摻雜區可以直接形成於基底202上、p井結構中、n井結構中、雙井(dual-well)結構中或使用凸起結構。摻雜區的形成可以藉由佈植摻質原子、原位(in-situ)摻雜的磊晶成長及/或其他合適的技術。在一些實施例中,藉由磊晶成長方法形成源極/汲極區。
第一區203可以適於形成一或多個p型鰭式場效電晶體,且第二區205可以適於形成一或多個n型鰭式場效電晶體。因此,位於鰭片207a上的通道區230a是p型通道,且分別位於鰭片207b和207c上的通道區230b和230c是n型通道。在替代實施例中,第一區203和第二區205可以適於形成具有不同臨界電壓設計規範的相似類型的鰭式場效電晶體,亦即兩者皆為n型或兩者皆為p型。第2A~2B圖中的配置僅用於說明目的,並非用於限制本發明實施例。鰭片207a~207c的製造可以使用包含微影和蝕刻製程的合適製程。微影製程可以包含形成覆蓋基底202的光阻層(光阻)、將光阻暴露於圖案、進行曝光後烘烤(post-exposure bake)製程以及將光阻顯影,以形成包含光阻的遮罩元件(未繪示)。然後,遮罩元件用於將凹槽蝕刻入基底202,將鰭片207a~207c留在基底202上。蝕刻製程可以包含乾式蝕刻,濕式蝕刻、反應離子蝕刻及/或其他合適的製程。
用於形成鰭片207a~207c的其他方法可以是合適的。舉例來說,可以使用雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程將鰭片207a~207c圖案化。通常而言,雙重圖案化或多重圖案化製程結合微影和自對準製程,舉例來說,允許產生的圖案的節距小於使用單一、直接微影製程可獲得的圖案的節距。舉例來說,在一實施例中,在基底上方形成犧牲層並且使用微影製程將犧牲層圖案化。使用自對準製程在圖案化的犧牲層旁形成間隔物。然後移除犧牲層,接著可以使用剩餘的間隔物或心軸(mandrels)將鰭片圖案化。
隔離結構208可以包含氧化矽、氮化矽、氮氧化矽、氟化物摻雜的矽酸鹽玻璃(fluoride-doped silicate glass,FSG)、低介電常數介電材料及/或其他合適的材料。隔離結構208可以包含淺溝槽隔離(shallow trench isolation,STI)部件。在一實施例中,隔離結構208的形成藉由在形成鰭片207a~207c期間蝕刻基底202中的溝槽。然後可以用上述隔離材料填充溝槽,接著進行化學機械平坦化(chemical mechanical planarization,CMP)製程。隔離結構208也可以採用其他隔離結構,例如場氧化物、矽局部氧化(local oxidation of silicon,LOCOS)及/或其他合適的結構。或者,隔離結構208可以包含例如具有一或多個熱氧化物襯層(liner layers)的多層結構。
閘極間隔物212形成閘極溝槽220的側壁。閘極間隔物212可以包含介電材料,例如氧化矽、氮化矽、碳化矽、氮氧化矽及/或其他合適的介電材料。閘極間隔物212可以是單層結構或多層結構。在一些實施例中,層間介電層218包含介電材料,例如四乙氧基矽烷(tetraethylorthosilicate,TEOS)、未摻雜的矽酸鹽玻璃或摻雜的氧化矽,例如硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、熔融石英玻璃(fused silica glass,FSG)、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、摻雜硼的矽玻璃(boron doped silicon glass,BSG)及/或其他合適的介電材料。層間介電層218可以包含具有多種介電材料的多層結構。應注意的是,雖然未繪示於第2B圖,裝置200可以包含許多額外的組件或部件,例如源極/汲極部件(形成於每個鰭片207a~207c中的通道區的兩端,但在第2B圖的剖面示意圖之外)。為了簡化的目的,在此不描述額外的組件。
參照第1圖和第3A圖,方法100在步驟104形成界面層(interfacial layer,IL)302於鰭片207a~207c上方的閘極溝槽220中。界面層302可以包含介電材料,例如氧化矽(SiOx
)或氮氧化矽(SiON)。界面層302可以形成為任何合適的厚度,例如約0.5 nm至約1.5 nm。在一實施例中,界面層302的厚度為約1 nm。界面層302的形成可以藉由任何合適的沉積技術,例如化學氧化、熱氧化、原子層沉積(atomic layer deposition,ALD)、化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)、低壓化學氣相沉積(low-pressure chemical vapor deposition,LP-CVD)、電漿增強化學氣相沉積(plasma-enhanced CVD,PE-CVD)、高密度電漿化學氣相沉積(high-density plasma CVD,HDP-CVD)、金屬有機化學氣相沉積(metal organic CVD,MO-CVD)、遠程電漿化學氣相沉積(remote plasma CVD,RP-CVD)、原子層化學氣相沉積(atomic layer CVD,AL-CVD)、常壓化學氣相沉積(atmospheric pressure CVD,AP-CVD)及/或其他合適的方法。
參考第1圖和第3B圖,方法100在步驟106在閘極溝槽220中形成高介電常數介電層304於界面層302上方。在本發明實施例中,「高介電常數(high-k)」介電質通常是指具有介電常數大於二氧化矽(SiO2
)的介電常數的一或多種材料。可以藉由原子層沉積及/或其他合適的方法將高介電常數介電層304形成為任何合適的厚度。在一實施例中,高介電常數介電層304具有約1 nm至約2 nm的厚度。替代地或額外地,高介電常數介電層304可以形成於中間材料層上方,使得高介電常數介電層304不直接接觸界面層302。在一些實施例中,高介電常數介電層304包含以鉿、鋯、矽及/或其他合適材料為主的氧化物。舉例來說,高介電常數介電層304可以包含氧化鉿(HfO2
)、氧化鉿矽(HfSiOx
)及/或氧化鉿鋯(HfZrOx
)等。因為高介電常數介電層304和界面層兩者都是用於閘極結構的介電層,它們統稱為閘極介電層305。
在形成閘極介電層305之後,在閘極介電層305上形成功函數金屬(work function metal,WFM)結構,以提供需要的功函數以調整後續電晶體的臨界電壓。每個鰭片可以用於實現具有源極、汲極、通道和閘極的鰭式場效電晶體,且鰭片的臨界電壓指的是在源極和汲極之間的通道產生導電路徑所需的最小閘極至源極電壓。臨界電壓受到各種參數的影響,參數包含閘極的功函數。隨著裝置部件尺寸縮減,在微影和圖案化製程期間實施厚功函數金屬結構提出了許多挑戰。
本發明實施例提供了使用較薄的功函數金屬結構307調變(modulating)閘極結構的臨界電壓的方法。功函數金屬結構307的形成過程在以下進一步詳細描述,但先簡要描述功函數金屬結構307的概貌是有用的。在使用在此揭示的各種製程和實施例之後,功函數金屬結構307最終可以包含多個金屬層,每個金屬層設計成實現某種期望的功函數。舉例來說,在如第3L圖(以下進一步描述)所示的最終裝置200中,功函數金屬結構307包含圖案化的p型功函數金屬層308、圖案化的n型功函數金屬層310和膠合金屬層312。此外,因為功函數金屬結構307跨越鰭片207a~207c,每個鰭片207a~207c需要不同功函數,功函數金屬結構307可以被分成多個部分(在水平「Y」方向上),每個部分對應一鰭片。舉例來說,如第3L圖所示(以下進一步描述),功函數金屬結構307包含三個部分,包含:p型功函數金屬部分307a(形成於鰭片207a中的p型通道區230a上);n型功函數金屬部分307c(形成於鰭片207c中的n型通道區230c上);以及第三、中間功函數金屬部分307b(形成於鰭片207b中的通道區230b上),其根據應用可以設計成p型或n型。在一些實施例中,由於在功函數金屬部分307a~307c中形成的不同金屬層,功函數金屬部分307a~307c中的每一個具有不同的厚度。舉例來說,如第3L圖所示(以下進一步描述),p型功函數金屬部分307a僅包含膠合金屬層312;n型功函數金屬部分307c包含n型功函數金屬層310和膠合金屬層312;中間功函數金屬部分307b包含p型功函數金屬層308、n型功函數金屬層310和膠合金屬層312。因此,p型功函數金屬部分307a比n型功函數金屬部分307c薄,n型功函數金屬部分307c又比中間功函數金屬部分307b薄。這種厚度分佈與現有的功函數金屬結構不同,現有的功函數金屬結構中p型功函數金屬部分會比n型功函數金屬部分厚(因為p型通道使用比n型通道更高的功函數)。以下描述功函數金屬結構307的形成過程。
參照第1圖和第3C圖,方法100在步驟108形成(藉由沉積)p型功函數金屬層308於閘極溝槽220中的高介電常數介電層304上。在許多實施例中,將p型功函數金屬層308設計成(就材料及/或厚度而言)與上層(例如n型功函數金屬層310)一起工作以調節鰭片207b上的功函數(並藉此調節臨界電壓)。p型功函數金屬層308可以包含具有足夠大的有效功函數的金屬,其選自但不限於氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)、碳氮化鎢(WCN)、氮化鈦鋁(TiAlN)或前述之組合。可以藉由沉積製程形成p型功函數金屬層308,沉積製程例如原子層沉積、化學氣相沉積、物理氣相沉積及/或其他合適製程。因此,取決於鰭片207b上的所需功函數,p型功函數金屬層308可具有任何合適的厚度,例如約1 nm至約2 nm。在一實施例中,為了圖案化的效率,p型功函數金屬層308的厚度小於1.5 nm。此外,參照第3C圖,在至少一實施例中,p型功函數金屬層308直接接觸高介電常數介電層304而沒有任何中間層,例如阻障層或高介電常數蓋層(例如氮化矽)。
參照第1圖和第3D~3F圖,方法100在步驟110藉由移除鰭片207a和207c上方的p型功函數金屬層308而將p型功函數金屬層308圖案化,藉此將p型功函數金屬層308留在鰭片207b上。如第3D圖所示,方法100可以先形成遮罩元件於閘極溝槽220以及層間介電層218的部分上方,遮罩元件包含光阻層404和可選的光阻底層402,光阻底層402例如底部抗反射塗層(bottom antireflective coating,BARC)。如第3E圖所示,方法100然後繼續形成開口406以露出鰭片207a和207c上(但不在鰭片207b上)的高介電常數介電層304。開口406的形成可以藉由將光阻層404和光阻底層402暴露於圖案、進行曝光後烘烤製程、以及將光阻顯影。或者,開口406的形成可以藉由蝕刻(乾式蝕刻、濕式蝕刻、反應離子蝕刻等)及/或其他合適的製程。在一實施例中,開口406的形成藉由蝕刻如第3D圖所示的光阻層404和光阻底層402的選擇部分,其中選擇性蝕刻包含乾式蝕刻製程,其利用含氮蝕刻氣體(例如N2
)、含氫蝕刻氣體(例如H2
)、含氟蝕刻氣體(例如CF4
、SF6
、CH2
F2
、CHF3
及/或C2
F6
)、含氧氣體、含氯氣體(例如Cl2
、CHCl3
、CCl4
及/或BCl3
)、含溴氣體(例如HBr及/或CHBr3
)、含碘氣體、氦氣及/或其他合適的氣體及/或電漿。在一實施例中,乾式蝕刻製程實施N2
和H2
氣體的混合物。
繼續參照第3E圖,方法100使用蝕刻製程移除閘極溝槽220中的p型功函數金屬層308的露出部分,藉此露出鰭片207a和207c上的高介電常數介電層304。可以使用任何合適的蝕刻製程,包含乾式蝕刻、濕式蝕刻、反應離子蝕刻及/或其他合適的製程。可以使用合適的蝕刻劑,例如標準清潔溶液(standard cleaning solutions)SC1(含有NH4
OH或其他鹼性溶液)和SC2(含有鹽酸、磷酸、硫酸或其他酸性溶液)來選擇性地蝕刻p型功函數金屬層308。雖然p型功函數金屬層308直接接觸高介電常數介電層304,但由於p型功函數金屬層308與高介電常數介電層304之間的蝕刻選擇性,蝕刻製程不會移除或以其他方式損壞高介電常數介電層304。在一些實施例中,蝕刻劑以比高介電常數介電層304快至少100倍的蝕刻速率移除p型功函數金屬層308。蝕刻速率這樣的顯著差異確保p型功函數金屬層308的露出部分的移除大致上不會移除或以其他方式損壞高介電常數介電層304的任何部分。如第3F圖所示,方法100然後移除光阻層404和光阻底層402。可以使用任何合適的蝕刻製程。
如第1圖和第3G圖所示,方法100在步驟112在閘極溝槽220中的圖案化p型功函數金屬層308上形成n型功函數金屬層310。在許多實施例中,將n型功函數金屬層310(就材料及/或厚度而言)設計成調整或調變鰭片207a~207c的臨界電壓。n型功函數金屬層310可以包含具有足夠低的有效功函數的金屬,選自但不限於鈦(Ti)、鋁(Al)、鈦鋁(TiAl)、碳化鋁鋁(TiAlC)、氮化鈦鋁(TiAlN)、碳化鉭(TaC)、碳化鉭矽(TaSiC)、碳化鉭鋁(TaAlC)、碳氮化鉭(TaCN)、氮化鉭矽(TaSiN)、氮化鈦矽(TiSiN)、碳化鈮鋁(NbAlC)、碳化鉿(HfC)或前述之組合。n型功函數金屬層310的形成可以藉由沉積製程,例如原子層沉積、化學氣相沉積、物理氣相沉積及/或其他合適製程。取決於鰭片207b和207c上的所需功函數,n型功函數金屬層310可以形成為合適的厚度(例如約2 nm至約3 nm)。
參照第1圖和第3H~3J圖,方法100在步驟114將n型功函數金屬層310圖案化,藉由移除n型功函數金屬層310形成於鰭片207a上的部分,同時保持形成於鰭片207b和207c上的部分。如第3H圖所示,方法100可以先在閘極溝槽220上方形成遮罩元件,然後繼續形成開口418以露出鰭片207a上的n型功函數金屬層310(但不是鰭片207b和207c上的n型功函數金屬層310)。遮罩元件可以類似於先前用於將p型功函數金屬層308圖案化(第3D和3E圖)的遮罩元件。舉例來說,遮罩元件包含光阻層504和光阻底層502,其分別類似於光阻層404和光阻底層402,如前所述。開口418的形成可以藉由任何合適的製程,例如將光阻層504和光阻底層502暴露於圖案、進行曝光後烘烤製程、將光阻顯影或蝕刻(乾式蝕刻、濕式蝕刻、反應離子蝕刻等)及/或其他合適的製程。
參照第3I圖,方法100將n型功函數金屬層310圖案化,藉由移除開口418中的n型功函數金屬層310的一部分,藉此在開口418中露出高介電常數介電層304的一部分。光阻層504和光阻底層502保護設置於鰭片207b和207c上的n型功函數金屬層310的部分免於受到步驟114中使用的蝕刻劑的影響,藉此允許n型功函數金屬層310的圖案化。可以使用任何合適的圖案化製程,包含乾式蝕刻、濕式蝕刻、反應離子蝕刻及/或其他合適的製程。可以使用任何合適的蝕刻劑,例如標準清潔溶液SC1(具有NH4
OH或其他鹼性溶液)和SC2(具有鹽酸、磷酸、硫酸或其他酸性溶液)來選擇性地蝕刻n型功函數金屬層310。
在將n型功函數金屬層310圖案化時,n型功函數金屬層310直接接觸高介電常數介電層304,由於n型功函數金屬層310和高介電常數介電層304之間的蝕刻選擇性,蝕刻劑不會移除或以其他方式損壞高介電常數介電層304。如前所述,高介電常數介電層304可以是以鉿為主的(例如氧化鉿、氧化鉿矽及/或氧化鉿鋯),而n型功函數金屬層310可以是以鈦為主的(例如鈦鋁、碳化鈦鋁、氮化鈦鋁),因此高介電常數介電層304和n型功函數金屬層310可以經歷不同的蝕刻速率。在一些實施例中,蝕刻劑以比高介電常數介電層304快至少100倍的蝕刻速率移除n型功函數金屬層310。在一實施例中,在蝕刻製程期間(包含步驟110和114),高介電常數介電層304的總厚度損失小於1埃(angstrom,Å)。高蝕刻選擇性有助於減少功函數層的總厚度。在一些實施例中,不需要在高介電常數介電層304上的高介電常數蓋層,例如氮化鈦或氮化鈦矽。因此,在此揭示的蝕刻製程簡化了生產製程並節省製造成本。
繼續參照第3I圖,當將n型功函數金屬層310圖案化時,蝕刻劑大致上不「底切(undercut)」設置於開口418的邊緣處的n型功函數金屬層310和p型功函數金屬層308的遮蔽部分。在一實施例中,由於蝕刻製程期間的底切而導致的n型功函數金屬層310和p型功函數金屬層308的橫向損耗小於2 nm。參照第3J圖,在將n型功函數金屬層310圖案化之後,方法100移除光阻層504和光阻底層502的剩餘部分。可以使用任何合適的移除製程,例如光阻層504和光阻底層502的顯影。在一些實施例中,可以在分開的製程中移除光阻層504和光阻底層502。
參照第1圖和第3K圖,方法100在步驟116在圖案化的n型功函數金屬層310和高介電常數介電層304上方的閘極溝槽220中形成膠合金屬層312。在一實施例中,均勻厚度的膠合金屬層312是形成以覆蓋鰭片207a~207c。或者,膠合金屬層312可以在鰭片207a~207c上具有不同的厚度(例如在p型鰭片207a上較厚且在n型鰭片207c上較薄)。膠合金屬層312的沉積可以藉由原子層沉積、化學氣相沉積、物理氣相沉積及/或其他合適的製程。膠合金屬層312用於多種目的。舉例來說,膠合金屬層312使用促進或增強對填充金屬層320的黏著的材料,而填充金屬層320將形成在膠合金屬層312上。膠合金屬層312也提供想要的功函數並調整後續電晶體的臨界電壓。如本發明實施例所示,鰭片207a用於實現p型鰭式場效電晶體,因此膠合金屬層312是p型功函數金屬層。在一實施例中,膠合金屬層312在鰭片207a~207c上方具有相對小的厚度(例如小於3 nm或是約2 nm至約3 nm),以達到鰭片207a上的p型鰭式場效電晶體的設計功函數,而沒有顯著地抵消(升高)鰭片207c上的n型鰭式場效電晶體的功函數值。或者,膠合金屬層312可以在鰭片207a上較厚並且在n型鰭片207c上較薄。由於膠合金屬層312的多種用途,膠合金屬層312也可以稱為p型功函數金屬及膠合層。
膠合金屬層312使用任何合適的金屬,其配置成作為鰭片207a的功函數金屬。包含於膠合金屬層312中的金屬的選擇可以由形成於鰭片207a上的場效電晶體裝置(例如n型或p型)所需的總臨界電壓決定。例示性的p型功函數金屬包含Ti、TiN、TaN、Ru、Mo、Al、WN、ZrSi2
、MoSi2
、TaSi2
、NiSi2
、WN及/或前述之組合。應注意的是,如果鰭片207a用於實現n型鰭式場效電晶體,則可以改成使用合適的n型功函數金屬,例如Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr及/或前述之組合。在一些實施例中,因為功函數大致上由p型功函數金屬層308及/或n型功函數金屬層310決定,膠合金屬層312不會顯著影響功函數(例如藉由保持膠合金屬層312相對薄)。
根據本發明實施例揭示的一些實施例,p型功函數金屬層308、n型功函數金屬層310和膠合金屬層312一起形成功函數金屬結構307,其決定鰭式場效電晶體在鰭片207a~207c上的有效功函數。功函數金屬結構307在不同的水平功函數金屬部分307a、307b和307c中具有不同膜層。具體而言,在功函數金屬結構307中,形成於鰭片207a上方的p型功函數金屬部分307a僅包含膠合金屬層312;形成於鰭片207c上方的n型功函數金屬部分307c包含n型功函數金屬層310和膠合金屬層312;以及功函數金屬部分307b包含p型功函數金屬層308、n型功函數金屬層310和膠合金屬層312。因此,p型功函數金屬部分307a比n型功函數金屬部分307c薄(雖然p型功函數金屬部分307a的功函數比n型功函數金屬部分307c高),n型功函數金屬部分307c又比功函數金屬部分307b薄。這樣的厚度分佈與其他功函數金屬結構(其中功函數金屬部分需要最厚以獲得最高功函數)不同。因此,本發明實施例減少在鰭片207a~207c的頂表面上的功函數金屬結構307的總厚度。在一些實施例中,功函數金屬結構307(包含p型功函數金屬層308、n型功函數金屬層310和膠合金屬層312)的總厚度為約3 nm至約13 nm。總厚度的決定可以基於例如所選擇的閘極結構的電功函數特性以及在鰭片至鰭片節距距離、閘極長度、金屬閘極高度等項目的物理空間限制的因素。舉例來說,就電功函數特性而言,厚度大於約13 nm的功函數金屬結構可能無法充分反應功函數讀數(read-out)。在一實施例中,鰭片至鰭片節距距離為約20 nm至約40 nm,其設計係基於包含裝置密度、鰭片蝕刻能力、閘極圖案化寬裕度的考量。如第3K圖所示,功函數金屬結構307的總厚度受到鰭片207b和207c之間的鰭片至鰭片節距距離的限制,因為在功函數金屬部分307b和307c之間需要一些間隙或空間以形成填充金屬層320(如第3L圖所示)。
本發明實施例提供極高及/或極低功函數。如第3K圖所示,在p型通道區230a上方形成的p型功函數金屬部分307a僅包含膠合金屬層312而不含n型功函數金屬層。因此,膠合金屬層312可以使用實現極高功函數的p型功函數金屬。在一些實施例中,膠合金屬層312的功函數等於或大於4.8 eV。另一方面,在n型通道區230c上方形成的n型功函數金屬部分307c僅包含n型功函數金屬層310和膠合金屬層312(而不含p型功函數金屬層308)。當在n型通道區230c上需要極低功函數時,n型功函數金屬層310可以使用實現極低功函數的n型功函數金屬。在一些實施例中,n型功函數金屬層310的功函數等於或小於4.4 eV。此外,n型功函數金屬層310和膠合金屬層312的材料和厚度可以採用組合的方式定制,以分別在p型功函數金屬部分307a和n型功函數金屬部分307c中提供極高功函數(例如等於或大於4.8 eV)和極低功函數(例如等於或小於4.4 eV)兩者。舉例來說,膠合金屬層312可以使用高功函數金屬的薄層,並且n型功函數金屬層310可以使用低功函數金屬的厚層。中間功函數金屬部分307b可以藉由調節其中的膜層的材料及/或厚度來微調或定制為n型或p型。
相較於其他方法,本發明實施例以較少材料層增加可能的功函數和臨界電壓值的數量。作為好處,即使鰭片之間的節距距離縮減,也存在足夠的空間來將功函數金屬層進行圖案化。如果沒有本發明實施例揭示的技術,n型和p型功函數金屬層會更厚(或者將存在更多這種膜層),並且鰭片之間沒有空間以在n型和p型功函數金屬層上適當地填充膠合金屬層。因此,本發明實施例可以在較小的電晶體裝置(例如較小的鰭式場效電晶體)中實現多臨界電壓能力。
參照第1圖和第3L圖,方法100在步驟118在閘極溝槽220的剩餘空間中形成填充金屬層320,以完成金屬閘極結構。填充金屬層320可以包含銅(Cu)、鎢(W)、鋁(Al)、鈷(Co)及/或其他合適的材料。填充金屬層320的形成可以藉由原子層沉積、化學氣相沉積、物理氣相沉積、電鍍及/或其他合適的製程。可以進行化學機械研磨製程以移除多餘的材料以平坦化裝置200的頂表面。在形成填充金屬層320之後,完成閘極結構。閘極結構(包含界面層302、高介電常數介電層304、功函數金屬結構307和填充金屬層320)形成於通道上方並環繞通道,通道位於每個鰭片上的源極和汲極之間。因此,每個鰭片是鰭式場效電晶體的一部分,其包含源極、汲極、通道和閘極。當在鰭片上實施多個源極、汲極和通道時,鰭片可以被認為是多個鰭式場效電晶體的一部分。如第3L圖所示,填充金屬層320設置於功函數金屬結構307上方並直接接觸功函數金屬結構307。此外,功函數金屬結構307設置於高介電常數介電層304上方並直接接觸高介電常數介電層304。換句話說,在功函數金屬結構307和高介電常數介電層304之間不使用中間層,例如阻障層或高介電常數蓋層(例如氮化矽)。結果,功函數金屬結構307更靠近通道區230a~230c,其改善功函數控制的效率。
如第3L圖所示,藉由控制功函數金屬結構307中的膜層輪廓,在三個鰭片207a~207c上實現三種不同的功函數。從右到左,p型鰭片207a具有最高功函數(WF1),中間鰭片207b具有中間功函數(WF2),以及n型鰭片207c具有最低功函數(WF3)。結果,可以在鰭片207a~207c上實現三種不同的臨界電壓。在一實施例中,鰭片207a具有功函數為4.7 eV的p型低臨界電壓(p-type low Vt,P-LVt),鰭片207b具有功函數為4.6 eV的p型標準臨界電壓(p-type standard Vt,P-SVt)或具有功函數為4.5 eV的n型標準臨界電壓(n-type standard Vt,N-SVt),並且鰭片207c具有功函數為4.4 eV的n型低臨界電壓(n-type low Vt,N-LVt)。因此,使用本發明實施例揭示的技術,可以靈活地設計和定制特定的臨界電壓值及其相應的功函數,以適應各種應用需求。
雖然本發明實施例主要描述控制功函數金屬結構307中的金屬層以調製功函數,但應理解的是,如果需要,也可以調整閘極介電層305以實現不同的功函數。這種額外的調整能力進一步增加了可能的功函數和臨界電壓值的數量。
第3L圖繪示整個閘極結構(包含界面層302、高介電常數介電層304、功函數金屬結構307和填充金屬層320)連接並接合鰭片207a~207c。因此,共閘極(common gate)結構可用於n型和p型鰭式場效電晶體兩者。在一些實施例中,在步驟120,方法100可以切割閘極結構以隔開具有不同臨界電壓的各個鰭式場效電晶體。舉例來說,藉由閘極切割,鰭片207a上的p型鰭式場效電晶體可以具有第一閘極結構,鰭片207c上的n型鰭式場效電晶體可以具有單獨的第二閘極結構,以及鰭片207b上的另一n型或p型鰭式場效電晶體可以具有另一單獨的第三閘極結構。在一些實施例中,兩個或更多個鰭片共享相同的閘極結構,而其他鰭片具有單獨的閘極結構。此外,第3L圖中所示的閘極結構也可以與第3L圖中未繪示的其他鰭片共享。
隨後,在步驟122,方法100進行額外的製程步驟以完成裝置200的製造。舉例來說,可以在裝置200上方形成垂直互連部件(例如接觸件及/或導孔(vias))及/或水平互連部件(例如線)以及多層互連結構(例如金屬層和層間介電質)。各種互連部件可以實施各種導電材料,包含銅(Cu)、鎢(W)、鈷(Co)、鋁(Al)、鈦(Ti)、鉭(Ta)、鉑(Pt)、鉬(Mo)、銀(Ag)、金(Au)、錳(Mn)、鋯(Zr)、釕(Ru)、前述各自的合金、金屬矽化物及/或其他合適的材料。金屬矽化物可以包含矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀及/或其他合適的金屬矽化物。
第2A~2B和3A~3L圖繪示一個閘極溝槽220接合多個鰭片207a~207c的實施例。在其他實施例中,可以對應於具有預定臨界電壓的不同鰭片形成單獨的閘極溝槽。第4A圖是半導體裝置(又稱為裝置)400的另一實施例的局部上視示意圖,其中每個閘極溝槽對應預定臨界電壓,而第4B圖是相同半導體裝置400的局部Y切割剖面示意圖。第4A和4B圖所示之裝置400與第2A和2B圖所示之裝置200處於相同製造階段。裝置400的許多面向與裝置200相同,並且方法100對裝置400的應用如同方法100對裝置200的應用。因此,為了簡化起見,僅進一步描述裝置200和400之間的差異。不同於具有一個閘極溝槽220接合鰭片207a~207c上的具有不同臨界電壓的多個鰭式場效電晶體的裝置200,裝置400具有多個閘極溝槽形成於其中,包含閘極溝槽420和424,閘極溝槽420和424各自接合鰭片上的具有不同的臨界電壓的單獨的鰭式場效電晶體。除了使用多個閘極溝槽420和424取代單一閘極溝槽220之外,方法100的步驟仍對裝置400運作。此外,在執行方法100之後,最終裝置400具有由閘極間隔物212和層間介電層218隔開的多個閘極結構。舉例來說,在最終裝置400中,鰭片207a上的p型鰭式場效電晶體可以具有帶有第一臨界電壓的第一閘極結構,以及鰭片207c上的n型鰭式場效電晶體可以具有帶有不同臨界電壓的閘極結構。雖然在第4A和4B圖中僅繪示兩個閘極溝槽420和424,但可以使用本發明實施例揭示的原則形成額外的閘極溝槽和鰭片。
雖然並非用於限制,但是本發明實施例的一或多個實施例為半導體裝置及其形成方法提供了許多好處。舉例來說,本發明實施例中的一些實施例提供了使用薄功函數金屬結構實現極端臨界電壓的方法。改善較小鰭式場效電晶體裝置的間隙填充能力。在早期的材料層的圖案化產生更大的圖案化寬裕度。此外,形成一般膠合金屬層和填充金屬層用於多臨界電壓而無需額外的圖案化。簡化製造降低了成本。本發明實施例揭示的技術可以取代或補充其他臨界電壓調整技術,例如多圖案化閘極(multiple patterning gate,MPG)。
在一面向,本發明實施例關於一種積體電路(IC)的製造方法,其包含露出複數個通道區,其包含p型通道區和n型通道區;在露出的通道區上方形成閘極介電層;以及在閘極介電層上方形成功函數金屬(WFM)結構。功函數金屬結構包含形成於p型通道區上方的p型功函數金屬部分和形成於n型通道區上方的n型功函數金屬部分,並且p型功函數金屬部分比n型功函數金屬部分薄。此方法還包含在功函數金屬結構上方形成填充金屬層,使得填充金屬層直接接觸p型功函數金屬部分和n型功函數金屬部分兩者。
在一些實施例中,功函數金屬結構的形成包含:在閘極介電層上方沉積n型功函數金屬層;以及將n型功函數金屬層圖案化,以移除沉積於p型通道區上方的n型功函數金屬層的一部分。
在一些實施例中,n型功函數金屬層的圖案化使用濕式蝕刻製程,其係基於n型功函數金屬層和閘極介電層之間的蝕刻選擇性。
在一些實施例中,蝕刻選擇性是使得濕式蝕刻製程以比蝕刻閘極介電層至少快100倍的蝕刻速率蝕刻n型功函數金屬層。
在一些實施例中,功函數金屬結構的形成更包含在圖案化的n型功函數金屬層上方形成膠合金屬層。
在一些實施例中,膠合金屬層的一部分屬於p型功函數金屬,膠合金屬層的所述部分直接接觸閘極介電層。
在一些實施例中,露出的通道區更包含第三通道區,其中功函數金屬結構的形成更包含,在n型功函數金屬層沉積於閘極介電層上方之前,在第三通道區上方形成圖案化的p型功函數金屬層,其中n型功函數金屬層的一部分沉積於圖案化的p型功函數金屬層上方。
在另一面向,本發明實施例關於一種積體電路(IC)的製造方法,包含提供半導體裝置結構,其包含基底;複數個鰭片設置於基底上方並沿著第一方向延伸;以及閘極溝槽設置於基底上方並沿著與第一方向交叉的第二方向延伸,閘極溝槽露出所述鰭片中的每一個的一部分。此方法更包含在所述鰭片的所述露出部分上方沉積界面層;在界面層上方沉積高介電常數介電層;以及在高介電常數介電層上方沉積n型功函數金屬(WFM)層。基於n型功函數金屬層和高介電常數介電層之間的蝕刻選擇性而將n型功函數金屬層圖案化以露出高介電常數介電層的一部分。此方法更包含在圖案化的n型功函數金屬層和高介電常數介電層的露出部分上方沉積p型功函數金屬層。
在一些實施例中,此方法更包含在n型功函數金屬層的沉積之前:在高介電常數介電層上方沉積p型功函數金屬層;以及將p型功函數金屬層圖案化以露出至少高介電常數介電層的所述部分。
在一些實施例中,此方法更包含在p型功函數金屬層的沉積之後,在p型功函數金屬層上方形成填充金屬層。
在一些實施例中,在n型功函數金屬層的圖案化期間,蝕刻選擇性是使得蝕刻製程以比蝕刻高介電常數介電層至少快100倍的蝕刻速率蝕刻n型功函數金屬層。
在又另一面向,本發明實施例關於一種半導體裝置,其包含半導體基底;複數個通道區,包含p型通道區和n型通道區,設置於半導體基底上方;以及閘極結構。閘極結構包含設置於所述通道區上方的閘極介電層和設置於閘極介電層上方的功函數金屬(WFM)結構。功函數金屬結構包含分別設置在p型通道區和n型通道區上方的p型功函數金屬部分和n型功函數金屬部分,且其中p型功函數金屬部分比n型功函數金屬部分薄。閘極結構更包含設置於n型功函數金屬部分和p型功函數金屬部分兩者上方的填充金屬層。
在一些實施例中,n型功函數金屬部分包含:n型功函數金屬層,設置於閘極介電層上方且直接接觸閘極介電層;以及膠合金屬層,設置於n型功函數金屬層上方。
在一些實施例中,n型功函數金屬層的功函數等於或小於4.4 eV。
在一些實施例中,p型功函數金屬部分包含膠合金屬層,設置於閘極介電層上方且直接接觸閘極介電層。
在一些實施例中,位於p型功函數金屬部分中的膠合金屬層作為p型通道區中的p型功函數金屬,且其中膠合金屬層的功函數等於或大於4.8 eV。
在一些實施例中,p型通道區和n型通道區分別是第一通道區和第二通道區,其中所述通道區更包含第三通道區,其中p型功函數金屬部分和n型功函數金屬部分分別是第一功函數金屬部分和第二功函數金屬部分,其中功函數金屬結構更包含第三功函數金屬部分,設置於第三通道區上方,且其中第三功函數金屬部分比第一功函數金屬部分和第二功函數金屬部分兩者厚。
在一些實施例中,第二功函數金屬部分的有效功函數低於第三功函數金屬部分的有效功函數,且其中第三功函數金屬部分的有效功函數低於第一功函數金屬部分的有效功函數。
在一些實施例中,此半導體裝置更包含複數個鰭式場效電晶體設置於半導體基底上方,其中所述鰭式場效電晶體各自包含:源極;汲極;以及所述通道區中的一個,設置於源極和汲極之間。
在一些實施例中,閘極結構被配置以實施對所述鰭式場效電晶體各自的不同臨界電壓。
以上概述數個實施例之部件,使得在發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的面向。在發明所屬技術領域中具有通常知識者應該理解,他們能以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。發明所屬技術領域中具有通常知識者也應該理解到,此類等效的結構並未悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和取代。
100:方法;
102、104、106、108、110、112、114、116、118、120、122:步驟;
200、400:裝置;
202:基底;
203:第一區;
205:第二區;
207a、207b、207c:鰭片;
208:隔離結構;
212:閘極間隔物;
218:層間介電層;
220、222、420、424:閘極溝槽;
230a、230b、230c:通道區;
302:界面層;
304:高介電常數介電層;
305:閘極介電層;
307:功函數金屬結構;
307a:p型功函數金屬部分;
307b:中間功函數金屬部分;
307c:n型功函數金屬部分;
308:p型功函數金屬層;
310:n型功函數金屬層;
312:膠合金屬層;
320:填充金屬層;
402、502:光阻底層;
404、504:光阻層;
406、418:開口。
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件(feature)並未按照比例繪製,且僅用於繪示的目的。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。
第1圖根據本發明實施例的各個面向繪示半導體裝置的製造方法的流程圖。
第2A圖係根據本發明實施例的各個面向之半導體裝置的一實施例的上視示意圖。
第2B圖係根據本發明實施例的各個面向之與第2A圖相同的半導體裝置的Y切割剖面示意圖。
第3A、3B、3C、3D、3E、3F、3G、3H、3I、3J、3K和3L圖係根據本發明實施例的各個面向之在第1圖的方法的中間步驟期間之第2A和2B圖的半導體裝置的額外的Y切割剖面示意圖。
第4A圖係根據本發明實施例的各個面向之半導體裝置的另一實施例的上視示意圖。
第4B圖係根據本發明實施例的各個面向之與第4A圖相同的半導體裝置的Y切割剖面示意圖。
200:裝置
202:基底
207a、207b、207c:鰭片
208:隔離結構
212:閘極間隔物
218:層間介電層
220:閘極溝槽
230a、230b、230c:通道區
302:界面層
304:高介電常數介電層
307:功函數金屬結構
307a:p型功函數金屬部分
307b:中間功函數金屬部分
307c:n型功函數金屬部分
308:p型功函數金屬層
310:n型功函數金屬層
312:膠合金屬層
320:填充金屬層
Claims (1)
- 一種積體電路的製造方法,包括: 露出複數個通道區,包含一p型通道區和一n型通道區; 在露出的該些通道區上方形成一閘極介電層; 在該閘極介電層上方形成一功函數金屬結構,其中該功函數金屬結構包含形成於該p型通道區上方的一p型功函數金屬部分和形成於該n型通道區上方的一n型功函數金屬部分,且其中該p型功函數金屬部分比該n型功函數金屬部分薄;以及 在該功函數金屬結構上方形成一填充金屬層,使得該填充金屬層直接接觸該p型功函數金屬部分和該n型功函數金屬部分兩者。
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US16/381,232 | 2019-04-11 | ||
US16/381,232 US11264288B2 (en) | 2018-09-28 | 2019-04-11 | Gate structure and patterning method |
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US11177181B2 (en) | 2020-01-15 | 2021-11-16 | International Business Machines Corporation | Scalable device for FINFET technology |
US11302692B2 (en) * | 2020-01-16 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same |
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US8101485B2 (en) * | 2005-12-16 | 2012-01-24 | Intel Corporation | Replacement gates to enhance transistor strain |
US20110147831A1 (en) * | 2009-12-23 | 2011-06-23 | Steigerwald Joseph M | Method for replacement metal gate fill |
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US9236480B2 (en) * | 2013-10-02 | 2016-01-12 | Globalfoundries Inc. | Methods of forming finFET semiconductor devices using a replacement gate technique and the resulting devices |
US9455202B2 (en) * | 2014-05-29 | 2016-09-27 | United Microelectronics Corp. | Mask set and method for fabricating semiconductor device by using the same |
US9209186B1 (en) * | 2014-06-26 | 2015-12-08 | Globalfoundries Inc. | Threshold voltage control for mixed-type non-planar semiconductor devices |
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US10643904B2 (en) * | 2016-11-01 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for forming a semiconductor device and related semiconductor device structures |
US10056390B1 (en) * | 2017-04-20 | 2018-08-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET SRAM having discontinuous PMOS fin lines |
US10607895B2 (en) * | 2017-09-18 | 2020-03-31 | Asm Ip Holdings B.V. | Method for forming a semiconductor device structure comprising a gate fill metal |
US10529815B2 (en) * | 2017-10-31 | 2020-01-07 | International Business Machines Corporation | Conformal replacement gate electrode for short channel devices |
US10497571B2 (en) * | 2018-04-27 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device having work function metal stack and method of forming the same |
US10553700B2 (en) * | 2018-05-29 | 2020-02-04 | International Business Machines Corporation | Gate cut in RMG |
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