TW202018774A - 具有增強局部等向性之磊晶半導體材料生長 - Google Patents
具有增強局部等向性之磊晶半導體材料生長 Download PDFInfo
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Abstract
本發明提供用於場效電晶體的結構和用來製作用於場效電晶體的結構的方法。第一磊晶層具有第一表面和相對於該第一表面傾斜的第二表面。表面層配置在該第一磊晶層的該第一和第二表面上。第二磊晶層配置在該第一磊晶層的該第一和第二表面上的該表面層上方。該第一磊晶層的一部分定義與該表面層的介面。該第一磊晶層的該部分含有第一濃度的摻質。該表面層含有大於該第一磊晶層的該部分中的該第一濃度的該摻質的第二濃度的該摻質。
Description
本發明大致上關於半導體裝置和積體電路製作,並且特別地關於用於場效電晶體的結構和用來製作用於場效電晶體的結構的方法。
可使用互補式金屬氧化物半導體程序來建造p-型和n-型場效電晶體的組合,該p-型和n-型場效電晶體是使用來建構邏輯閘極,並且也在其它類型的電路中使用作為主動組件,例如,使用在射頻電路中的開關。場效電晶體大致上包括通道區域、源極、汲極、以及閘極電極。當超過特性臨界電壓的控制電壓施加至該閘極電極時,在該源極與汲極之間的通道區域發生載子流動,以產生裝置輸出電流。
可使用磊晶半導體膜來修正場效電晶體的效能。舉例來說,可使用磊晶半導體膜來藉由引發通道中的應力,而增加通過通道區域的載子遷移率。舉例來說,在p-型場效電晶體中,可藉由施加壓縮應力至通道區域,而增強電洞遷移率。可藉由在通道的相對端點嵌入磊晶半導體材料(例如,矽-鍺),以施加壓縮應力。嵌入的應力源(stressor)也可操作如該場效電晶體的升起式源極和升起式汲極。
可藉由選擇性磊晶生長程序形成升起式源極和汲極的磊晶半導體材料,在該選擇性磊晶生長程序中,僅從暴露的半導體表面初始化生長,而非從例如暴露的介電表面初始化生長。選擇性磊晶生長程序針對不同結晶平面展現不同生長速率,這導致沿著慢生長平面形成小平面(facet)。舉例來說,磊晶地生長的矽-鍺在<100>方向中的生長速率可大於在<111>方向的生長速率,這導致正交於該<111>方向形成小平面。
矽的覆蓋層可形成在升起式源極和汲極的小平面化半導體材料上方。覆蓋層的厚度應足以提昇矽化以製備用於接觸形成。為了維持該選擇性,可調整用於磊晶生長程序的程序參數。然而,對程序參數的調整也可以在小平面上可忽略的生長速率而導致覆蓋層的非等向性磊晶生長,這導致在該小平面上生長的該覆蓋層的厚度不足以充分地支持矽化。
需要用於場效電晶體的改進結構和用來製作用於場效電晶體的結構的方法。
在本發明的實施例中,結構包括具有第一表面和相對於該第一表面傾斜的第二表面的第一磊晶層、在該第一磊晶層的該第一表面和該第二表面上的表面層、以及配置在該第一磊晶層的該第一表面和該第二表面上的該表面層上方的第二磊晶層。該第一磊晶層的一部分定義與該表面層的介面。該第一磊晶層的該部分含有第一濃度的摻質。該表面層含有大於該第一磊晶層的該部分中的該第一濃度的該摻質的第二濃度的該摻質。
在本發明的實施例中,方法包括磊晶地生長具有第一表面和相對於該第一表面傾斜的第二表面的第一磊晶層、形成表面層在該第一磊晶層的該第一表面和該第二表面上、以及磊晶地生長配置在該第一磊晶層的該第一表面和該第二表面上的該表面層上方的第二磊晶層。該第一磊晶層的一部分定義與該表面層的介面。該第一磊晶層的該部分含有第一濃度的摻質。該表面層含有大於該第一磊晶層的該部分中的該第一濃度的該摻質的第二濃度的該摻質。
10‧‧‧絕緣體上覆矽晶圓、SOI晶圓
12‧‧‧裝置層
14‧‧‧埋置絕緣層
16‧‧‧基底
18‧‧‧溝槽隔離區域
20、22‧‧‧場效電晶體
24、25‧‧‧閘極電極
26、27‧‧‧閘極介電質
28、30‧‧‧通道區域
31‧‧‧介電覆蓋件
32‧‧‧非導電間隔件
34‧‧‧升起式源極/汲極區域
40‧‧‧表面層
42‧‧‧覆蓋層
48‧‧‧保護層
52、54、56‧‧‧表面
併入至此說明書及構成此說明書的一部分的伴隨圖式例示本發明的各種實施例,並且連同上方給定的本發明的大致性描述及下方給定的實施例的詳細描述,用作解釋本發明的實施例。
第1-4圖是依據本發明的實施例的處理方法的連續性製作階段處的結構的剖面視圖。
第3A圖是顯示升起式源極/汲極區域和該升起式源極/汲極區域上的表面層中的摻質濃度的代表性深度輪廓的圖形。
第5-6圖是依據本發明的不同實施例的處理方法的連續性製作階段處的結構的剖面視圖。
參考第1圖並依據本發明的實施例,絕緣體上覆矽(SOI)晶圓10包括裝置層12、可由矽的氧化物(例如,SiO2)組成的埋置絕緣層14、以及基底16。裝置層12和基底16可由單晶半導體材料組成,例如,單晶矽。裝置層12
藉由中介的埋置絕緣層14而與基底16分離,並且比起該基底16可相當地薄。埋置絕緣層14沿著介面直接地接觸基底16,並且沿著另一個介面直接地接觸裝置層12,而這些介面藉由該埋置絕緣層14的厚度分離,並且可在SOI晶圓10的外圈處終止。基底16可輕度摻雜成具有例如p-型導電性。
可藉由淺溝槽隔離(STI)技術形成溝槽隔離區域18,該淺溝槽隔離技術依賴微影和蝕刻,以定義溝槽在SOI晶圓10中、沉積介電材料以填充該溝槽、以及平坦化及/或凹化該介電材料。包含溝槽隔離區域18的介電材料可為矽的氧化物(例如,二氧化矽)及/或由化學氣相沉積法沉積的另一個電性絕緣體。
可於前段(FEOL)處理期間藉由互補式金屬氧化物半導體(CMOS)程序製作場效電晶體20、22。場效電晶體20包括由閘極電極24和閘極介電質26所構成的閘極結構,而場效電晶體22包括由閘極電極25和閘極介電質27所構成的閘極結構。場效電晶體20的閘極結構配置在通道區域28上方,而場效電晶體22的閘極結構配置在通道區域30上方。閘極電極24、25可由導體(例如,一個或更多個金屬或多結晶矽(多晶矽))組成、由物理氣相沉積(PVD)、化學氣相沉積(CVD)等沉積而成。閘極介電質26、27可由介電材料(例如,二氧化矽或氧氮化矽)、高-k介電材料(例如,氧化鉿或矽酸鉿)、或由化學氣相沉積、原子層沉積(ALD)等沉積的這些介電材料的層式組合組成。介電覆蓋件31可配置在閘極結構上方。
非導電間隔件32形成在場效電晶體20的閘極結構的側壁處及在場效電晶體22的閘極結構的側壁處的裝置層12上。可藉由沉積共形層(其由介電材料(例如,由化學氣相沉積所沉積的矽氮化物(Si3N4))組成)、以及以非等向性
蝕刻程序(例如,反應式離子蝕刻,其從水平表面優先地移除介電材料)成形該共形層,來形成非導電間隔件32。
參考第2圖,其中,相同的元件符號是指第1圖中的相同特徵,並且在後續製作階段中,在提供場效電晶體20的閘極結構的閘極電極24和閘極介電質26的鄰近處形成升起式源極/汲極區域34,並且也在提供場效電晶體22的閘極結構的閘極電極25和閘極介電質27的鄰近處形成升起式源極/汲極區域34。升起式源極/汲極區域34由磊晶半導體材料組成,該磊晶半導體材料由使用裝置層12的單晶半導體材料的結晶結構作為生長模板的磊晶生長程序所生長。如本文中所使用的,術語「源極/汲極區域」意指可作用為場效電晶體的源極或汲極的半導體材料的摻雜區域。場效電晶體20、22的閘極結構可作用成自我對準升起式源極/汲極區域34的半導體材料的同時磊晶生長。
在實施例中,構成升起式源極/汲極區域34的半導體材料可為矽-鍺(SiGe),具有範圍從百分之二十(20%)至百分之五十(50%)的鍺含量。在實施例中,升起式源極/汲極區域34可藉由選擇性磊晶生長程序(例如,低壓化學氣相沉積)加以形成,在該選擇性磊晶生長程序中,半導體材料成核(nucleate)以磊晶生長在半導體表面上,但沒有成核以從絕緣體表面磊晶生長。用來磊晶地生長矽-鍺的程序可涉及在給定程序條件組(例如,基底溫度、壓力和氣體流動)下的氣體/蒸汽混合物,其包括矽基前驅物、載子氣體、鹽酸蒸汽、以及鍺基前驅物(例如,鍺烷)。
升起式源極/汲極區域34的半導體材料可以有效地提昇其電性導電性的摻質濃度予以摻雜。舉例來說,升起式源極/汲極區域34的半導體材料可含有選自週期表的第III族(例如,硼(B))產生p-型導電性的p-型摻質。升起式源
極/汲極區域34的半導體材料可於磊晶生長期間藉由添加摻質的氣體或蒸汽源至氣體/蒸汽混合物,而予以原位(in situ)摻雜。舉例來說,升起式源極/汲極區域34的半導體材料可以利用從添加至氣體/蒸汽混合物的硼前驅物(例如,二硼烷氣體)供應的硼,而予以摻雜。
升起式源極/汲極區域34的外部的輪廓可具有多個表面52、54、56,其具有彼此相對的給定配置。表面52可代表升起式源極/汲極區域34的最頂表面,而表面54可藉由表面52而與表面56連接。表面56可比表面52、54的任一者更接近場效電晶體20、22的閘極結構。正交於表面52的方向不同於正交於表面54的方向和正交於表面56的方向。在實施例中,正交於表面54的方向和正交於表面56的方向可為<111>方向,而正交於表面52的方向可為<100>方向。在那方面,表面54、56可以是在與結晶方向相依的選擇性磊晶生長程序期間因為生長速率所引發的傾斜朝向的小平面。
參考第3、3A圖,其中,相同的元件符號是指第2圖中的相同特徵,並且在後續製作階段中,表面層40形成在升起式源極/汲極區域34的磊晶半導體材料上方和在升起式源極/汲極區域34的表面52、54、56上。在實施例中,表面層40可與位置無關的厚度共形。表面層40可顯著地比升起式源極/汲極區域34的磊晶半導體材料薄。表面層40含有摻質,其與升起式源極/汲極區域34的磊晶半導體材料中所含有的摻質具有相同導電性類型。在實施例中,升起式源極/汲極區域34和表面層40可含有p-型摻質。在實施例中,升起式源極/汲極區域34和表面層40可含有硼作為p-型摻質。
表面層40和升起式源極/汲極區域34在由該升起式源極/汲極區域34的表面52、54、56所定義的介面上方具有共同邊界(coextensive)(也就是,
共享邊界)。如由第3A圖中的曲線所顯示的,表面層40中的摻質(例如,硼)的濃度大於升起式源極/汲極區域34在其鄰近表面層40的深度範圍的部分的摻質(例如,硼)的濃度。在實施例中,深度的範圍可為升起式源極/汲極區域34的厚度的大部分。摻質濃度包括在靠近零深度處具有峰值,其反應出源自於表面層40的增強的濃度。因為表面層40是薄的,所以該表面層40中的摻質濃度可大略等於峰值濃度。在實施例中,表面層40含有峰值濃度的硼(B),其在1x1021cm-3至1x1022cm-3的範圍內。峰值濃度在表面層40與升起式源極/汲極區域34之間的介面處或附近減少至最小數值。摻質濃度之後隨著進入升起式源極/汲極區域34內的增加深度而增加。雖然隨著深度而增加數值,但升起式源極/汲極區域34中的此深度範圍的摻質濃度小於表面層40中的峰值摻質濃度。摻質濃度在升起式源極/汲極區域34與裝置層12之間的介面處包括另一個峰值。
在實施例中,表面層40可在用以磊晶地生長升起式源極/汲極區域34的半導體材料的沉積工具中原位形成。舉例來說,用以形成升起式源極/汲極區域34的磊晶半導體材料的磊晶生長程序可在不同程序條件下繼續,以形成表面層40。作為特定範例,在形成升起式源極/汲極區域34的磊晶半導體材料後可停止矽基前驅物和鍺烷的流動,但繼續摻質前驅物(例如,二硼烷)和載子氣體的流動。摻質(例如,硼)將沉積在升起式源極/汲極區域34的暴露表面52、54、56上,並且產生摻質堆積而產生表面層40。舉例來說,表面層40可包括摻質的原子,其吸收在升起式源極/汲極區域34的暴露表面52、54、56上的一個或更多單層的原子、或單層的該原子的片段。
在實施例中,可藉由在接著升起式源極/汲極區域34的形成而增加摻質前驅物(例如,二硼烷)的流動速率之後繼續磊晶生長程序,而在原位形成
表面層40。舉例來說,該表面層40可由磊晶半導體材料(例如,矽-鍺)組成,其併入比升起式源極/汲極區域34中鄰近與表面層40的介面的該部分的半導體材料(例如,矽-鍺)更高含量的摻質(例如,硼)。具有給定濃度的表面層40內含有摻質原子。
在實施例中,表面層40可於形成升起式源極/汲極區域34之後異位(ex situ)形成。舉例來說,可藉由在給定布植條件下(例如,離子物種、劑量、動能、布植角度),以含有摻質的離子布植而在表面52、54、56處形成表面層40。在實施例中,升起式源極/汲極區域34可在給定布植條件下以含有硼的離子布植,以提供表面52、54、56的淺布植。用來形成表面層40的離子可從適合的源氣體產生,並且可使用離子布植工具,以給定布植條件布植至升起式源極/汲極區域34內。接著布植之後,具有給定濃度的表面層40內含有摻質原子。
參考第4圖,其中,相同的元件符號是指第3圖中的相同特徵,並且在後續製作階段中,覆蓋層42形成在升起式源極/汲極區域34的磊晶半導體材料上的表面層40上方。可使用磊晶生長程序以形成升起式源極/汲極區域34的半導體材料。升起式源極/汲極區域34的單晶半導體材料可提供結晶結構,作為用於覆蓋層42的磊晶生長的生長模板。在實施例中,構成覆蓋層42的半導體材料可為矽(Si)。在實施例中,構成覆蓋層42的半導體材料可為矽-鍺(SiGe)。在實施例中,覆蓋層42可藉由選擇性磊晶生長程序(例如,低壓化學氣相沉積)形成。磊晶生長程序可涉及在給定程序條件組(例如,基底溫度、壓力、及氣體流動)下的氣體/蒸汽混合物,其包括矽基前驅物、載子氣體、以及蒸汽化的鹽酸。表面層40配置在升起式源極/汲極區域34的各者與相關聯的覆蓋層42之間。
在實施例中,覆蓋層42的半導體材料於磊晶生長程序期間,可以一摻質濃度視需要地摻雜,該摻質濃度可有效地提昇材料的電性導電性。舉例來說,覆蓋層42的半導體材料可含有選自週期表的第III族(例如,硼(B))產生p-型導電性的p-型摻質。覆蓋層42的半導體材料可於磊晶生長期間藉由添加摻質的氣體或蒸汽源(例如,二硼烷氣體),而在原位摻雜。
接著矽化、中段(MOL)處理、以及後段(BEOL)處理,以提供與場效電晶體20、22耦接的互連結構。
表面層40催化覆蓋層42從升起式源極/汲極區域34的表面54和56的生長,使得表面54、56的覆蓋層42以一厚度生長,該厚度大於將導致缺乏表面層40的厚度。表面層40的出現可提昇覆蓋層42在由低磊晶生長速率所特性化的結晶方向中的總體磊晶生長速率。覆蓋層42在表面52、54、56上的厚度可更等向性,其中,該覆蓋層42在表面54和56上的厚度比缺乏表面層40的相對厚度更接近該覆蓋層42在該表面52上的厚度。此外,針對用於提昇選擇性磊晶生長程序的程序參數的調整可較不影響覆蓋層42的形成。
參考第5圖,其中,相同的元件符號是指第2圖中的相同特徵,並且依據不同實施例,場效電晶體22及其升起式源極/汲極區域34可於形成表面層40的程序期間,被保護層48覆蓋及遮蔽。舉例來說,保護層48可以是被鋪設作為布植遮罩的光阻層。表面層40形成在與場效電晶體20相關聯的升起式源極/汲極區域34的表面52、54、56上。然而,保護層48阻擋表面層40形成在與場效電晶體22相關聯的升起式源極/汲極區域34的表面52、54、56上,使得這些表面52、54、56沒有該表面層40。
參考第6圖,其中,相同的元件符號是指第5圖中的相同特徵,並且在後續製作階段中,因為缺乏表面層40,使得形成在與場效電晶體22相關聯的升起式源極/汲極區域34上的覆蓋層42沒有展現出從表面52、54、56的等向性生長。相反地,覆蓋層42主要是從表面52磊晶生長,而從表面54、56的磊晶生長則因視生長方向而定的磊晶生長速率的差異而被抑制。具體而言,在正交於表面52的方向(例如,<100>方向)中形成在與場效電晶體22相關聯的升起式源極/汲極區域34上的覆蓋層42的磊晶生長速率高於在正交於表面54、56(其可包括該覆蓋層42的可忽略厚度)的方向(例如,<111>方向)中的磊晶生長速率。對比之下,因為表面層40的出現,使得形成在與場效電晶體20相關聯的升起式源極/汲極區域34的表面52、54、56上的覆蓋層42展現等向性磊晶生長速率。
作為範例、而非作為限制,在本文中作出對於術語例如「直立」、「水平」等的參考,以建立參考的框架。本文中所使用的術語「水平」是定義為與半導體基底的傳統平面平行的平面,不論其真正的三維空間朝向。術語「直立」和「正交」是指與水平垂直的方向,如剛才所定義的。術語「側向的」是指水平平面內的方向。
「連接」或「耦接」至另一個特徵或與另一個特徵「連接」或「耦接」的特徵可直接地連接或耦接至其它特徵或與其它特徵直接地連接或耦接,或者取而代之,可出現一個或更多個中介特徵。如果缺乏中介特徵,特徵可「直接地連接」或「直接地耦接」至另一個特徵或與另一個特徵「直接地連接」或「直接地耦接」。如果出現至少一個中介特徵,特徵可「間接地連接」或「間接地耦接」至另一個特徵或與另一個特徵「間接地連接」或「間接地耦接」。在另一個特徵「上」或與另一個特徵「接觸」的特徵可直接地在其它特徵上或與其它特徵
接觸,或者取而代之,出現一個或更多個中介特徵。如果缺乏中介特徵,特徵可為「直接地在」另一個特徵「上」或與另一個特徵「直接接觸」。如果出現至少一個中介特徵,特徵可為「間接地在」另一個特徵「上」或與另一個特徵「間接接觸」。
為了例示已經呈現本發明的各種實施例的描述,而不意圖窮盡或限制至所揭露的實施例。許多修正和變化對於本領域中具有通常技術者而言是明顯的,而不致於偏離該描述的實施例的範疇和精神。本文中所使用的技術用語經選擇以最佳地解釋實施例的原則、對於市場上所發現的科技的實際應用或技術改進、或致能本領域中具有通常技術者了解本文所揭露的實施例。
10‧‧‧絕緣體上覆矽晶圓、SOI晶圓
12‧‧‧裝置層
14‧‧‧埋置絕緣層
16‧‧‧基底
18‧‧‧溝槽隔離區域
20、22‧‧‧場效電晶體
24、25‧‧‧閘極電極
26、27‧‧‧閘極介電質
28、30‧‧‧通道區域
31‧‧‧介電覆蓋件
32‧‧‧非導電間隔件
Claims (20)
- 一種結構,包含:第一磊晶層,具有第一表面和相對於該第一表面傾斜的第二表面;表面層,在該第一磊晶層的該第一表面和該第二表面上;以及第二磊晶層,配置在該第一磊晶層的該第一表面和該第二表面上的該表面層上方;其中,該第一磊晶層的一部分定義與該表面層的介面,該第一磊晶層的該部分含有第一濃度的摻質,而該表面層含有第二濃度的該摻質,該第二濃度的該摻質大於該第一磊晶層的該部分中的該第一濃度的該摻質。
- 如申請專利範圍第1項所述之結構,其中,該摻質是p-型摻質。
- 如申請專利範圍第2項所述之結構,其中,該摻質是硼。
- 如申請專利範圍第1項所述之結構,其中,該第一磊晶層是矽-鍺,而該第二磊晶層是矽或矽-鍺。
- 如申請專利範圍第1項所述之結構,其中,該第一磊晶層是第一場效電晶體的升起式源極/汲極。
- 如申請專利範圍第5項所述之結構,進一步包含:第二場效電晶體,包括具有第一表面和相對於該第一表面傾斜的第二表面的升起式源極/汲極區域,其中,該第二場效電晶體的該升起式源極/汲極區域的該第一表面和該第二表面沒有該表面層。
- 如申請專利範圍第1項所述之結構,其中,該第一磊晶層的該第一表面是朝向正交於該第一磊晶層的結晶結構中的<100>結晶方向,而該第一磊 晶層的該第二表面是朝向正交於該第一磊晶層的該結晶結構中的<111>結晶方向。
- 如申請專利範圍第1項所述之結構,其中,該第一磊晶層的該第一表面是朝向正交於該第一磊晶層的結晶結構中的第一結晶方向,而該第一磊晶層的該第二表面是朝向該第一磊晶層的該結晶結構中的第二結晶方向。
- 如申請專利範圍第1項所述之結構,其中,該摻質是硼,而該第二濃度的範圍從1x1021cm-3至1x1022cm-3。
- 一種方法,包含:磊晶地生長具有第一表面和相對於該第一表面傾斜的第二表面的第一磊晶層;形成表面層在該第一磊晶層的該第一表面和該第二表面上;以及磊晶地生長配置在該第一磊晶層的該第一表面和該第二表面上的該表面層上方的第二磊晶層,其中,該第一磊晶層的一部分定義與該表面層的介面,該第一磊晶層的該部分含有第一濃度的摻質,而該表面層含有第二濃度的該摻質,該第二濃度的該摻質大於該第一磊晶層的該部分中的該第一濃度的該摻質。
- 如申請專利範圍第10項所述之方法,其中,形成該表面層在該第一磊晶層的該第一表面和該第二表面上包含:吸收該第一表面和該第二表面上的該摻質以提供該第二濃度的該摻質。
- 如申請專利範圍第11項所述之方法,其中,該第一磊晶層是藉由使用氣體/蒸汽混合物的磊晶生長程序形成的矽-鍺,該氣體/蒸汽混合物包含矽 基前驅物、鍺基前驅物、以及含硼前驅物,並且吸收該第一表面和該第二表面上的該摻質以提供該第二濃度的該摻質包含:修正該氣體/蒸汽混合物,以僅包括該含硼前驅物。
- 如申請專利範圍第10項所述之方法,其中,形成該表面層在該第一磊晶層的該第一表面和該第二表面上包含:磊晶地生長第三磊晶層在該第一磊晶層的該第一表面和該第二表面上,該第三磊晶層含有該第二濃度的該摻質,以形成該表面層。
- 如申請專利範圍第13項所述之方法,其中,該第一磊晶層是藉由使用氣體/蒸汽混合物的磊晶生長程序形成的矽-鍺,該氣體/蒸汽混合物包含矽基前驅物、鍺基前驅物、以及含硼前驅物,並且吸收該第一表面和該第二表面上的該摻質以提供該第二濃度的該摻質包含:當形成該表面層時,增加該氣體/蒸汽混合物中的該含硼前驅物的流動。
- 如申請專利範圍第10項所述之方法,其中,形成該表面層在該第一磊晶層的該第一表面和該第二表面上包含:離子布植該第一磊晶層的該第一表面和該第二表面,以提供該第二濃度的該摻質並藉此形成該表面層。
- 如申請專利範圍第10項所述之方法,其中,該第一磊晶層是第一場效電晶體的升起式源極/汲極。
- 如申請專利範圍第16項所述之方法,進一步包含:磊晶地生長第二場效電晶體的升起式源極/汲極區域,該升起式源極/汲極區域包括第一表面和相對於該第一表面傾斜的第二表面;以及於形成該表面層在該第一磊晶層的該第一表面和該第二表面上期間,遮蔽該第二場效電晶體的該升起式源極/汲極區域的該第一表面和該第二表面,其中,該第二場效電晶體的該升起式源極/汲極區域的該第一表面和該第二表面沒有該表面層。
- 如申請專利範圍第10項所述之方法,其中,該第一磊晶層的該第一表面是朝向正交於該第一磊晶層的結晶結構中的<100>結晶方向,而該第一磊晶層的該第二表面是朝向正交於該第一磊晶層的該結晶結構中的<111>結晶方向。
- 如申請專利範圍第10項所述之方法,其中,該第一磊晶層的該第一表面是朝向正交於該第一磊晶層的結晶結構中的第一結晶方向,而該第一磊晶層的該第二表面是朝向正交於該第一磊晶層的該結晶結構中的第二結晶方向。
- 如申請專利範圍第10項所述之方法,其中,該摻質是硼,而該第二濃度的範圍從1x1021cm-3至1x1022cm-3。
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US10361279B2 (en) * | 2017-11-24 | 2019-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing FinFET structure with doped region |
US10347762B1 (en) * | 2018-05-29 | 2019-07-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Field effect transistor contact with reduced contact resistance using implantation process |
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