TW200425278A - Relaxed film layer structure and manufacturing method thereof - Google Patents

Abstract

This invention provides a manufacturing method of the relaxed film layer structure, which comprises providing a silicon-on-insulator (SOI) substrate, then, performing an ion implantation process onto the substrate to form a defect region in the silicon layer and finally growing a relaxed film layer on the silicon layer. This invention further provides a relaxed film layer structure, which comprises an SOI substrate, a defect region formed in the silicon layer by an ion implantation process onto the substrate, and a relaxed film layer formed on the silicon layer.

Description

200425278

V. Description of the invention (1) The technical field to which the invention belongs: The present invention relates to a semiconductor structure, and more particularly to a thin film layer structure with slack and a method for manufacturing the same. Prior art: With the reduction in the size of gate elements, it is often difficult to make metal-oxide-semiconductor field-effect transistor (MOSFET) devices with high actuation current and high-speed performance at low operating voltages. Therefore, many people are trying to find a way to improve the performance of metal-oxygen half-efficiency transistor elements. Strain-induced band structure modification is used to increase carrier mobility to increase the field current transistor's actuating current, which can improve the performance of field effect transistor devices, and this method has been applied to various devices. When the channel of Shixi MoSFET element is under tensile strain, the migration rate of electrons and holes can be increased. The traditional manufacturing of a strained stone layer, as shown in FIG. 1, epitaxially grows a strained silicon thin film layer 14 on a loose stone substrate 12 which is formed on the stone. Evening on the substrate 10. The high-quality strained silicon layer 14 and the relaxed silicon germanium layer 12 are important factors for improving the performance of the strained silicon MOSFET device. The southern defect 16 (such as dislocation, stacking fault, twin, etc.) density will reduce the carrier's f mobility. A high-quality, relaxed SiGe layer can be obtained by forming a thick SiGe buffer layer with a concentration gradient (Rim K. ET AL. ,, Fab r i cat i on and analysis of deep submicron strained-Si

200425278 V. Description of the invention (2) η-M0SFETs ", IEEE Trans. Elect. Dev ·, vol · 47, ηο · 7, PP. 1 406, Jul. 2000 ·), as shown in Figure 2A, slack silicon (Bx) The germanium-rhenium layer 20 is formed on a silicon (1-y) germanium (y) buffer layer 22, where y = 0-X. The silicon m germanium (y) buffer layer 22 is formed on a silicon substrate 24. However The use of such a thick silicon germanium buffer layer has the following disadvantages. First, the thickness of this silicon germanium buffer layer is about 1 to several microns thick, and the cost of mass production is too high and the yield is too small. Furthermore, the difference in row density It is still very high, between 1E4 and lE7cm_2. Another method for forming a high-quality relaxed SiGe layer is to use a substrate with a silicon layer (S01) on the insulating layer, and the silicon germanium layer is formed on the insulating layer One thin stone evening layer (Z · Yang et al, " In situ relaxed SiGe epitaxial layers with low threading dislocation densities grown on compliant SOI substrate1 丨, J ·

Vacuum Science Technology B, vol · 16, no · 3, pp · 1 4 89, 1 998 ·). As shown in FIG. 2B, a relaxed silicon (1 x) germanium-rhenium layer 30 is formed on a substrate with a silicon layer (SO I) on an insulating layer. The reference numeral 32 in the base is a stone evening layer and the reference numeral 34 is insulation. The layer and reference numeral 36 are silicon substrates. As the thickness of Shi Xi (ι χ misalignment layer 30 increases, most of the strain is transferred from the silicon germanium hafnium layer 30 to the underlying silicon layer 32. Therefore, the strain in the silicon layer 32 is high enough to form a differential row 3 8 relaxation strain. The application of this method requires the use of a very thin Shi Xi layer to obtain a relaxed SiGe layer, and the effect of differential row proliferation is from the Shi Xilu (x) / S0I interface is an SOI substrate , It is not facing the worm crystal layer. Therefore, compared with the formation of a shixi co-buffer layer with a concentration gradient on the shixi substrate, this method can reach the surface of the subsequently formed stupid crystal layer, and it is less bad. The purpose of row density. However, the difference between the epitaxial layer formed by this method ^ ^

200425278

The degree is about 1E6 cur2, and it is still not low enough to make a famous person Gai Chan ^. The component layer is manufactured on the remote crystal layer of this poorly-arranged progress. =: The wormhole layer with a very low differential-row density is waiting for improvement. Summary of the invention: In view of this, the objective layer structure of the present invention and the manufacturing method thereof, by using a gradient buffer layer or a growth concentration with a poor row growth direction, are directed toward the base so that a relaxed thin film layer can be obtained, The manufacturing method of the present structure first provides a bottom. Next, a relaxed thin film layer is grown on the inner layer of the silicon layer. In order to provide a thin film layer with a slack to form a defect region, or grow a stacked layer structure with a gradually increasing concentration, so that the bottom layer is not oriented toward the slack film layer, ming proposes a thin film layer with a slack on an insulating layer. The base of the silicon layer (SOI) forms a defect area. Finally, in the above-mentioned silicon, the present invention further proposes a structure with a thin film layer, including a substrate with a silicon layer (so I) on top of four layers, and a defect region which is formed by ionizing the substrate. An implantation process is formed in the silicon layer; and a relaxed thin film layer is formed on the silicon layer. The advantages of the method of the present invention are that it is possible to obtain a slack thin film layer with a very low differential density compared with the conventional method, and the cost of mass production is low, and the productivity is increased. ▲ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible ', the preferred embodiments will be described below in detail with the accompanying drawings as follows:

200425278 V. Description of the invention (4) Implementation method: Example 1 The present invention provides a thin film layer structure with a slack and a manufacturing method thereof. The structure of the thin film layer can be made by the method described later. First, referring to FIG. 3A, a buried = edge layer 102 and a semiconductor layer are formed on a semiconductor substrate 100. 4. In this embodiment, a wafer with an insulation layer and a silicon layer (sillcon-on-insulat (s0I)) is used as an example. The starting material can be implanted with oxygen (SIM0X) or SmartCut®. Technology, to isolation, but not as a limitation. The semiconductor layer (soi layer) 104 is generally a silicon material having a thickness of less than 1000 A. The buried insulating layer is generally composed of silicon oxide. After that, referring to FIG. 3B, an ion implantation process is performed on the substrate 00 to form a -defective region 1G6 in the layer 104. The ions used in the above-mentioned ion implantation procedure can be boron, phosphorus and arsenic, argon, A, helium, nitrogen, oxygen, and indium. Next, referring to FIG. 3C, a thin film layer 108 is grown on the silicon layer 104. The lattice constant of the relaxed thin film layer 108 is different from the lattice constant of the silicon layer 107. The method of growing a thin film layer 08 such as selective selective epitaxy, chemical vapor deposition epitaxy, or chemical vapor film layer 108 may be a element, a mixture, or a yam conductor such as silicon germanium, silicon A layer of germanium carbon, indium germanium arsenic, germanium arsenic, aluminum germanium arsenic, germanium carbon, or indium germanium carbon. Due to the thin lattices with different lattice constants between the loose 0503-7589TWF (Nl); TSMC200M524; ycchen.ptd 200425278 V. Description of the invention (5) ^: The semiconductor phase with a large lattice in the relaxed state Book: ϊ, under the strain of Lu, ❿ semiconductors with smaller lattice constants are formed under compressive strain, and then formed-with strain flatness, this is in the silicon layer 1 04 and the relaxed thin film layer 1 08 The formed stack 'If the relaxed film layer 108 < lattice constant is greater than that of the silicon layer 104, the relaxed film layer 108 is under biaxial compressive strain condition 2 = Shixi layer 1 04 It is under the condition of biaxial tensile strain, and vice versa. Φ 'film H step / defective zone 106 is formed in Shixi layer 104, so the difference of row and proliferation caused by Songta 100 and drinking is not long. The direction is toward the substrate ΓιοΙ to loosen the thin film layer 1G8 ', so that a thin thin film can be obtained, and a strained silicon layer 11 () can be grown on the relaxed thin film layer 108. = ’Can be used to fabricate general electrical devices, bipolar transistors, and metal-oxide half-field-effect transistors on the strained silicon layer 110 (not shown). The dried substance has a thin film layer structure. As shown in FIG. 3C, the thin film layer structure including the above components is not included. The first element Ιΐί: a substrate 100 having a stone layer on an insulating layer. The insulating layer has a stone layer on it; a semi-solid substrate m forms a buried insulating layer 102 and the semi-permanent embodiment uses an insulating layer and a wafer with a stone layer as a base. Layer) 104 is typically a silicon material having a thickness of less than 250 A. Li Zang insulation layer 102 is generally composed of stone oxide. -Li Niu! A defect region 106 'is formed in the stone evening layer 1 () 4 by performing an ion implantation procedure on the substrate m. The above ion implantation procedure

734 200425278 V. Description of the invention (6) 'The ions used can be butterfly, filling and god ions. The second element is a relaxed thin film layer 108 formed on the silicon layer 104. It is grown on the silicon layer using the method and material of Example i, and the relaxed thin film layer 108 is crystallized. The lattice constant is different from the lattice constant of the silicon layer. This thin film layer structure also includes the following sub-elements. A strained stone layer 110 is grown on the relaxed thin film layer 08. Integrated circuit elements, microcomputers, bipolar transistors, metal-oxide-semiconductor field-effect transistors, or light-emitting diodes (not shown) 'are fabricated on the strained silicon layer 110. In the first embodiment of the present invention, since a defect region 10 6 is formed in the silicon layer 104, f is obtained from a relaxed thin film layer. The growth direction of the differential row generated during growth is toward the substrate 100, not toward the substrate 100. The slack film layer 108 is obtained, so that a slack film layer 108 can be obtained. Embodiment 2 A structure of a thin film layer having a slack can be produced by a method described later. Referring to FIG. 4, a buried insulating layer 202 and a semiconductor layer 204 are formed on a semiconductor substrate 200. In the embodiment, a wafer with a silicon layer (S1 1 1 COn ~ on-insulator, SOI) on the insulating layer is taken as an example. As a starting material, implanted oxygen (SI M 0 X) or Smartc can be used. Cut ® technology is used to obtain isolation, but it is not limited to this. The semiconductor layer (SOI layer) 204 is generally a silicon material with a thickness of less than 250 A. The buried insulating layer 20 is generally composed of silicon oxide. t, Secondly, an A (1-y) B (y) buffer layer 206 with a concentration gradient is grown on the Jane layer 204, where y = 0-X, and the A (1-y) B (y) buffer layer 20 6 The thickness is between 0.

200425278 V. Description of the invention (7) 〇1 to 0.5 microns. A atom can be Shi Xi, germanium, carbon, indium or Ming atom, and B atom can be germanium, carbon, indium, Shi Shen or Ming atom. The method of growing the buffer layer 206 is, for example, a molecular beam epitaxy method, a selective epitaxy method, a chemical vapor deposition epitaxy method, or a chemical vapor deposition method. Next, an α (ιχ) β (χ) relaxed film layer 208 is grown on the A (1_y) B (y) buffer layer 206. The thickness of the relaxed film layer 208 is between 0.01 and 1 micron. . The method for growing the relaxed thin film layer 208 is, for example, a sub-beam epitaxy method, a selective epitaxy method, a chemical vapor deposition epitaxy method, or a chemical vapor deposition method.

Then, a strained silicon layer 210 can be grown on the sacrificial film layer 208. Finally, general integrated circuit elements, micro-electromechanical devices, bipolar transistors, metal-oxide-semiconductor field-effect transistors, or light-emitting diodes (not shown) can be fabricated on the strained silicon layer 210. The present invention also proposes a thin film layer structure having slack, as shown in FIG. 4. The thin film layer structure having slack includes the following sub-elements. The first element is a substrate 200 having a silicon layer on an insulating layer. The substrate with a silicon layer on the insulating layer is a buried insulating layer 200 and a semiconducting layer 204 formed on a semiconductor substrate 200. In this embodiment, a wafer with a silicon layer on an insulating layer is taken as an example. The semiconductor layer (SOI layer) 204 is generally a silicon material with a thickness of less than 250 people. The buried insulating layer 202 is generally composed of silicon oxide. The second element is an A (1_y) B⑺ buffer layer 206 with a concentration gradient, which is longer than the silicon layer 204, where y = 0-x, and the thickness of the A (iy) B (y) buffer layer 206. Is between "01 and 0.5 micrometers. A0 buffer layer 206 is an example of use.

200425278 V. Description of the invention (8) * ------ 2 The method and materials are grown on the silicon layer 204, the A atom can be silicon, germanium, stone, indium, arsenic or aluminum atom, and the B atom It can be germanium, carbon, indium, aluminum atoms. % The second element is an A + yB⑴ relaxed film layer 208, grown on the α (η) β (30 buffer layer 206, and the thickness of the Ao-wB⑴ relaxed film layer 208 is between 0.01 and 0.01. To 1 micron. A (! XAw relaxed film layer 208 was grown on the 'y) B (y) buffer layer 206 using the method and material of Example 2. The structure of this thin film layer is still Including the following sub-elements, a strained silicon layer 210 is grown on a relaxed thin-film layer 208. Integrated circuit elements, micro-electromechanical devices, bipolar transistors, metal-oxide-semiconductor field-effect transistors or light-emitting diodes ), Manufactured on the strained silicon layer 210. In the second embodiment of the present invention, the A (1_y) B (y) buffer layer 20 6 with a concentration gradient is grown to prevent the difference in the orientation of the thin film layer 208. Directional proliferation. Example 3 A thin film layer structure having a looseness can be produced by a method described later, please refer to FIG. 5 to form a buried insulating layer 302 and a semiconductor layer 3 on a semiconductor substrate 300. 4. In this embodiment, a wafer with silicon 1 (si 1 icon-on-insulat〇r, so) on an insulating layer is used as an example as a starting material. The implanted oxygen (SIM0x) or SmartCUT® technology can be used to obtain & ion, but it is not limited to this. The semiconductor layer (SOI layer) 304 is generally a silicon material with a thickness less than 250 A. Buried insulation layer 2〇2 is generally made of silicon oxide ^

200425278 V. Description of the invention (9) Secondly, an A (bu Z) B⑴ buffer layer 306 is grown on the silicon layer 304. The A atom can be silicon, germanium, carbon, indium, arsenic or aluminum atom, and the B atom can be recorded. , Carbon, indium, arsenic, or aluminum atoms. The method of growing the A (i y) B (y) buffer layer 206 is, for example, a molecular beam epitaxy method, a selective epitaxy method, a chemical vapor deposition epitaxy method, or a chemical vapor deposition method. Next, "An (u) B" buffer layer 308 is grown on the A (1_Z) B "buffer layer 306, where u > z. The method for growing the A (1_u) B (u) buffer 308 is, for example, a molecular beam stupid method, a selective epitaxy method, a chemical vapor deposition epitaxy method, or a chemical gas phase deposition method. Then, "A (1_W) B" buffer layer 310 is grown on the A (1_U) B (U) buffer layer 308, where w > u. The method of growing the A (1_W) B (W) buffer 310 is, for example, a molecular beam epitaxy method, a selective epitaxy method, a chemical vapor deposition epitaxy method, or a chemical vapor deposition method. Next, an A (1_y) B (y) buffer layer 312 is grown on the buffer layer 310, where y > w. The method of the growth buffer 312 is, for example, a molecular beam stupid method, a selective epitaxy method, a chemical vapor deposition epitaxy method, or a chemical vapor deposition method. Next, a method of growing an a (1_x) b⑴relaxed thin film layer 3 1 4 on the A (1_y) B (y) buffer layer 312 is to grow a B⑴relaxed thin film layer 3 1 4 such as using a molecular beam stupid crystal method, selection Stupid crystal method, chemical vapor deposition epitaxy method or chemical vapor deposition method.

Then, a strained silicon can be grown on the loose film layer 3 丨 4 of the A (1-χ) B (x) layer 316. Finally, a general integrated circuit element can be fabricated on the strained stone layer 316

0503-7589TWF (Nl); TSMC2001-1524; ycchen.ptd Page 13 200425278 V. Description of the invention (10) " " " pieces, micro-electromechanical devices, bipolar transistors, metal oxide half field effect transistors or light emitting diodes Body (not shown). < The present invention also proposes a thin film layer structure having a slack, as shown in Fig. 5 'This thin film layer structure having a slack includes the following sub-elements. The first element is a substrate 300 having a silicon layer on an insulating layer. The substrate with a silicon layer on the insulating layer is a buried insulating layer 302 and a semi-conductive layer 304 formed on a semiconductor substrate 300. In this embodiment, a wafer with a silicon layer on the insulating layer is taken as an example. The semiconductor layer (SOI layer) 304 is typically a silicon material with a thickness of less than 250 A. The buried insulating layer 3 02 is generally composed of silicon oxide. The second element is an Απ—z) B⑴ buffer layer 306, which is grown on the silicon layer 304. Απ- ^ Β ^ The buffer layer 306 is grown on the layer 304 using the method and material of Example 3. Α The atom can be a stone, germanium, carbon, indium, sand or shaw atom, and the B atom can be a germanium, carbon'indium, arsenic or aluminum atom. The third layer 06, the Sanguang V system, a Vu) B buffer layer 308 'grown on' The buffer layer 308 was grown using the method of Example 3 and the data. He Chong 3rd, 0th, 8th, 4th, V 糸 t, two (M,) buffer layer 31 ° ′ grown on, expected to grow (1d (w) buffer layer 310 uses the method and material of Example 3

Α (1-χ) B (x) The sixth element system is one eight (11) 1) on the buffer layer 312 The slack film layer 3 1 4 grows; ^ The slack film layer 3 1 4 system uses solid

200425278 V. Description of the invention (11) The method and material of Example 3 are grown on the A (i y) B⑺ buffer layer 312. The thin film layer structure with slack also includes the following sub-elements. A strained silicon layer 316 is grown on the slack film layer 314. Integrated circuit elements, microcomputers, bipolar transistors, metal-oxide-semiconductor field-effect transistors, or light-emitting diodes (not shown) are fabricated on the strained silicon layer 316. The number of buffer layers grown in Embodiment 3 of the present invention is illustrated by using five buffer layers. However, for any person skilled in the art, the number of buffer layers can be two to dozens of layers, which are all included in the invention. The scope is not limited. In the third embodiment of the present invention, the buffer layer stacking structure with a gradually increasing concentration is used to prevent the differential rows from growing toward the relaxed film layer 316. The size is not limited to the replacement by the formation method described in the embodiment. As above, however, it is not intended to depart from the spirit of the present invention and the scope of protection of the invention. The material materials used in the present invention should be considered, and it can be composed of various materials with appropriate characteristics and the structural space of the invention is not limited to implementation. Examples Although the present invention has disclosed the limited edition in the preferred embodiment, anyone skilled in the art is not allowed to make changes and retouching within the scope. Therefore, the scope of the patent application attached hereto shall prevail.

2UU425278 I 1 丨 Photo _, 丨 丨 丨 丨 _ Brief description of the diagram Figure 1 shows the traditional enthusiasm Figures 2A and 2B show the thin film layer structure with W relaxation. The cage: 3: to 3c diagram shows the thin dielectric layer structure according to :: d. The cross-sectional view of the process of the thin film layer structure of this example is shown in Example 1 with slack. Figure 4 is a cross-sectional view of the process based on the super-layer structure. Fig. 5 is a cross-sectional view showing a process of a layer structure according to the present invention. Description of the thin film symbol with slack in Shell 3: 100, 200, 300 ~ semiconductor substrate; 10, 2 0, 3 0 2 ~ buried insulation; 104, 204, 304 ~ Shi Xi layer; 1 0 6 ~ Defective area; 108, 208, 314 ~ relaxed film layer; 110, 210, 316 ~ strain stone layer; 206, 306, 308, 310, 312 ~ buffer layer. < 1 0503-7589TWF (Nl); TSMC2001-1524; ycchen.ptd page 16

Claims (1)

200425278 1. A manufacturing method with a relaxed thin film layer structure, comprising the steps of: providing a substrate with a silicon layer (SOI) on an insulating layer; performing an ion implantation procedure on the substrate to form a silicon layer in the silicon layer; Depressions; and + a thin film layer is grown on the silicon layer. 2. The manufacturing method of a thin film layer structure as described in item 1 of the scope of the patent application, wherein the lattice constant of the relaxed film layer is different from the lattice constant of the silicon layer. 3, The method for manufacturing a thin film layer structure as described in item 1 of the scope of the patent application, wherein the relaxed film layer is silicon germanium, silicon germanium carbon " germanium arsenic, germanium arsenic, aluminum germanium arsenic, germanium Carbon or indium germanium carbon layer. 4. The manufacturing method of the thin film layer structure described in item 1 of the scope of patent application, wherein the growth of the thin film layer is performed by molecular beam epitaxy, selective epitaxy, and chemical vapor deposition epitaxy. Method or chemical vapor product. / b 5. The method for manufacturing a thin film layer structure as described in item 1 of the scope of the patent application, wherein the ion implantation procedure is performed on the substrate ^ The ions used are side, scale, and stone ions. 6 · As described in the first patent application, the manufacturing method with a thin film layer structure further includes growing a strained silicon layer on the loose film layer. 7 · The method for manufacturing a thin film layer structure with a slack as described in item 6 of the scope of the patent application 'further includes manufacturing integrated circuit elements, Ί A /} 200425278 6. Application scope of patent $ Electric device, bipolar transistor, metal-oxide-semiconductor field-effect transistor or light-emitting diode 8 · A kind of thin film layer structure, including: a silicon layer on the insulation layer ( SOI) substrate; ^ ^ a depression area, which is formed in the silicon layer by performing an ion implantation procedure on the substrate; and a sequenced and relaxed film layer is formed on the silicon layer. ^ The structure of the thin film drawer with relaxation as described in item 8 of the scope of the patent application, wherein the lattice constant of the loose film layer is different from that of the silicon. constant. Rigri grid 0. The thin structure with relaxation as described in item 8 of the scope of patent application, wherein the relaxed thin film layer is silicon germanium, silicon germanium carbon, indium germanium arsenic, arsenic, aluminum arsenic, germanium Carbon or indium germanium carbon layer. Structure 11 · The thin layered layer clock with relaxation as described in item 8 of the scope of patent application, wherein the relaxed thin film layer is grown using a molecular beam epitaxy method, a stupid crystal method, a chemical vapor deposition epitaxy method, or a chemical Vapor deposition.释 2. As described in item 8 of the scope of the patent application, the thin osmium layer structure with slackness, wherein the ion implantation procedure is performed on the substrate, and the ions used are: boron, phosphorus, and arsenic ions. 13. The structure of the thin thin layer with relaxation as described in item 8 of the scope of patent application, further comprising a strained silicon layer, grown on the relaxed thin film layer. 1 4 · The thin layer structure with slack as described in item No. 丨 3 of the scope of application patents further includes integrated circuit elements, micro-electromechanical devices, bipolar transistor Q-body, metal-oxide half-field-effect transistor or light-emitting diode Body, manufactured on the strained silicon layer 0503-7589TW (Nl); TSMC2001 -1524; ycchen.ptd page 18 200425278 6. Application for patent scope. 1 ·· A method for manufacturing a thin film layer structure, including the following steps: providing a substrate with a stone layer (s0I) on an insulating layer; and growing an A (1 ~ y) a B (y) buffer layer, where y = 0-X; and growing a thin film layer on the 6-bit buffer layer. 16. The method for manufacturing a thin film layer structure as described in item 15 of the scope of the patent application, wherein the thickness of the A (iy) B (y) warm stamping layer is between 0 · 〇1 and 0 · 5 Between micrometers. 17. The method for manufacturing a thin slab layer structure with relaxation as described in item 15 of the scope of patent application, wherein the sound of the 'wk) slack layer is between 0.01 and 1 micron. X Ma 18. The manufacturing method with a relaxed structure as described in item 15 of the scope of patent application, wherein the A atom is a silicon, germanium, carbon, indium, or aluminum atom. , ', Bell, or 19. A manufacturing method having a relaxed structure as described in item 15 of the scope of patent application, wherein the B atom is germanium, carbon, indium, or a layer. T or Niuhara 20. The manufacturing method with a junction as described in item 15 of the scope of the patent application, in which the A (iy) B (y) buffer layer is grown, a stupid method, a selective stupid method, Chemical Vapor Deposition: Beam Deposition. Stone 4 Chemical Vapor Phase 21 As described in the patent application No. 15 < Thin layer with slack 0503-7589TWF (Nl); TSMC200M524; ycchen.ptd Page 19 744 200425278 6. Application scope of patents, and ti structure method, in which the Α (ιχ) β acetonine is grown by molecular beam worm crystal method, Selective vermicular method, chemical vapor deposition: membrane two chemical vapor deposition method. 22. The method for manufacturing a thin film layer structure as described in item 5 of the patent application scope, further comprising forming a strained silicon layer on the relaxed thin film layer. 23. The method for manufacturing a thin film layer structure as described in item 22 of the scope of the patent application, further comprising manufacturing integrated circuit elements, micro-electromechanical devices, bipolar transistors, and metal-oxide-semiconductor half-effect transistors on the strained silicon layer. Crystal or light-emitting diode. 2 4 · A method for manufacturing a thin film layer structure with the following steps: providing a substrate with a silicon layer (SOI) on an insulating layer; and growing a B⑺ buffer layer with a concentration gradient on the substrate, In other words, the thickness of the A (1_y) B (y) buffer layer is between 0.01 and 0.5 micrometers and grown on the A (1_y) B (y) buffer layer. A (1-x) B (x ) Relaxed film layer 'The thickness of the A (1_X) B⑴ relaxed film layer is between 0.01 and 1 micrometer. 25. The method for manufacturing a thin film layer structure according to item 24 of the patent application, wherein the A atom is a silicon, germanium, carbon, indium, arsenic or aluminum atom. 2 6 · The method for manufacturing a thin film layer structure as described in item 24 of the patent application scope, wherein the B atom is a germanium, carbon, indium, arsenic or aluminum atom 0503-7589TW (Nl); TSMC2001-1524: ycchen.ptd 20th buy 200425278 6. Application patent scope 27. The method for manufacturing a thin film layer structure as described in item 24 of the patent application scope, wherein the buffer layer is grown The system uses molecular beam stupid crystal method, selective epitaxy method, chemical vapor deposition telecrystallization method or chemical vapor deposition method. 28. The method for manufacturing a relaxed thin film layer structure as described in item 24 of the scope of the patent application, wherein growing the relaxed thin film layer uses a molecular beam epitaxy method, a selective epitaxy method, and a chemical vapor deposition epitaxy method Or chemical vapor deposition. 29. The manufacturing method of a thin film layer structure as described in item 24 of the scope of patent application, further comprising forming a strained stone layer on the loose film layer. 30. The method for manufacturing a thin film layer structure as described in item 29 of the scope of the patent application, further comprising manufacturing integrated circuit elements, micro-electromechanical devices, bipolar transistors, and metal-oxygen half field effects on the strained silicon layer. Transistor or light emitting diode. 3 1 · A thin film layer structure including: a substrate with a silicon layer on an insulating layer; an A (1_y) B (y) buffer layer with a concentration gradient, grown on the substrate, where y = 0 —X, the thickness of the An y) B (y) buffer layer is between 0.001 and 0.5 micrometers; and Au-χ) B (x) the A (1 fluorene-relaxed thin film layer, grown on The thickness of the slack film layer of the A (1_y) B (y) buffer layer is between Q 01 and 1 micron. 32. The slack film layer according to item 31 of the scope of patent application 74 & 200425278 6. Scope of patent application '" Structure' wherein the A atom is a silicon, germanium, carbon, indium, arsenic or aluminum atom. 3 3 · The structure of the thin film layer having relaxation as described in item 3 of the patent application range, wherein the B atom is a germanium, carbon, indium, arsenic or aluminum atom. 3 4 · The thin film layer structure with relaxation described in item 31 of the patent application 'wherein the An_y) B (y) buffer layer is grown using molecular beam epitaxy, selective epitaxy, and vapor deposition epitaxy Crystal or chemical vapor deposition. 3 5 · The structure of the thin film layer with relaxation described in item 31 of the scope of patent application, wherein the growth of the A (1_X) B (X) relaxed film layer is performed using a molecular beam epitaxy method, a selective stupid crystal method, Chemical vapor deposition method or chemical vapor deposition method. Qin 36 · The thin film layer structure described in item 31 of the scope of patent application, further comprising growing a strained silicon layer on the A (1_X) B (X) relaxed film layer. 37. The thin film layer structure as described in item 36 of the scope of patent application, further including manufacturing integrated circuit elements, micro-electromechanical devices, bipolar transistors, and metal-oxide-semiconductor half-effect transistors on the strained silicon layer. Or light-emitting diode. 38 · A method for manufacturing a thin film layer structure, comprising the following steps: providing a substrate with a silicon layer (I) on an insulating layer; growing an A (1_z) B ⑴moderating layer on the substrate; A (1-y) B (y) buffer layer is grown on the Α (ι-Z) Β (Z) buffer layer, and y> z in the base; and 'grown on the A (1_y) B (y) buffer layer -A (1-x) B (x) relaxed film layer 'where x > y. 0503-7589TWF (Nl); TSMC200M524; ycchen.ptd Page 22 7i7 200425278 6. Application for patent scope 39 · The manufacturing method with a loose film layer structure as described in item 38 of the scope of patent application, including the 'ζ An A (i_w) b (w) buffer layer is grown between the β⑴ buffer layer and the An_y) B (y) buffer layer, where y > w > z. 40. The method for manufacturing a thin film layer structure according to item 38 of the patent application park, wherein the A atom is silicon, germanium, carbon, indium, arsenic, or 18 atoms. 4 1 · The method for manufacturing a thin film layer structure as described in item 38 of the scope of the patent application, wherein the β atom is germanium, carbon, indium, arsenic or aluminum atom 0 4 2 · As the scope of patent application 3 8 The method for manufacturing a thin film layer structure according to the above item, wherein growing the A (ιz) B (z> buffer layer is performed using a molecular beam stupid crystal method, a selective telecrystal method, a chemical vapor deposition worm crystal method, or Chemical vapor deposition method 4 3 · The manufacturing method with a relaxed thin film layer structure as described in item 38 of the patent application scope, wherein the growth of the buffer layer is performed using a molecular beam epitaxy method, a selective epitaxy method, a chemical method Vapor deposition epitaxy or chemical vapor deposition. 44. The manufacturing method with a relaxed thin film layer structure as described in item 38 of the patent application scope, wherein the relaxed thin film layer is grown using a molecular beam epitaxy method , Selective stupid crystal method, chemical vapor deposition epitaxial method or chemical vapor deposition method. 45. The method for manufacturing a thin film layer structure as described in item 38 of the patent application scope, further including the relaxed film Grow a strain on the layer > 6 evening layer. 0503-7589TWF (Nl); TSMC200M524: ycchen.ptd 200425278 ^ 46. The method for manufacturing a slack thin film layer structure as described in item 45 of the scope of patent application, further comprising manufacturing integrated circuit elements, micro-electromechanical devices, bipolar transistors, and metal-oxygen half field effects on the strained silicon layer. Transistor or light emitting diode. A structure with a thin film layer including a substrate with a silicon layer on the insulating layer; an Ααα⑴ buffer layer growing on the substrate; and a ⑴ ^ ⑴ buffer layer growing on the Απ-Z ) On the B (ζ) buffer layer, y >z; and an Au-d " relaxed thin film layer are grown on the A (1_y) B (y) buffer layer, where x > y. 4 8 · The method for manufacturing a thin film layer structure as described in item 38 of the scope of patent application, further including the A (ι z) B (z) buffer layer and the au y) B (y) buffer layer An a (1w) b (w) buffer layer is grown between them, where y > w > z. 49. The method for manufacturing a thin film layer structure according to item 38 of the scope of patent application, wherein the A atom is a germanium, carbon, indium, arsenic or aluminum atom. 50. The method for manufacturing a thin film layer structure as described in item 38 of the scope of the patent application, wherein the B atom is a, a, a, an indium, a europium, or a shaw atom. 5 1 · The manufacturing method with a relaxed thin film layer structure as described in item 38 of the scope of the patent application, wherein the growth of the buffer layer is performed using a molecular beam epitaxy method, a selective epitaxy method, a chemical vapor deposition method, or Chemical vapor deposition. 749 200425278 6. Application patent scope 52. The manufacturing method with a relaxed thin film layer structure as described in item 38 of the patent application scope, wherein the growth of the buffer layer is performed using molecular beam epitaxy, selective epitaxy, and chemical gas. Phase deposition method or chemical vapor deposition method. 5 3 · The manufacturing method of a thin film layer structure as described in item 38 of the scope of the patent application, wherein the growth of the thin film layer is by molecular beam epitaxy, selective epitaxy, and chemical vapor deposition. Crystal or chemical vapor deposition. 54. The method for manufacturing a slack film layer structure as described in item 38 of the scope of the patent application, further comprising 1 || growing a strained stone layer on the slack film layer. Stomach [55. The manufacturing method with a relaxed structure as described in item 54 of the scope of the patent application 'further includes manufacturing integrated circuits, components, micro-electromechanical devices, bipolar transistors, and metal-oxygen half field effects on the strained silicon layer. Transistor: hair 0503-7589TW (Nl): TSMC2001-1524: ycchen.ptd Page 25