TW202016954A - 異向性導電膜 - Google Patents

異向性導電膜 Download PDF

Info

Publication number
TW202016954A
TW202016954A TW108128352A TW108128352A TW202016954A TW 202016954 A TW202016954 A TW 202016954A TW 108128352 A TW108128352 A TW 108128352A TW 108128352 A TW108128352 A TW 108128352A TW 202016954 A TW202016954 A TW 202016954A
Authority
TW
Taiwan
Prior art keywords
conductive particles
arrangement
rhombic lattice
terminal
lattice region
Prior art date
Application number
TW108128352A
Other languages
English (en)
Other versions
TWI845540B (zh
Inventor
尾怜司
谷口雅樹
Original Assignee
日商迪睿合股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商迪睿合股份有限公司 filed Critical 日商迪睿合股份有限公司
Publication of TW202016954A publication Critical patent/TW202016954A/zh
Application granted granted Critical
Publication of TWI845540B publication Critical patent/TWI845540B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R11/00—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts
    • H01R11/01—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts characterised by the form or arrangement of the conductive interconnection between the connecting locations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H01L2224/2711—Shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29355—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29357—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29364—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/2939—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29399—Coating material
    • H01L2224/294—Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/2957—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83871—Visible light curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83885—Combinations of two or more hardening methods provided for in at least two different groups from H01L2224/83855 - H01L2224/8388, e.g. for hybrid thermoplastic-thermosetting adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0221—Insulating particles having an electrically conductive coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Insulated Conductors (AREA)
  • Manufacturing Of Electrical Connectors (AREA)

Abstract

本發明係一種異向性導電膜，其係於絕緣性樹脂層2配置有導電粒子1者，且具有重複配置有第1斜方格子區域11與第2斜方格子區域12之導電粒子之粒子配置，該第1斜方格子區域11係於以角度α與a方向斜交之b方向上排列有複數個將導電粒子1以規定間距配置於a方向而成之導電粒子排列軸a1，該第2斜方格子區域12係於使上述b方向相對於a方向反轉後之c方向上排列有複數個將導電粒子1以規定間距配置於a方向而成之導電粒子排列軸a2。藉此，無關於端子排列之形狀或電子零件之材質，由各端子夾持導電粒子而得以確保良好之導通狀態，亦得以防止短路之發生。

Description

異向性導電膜
本發明係關於一種異向性導電膜。
供安裝IC晶片等電子零件之基板由於被要求輕量化與可撓性，故而多使用塑膠基板或FPC（Flexible Printed Circuits）。又，於IC晶片等電子零件中，端子之微間距化不斷發展，有於電子零件之安裝時塑膠基板或FPC之熱膨脹成為問題之情形。因此，為了實現即便因電子零件之安裝時之溫度變動而導致端子之位置發生偏移亦能夠確實地進行電子零件之連接，使構成電子零件之端子行之各端子呈放射狀並列（所謂扇出配線）來取代先前之相同方向上並列之情況（專利文獻1）。
另一方面，電子零件之安裝廣泛地使用使導電粒子分散於絕緣性樹脂層所得之異向性導電膜。對於使用有異向性導電膜之電子零件之連接，提出有如下內容：為了實現即便電子零件之端子之微間距化發展，亦能夠利用電子零件之端子穩定地捕捉異向性導電膜之導電粒子，於異向性導電膜中將導電粒子配置成六方格子等格子狀，並使其排列軸相對於端子之長邊方向傾斜（專利文獻2）。又，作為異向性導電膜之粒子配置，亦提出有如下內容：使導電粒子排列於相對於膜之長邊方向斜交之第1方向，使複數個該第1方向之粒子行於與其排列方向不同之第2方向上並列，且不使第1方向之粒子行為一條直線狀，而使該粒子行具有未達導電粒子之粒徑之2.5倍之寬度（專利文獻3）或重複配置導電粒子以規定之間隔排列而成之單元（專利文獻4、5）。 先前技術文獻 專利文獻
專利文獻1：日本特開2015-232660號公報 專利文獻2：日本特開平9-320345號公報 專利文獻3：日本特開2017-168465號公報 專利文獻4：日本特開2017-204462號公報 專利文獻5：日本特開2017-204463號公報
[發明所欲解決之課題]
然而，於使用異向性導電膜進行例如FOG（Film On Glass）連接時，如圖6A所示，連接之各端子於相同方向上並列，異向性導電膜之導電粒子1配置成六方格子，即便其排列軸相對於端子20之長邊方向（與排列方向x垂直之方向）以角度δ傾斜，因連接時之熱壓接而於端子間產生箭頭方向之樹脂流動，故而根據條件不同，連接後如圖6B所示，於端子間產生導電粒子1之密集區域A而造成短路。
又，如圖5A所示，若欲以六方格子之排列軸朝膜之長邊方向傾斜（傾斜角γ）之方式，使用導電粒子1呈六方格子配置之異向性導電膜來連接扇出型端子行，則因扇出角β（即端子20之長邊方向相對於端子之排列方向x之角度）針對每個端子逐個稍許不同，故而於扇出型端子行之右側與左側，由一個端子捕捉到之導電粒子1之數量或分佈狀態不同，連接後之壓痕之痕跡亦不同。除此以外，於圖5A所示之導電粒子之配置中，在端子行之熱壓接前之暫貼狀態下，於紙面左側之端子20a上，導電粒子1僅由端子之緣部捕捉，故而擔心於連接後發生導通不良。
又，若使用導電粒子呈六方格子配置之異向性導電膜來連接端子行，則與端子之排列方向x垂直之排列軸之幾行導電粒子與捕捉相關針對每個端子有所不同，亦有由一個端子捕捉到之導電粒子之捕捉數存在較大偏差，捕捉數之分佈成為雙峰分佈之情形。該情況並不限定於六方格子，即便為正方格子或斜方格子亦可能產生。例如，如圖5B所示，由端子20b捕捉到之導電粒子1屬於與端子之排列方向x垂直之一個排列軸y1，但於端子20c中，捕捉到屬於2個排列軸y2、y3之導電粒子1。如圖5C所示，此種現象於端子行並非扇出型且各端子之軸為相同方向之端子行中較為明顯，1個排列軸y1與連接相關之端子20b及2個排列軸y2、y3與連接相關之端子20c分別存在相當之數量，由一個端子捕捉到之導電粒子數之偏差變大。因此，若將一個端子中之導電粒子之捕捉數與該捕捉數之端子之出現頻度圖表化，則有成為複數個峰之情況。即，因端子寬度與端子間空間、及粒徑與粒子間距離等複數個因素，例如有發現雙峰之情形。雖然並不會由於為雙峰而直接導致產生實用上之問題，但對於端子行中之各個端子，導電粒子之捕捉數之控制難以實用上不存在問題之範圍，例如即便所有端子均滿足不存在問題之捕獲數，亦會產生於端子行中混合有捕捉數較多之端子與較少之端子之情況。再者，由一個端子捕捉之導電粒子數之偏差並不限於以雙峰之形式出現。
又，因連接時之熱壓接，於端子上，導電粒子之間隔與端子之長邊方向相比於短邊方向上大幅地擴寬，端子上之導電粒子被擠出至端子間，亦包含被擠出之導電粒子在內而存在於端子間之導電粒子因熱壓接時之樹脂流動而移動。因此，若於端子行之右側與左側針對端子之導電粒子之分佈不同，於端子間形成導電粒子之密集部分，則產生容易於該部分發生短路之問題。
因熱壓接時之樹脂流動而導致由端子間之導電粒子引起短路之現象於端子行為放射狀之扇出型之情形時及於筆直之端子於相同方向上筆直地並列之情形時（筆直之平行排列）均會產生。對此，考慮對異向性導電膜之絕緣性樹脂層使用光硬化性樹脂來減少由導電粒子之樹脂流動引起之移動。然而，當藉由使用硬化性樹脂來抑制導電粒子之樹脂流動時，於熱壓接時對導電粒子之加壓容易變得不充分，擔心端子與導電粒子產生連接不良。因此，如日本專利6187665號公報中所記載般，亦考慮藉由使絕緣性樹脂層含有填料等而提昇絕緣性樹脂層之熔融黏度，於熱壓接時一面充分加壓一面抑制樹脂流動。然而，不論針對筆直之平行排列型之端子行，抑或針對扇出型之端子行，均要求更不易發生短路。其原因在於，僅藉由保持導電粒子之絕緣性樹脂之硬化性或黏度，難以完全防止導電粒子之短路。尤其是，於在生產線等中連續地製造複數個連接構造體之情形時，當產生不規則之樹脂流動或對準偏移時，擔心無法完全防止短路之發生。進而，若使端子佈局或電子零件之材質多樣化，則於任意之端子佈局或電子零件之材質中兼顧導通之確保與短路之防止將變得更難。
當為了使各端子中之導電粒子之捕捉數穩定，且抑制由樹脂流動所致之短路，而如專利文獻3中所記載般不使導電粒子之第1粒子行成為直線狀，而使粒子行具有粒徑以上之寬度時，無法嚴格地控制粒子配置，因此難以將各端子中之導電粒子之捕捉數收斂於規定之範圍內，於此情形時，當於連續地製造連接構造體之生產線等中產生不規則之樹脂流動或對準偏移時，難以將導電粒子之捕捉數收斂於規定之範圍內。該難度係連續地製造之連接構造體之數量越多則越高。又，即便如專利文獻4、5中所記載般重複配置導電粒子之單元來進行粒子配置，亦難以使扇出側之端子行之右側與左側之導電粒子之分佈相同，尤其是，若端子長度變短則該傾向增強，難以減少各端子中之導電粒子之捕捉數之偏差。
針對上述問題，本發明之課題在於，連接之端子行之各端子之軸於相同方向上並列，於端子行為直線之情形時及放射狀之扇出型之情形時，無關於電子零件之材質，均可利用各端子夾持充分之導電粒子，從而確保良好之導通狀態，藉此，可利用壓痕等確認之連接後之端子中之導電粒子之捕捉狀態相同，又，於連接微間距化之端子之情形時，亦能夠防止短路之發生。 [解決課題之技術手段]
本發明人想到如下內容而完成本發明：於異向性導電膜之導電粒子之配置中，重複配置第1斜方格子區域與第2斜方格子區域，該第1斜方格子區域由a方向之排列軸、及以角度α與該a方向斜交之b方向之排列軸所形成，該第2斜方格子區域由a方向之排列軸、及使上述b方向相對於a方向反轉後之c方向之排列軸（換言之，以角度-α與a方向斜交之c方向之排列軸）所形成，藉此，作為異向性導電膜整體，當使與a方向交叉之軸向起伏時，則於連接之各端子於相同方向上並列之情形時及於為扇出型之情形時，均可藉由使各端子中之導電粒子之捕捉數或分佈狀況均勻化，又，使端子間之導電粒子之相連容易斷開，而抑制短路。
即，本發明提供一種異向性導電膜，其係於絕緣性樹脂層配置有導電粒子者，且重複配置有第1斜方格子區域與第2斜方格子區域， 該第1斜方格子區域係於以角度α與a方向斜交之b方向上排列有複數個將導電粒子以規定間距配置於a方向而成之導電粒子排列軸a1； 該第2斜方格子區域係於使上述b方向相對於a方向反轉後之c方向上排列有複數個將導電粒子以規定間距配置於a方向而成之導電粒子排列軸a2。
再者，於本發明中，所謂異向性導電膜係指可形成異向性導電連接之膜。又，所謂異向性導電連接狀態係指具備複數個端子之電子零件彼此之對向之端子彼此電性連接，但鄰接之端子彼此未電性地連接之狀態。 [發明之效果]
根據本發明，重複配置有第1斜方格子區域與第2斜方格子區域，該第1斜方格子區域由a方向之排列軸、及以角度α與該a方向斜交之b方向之排列軸所形成，上述第2斜方格子區域由a方向之排列軸、及使上述b方向相對於a方向反轉後之c方向之排列軸（換言之，以角度-α與a方向斜交之c方向之排列軸）所形成，故而作為異向性導電膜整體，與a方向交叉之軸向呈鋸齒狀起伏。因此，即便於連接扇出型端子行之情形時，亦得以抑制連接後於特定之端子中導電粒子近接地複數個相連而導致壓痕之痕跡變淺等導電粒子之端子間之夾持狀態難以分辨之情況，或於端子間導電粒子複數個相連而導致發生短路之情況。
又，於在生產線中連續地進行熱壓接之情形等時，即便熱壓接意外地偏離規定之溫度條件等而不規則地產生樹脂流動時，亦能夠防止其影響過度地顯現，故而能夠抑制短路。
如此，於連接後之端子行中壓痕之痕跡均勻，又，端子間之短路得到抑制之效果並不限於扇出型端子行，亦可於複數個端子筆直地排列於一方向上之情形時獲得。
以下，一面參照圖式，一面對本發明之異向性導電膜之一例進行詳細說明。再者，於各圖中，相同符號表示相同或同等之構成要素。
＜異向性導電膜之整體構成＞ 圖1A係表示實施例之異向性導電膜10A之導電粒子之配置的俯視圖，圖2係其X-X剖面圖。該異向性導電膜10A具有如下層構成：導電粒子1以單層配置於絕緣性樹脂層2之表面或其附近，且於其上積層有低黏度樹脂層3。再者，於本發明中，低黏度樹脂層3係視需要而設置，如圖3所示之異向性導電膜10B之剖面圖，亦可設為省略了低黏度樹脂層3之層構成。該異向性導電膜10B之導電粒子1之平面配置可設為與具有低黏度樹脂層3之異向性導電膜10A相同。
本實施例之異向性導電膜10A、10B中之導電粒子1之平面配置係如下所述，交替地重複配置有第1斜方格子區域11與第2斜方格子區域12。此處，第1斜方格子區域11係排列軸為a方向與b方向之斜方格子（a方向與b方向所成之角度：α），第2斜方格子區域12係排列軸為a方向與c方向之斜方格子（a方向與c方向所成之角度：-α）。
＜導電粒子＞ ・粒子材料 作為導電粒子1，可列舉鎳、鈷、銀、銅、金、鈀等金屬粒子、焊料等合金粒子、金屬被覆樹脂粒子等。亦可併用兩種以上。其中，就於連接後因樹脂粒子排斥而容易維持與端子之接觸，導通性能穩定之方面而言，金屬被覆樹脂粒子較佳。又，對導電粒子之表面可實施不會對導通特性造成妨礙之絕緣處理，例如可藉由公知之技術使絕緣性微粒子附著，亦可利用絕緣性樹脂進行絕緣塗佈。
・粒徑 導電粒子1之粒徑係根據用途而適當選擇。通常，為了抑制導通電阻之上升且抑制短路之發生，較佳為1 μm以上且30 μm以下，若為微間距用途，則較佳為2 μm以上且未達10 μm。分散至絕緣性樹脂層之前之導電粒子之粒徑可利用通常之粒度分佈測定裝置進行測定，又，平均粒徑亦可使用粒度分佈測定裝置而求出。作為測定裝置，可列舉圖像型之FPIA-3000（Malvern公司）作為一例。於此情形時，較理想為將測定導電粒徑之樣本數設為1000以上、較佳為2000以上。異向性導電膜中之導電粒子之粒徑可由SEM等電子顯微鏡觀察而求出。於此情形時，較理想為將測定導電粒徑之樣本數設為200以上、較佳為1000以上。
又，關於粒徑之偏差，粒徑之CV值較佳為20%以下。因粒徑之偏差較小，故而可獲得較大之熱壓接時之加熱加壓條件之範圍。
再者，於使用對導電粒子之表面實施有上述絕緣處理者作為導電粒子之情形時，本發明中之導電粒子之粒徑意指不包含絕緣處理之部分之粒徑。
・平面配置 如圖1A所示，導電粒子之平面配置係於與a方向垂直之y方向上交替重複配置有第1斜方格子區域11與第2斜方格子區域12者。於本實施例中，第1斜方格子區域11係如下區域：於以角度α與a方向斜交之b方向上排列有複數個將導電粒子1以固定間距pa配置於a方向而成之排列軸a1。又，第2斜方格子區域12係如下區域：於c方向上排列有複數個將導電粒子1以上述間距pa配置於a方向而成之導電粒子排列軸a2，該c方向係將與a方向之排列軸平行之直線設為對象之軸使b方向反轉後之方向。或者，c方向係以角度-α與a方向斜交之方向。該粒子配置亦可視作以彎曲之排列d為單位，該排列d係由第1斜方格子區域11之b方向之排列及第2斜方格子區域12之c方向之排列所構成，且於圖1A中由二點鏈線包圍。
再者，第2斜方格子區域12之排列軸a2上之粒子間距亦可與第1斜方格子區域11之排列軸a1上之粒子間距pa不同，但為了粒子配置之設計上之方便，較佳為使排列軸a2與排列軸a1之間距pa相等。
如本實施例，關於導電粒子1之配置，若使將a方向及與該a方向斜交之b方向設為排列軸之第1斜方格子區域、和將a方向及使上述b方向反轉後之c方向設為排列軸之第2斜方格子區域交替地重複，則不論於利用異向性導電膜將如圖4A所示之扇出型端子行（即，端子20之長邊方向相對於端子20之排列方向x之角度（扇出角β）依次不同之端子行）之情形時，抑或於將如圖4B所示各端子之軸為相同方向之直線狀之端子行連接之情形時，針對各端子之導電粒子之配置均為均等，且連接後各端子中之導電粒子之捕捉數均穩定。與此相對，當異向性導電膜中之導電粒子之配置僅為第1斜方格子區域或僅為第2斜方格子區域時，被端子捕捉到之導電粒子之數量或端子中之導電粒子之分佈狀態之偏差變大，於扇出型端子行中之任一端子中，於異向性導電膜中配置成格子狀之導電粒子之排列軸之方向與端子之長邊方向重疊，排列於端子之緣部之導電粒子之捕捉性急遽下降，或因於任一端子中捕捉到複數個導電粒子近接地排列而得之粒子群，導致端子中之各個導電粒子之壓痕變淺，或於端子間形成導電粒子之密集區域。於本發明之異向性導電膜中不易產生此種問題。
又，如圖4A、圖4B所示，於本發明之異向性導電膜中，由於紙面左側之端子與紙面右側之端子中導電粒子之捕捉狀態或壓痕之痕跡相等，故而將a方向設為與端子之排列方向x相同之方向較佳，就方便使用異向性導電膜之方面而言，較佳為將a方向設為異向性導電膜之長邊方向。或者，較佳為將端子之排列方向x設為異向性導電膜之長邊方向。又，較佳為第1斜方格子區域11與第2斜方格子區域12之重複數量相對於端子之長邊方向之長度足夠多，例如，相對於設為連接對象之端子之端子長度，該重複數量較佳為設為1以上，更佳為3以上。換言之，較佳為第1斜方格子區域11與第2斜方格子區域12之y方向之重複間距為設為連接對象之端子之端子長度以下或端子長度之1/3以下。或者，以各端子中之導電粒子之捕捉數較佳為3個以上，更佳為11個以上之方式來決定由第1斜方格子區域11之b方向之排列軸與第2斜方格子區域12之c方向之排列軸所形成之排列軸之彎曲數。
於第1斜方格子區域11中，關於a方向與b方向所成之角度α，於連接之端子行為扇出型之情形時，使角度α之絕對值小於扇出角β之絕對值之最小值。藉此，於構成端子行之任一端子中，於第1斜方格子區域11中端子之長邊方向與b方向亦變得不一致，故而能夠防止存在於端子之長邊方向之緣部之導電粒子之捕捉性急遽下降之情況、或於端子上複數個導電粒子連續地成行被捕捉而導致壓痕減少之情況。另一方面，於連接之端子行並非扇出排列之情形時，若使角度α之絕對值為端子之排列方向與端子之長邊方向所成之角度β之絕對值以下，則於端子之排列方向與端子之長邊方向正交之端子行（即，角度β＝90°）中，導電粒子之捕捉數穩定，故而較佳。又，即便於如周圍配置般混合有0°與90°之角度β之情形時，導電粒子之捕捉數亦穩定，故而較佳。
又，於第2斜方格子區域12中，c方向係使b方向相對於a方向反轉後之方向，a方向與c方向所成之角度為-α。藉由如上所述地設定角度α，於第2斜方格子區域12中，端子之長邊方向與c方向亦變得不一致，故而可獲得與上述相同之效果。
再者，當角度α為90°時，第1斜方格子區域11及第2斜方格子區域12中之粒子配置成為正方格子或長方格子，故而角度α亦可表示為正方格子或長方格子之a方向之應變量s（圖1A）。若應變量s大於平均粒徑，則於異向性導電連接時，同一斜方格子區域內之導電粒子不易產生y方向上之連結。另一方面，若應變量s為平均粒徑以下、較佳為未達平均粒徑，則即便端子寬度較窄，導電粒子亦容易被異向性導電連接後之端子捕捉到，故而較佳。
又，c方向與a方向所成之角度亦可並非嚴格地為使角度α之符號反轉而成者。即，b方向與a方向所成之角度之絕對值和c方向與a方向所成之角度之絕對值可並非嚴格地相同，亦可針對每個斜方格子區域有所不同。於此情形時，較佳為所有斜方格子區域中之該等角度之合計為0°。
且說，於將任意之排列軸a11 中鄰接之導電粒子之中心位置設為P1、P2，並將鄰接於該排列軸a11 之排列軸a1（a12 ）上之導電粒子且a方向之位置處於P1、P2之間之導電粒子的中心位置設為P3之情形時，若∠P3P1P2≠∠P3P2P1，則如圖1A所示，第1斜方格子區域11之粒子配置與第2斜方格子區域12之粒子配置成為線對稱且不同之粒子配置，即便使該等區域平行移動，粒子配置亦不會重疊。即，該等斜方格子區域11、12中之一區域之與a方向斜交的任意之排列軸之延長線亦不成為另一區域之排列軸。
與此相對，如圖1B所示，若∠P3P1P2＝∠P3P2P1，則第1斜方格子區域11之粒子配置與第2斜方格子區域12之粒子配置本身相等。此處， 於將第1斜方格子區域11與第2斜方格子區域12之距離設為L3， 將於第1斜方格子區域11中鄰接之排列軸a1彼此之距離設為L1， 將於第2斜方格子區域12中鄰接之排列軸a2彼此之距離設為L2， 將鄰接之第1斜方格子區域11之排列軸a1與第2斜方格子區域12之排列軸a2上的導電粒子之位置之a方向之偏移量設為Ld， 將排列軸a1、a2之間距設為pa時， 若L3＝L1、L2，且Ld＝（1/2）×pa，則與第1斜方格子區域11中之b方向之排列軸相同方向之排列軸亦存在於第2斜方格子區域12，且該第2斜方格子區域之排列軸之延長線成為第1斜方格子區域之b方向之排列軸。關於如此與a方向斜交之排列軸，當兩斜方格子區域11、12中之一斜方格子區域之排列軸亦直接成為另一斜方格子區域之排列軸時，於異向性導電膜整體中，與a方向交叉之排列軸未成為鋸齒狀，此種粒子配置無法獲得本發明之效果。因此，此種粒子配置將自本發明中排除。
另一方面，若∠P3P1P2≠∠P3P2P1，則即便L3＝L1、L2，且Ld＝（1/2）×pa，亦可獲得本發明之效果。例如可將導電粒子之平均粒徑設為3.2 μm，將第1斜方格子區域11與第2斜方格子區域12中之a方向之排列軸之數量分別設為2，且設為L1＝L2＝L3＝9.5 μm、pa＝9 μm、Ld＝（1/2）×pa＝4.5 μm、應變量s＝2.25 μm、α＝76°、個數密度12000個/mm2 （圖1I）。
又，可使用相同之平均粒徑之導電粒子，將第1斜方格子區域11與第2斜方格子區域12中之a方向之排列軸之數量分別設為2，且設為L1＝L2＝10.4 μm、L3＝8.8 μm、pa＝8.8 μm、Ld＝（1/2）×pa＝4.4 μm、應變量s＝2.2 μm、α＝78°、個數密度12000個/mm2 （圖1J）。
可使用相同之平均粒徑之導電粒子，將第1斜方格子區域11與第2斜方格子區域12中之a方向之排列軸之數量分別設為2，且設為L1＝L2＝L3＝7.5 μm、pa＝8.4 μm、Ld＝（1/2）×pa＝4.2 μm、應變量s＝2.1 μm、α＝75°、個數密度16000個/mm2 （圖1K）。如此，間距pa亦可大於L1、L2、L3。
再者，於圖1I、圖1J、圖1K所示之態樣中，將間距pa之1/2設為偏移量Ld，將偏移量Ld之1/2設為應變量s。若使間距pa、偏移量Ld及應變量s具有該關係，則於方便設計粒子配置之方面較佳。又，容易於製造異向性導電膜之後進行導電粒子之配置狀態之確認。例如，若於拍攝有異向性導電膜之圖像中進行畫出連結導電粒子之中心點或外切線之輔助線等操作，則可容易地確認偏移量Ld或應變量s。
又，如圖1B所示，即便∠P3P1P2＝∠P3P2P1，若L3≠L1、L2，或Ld≠（1/2）×pa，則可將第1斜方格子區域11與第2斜方格子區域12識別為不同之區域，於異向性導電膜整體中，與a方向交叉之排列軸成為鋸齒狀，可獲得本發明之效果。
於本發明中，關於偏移量Ld，為了適度地擴大異向性導電膜中之y方向之粒子間距離，於各端子中確保適當之捕捉粒子數，且防止於連接時端子間之粒子連結而引起短路，較佳為偏移量不為零。即，若將偏移量Ld設為零，則於y方向上相鄰之第1斜方格子區域之導電粒子與第2斜方格子區域之導電粒子於y方向上重疊，故而當距離L3較短時，因連接時之端子間之樹脂流動而容易產生導電粒子彼此之連結。因此，偏移量Ld之絕對值較佳為大於零，更佳為大於平均粒徑之0.5倍以上，進而較佳為大於平均粒徑之1倍以上，特佳為大於平均粒徑之1倍。另一方面，偏移量Ld之上限較佳為排列軸a1、a2之間距pa之0.5倍以下，更佳為未達0.5倍，進而更佳為0.3倍以下。
圖1C所示之粒子配置係於圖1A所示之粒子配置中將偏移量Ld設為0而成者。於距離L3相對於連接時之端子間之導電粒子之移動量較長之情形時，亦可將偏移量Ld設為0。
圖1D所示之粒子配置係於圖1A所示之粒子配置中，藉由偏移量Ld之調整，使第1斜方格子區域11之b方向之排列軸與第2斜方格子區域12之c方向之排列軸於導電粒子1上交叉而成者。藉此，b方向與c方向之反轉之對稱軸成為a1軸或a2軸，藉由於y方向上無間隙地重複反轉形狀，可使導電粒子之配置之設計或配置後之檢查步驟變得簡單，故而較佳。
圖1E所示之粒子配置係於圖1A所示之粒子配置中，使第1斜方格子區域11與第2斜方格子區域12之距離L3和第1斜方格子區域11中鄰接之排列軸a1彼此之距離L1或第2斜方格子區域12中鄰接之排列軸a2彼此之距離L2不同而成者。關於該等距離L1、L2、L3，於本發明中，就粒子配置之設計上之方便、相同端子行內之端子彼此之導電粒子之捕捉狀態進行比較之容易度等方面而言，較佳為設為L1＝L2或L1＝L2＝L3。另一方面，於扇出排列中，例如於以左右之最外側之端子彼此獲得同等之捕捉狀態之方式調整角度α、間距pa、第1斜方格子區域11與第2斜方格子區域12之重複間距等之情形時，為了容易於檢查中比較連接後之捕捉狀態等，亦可設為L3≠L1、L2。於此情形時，亦可設為L1≠L2。
又，距離L1、L2較佳為根據端子佈局來決定，其本身上限、下限均無特別限制。作為一例，當距離L1、L2過小時，導電粒子容易被捕捉，但容易發生短路，因此距離L1、L2較佳為導電粒子之平均粒徑D之1.4倍以上。
第1斜方格子區域11之排列軸a1及第2斜方格子區域12之排列軸a2上之導電粒子之間距pa較佳為根據端子佈局來決定，上限、下限均無特別限制。作為一例，當間距pa過小時，容易發生短路，故而間距pa較佳為導電粒子之平均粒徑D之1.5倍以上，特佳為設為對平均粒徑D之2倍加上0.5 μm所得之距離以上。藉此，即便因異向性導電連接時之熱壓接之樹脂流動，由對向端子夾持之導電粒子移動至端子間空間，亦能夠防止端子間空間之導電粒子1之連結，從而謀求防止進一步之短路。
另一方面，若增大間距pa，則可削減異向性導電膜中所需之導電粒子之個數。又，即便端子寬度較窄，只要端子長度足夠長，則由每個端子捕捉到之導電粒子之數量亦滿足規定數量。因此，於將a方向設為與端子之排列方向相同方向之情形時，間距pa較佳為成為經由異向性導電膜連接之電子零件之端子彼此的連接後之有效連接區域之最小寬度之1/2～2/3。
又，就整個面中捕捉狀態均等之方面而言，較佳為使距離L1、L2、L3與間距pa相等，即，將第1斜方格子區域11及第2斜方格子區域12各自之粒子配置設為使正方格子於a方向上歪斜所得之斜方格子，進而亦使第1斜方格子區域11與第2斜方格子區域12之距離L3與格子間距相等。
圖1F所示之粒子配置係於圖1A所示之粒子配置中，將第1斜方格子區域11中之排列軸a1之排列數n1、及第2斜方格子區域12中之排列軸a2之排列數n2設為2所得者，上述圖1I、圖1J、圖1K係將其進一步具體化所得之態樣。於本發明中，關於第1斜方格子區域11中之排列軸a1之排列數n1與第2斜方格子區域12中之排列軸a2之排列數n2，較佳為使兩者相等，但亦可使兩者不同。又，該等排列數n1、n2能夠根據端子佈局來決定，故而無特別限定。於微間距中，為了兼顧導電粒子之捕獲與短路之抑制，較佳為將排列數n1、n2設為4以下，更佳為設為3以下，進而較佳為設為2。其原因在於，若將第1斜方格子區域中之排列軸a1之排列數n1與第2斜方格子區域中之排列軸a2之排列數n2設為2至4，則與較其多之情形相比，排列軸之鋸齒之間距變細，故而可使連接扇出型端子行之情形時之右側端子與左側端子中之導電粒子之分佈狀態更進一步均等，即便導電粒子因異向性導電連接時之樹脂流動而移動，導電粒子彼此亦不易接觸。
圖1G所示之粒子配置係於圖1A所示之粒子配置中，代替將第1斜方格子區域11中之a方向之導電粒子之間距設為單一之間距pa，而使其交替地重複不同之間距pa1與間距pa2，於第2斜方格子區域12中亦使a方向之導電粒子之間距pal與間距pa2交替重複。如此，於本發明中，配置於a方向上之導電粒子之間距只要為規律性之間距即可，亦可不必為固定之間距。
圖1H所示之粒子配置係於圖1A所示之粒子配置中，在第1斜方格子區域11中設置有b方向之排列軸於a方向上偏移所得之2個第1斜方格子區域11a、11b，於第2斜方格子區域12中亦設置有c方向之排列軸於a方向上偏移所得之兩個第2斜方格子區域12a、12b者。於此情形時，2個第1斜方格子區域11a、11b之鄰接之排列軸a1彼此之a方向之偏移量Ld1與2個第2斜方格子區域12a、12b之鄰接之排列軸a2彼此之a方向之偏移量Ld2可相同亦可不同。
如此，於本發明中，只要使第1斜方格子區域與第2斜方格子區域於y方向上重複即可，亦可不必使其等交替地重複。於此情形時，較佳為在y方向之單位長度中，第1斜方格子區域之排列軸a1之y方向之重複數之總數與第2斜方格子區域之排列軸a2之y方向之重複數之總數相等。
・個數密度 於圖1A～圖1K之任一粒子配置中，就本發明之異向性導電膜而言，亦能夠根據連接之電子零件之端子之形狀、大小、排列間距等來決定導電粒子之個數密度。通常，為了根據連接之電子零件之組合或用途來改變較佳之條件，導電粒子之個數密度並無特別限制，下限於實用上只要為30個/mm2 以上即可，較佳為150個/mm2 以上。若導電粒子數較少，則預計有成本削減效果。又，上限於實用上較佳為70000個/mm2 以下，更佳為42000個/mm2 以下，尤其是於微間距用途之情形時，較佳設為6000～35000個/mm2 之範圍。又，於導電粒子之平均粒徑為10 μm以上之情形時，較佳設為50～2000個/mm2 之範圍。
再者，於本發明中，導電粒子之個數密度與將角度α設為90°且將第1斜方格子區域11及第2斜方格子區域12設為正方格子或長方格子而非斜方格子之情形時之個數密度相等，故而可藉由利用該正方格子或長方格子算出格子間距離來決定間距pa或距離L1、L2。
作為測定個數密度之情形時之測定區域，較佳為任意地設定多處（較佳為5處以上，更佳為10處以上）一邊為100 μm以上之矩形區域，使測定區域之合計面積為2 mm2 以上。矩形區域之邊之長度或合計面積只要根據平均粒徑調整即可。各個測定區域之大小或數量只要根據個數密度之狀態適當調整即可。例如只要於一個矩形區域中存在數十個以上之導電粒子即可。作為更具體之例，於微間距用途中導電粒子之個數密度相對較大之異向性導電膜之情形時，對於200處面積100 μm×100 μm之區域（2 mm2 ），可藉由使用利用金屬顯微鏡等所得之觀察圖像來測定個數密度並將其平均而求出。個數密度亦可藉由圖像解析軟體（例如三谷商事股份有限公司製造之WinROOF、旭化成工程公司製造之A Image-kun等）計測觀察圖像而求出。另一方面，於導電粒子之個數密度較小之情形時，亦可基於規則地配置有導電粒子，而根據膜之長邊方向之排列軸上之間距與該排列軸之膜寬度方向之排列間距算出個數密度。再者，矩形之邊之長度與測定處之數量並非限定於上述數值者。
又，關於導電粒子之個數密度，就降低導通電阻之方面而言，較佳為將利用下式算出之導電粒子之面積佔有率設為0.3%以上。另一方面，就抑制連接時按壓治具所需之推力之方面而言，較佳為將該面積佔有率設為35%以下，更佳為設為30%以下。 導電粒子之面積佔有率（%）＝[俯視下之導電粒子之個數密度]×[1個導電粒子之俯視面積之平均]×100
・導電粒子之膜厚方向之位置 導電粒子1之膜厚方向之位置較佳為一致。例如，如圖2所示，可使導電粒子1之膜厚方向之埋入量Lb一致。藉此，端子中之導電粒子1之捕捉性容易穩定。另一方面，於本發明中，導電粒子1可自絕緣性樹脂層2露出，亦可完全埋入。
此處，埋入量Lb係指埋入有導電粒子1之絕緣性樹脂層2之表面（絕緣性樹脂層2之正面與背面中之露出有導電粒子1之側之表面；或於導電粒子1完全埋入至絕緣性樹脂層2之情形時與導電粒子1之距離較近之表面）且鄰接之導電粒子間之中央部之切線面2p、與導電粒子1之最深部之距離。
再者，埋入量Lb可藉由利用SEM圖像觀察異向性導電膜之膜剖面之一部分而求出。於此情形時，較佳為自異向性導電膜任意抽取10處以上面積30 mm2 以上之區域，計測較佳為合計50個以上、更佳為200個以上之導電粒子之埋入量，並求出其平均。
・埋入率 於將導電粒子1之埋入量Lb相對於平均粒徑D之比率設為埋入率（Lb/D）之情形時，埋入率較佳為30%以上且105%以下。藉由將埋入率（Lb/D）設為30%以上，可利用絕緣性樹脂層2將導電粒子1維持於規定之位置，又，藉由將埋入率（Lb/D）設為105%以下，可減少於異向性導電連接時以使端子間之導電粒子無用地流動之方式發揮作用之絕緣性樹脂層之樹脂量。
＜絕緣性樹脂層＞ 於本發明中，絕緣性樹脂層2可與日本專利6187665號公報中所記載之異向性導電膜之絕緣性樹脂層同樣地，使用由聚合性化合物與聚合起始劑形成之硬化性樹脂組成物而形成。於此情形時，作為聚合起始劑，可使用熱聚合起始劑，可使用光聚合起始劑，亦可併用其等。例如使用陽離子系聚合起始劑作為熱聚合起始劑，使用環氧樹脂作為熱聚合性化合物，使用光自由基聚合起始劑作為光聚合起始劑，使用丙烯酸酯化合物作為光聚合性化合物。亦可使用陰離子熱聚合起始劑作為熱聚合起始劑。作為陰離子熱聚合起始劑，較佳為使用以咪唑改質體為核心，利用聚胺酯（polyurethane）被覆其表面而成之微膠囊型潛在性硬化劑。
＜絕緣性樹脂層之最低熔融黏度＞ 絕緣性樹脂層2之最低熔融黏度並無特別限定，可為1000 Pa∙s以上，且可設為與日本專利6187665號公報中所記載之異向性導電膜之絕緣性樹脂層之最低熔融黏度相同，較佳為1500 Pa∙s以上，更佳為2000 Pa∙s以上，進而較佳為3000～15000 Pa∙s，特佳為3000～10000 Pa∙s。該最低熔融黏度可使用作為一例之旋轉式流變儀（TA Instrument公司製造），於5 g之測定壓力下保持為固定，使用直徑8 mm之測定板求出，更具體而言，可藉由於30～200℃之溫度範圍內，將升溫速度設為10℃/分，將測定頻率設為10 Hz，將相對於上述測定板之負重變動設為5 g而求出。再者，最低熔融黏度之調整可藉由作為熔融黏度調整劑而含有之微小固形物之種類或摻合量、樹脂組成物之調整條件之變更等而進行。
＜低黏度樹脂層＞ 低黏度樹脂層3係30～200℃之範圍之最低熔融黏度較絕緣性樹脂層2低之樹脂層。於本發明中，低黏度樹脂層3視需要而設置，於藉由將低黏度樹脂層3積層於絕緣性樹脂層2，而將介隔異向性導電膜10A相對之電子零件進行熱壓接之情形時，能夠利用低黏度樹脂層3填充由電子零件之電極或凸塊形成之空間，從而提高電子零件彼此之接著性。
又，絕緣性樹脂層2之最低熔融黏度與低黏度樹脂層3之最低熔融黏度之差越大，則經由異向性導電膜10A連接之電子零件間之空間越被低黏度樹脂層3填充，電子零件彼此之接著性容易提高。又，該差越大，則保持導電粒子1之絕緣性樹脂層2之熱壓接時之移動量相對於低黏度樹脂層3相對地變小，因此端子之導電粒子1之捕捉性容易提高。
絕緣性樹脂層2與低黏度樹脂層3之最低熔融黏度比亦取決於絕緣性樹脂層2與低黏度樹脂層3之層厚之比率，較佳為2以上，更佳為5以上，進而較佳為8以上。另一方面，若該比過大，則於使長條之異向性導電膜成為捲裝體之情形時，有產生樹脂之溢出或黏連之虞，故而實用上較佳為15以下。低黏度樹脂層3之較佳之最低熔融黏度更具體而言滿足上述絕緣性樹脂層之最低熔融黏度比，且較佳為3000 Pa∙s以下，更佳為2000 Pa∙s以下，進而較佳為100～2000 Pa∙s。
再者，低黏度樹脂層3可藉由對與絕緣性樹脂層2相同之樹脂組成物調整黏度而形成。
＜絕緣性樹脂層與低黏度樹脂層之層厚＞ 為了於下述異向性導電膜之製造步驟中，將導電粒子1穩定地壓入至絕緣性樹脂層2，絕緣性樹脂層2之層厚相對於導電粒子1之平均粒徑D較佳為0.3倍以上，更佳為0.6倍以上，進而較佳為0.8倍以上，特佳為1倍以上。又，關於絕緣性樹脂層2之層厚之上限，可根據連接之電子零件之端子形狀、端子厚度、排列間距等而決定，但若層厚過厚，則於連接時導電粒子1容易多餘地受到樹脂流動之影響，因此較佳為導電粒子1之平均粒徑D之20倍以下，更佳為15倍以下。
低黏度樹脂層3於本發明中視需要而設置，於設置低黏度樹脂層之情形時，作為其層厚之下限，較佳為導電粒子1之平均粒徑D之0.2倍以上，更佳為1倍以上。又，關於低黏度樹脂層3之層厚之上限，若過厚則與絕緣性樹脂層2之積層之困難性增加，故而較佳為導電粒子1之平均粒徑D之50倍以下，更佳為15倍以下，進而較佳為8倍以下。
又，就於電子零件之連接時抑制導電粒子1之多餘之流動之方面、抑制將異向性導電膜設為捲裝體之情形時之樹脂之溢出或黏連之方面、使異向性導電膜之每單位重量之膜長變長之方面等而言，絕緣性樹脂層2與低黏度樹脂層3之總厚度較佳為較薄。但，若過薄，則異向性導電膜之操作性變差。又，有難以將異向性導電膜貼合於電子零件，於連接電子零件時之暫時壓接中無法獲得所需之黏著力之虞，於正式壓接中亦有因樹脂量不足而導致無法獲得所需之接著力之虞。因此，總厚度相對於導電粒子1之平均粒徑D較佳為0.6倍以上，更佳為0.8倍以上，進而較佳為1倍以上，特佳為1.2倍以上。
關於絕緣性樹脂層2與低黏度樹脂層3之厚度之比率，可根據連接所使用之電子零件之組合、或其被要求之性能等之關係進行適當調整。該等層厚可利用市售之數位厚度規等進行測定。數位厚度規之分辨率較佳為0.1 μm以下。
＜異向性導電膜之捲裝體＞ 本發明之異向性導電膜於其製品形態下可設為捲裝體。關於捲裝體之長度並無特別限制，就出廠貨之操作性之方面而言較佳為5000 m以下，更佳為1000 m以下，進而較佳為500 m以下。另一方面，就捲裝體之量產性之方面而言較佳為5 m以上。作為膜寬度，並無特別限制，就安裝體之小型化之觀點而言要求較窄。另一方面，就統一將複數個零件進行異向性導電連接或者以某種程度較大之尺寸統一進行異向性導電連接後進行切削等使用方法之觀點而言，要求面積較大，故而亦需要寬度較寬者。
＜異向性導電膜之製造方法＞ 本發明之異向性導電膜之製造方法本身並無特別限定，例如藉由如下方法製造異向性導電膜：製造用以將導電粒子配置成規定之排列之轉印模，於轉印模之凹部填充導電粒子，於其上被覆形成於剝離膜上之絕緣性樹脂層並施加壓力，將導電粒子壓入至絕緣性樹脂層，藉此使導電粒子轉接著於絕緣性樹脂層，或者進一步於該導電粒子上或與轉接著有導電粒子之面相反之面上積層低黏度樹脂層。
又，亦可藉由如下方法製造異向性導電膜：於轉印模之凹部填充導電粒子之後，於其上被覆絕緣性樹脂層，在轉印模中不將導電粒子壓入至絕緣性樹脂層，而使導電粒子自轉印模轉印至絕緣性樹脂層之表面，於轉印後將絕緣性樹脂層上之導電粒子壓入至絕緣性樹脂層內。
再者，作為轉印模，除使用於凹部填充導電粒子者以外，亦可使用對凸部之頂面賦予微黏著劑而使導電粒子附著於該頂面者。該等轉印模可使用機械加工、光微影法、印刷法等公知之技術製造。
又，作為將導電粒子配置成規定之排列之方法，亦可代替使用轉印模之方法，而使用使導電粒子通過以規定之配置設置之貫通孔之方法、將導電粒子直接散佈於膜上之方法、使緊密地配置有導電粒子之膜延伸之方法等。
＜使用異向性導電膜之電子零件之連接方法＞ 作為使用本發明之異向性導電膜連接電子零件之方法，例如於載台上載置一電子零件，於其上介隔異向性導電膜載置另一電子零件，利用壓接工具進行加熱按壓，藉此將兩電子零件之端子彼此進行異向性導電連接而製造連接構造體。於此情形時，將載置於載台之電子零件設為IC晶片、IC模組、FPC、玻璃基板、塑膠基板、剛性基板及陶瓷基板等第2電子零件，將利用壓接工具進行加熱加壓之電子零件設為FPC、IC晶片、IC模組等第1電子零件。作為更詳細之方法，將異向性導電膜暫貼於各種基板等第2電子零件並進行暫時壓接，將IC晶片等第1電子零件與暫時壓接之異向性導電膜接合且進行熱壓接，藉此進行異向性導電連接而製造連接構造體。再者，亦可將異向性導電膜暫貼於第1電子零件而非第2電子零件來製造連接構造體。又，連接方法並不限定熱壓接，亦可進行利用光硬化之壓接或併用熱與光之壓接等。
本發明之異向性導電膜於將第1電子零件及第2電子零件之至少一者設為FPC或塑膠基板等容易熱膨脹之材質之情形時意義重大。於端子行為扇出型之情形時，尤其會發揮出效果。又，即便為端子之長邊方向相對於端子之排列方向未傾斜之端子行之連接、或如周圍配置之端子般端子之排列方向於零件之各邊不同之情形時之連接，進而不論端子形狀為矩形抑或圓形，針對導電粒子均同樣地配置導電粒子，故而能夠確實地連接該等端子且抑制短路之發生，壓痕檢查亦變得容易。因此，本發明之異向性導電膜不論連接之端子行之形狀或配置如何均可通用。藉此，準備根據連接之對象而導電粒子之配置或個數密度不同之異向性導電膜，可削減所使用之工時，故而該工時削減所帶來之經濟上優勢亦較高。因此，本發明包含使用本發明之異向性導電膜將第1電子零件之端子與第2電子零件之端子異向性導電連接之連接構造體之製造方法、或經由本發明之異向性導電膜將第1電子零件與第2電子零件異向性導電連接之連接構造體。
本發明之異向性導電膜之粒子配置亦可應用於使用各種填料來代替導電粒子者。作為此情形時之填料，例如可使用日本特開2019-033060號公報、日本特開2018-090768號公報等中所記載之填料。因此，可將本發明應用於按照本發明之粒子配置而配置有該等公報中所記載之填料之含填料膜（即填料配置膜）、使用該含填料膜連接第1物品與第2物品之方法、第1物品與第2物品之連接構造體之製造方法、及藉此獲得之連接構造體等。又，亦可將本發明應用於僅於第1物品貼附有含填料膜之連接體或其製造方法等。 [實施例]
以下，根據實施例對本發明進行具體說明。 實驗例1～5 於表1之規格之扇出型端子行A或B中，藉由模擬而計測並評價了將表2所示之實驗例1～5之粒子配置之異向性導電膜進行連接之情形時之以下（a）～（d）之評價項目。其中，實驗例1～3為本發明之實施例。將評價結果示於表2。與（d）之評價結果關聯，將於實驗例1、3、4、5導電粒子之配置中將個數密度設為16000個/mm2 之情形時之端子行B中之導電粒子之捕捉狀態之模擬結果（端子上及端子間之粒子間距離之擴大比率亦與表1相同）示於圖7A～圖7D。
再者，於該模擬中，使端子之排列方向即x方向與異向性導電膜之a方向為同一方向。又，端子上之關於x方向或y方向之壓接後之粒子間距離與壓接前之粒子間距離之比率、及端子間之關於x方向或y方向之壓接後之粒子間距離與壓接前之粒子間距離之比率係藉由事先於相同之端子行中對異向性導電膜之對應之比率進行多次實測而獲得之平均值。
（a）各個端子之導電粒子之最低捕捉數（端子行A之模擬） OK：5個以上 NG：4個以下 再者，該評價基準係模擬中之評價，故而設為更嚴格之評價基準。 （b）於端子間在端子之長邊方向上連結之導電粒子數（端子行B之模擬） OK：3個以下 NG：4個以上 （c）於端子上呈直線狀排列之導電粒子數（端子行B之模擬） OK：3個以下 NG：4個以上 （d）端子排列之右側與左側之導電粒子的捕捉性之左右之均勻性（端子行B之模擬） 均勻：由端子排列中處於左右對稱之距離之端子捕捉之導電粒子之分佈圖案彼此看上去相同之情形 不均勻：由端子排列中處於左右對稱之距離之端子捕捉之導電粒子之分佈圖案彼此看上去不同之情形
[表1]
Figure 108128352-A0304-0001
 （註）x方向：端子之排列方向 y方向：與x方向垂直之方向 （*1）端子上之關於x方向之壓接後之粒子間距離與壓接前之粒子間距離之比率 （*2）端子上之關於y方向之壓接後之粒子間距離與壓接前之粒子間距離之比率 （*3）端子間之關於x方向之壓接後之粒子間距離與壓接前之粒子間距離之比率 （*4）端子間之關於y方向之壓接後之粒子間距離與壓接前之粒子間距離之比率 （*5）放射狀排列之基端側之端子間距（最窄之端子間距）
[表2]
Figure 108128352-A0304-0002
Figure 108128352-A0304-0003
 （*3）端子行A上之模擬 （*4）端子行B上之模擬
根據表2可知，實驗例1～3之任一評價項目均為良好，於各端子充分地確保粒子捕捉數，且於配線間在y方向上連結之粒子數或排列於配線上之粒子數減少，扇出排列之左右之均勻性良好。
與此相對，於實驗例4中，可知因排列於端子上之粒子數或於端子間在y方向上連結之粒子數較多，故而容易發生短路，左右之均勻性亦變差。又，於實驗例5中，可知左右之均勻性良好，但端子之粒子捕捉數不足。根據圖7A～圖7D所示之模擬結果亦可知，根據與本發明之實施例相當之實驗例之粒子配置，端子行之粒子捕捉之均勻性良好。
實驗例6～9 （異向性導電膜之製作） 以表3所示之摻合來製備絕緣性樹脂層形成用樹脂組成物及低黏度樹脂層形成用樹脂組成物，使用該樹脂組成物以與日本專利第6187665號之實施例3相同之方式製作實驗例6～9之異向性導電膜。於此情形時，將絕緣性樹脂層之層厚設為4 μm，將低黏度樹脂層之層厚設為14 μm。作為導電粒子，使用有金屬被覆樹脂粒子（積水化學工業（股），AUL703，平均粒徑3 μm）。
導電粒子之平面配置如下所述。 實驗例6：圖1K所示之配置（L1＝L2＝L3：7.5 μm、間距pa：8.4 μm、應變量s：2.1 μm、角度α：75°、粒子個數密度：16000個/mm2 ）。 實驗例7：圖1A所示之配置（L1＝L2＝L3：7.4 μm、間距pa：8.6 μm、應變量s：1.8 μm、角度α：76°、粒子個數密度：16000個/mm2 ）。 實驗例8：於六方格子中，如圖5B所示，排列軸相對於x方向之傾斜角為0°（x方向之粒子間距（粒子中心間距離）：8.5 μm、粒子個數密度：16000個/mm2 ）。 實驗例9：於六方格子中，圖5A所示之排列軸相對於x方向之傾斜角γ為15°（粒子個數密度：16000個/mm2 ）。 因此，實驗例6、7成為本發明之實施例。
[表3]
Figure 108128352-A0304-0004
（連接試驗1） 使用實驗例6～9中所製造之異向性導電膜，利用以下熱壓接方法將具有各端子之軸筆直且筆直地排列於相同方向之端子行之以下導通評價用IC與玻璃基板連接，對各端子之導電粒子之捕捉數進行計數。
導通評價用IC 外形：0.7×20 mm、厚度t＝0.2 mm 端子寬度：14 μm 端子長度：100 μm 端子高度：12 μm 端子間空間：14 μm
玻璃基板 無鹼玻璃基板 電極：ITO配線 厚度：0.7 mm
熱壓接方法 將實驗例6～9之異向性導電膜夾於導通評價用IC與玻璃基板之間，利用熱壓接工具（工具寬度1.0 mm）進行加熱加壓（180℃、60 MPa、5秒），獲得評價用之連接構造體。於此情形時，於實驗例6、7中，將粒子配置之a方向設為端子之排列方向x。
藉由利用金屬顯微鏡自玻璃側觀察藉由熱壓接所獲得之實驗例6～9之連接構造體，而計測被各個端子捕捉到之導電粒子數，求出每1個端子之捕捉數（以下亦簡稱為捕捉數）與成為該捕捉數之端子之出現數，進而求出其出現比率（以下亦稱為頻度）。所計測之端子數分別為1800個。將結果示於圖8A～圖8D。
根據圖8A～圖8D可知，於實驗例8之異向性導電膜中，成為於捕捉數為10個與15個時具有峰值之雙峰之分佈圖案，於實驗例9之異向性導電膜中，雖然為單峰但捕捉數集中於12個與13個，整體上捕捉數較少。
與此相對，若使用實驗例6之異向性導電膜，則頻度最高之端子於捕捉數為13個時，頻度為36%，頻度第二高之端子於捕捉數為12個時，頻度為28%，頻度第三高之端子於捕捉數為14個時，頻度為25%。該等頻度之合計為89%。該分佈圖案係具有單峰者。
又，於實驗例7之異向性導電膜中，頻度最高之端子於捕捉數為13個時，頻度為37%，頻度第二高之端子於捕捉數為14個時，頻度為26%，頻度第三高之端子於捕捉數為12個時，頻度為17%，頻度第四高之端子於捕捉數為15個時，頻度為14%，該等頻度之合計為94%。該分佈圖案亦為單峰。
再者，最小捕捉數於實驗例8中為10個，於實驗例9中為11個，與此相對，於實驗例6中為12個，於實驗例7中為11個。
又，於計測捕捉數時，實驗例6、7與實驗例8、9相比計測不花費時間，計測相對較容易。
根據上述內容可知，於使用本發明之異向性導電膜進行異向性導電連接之情形時，於所獲得之連接構造體中，於各個端子中捕捉數極其穩定。
再者，可確認實驗例6～9之連接構造體之初始導通電阻均未達2 Ω，實用上不存在問題。
（連接試驗2） 使用實驗例6～9中所製造之異向性導電膜，以與連接試驗1相同之熱壓接方法連接以下規格之扇出型端子排列之導通評價用FPC與玻璃基板，以與連接試驗1相同之方法求出各端子之導電粒子之捕捉數與成為該捕捉數之端子之出現比率（頻度）。將結果示於圖9A～圖9D。又，關於實驗例6、8、9，將熱壓接後之壓痕照片示於圖10A～圖10C。
導通評價用FPC 聚醯亞胺膜（S'perFlex，住友金屬礦山股份有限公司）膜厚：38 μm、端子高度：8 μm 測定長度（用於端子測定之長度）：400 μm 端子寬度：8 μm 端子間距：20 μm 扇出角度：-9°～9°
玻璃基板 電極：ITO配線 厚度：0.7 mm
根據圖9A～圖9D可知，於使用實驗例6～實驗例9之任一異向性導電膜之情形時，捕捉數與頻度之關係亦成為單峰，但與實驗例8、9相比，使用實驗例6、7之異向性導電膜之情形時，每1個端子之捕捉數較多。
又，根據圖10A～圖10C可知，相對於導電粒子之配置為六方格子之情形（實驗例8、9），根據本發明之實施例之粒子配置，扇出型端子排列中之左右之壓痕之均勻性極高，因此，於整個端子排列中導電粒子之捕捉性均勻。
1:導電粒子 2:絕緣性樹脂層 3:低黏度樹脂層 10A、10B:異向性導電膜 11、11a、11b:第1斜方格子區域 12、12a、12b:第2斜方格子區域 20、20a、20b:端子 A:導電粒子之密集區域 a:排列軸之方向 a1:第1斜方格子區域之排列軸 a2:第2斜方格子區域之排列軸 b:於第1斜方格子區域中與排列軸a斜交之排列軸之方向 c:於第2斜方格子區域中與排列軸a斜交之排列軸之方向 D:導電粒子之平均粒徑 Lb:埋入量 Ld:偏移量 s:應變量 x:端子之排列方向 y:與a方向垂直之方向 pa:排列軸a上之粒子間距 α:a方向與b方向所成之角度 β:於扇出排列之情形時為扇出角，於非扇出排列之情形時為端子之排列方向與端子之長邊方向所成之角度 γ:六方格子之排列軸相對於x方向之傾斜角
圖1A係說明實施例之異向性導電膜10A中之導電粒子之配置的俯視圖。 圖1B係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1C係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1D係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1E係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1F係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1G係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1H係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1I係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1J係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖1K係說明實施例之異向性導電膜中之導電粒子之配置的俯視圖。 圖2係實施例之異向性導電膜10A之剖面圖。 圖3係實施例之異向性導電膜10B之剖面圖。 圖4A係將實施例之異向性導電膜10A與扇出型端子行重疊而得之俯視圖。 圖4B係將實施例之異向性導電膜10A與各端子之端子軸為相同方向之端子行重疊而得的俯視圖。 圖5A係將導電粒子呈六方格子（傾斜角γ）配置之異向性導電膜與扇出型端子行重疊之狀態之俯視圖。 圖5B係將導電粒子呈六方格子（傾斜角γ＝0°）配置之異向性導電膜與扇出型端子行重疊之狀態之俯視圖。 圖5C係將導電粒子呈六方格子（傾斜角γ＝0°）配置之異向性導電膜與各端子之端子軸為相同方向之端子行重疊之狀態的俯視圖。 圖6A係導電粒子呈六方格子配置之異向性導電膜之粒子配置之說明圖。 圖6B係使用導電粒子呈六方格子配置之異向性導電膜將端子行連接後之狀態之說明圖。 圖7A係以與實驗例1大致相同之粒子配置將扇出型端子排列連接之情形時的導電粒子之捕捉狀態之模擬結果。 圖7B係以與實驗例3大致相同之粒子配置將扇出型端子排列連接之情形時的導電粒子之捕捉狀態之模擬結果。 圖7C係以與實驗例4大致相同之粒子配置將扇出型端子排列連接之情形時的導電粒子之捕捉狀態之模擬結果。 圖7D係以與實驗例5大致相同之粒子配置將扇出型端子排列連接之情形時的導電粒子之捕捉狀態之模擬結果。 圖8A係實驗例6之連接試驗1中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖8B係實驗例7之連接試驗1中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖8C係實驗例8之連接試驗1中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖8D係實驗例9之連接試驗1中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖9A係實驗例6之連接試驗2中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖9B係實驗例7之連接試驗2中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖9C係實驗例8之連接試驗2中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖9D係實驗例9之連接試驗2中之每個端子之導電粒子的捕捉數、與成為該捕捉數之端子之出現比率（頻度）之關係圖。 圖10A係實驗例6之連接試驗2中之壓痕照片。 圖10B係實驗例8之連接試驗2中之壓痕照片。 圖10C係實驗例9之連接試驗2中之壓痕照片。

Claims (14)

  1. 一種異向性導電膜，其係於絕緣性樹脂層配置有導電粒子者，且重複配置有第1斜方格子區域與第2斜方格子區域， 該第1斜方格子區域係於以角度α與a方向斜交之b方向上排列有複數個將導電粒子以規定間距配置於a方向而成之導電粒子排列軸a1； 該第2斜方格子區域係於使上述b方向相對於a方向反轉後之c方向上排列有複數個將導電粒子以規定間距配置於a方向而成之導電粒子排列軸a2。
  2. 如請求項1所述之異向性導電膜，其中，關於與a方向斜交之排列軸，一斜方格子區域之排列軸之延長線未成為另一斜方格子區域之排列軸，而重複配置有第1斜方格子區域與第2斜方格子區域。
  3. 如請求項1或2所述之異向性導電膜，其交替地重複配置有第1斜方格子區域與第2斜方格子區域。
  4. 如請求項1至3中任一項所述之異向性導電膜，其中，於第1斜方格子區域之排列軸a1與第2斜方格子區域之排列軸a2上，分別以固定之間距配置有導電粒子。
  5. 如請求項4所述之異向性導電膜，其中，第1斜方格子區域之排列軸a1與第2斜方格子區域之排列軸a2之導電粒子之間距相等。
  6. 如請求項1至5中任一項所述之異向性導電膜，其中，於第1斜方格子區域中鄰接之排列軸a1彼此之距離L1與於第2斜方格子區域中鄰接之排列軸a2彼此之距離L2相等。
  7. 如請求項3至6中任一項所述之異向性導電膜，其中，於鄰接之第1斜方格子區域之排列軸a1與第2斜方格子區域之排列軸a2上，導電粒子之位置於a方向上偏移。
  8. 如請求項7所述之異向性導電膜，其中，鄰接之第1斜方格子區域之排列軸a1與第2斜方格子區域之排列軸a2上的導電粒子之a方向之偏移量Ld大於導電粒子之平均粒徑。
  9. 如請求項1至8中任一項所述之異向性導電膜，其中，第1斜方格子區域中之排列軸a1之排列數與第2斜方格子區域中之排列軸a2之排列數相等。
  10. 如請求項1至9中任一項所述之異向性導電膜，其中，第1斜方格子區域中之排列軸a1之排列數與第2斜方格子區域中之排列軸a2之排列數為4以下。
  11. 如請求項1至10中任一項所述之異向性導電膜，其中，排列軸a1與異向性導電膜之長邊方向平行。
  12. 如請求項3至11中任一項所述之異向性導電膜，其中，第1斜方格子區域與第2斜方格子區域之與a方向垂直之方向之重複間距為設為連接對象之端子之端子長度以下。
  13. 一種連接構造體之製造方法，其係使用請求項1至12中任一項所述之異向性導電膜，將第1電子零件之端子與第2電子零件之端子異向性導電連接。
  14. 一種連接構造體，其係經由請求項1至12中任一項所述之異向性導電膜將第1電子零件與第2電子零件異向性導電連接而成。
TW108128352A 2018-08-08 2019-08-08 異向性導電膜、連接構造體之製造方法、及連接構造體 TWI845540B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP2018-149702 2018-08-08
JP2018149702 2018-08-08
JPJP2019-145850 2019-08-07
JP2019145850A JP7381841B2 (ja) 2018-08-08 2019-08-07 異方性導電フィルム

Publications (2)

Publication Number Publication Date
TW202016954A true TW202016954A (zh) 2020-05-01
TWI845540B TWI845540B (zh) 2024-06-21

Family

ID=

Also Published As

Publication number Publication date
CN112534650B (zh) 2023-05-23
KR102570142B1 (ko) 2023-08-23
US11694988B2 (en) 2023-07-04
CN112534650A (zh) 2021-03-19
JP7381841B2 (ja) 2023-11-16
US20210305195A1 (en) 2021-09-30
KR20210009383A (ko) 2021-01-26
JP2020027798A (ja) 2020-02-20

Similar Documents

Publication Publication Date Title
TWI711222B (zh) 異向導電性膜、連接構造體及連接構造體之製造方法
KR20200029640A (ko) 이방 도전성 필름 및 접속 구조체
TWI834084B (zh) 異向導電性膜及其製造方法、以及使用有異向導電性膜之連接構造體及其製造方法
TW201833267A (zh) 含填料膜
KR20170113039A (ko) 전자 부품, 접속체, 전자 부품의 설계 방법
JP2023025009A (ja) 接続構造体
US11694988B2 (en) Anisotropic conductive film
WO2020032150A1 (ja) 異方性導電フィルム
KR20170113038A (ko) 전자 부품, 이방성 접속 구조체, 전자 부품의 설계 방법
TW202214441A (zh) 含有填料之膜
TWI814953B (zh) 異向性導電膜、連接構造體、及連接構造體之製造方法
TWI823170B (zh) 異向性導電膜之製造方法、異向性導電膜之設計方法、異向性導電膜、連接結構體、及連接結構體之製造方法
WO2021161935A1 (ja) 異方性導電フィルム
TWI764821B (zh) 異向性導電膜
KR20240091271A (ko) 이방성 도전 필름, 접속 구조체, 접속 구조체의 제조 방법
WO2023100697A1 (ja) 異方性導電フィルム
JP2021128936A (ja) 異方性導電フィルム