TW202011676A - High-boost direct current converter respectively controlling the main switch and the auxiliary switch to be switched between a conducting state and a non-conducting state - Google Patents

Abstract

This invention discloses a high-boost direct current converter including a first winding, a main switch, an auxiliary switch, a clamping capacitor, a voltage rising unit, a voltage superimposing unit, an output diode and an output capacitor; the main switch and the auxiliary switch are respectively controlled to be switched between a conducting state and a non-conducting state; the auxiliary switch and the clamping capacitor form an active clamping circuit so that the main switch and the auxiliary switch achieve the flexible switching performance of zero voltage switching; when the output diodes is turned on, the voltage rising unit charges the output capacitor so as to generate a capacitor voltage proportional to a rising voltage; and the voltage superimposing unit boosts by virtue of an induced voltage from the first winding to generate a superimposed voltage at an output side, so that an output voltage is raised, and a high boosting ratio is achieved.

Description

High boost DC converter

The invention relates to a DC converter, in particular to a high-boost DC converter.

Referring to FIG. 1, a conventional boost converter, without considering the influence of parasitic resistance, the relationship between its voltage gain and an output voltage V _O , an input voltage V _in , and a switch conduction ratio D is as follows, where, The conduction ratio D is a real number greater than 0 and less than 1.

It can be seen that the traditional boost converter has to operate at a very high switch turn-on ratio in order to obtain a high step-up ratio. However, a very high turn-on ratio will produce a large current ripple and severe diode inversion. To restore the current problem, the converter has a problem of power loss. In addition, the switch of the traditional boost converter belongs to hard switching. Furthermore, the voltage stress of the switch and the diode of the traditional boost converter is The high-voltage output voltage has a large on-resistance, resulting in a problem of higher power loss.

Therefore, the object of the present invention is to provide a high-boost DC converter that can achieve high voltage gain without extremely high turn-on ratio.

Therefore, the high-boost DC converter of the present invention includes a first winding, a main switch, an auxiliary switch, a clamping capacitor, a voltage lifting unit, an output diode, an output capacitor, and a voltage superposition unit.

The first winding has a first end electrically connected to an anode of an input voltage and a second end electrically connected to a first common contact, and the main switch has a first end electrically connected to the first common contact and A second terminal connected to ground, and the main switch is controlled to switch between a conducting state and a non-conducting state. The auxiliary switch has a first end and a second end electrically connected to the first common contact, and the auxiliary switch is controlled to switch between a conducting state and a non-conducting state.

The clamp capacitor has a first end electrically connected to the first end of the auxiliary switch, and a second end electrically connected to an anode of an input voltage. The voltage lifting unit has a lifting input terminal electrically connected to the first common contact, and a lifting output terminal for boosting an induced voltage from the first winding to generate a lifting voltage from the Lifting output output.

The voltage lifting unit includes a first lifting capacitor, a second lifting capacitor, a second winding, a first lifting diode, and a second lifting diode. The first lifting capacitor has a first end electrically connected to the lifting input end and a second end, and the second winding has a first end electrically connected to the second end of the first lifting capacitor and a second end , The second lifting capacitor has a first end electrically connected to the second end of the second winding, and a second end electrically connected to the lifting output end, the first lifting diode has an electrical connection to the first An anode at the first end of the second winding, and a cathode electrically connected to the lifting output, the second lifting diode has an anode electrically connected to the lifting input, and a second electrically connected to the second winding Cathode.

The output diode has an anode electrically connected to the lifting output end, and a cathode electrically connected to a second common contact. The output capacitor has a first terminal electrically connected to the second common contact and a second terminal connected to ground. When the output diode is turned on, it receives a charge from the lifting voltage to generate a proportional to the lifting The voltage of the capacitor. The voltage superimposing unit is electrically connected to the second common contact to be serially connected to the output capacitor, and is used to boost the induced voltage from the first winding to generate a superimposed voltage, which is added to the capacitor voltage In total, an output voltage is generated.

The voltage superimposing unit includes a first superimposed diode, a second superimposed diode, a third winding, a first superimposed capacitor, and a second superimposed capacitor. The first superposed diode has an anode and a cathode electrically connected to the second common contact, and the third winding has a first end and a second end electrically connected to the cathode of the first superposed diode, The first superimposed capacitor has a first end electrically connected to the second end of the third winding, and a second end electrically connected to the second common contact, and the second superimposed diode has an electrical connection to the first An anode and a cathode of the cathode of the superimposed diode, the second superimposed capacitor has a first end electrically connected to the cathode of the second superimposed diode, and a first end electrically connected to the first end of the first superimposed capacitor Two ends.

The effect of the present invention is that the voltage lifting unit and the voltage superimposing unit can effectively improve the overall boosting ratio without the need for switching operation at a high conduction ratio.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numbers.

Referring to FIG. 2, an embodiment of the high boost DC converter of the present invention includes a first winding N _{1 of} a coupled inductor, a main switch S ₁ , an auxiliary switch S ₂ , a clamping capacitor C _c , and a voltage lifting unit 2, an output diode D _0, an output capacitor C _0, a voltage superimposing unit 3, and a control unit 4.

The first winding N ₁ has a dotted first end and a second end, the main switch S ₁ has a first end electrically connected to a first common contact and a grounded second end, and the control unit 4. Control the main switch to switch between a conducting state and a non-conducting state through a first pulse modulation signal. When the main switch S _{1 is} in the on state, the first winding N ₁ receives a charging current i _In provided by an input voltage V _in , so that the first winding N ₁ generates a magnetizing inductance L _m A magnitude of a first induced voltage V _Lm . The main switch S ₁ is an N-type power semiconductor transistor, and a first terminal of the primary switch S ₁ is a drain, the second terminal of the primary switch S ₁ is a source.

The auxiliary switch S ₂ has a first end electrically connected to the first end of the clamping capacitor C _c , and a second end electrically connected to the first common contact, and the control unit 4 passes a second pulse wave The modulation signal controls the auxiliary switch S _{2 to} switch between a conductive state and a non-conductive state when the main switch S _{1 is} in the non-conductive state and the auxiliary switch S _{2 is} in the conductive state. The auxiliary switch S ₂ is an N-type power semiconductor transistor, and the first auxiliary switch S ₂ is a drain terminal, the second terminal of the auxiliary switch S ₂ is a source.

The clamping capacitor C _c having a terminal electrically connected to the second input voltage V _in the anode.

The voltage lifting unit 2 has a lifting input terminal and a lifting output terminal, and the voltage lifting unit 2 includes a first lifting capacitor C ₃ , a second winding N _{2 of} the coupling inductor, and a second lifting Capacitor C ₄ , a first lifting diode D ₃ , and a second lifting diode D ₄ . The first lifting capacitor C ₃ has a first terminal electrically connected to the first common contact (the lifting input terminal), and a second terminal electrically connected to the first terminal of the second winding N ₂ . The second winding N ₂ has a first end electrically connected to the second end of the first lifting capacitor C ₃ , and a second end electrically connected to the first end of the second lifting capacitor C ₄ . The second lifting capacitor C ₄ has a first end electrically connected to the second end of the second winding N ₂ , and a second end electrically connected to the anode of the output diode D ₀ (the lift output) . The first lifting diode D ₃ has an anode electrically connected to the first end of the second winding N ₂ , and a cathode electrically connected to the anode of the output diode D ₀ . The second lifting diode D ₄ has an anode electrically connected to the first common contact, and a cathode electrically connected to the second end of the second winding N ₂ .

The voltage superimposing unit 3 includes a first superimposing diode D ₁ , a third winding N _{3 of} the coupling inductor, a first superimposing capacitor C ₁ , a second superimposing diode D ₂ , and a second superimposing Capacitor C ₂ . The first superimposed diode D ₁ has an anode electrically connected to a second common contact and a cathode electrically connected to the first end of the third winding N ₃ . The third winding N ₃ has a first point electrically connected to the cathode of the first superimposed diode D ₁ and a second end electrically connected to the first end of the first superimposed capacitor C ₁ . The first superimposed capacitor C ₁ has a first end electrically connected to the second end of the third winding N ₃ , and a second end electrically connected to the second common contact. The second stacked diode D ₂ has a cathode electrically connected to the anode of the first stacked diode D ₁ and a cathode electrically connected to the first end of the second stacked capacitor C ₂ . The second superimposed capacitor C ₂ has a first end electrically connected to the cathode of the second superimposed diode D ₂ , and a second end electrically connected to the first end of the first superimposed capacitor C ₁ .

The control unit 4 generates a first pulse modulation signal that switches the main switch S _{1 and} a second pulse modulation signal that switches the auxiliary switch S _2. The main switch S will be further described in eleven stages below ₁ and a timing diagram of the high-boost DC converter of the present invention produced by the switching of the auxiliary switch S ₂ .

Referring to Figure 3, an equivalent circuit diagram of the embodiment of the present embodiment, for explaining the first non-over winding N ₁ of an equivalent circuit of the magnetizing inductance L _m, a leakage inductance L _k, the parasitic capacitance C a and the main switch _r, wherein the voltage across each of the pressure elements are: the input voltage V _in, V _N3 cross voltage across a voltage V _N1 of the first winding, a second cross voltage V _N2 winding, a third winding, An output voltage V _o , a parasitic capacitance across voltage V _Cr , a clamp capacitance across voltage V _Cc , a second overlay capacitance C ₂ across voltage V _C2 , a first overlay capacitance across voltage V _C1 , a Output capacitor cross voltage V _C0 , a first lift capacitor cross voltage V _C3 , a second lift capacitor cross voltage V _C4 , a first lift diode cross voltage V _D3 , a second lift The trans-voltage V _{D4 of the} rising diode, the trans-voltage V _D2 of a second superimposed diode, the trans-voltage V _{D1 of} a first superimposed diode, the trans-voltage V _{D0 of} an output diode, and a magnetization The voltage across the inductor V _Lm . The currents when each element is turned on are: an input current i _In , a main switch conduction current i _S1 , an auxiliary switch conduction current i _S2 , a first lifting diode conduction current i _D3 , a second On-state current i _{D4 of the} lifting diode, on-state current i _D2 of a second superimposed diode, on-state current i _{D1 of} a first superimposed diode, on-current i _{D0 of} an output diode, and magnetization The inductor current i _Lm and the leakage inductor current i _Lk .

The following are the circuit diagrams of the eleven-stage operation of this embodiment, in which the conducting elements are indicated by solid lines and the non-conducting elements are indicated by dashed lines, and the following analysis is based on five assumptions:

Hypothesis 1: the conduction voltage drop between all power switches and diodes is zero.

Hypothesis 2: the second superimposed capacitor C ₂ , the first superimposed capacitor C ₁ , and the output capacitor C ₀ are large enough to ignore the ripple of the capacitor voltage, the cross-over voltage V _{C2 of} the second superimposed capacitor C ₂ , the first A cross voltage V _{C 1 of the} superimposed capacitor C _{1 and} the cross voltage V C ₀ of the output capacitor _{C 0} can be regarded as constants.

)，且該磁化電感L_m 遠大於該漏電感L_k ，即一耦合係數

。Hypothesis 3: the number of turns of a first winding n ₁ , the number of turns of a second winding n ₂ , and the number of turns of a third winding n ₃ . A number of turns of the first winding and the second winding N ₁₂ is equal to a ratio of the first winding and the third winding has an equal coupling ratio of inductor turns ratio N ₁₃ n, where n is a real number not less than 1 (in other words ,

), and the magnetizing inductance L _{m is} much larger than the leakage inductance L _k , that is, a coupling coefficient

.

Hypothesis 4: The magnetizing inductor current i _{Lm of} the coupled inductor operates in continuous conduction mode (Continuous conduction mode, CCM).

Hypothesis 5: The main switch S ₁ and the auxiliary switch S ₂ are complementary drives, and there is a very short dead time between the two. Because the blind time is extremely short, if the main switch S ₁ has a conduction ratio D, the conduction ratio of the auxiliary switch can be regarded as 1 minus the conduction ratio D (in other words, 1-D).

Based on the above five assumptions, each stage is described in the following content, where the time t corresponds to the start time of each stage is a first start time t0 to an eleventh start time t10, when When the time t reaches an eleventh end time t11, the entire converter completes the eleventh phase of a cycle.

The first stage [t: t0~t1]:

4 and 5, the main switch S ₁ will be turned from non-conducting, the auxiliary switch S _{2 will} be non-conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , And the second superimposed diode D ₂ is conductive, and the first superimposed diode D ₁ and the output diode D ₀ are both non-conductive.

The time t at which this stage starts is equal to the sixth start time t0, the main switch S _{1 is} turned on, and the auxiliary switch S ₂ is turned off. The input voltage V _in spans the magnetizing inductance L _m and the leakage inductance L _k , and the current i _{Lm of} the magnetizing inductance and the current i _Lk of the leakage inductance increase linearly. With the second winding N _{2 of} the coupled inductor, the first lifting diode D ₃ , and the second lifting diode D ₄ , the first lifting capacitor C ₃ and the second lifting The capacitor C _{4 is} in a charged state. The current of the third winding N ₃ of the coupled inductor charges the second superimposed capacitor C ₂ by switching the second superimposed diode D ₂ . The output capacitor C ₀ , the first superimposed capacitor C ₁ , and the first superimposed capacitor C ₂ provide an output load _Ro energy. At this stage,

…式一

… Formula One

When the time t is equal to the second start time t1, the main switch S ₁ is switched to non-conducting state, for the end of this phase.

The second stage [t: t1~t2]:

4 and 6, the main switch S ₁ is non-conductive, the auxiliary switch S ₂ is non-conductive, the first lifting diode D ₃ , the second lifting diode D ₄ , and the first The second superimposed diode D ₂ is turned on, and both the first superimposed diode D ₁ and the output diode D ₀ are turned off.

Time start of the period t is equal to the second start time t1, the leakage inductance current i _Lk starts charging the parasitic capacitance of the main switch S is C _{1 r.} The cross voltage V _{Cr of} the parasitic capacitance increases from zero to the input voltage V _in resonance, plus the cross voltage V _{Cc of} the clamping capacitor (in other words, V _Cr =V _in + V _Cc ). The first lifting diode D ₃ , the second lifting diode D ₄ , and the second superimposed diode D _{2 are} kept in a conducting state. Because the parasitic capacitance C _{r of} the main switch S ₁ is very small, the voltage across the main switch v _ds1 can be approximated as:

…式二

...Form two

When the time t is equal to the third start time t2, the cross voltage V _{Cr of} the parasitic capacitance is charged to be equal to the input voltage V _in plus the cross voltage V _{Cc of} the clamping capacitor (in other words, V _Cr =V _in + V _Cc ), the body diode of the auxiliary switch S _{2 changes} from non-conducting to conducting, and this stage ends.

The third stage [t: t2~t3]:

4 and 7, the main switch S ₁ is non-conducting, the auxiliary switch S ₂ will be turned from non-conducting to conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , And the second superimposed diode D ₂ is conductive, and the first superimposed diode D ₁ and the output diode D ₀ are both non-conductive.

The time t at which this stage starts is equal to the third start time t2, and the parasitic capacitance C _{r is} charged across the voltage V _Cr to equal the input voltage V _in plus the clamp voltage V _Cc (in other words, V _Cr =V _in + V _Cc ), the body diode of the auxiliary switch S ₂ starts to conduct, and the leakage inductance current i _Lk passes through the body diode of the auxiliary switch S ₂ to start charging the clamping capacitor C _c . And the cross voltage that causes a leakage inductance is a negative voltage:

…式三

...Form three

The current i _{Lk of} the leakage inductance starts to decrease, and the currents of the second winding N ₂ and the third winding N ₃ of the coupling inductance also begin to decrease. Therefore, the conduction current i _{D3 of} the first lifting diode and the first The conduction current i _{D4 of the} two-lift diode and the conduction current i _{D2 of} the second stacked diode also decrease accordingly. At this stage, the cross voltage of the auxiliary switch S ₂ is zero, and the condition of zero voltage switching (ZVS) is satisfied. In order to allow the auxiliary switch S ₂ to achieve the soft switching performance of zero voltage switching, Before the current i _{Lk of} the leakage inductance is reversed, the auxiliary switch S ₂ must be turned on.

When the time t is equal to the third start time t3, and the auxiliary switch S2 is switched from non-conducting to conducting, the soft cut performance of the zero-voltage switching performance is achieved, and this stage ends.

The fourth stage [t: t3~t4]:

4 and 8, the main switch S ₁ is non-conducting, the auxiliary switch S ₂ is conducting in a state of zero voltage switching, the first lifting diode D ₃ and the second lifting diode D ₄ , and the second superimposed diode D ₂ will be switched from conducting to non-conducting, the first superimposed diode D _{1 will} remain non-conducting, and the output diode D ₀ will be switched from non-conducting to conducting.

The time t at which this stage starts is equal to the fourth start time t3, and the auxiliary switch S _{2 is} switched on, achieving zero voltage switching. Since the cross-voltage V _Lk of the leakage inductance is a negative voltage, the current i _{Lk of} the leakage inductance continues to decrease, the conduction current i _{D3 of} the first lifting diode, and the conduction current i of the second lifting diode _D4 and the conduction current i _{D2 of} the second superimposed diode continue to decrease. Because of the presence of the leakage inductance L _k in the coupled inductance, the on-current i _D3 of the first lifting diode, the on-current i _{D4 of} the second lifting diode, and the on-current i _{D4 of} the second lifting diode The rate at which the on-current i _D2 decreases is limited by the leakage inductance L _k , which moderates the first lifting diode D ₃ , the second lifting diode D ₄ , and the second superimposed diode D ₂ Reverse recovery problem.

When the time t is equal to the fifth start time t4, the conduction current i _D3 of the first lifting diode, the conduction current i _{D4 of} the second lifting diode, and the conduction current of the second superposed diode i _D2 drops to zero, the first lifting diode D ₃ , the second lifting diode D ₄ , and the second superimposed diode D ₂ naturally switch to non-conducting. At the same time, the current direction of the second winding N ₂ of the coupled inductor changes, and the output diode D ₀ is switched to conductive state, and this stage ends.

The fifth stage [t: t4~t5]:

4 and 9, the main switch S ₁ is non-conducting, the auxiliary switch S ₂ is conducting, the first lifting diode D ₃ , the second lifting diode D ₄ , and the second The superimposed diode D ₂ is non-conductive, the first superimposed diode D ₁ will be switched from non-conductive to conductive, and the output diode D ₀ is conductive.

The time t at which this stage starts is equal to the fifth start time t4, the first lifting capacitor C ₃ and the second lifting capacitor C ₄ start to discharge, and energy is provided to the output capacitor C ₀ . The voltage sum of the leakage inductance L _k and the magnetizing inductance L _m is equal to the negative voltage across the clamping capacitor V _Cc , so the current i _{Lk of} the leakage inductance continues to decrease. In this stage, the current i _{Lk of} the leakage inductance drops until the flow direction of the current changes, and the current i _{Lk of} the leakage inductance discharges the clamping capacitor C _c . When the clamping capacitor C _{c is} discharged, the cross voltage V _{Cc of} the clamping capacitor C _c drops, so that the voltage of the first winding N ₁ drops and the cross voltage V _N3 reflected to the third winding N ₃ also drops to be equal to When the voltage V _{C 1 of} the first superimposed capacitor is switched, the first superimposed diode D ₁ is switched to be conductive.

When the time t is equal to the sixth start time t5, when the cross-voltage V _{N3 of} the third winding is equal to the cross-voltage V _{C 1 of} the first superimposed capacitor, the first superimposed diode D ₁ is switched to on, This stage is over.

The sixth stage [t: t5~t6]:

4 and 10, the main switch S ₁ is non-conductive, the auxiliary switch S ₂ is conductive, the first lifting diode D ₃ , the second lifting diode D ₄ , and the second The superimposed diode D ₂ is non-conductive, the first superimposed diode D ₁ is conductive, and the output diode D ₀ will be switched from conductive to non-conductive.

Time start of the period t is equal to the start of the sixth time t5, the superposition of the first diode D ₁ is transited switched on, the first superimposition diode _Dl conduction current i starts to increase, the leakage inductance current i _Lk continues to decrease, and the on-current i _{D0 of} the output diode begins to decrease.

When the time t is equal to the seventh start time t6, the conduction current i _{D0 of} the output diode drops to zero, the output diode D ₀ transitions to non-conduction, and this stage ends.

The seventh stage [t: t6~t7]:

Referring to FIGS. 4 and 11, the main switch S ₁ is non-conducting, the auxiliary switch S ₂ will be switched from conducting to non-conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , And the second superimposed diode D ₂ is non-conductive, the first superimposed diode D ₁ is conductive, and the output diode D ₀ is non-conductive.

The time t at the beginning of this stage is equal to the seventh start time t6, the output diode D ₀ is non-conducting, and the energy stored in the magnetizing inductance L _m is transmitted to the third winding N ₃ through the coupling inductance. The first superimposed capacitor C _{1 is} charged.

When the time t is equal to the eighth start time t7, and the auxiliary switch S ₂ is switched from conductive to non-conductive, this stage ends.

The eighth stage [t: t7~t8]:

4 and 12, the main switch S ₁ is non-conductive, the auxiliary switch S ₂ is non-conductive, the first lifting diode D ₃ , the second lifting diode D ₄ , and the first The second superimposed diode D ₂ is non-conductive, the first superimposed diode D ₁ is conductive, and the output diode D ₀ is non-conductive.

Time start of the period t is equal to the eighth start time T7, because of the auxiliary switch S ₂ is not turned on, the leakage inductance L _k and the parasitic capacitance Cr form a new resonant circuit, and starts releasing the parasitic capacitance C _r energy because the parasitic capacitance C _r is small, the voltage across the parasitic capacitance decreases rapidly V _Cr. Since the cross voltage V _{Cr of} the parasitic capacitance continues to decrease, when the cross voltage of the leakage inductance L _k is a positive voltage, the current i _{Lk of} the leakage inductance starts to rise.

When the time t is equal to the ninth start time t8, since the voltage V _{Cr of} the parasitic capacitance drops to zero, the body diode of the main switch S ₁ is turned on, and this stage ends.

The ninth stage [t: t8~t9]:

4 and 13, the main switch S ₁ will be turned from non-conducting to conductive, the auxiliary switch S ₂ is non-conducting, the first lifting diode D ₃ and the second lifting diode D ₄ , And the second superimposed diode D ₂ is non-conductive, the first superimposed diode D ₁ is conductive, and the output diode D ₀ is non-conductive.

Start time t equal to the ninth stage of this start time T8, the main body ₁ of the switch S diode conducting, the voltage across the primary switch S ₁ of zero, the main switch S ₁ includes a condition of zero-voltage switching, In order for the main switch S ₁ to achieve the soft cut performance of zero voltage switching, before the current i _Lk direction of the leakage inductance changes from negative to positive, the main switch S ₁ must be switched on.

When the time t is equal to a tenth of the start time T9, the main switch S ₁ is switched from the non-conducting to a conducting, to reach zero voltage switching, the end of this phase.

The tenth stage [t: t9~t10]:

4 and 14, the main switch S ₁ is turned on, the auxiliary switch S ₂ is turned off, and the first lifting diode D ₃ and the second lifting diode D ₄ will be turned from non-conducting to Turn on, the second superimposed diode D ₂ is non-conductive, the first superimposed diode D ₁ will turn from conductive to non-conductive, and the output diode D ₀ is non-conductive.

The time t at which this stage starts is equal to the tenth start time t9, and the main switch S ₁ is switched from non-conducting to conducting, achieving zero voltage switching. The current i _{Lk of} this leakage inductance continues to rise. Due to the transformer current relationship of the coupled inductor, the on-current i _{D1 of} the first superimposed diode continues to decrease.

When the time t is equal to the eleventh start time t10, when the current i _{Lk of} the leakage inductance rises to be equal to the current i _{Lm of} the magnetizing inductance (in other words, i _Lk = i _Lm ), then a first of the coupled inductance The current i _{N1 of the} winding is equal to zero, so that the current i _N3 of the third winding of the coupled inductor is equal to zero, and the first superimposed diode D ₁ transitions to non-conduction, and this stage ends.

The eleventh stage [t: t10~t11]:

4 and 15, the main switch S ₁ is on, the auxiliary switch S ₂ is off, the first lifting diode D ₃ and the second lifting diode D ₄ are on, the first The second superimposed diode D ₂ will turn from non-conducting to conductive, and the first superimposed diode D ₁ and the output diode D ₀ are non-conducting.

The time t at the beginning of this stage is equal to the eleventh start time t10, the current i _{Lk of} the leakage inductance continues to rise, so that the current i _{Lk of} the leakage inductance rises to be greater than the current i _{Lm of} the magnetizing inductance (in other words, i _Lk >i _Lm ), so the current i _N1 of the first winding of the coupled inductor is greater than zero, and at the same time an induced current of the second winding N ₂ of the coupled inductor is generated, thus flowing through the first lifting diode D ₃ and lifting the second current diode D ₄ respectively on the first capacitor C ₃ and the lifting of the second lift charging capacitor C _4. The output capacitor C ₀ , the first superimposed capacitor C ₁ , and the second superimposed capacitor C ₂ connected in series provide energy to the output load R _o .

When the time t is equal to the eleventh end time t11, when the second superimposed capacitor C _{2 is} discharged, so that the cross voltage V _{C2 of} the second superimposed capacitor C ₂ is equal to the cross voltage of the third winding N ₃ , the second The transition of the superimposed diode D ₂ is turned on, and this stage ends.

After the above eleventh stage is completed, it enters the next switching cycle T _s and restarts the first stage circuit operation.

Before doing steady-state voltage gain analysis, in order to simplify the analysis, it is necessary to base on the following assumptions:

Hypothesis 1: Ignore the transient phase with extremely short time.

。Hypothesis 2: Because the magnetizing inductance L _{m is} much larger than the leakage inductance L _k , the leakage inductance L _{k is} ignored, so the coupling coefficient

.

Hypothesis 3: All the capacitors in the converter are large enough to ignore the voltage ripple of the capacitor, so that the electric (trans) voltage of the capacitor can be regarded as a constant.

Hypothesis 4: The main switch S ₁ and the auxiliary switch S ₂ are complementary drives, and there is a very short blind time between the two. Because the blind time is extremely short, if the main switch S ₁ has a conduction ratio D, the auxiliary The conduction ratio of the switch can be regarded as 1 minus the conduction ratio D (in other words, 1-D).

Voltage gain analysis:

In the operation analysis, when the main switch S _{1 is} turned on, the time is the turn-on ratio D times the switching period T _s , in other words, there is a turn-on time DT _s of the main switch, and the voltage across the magnetizing inductance V _Lm is equal to the input voltage V _in . When the main switch S _{1 is} not conducting, the time is the switching period T _s minus the main switch S ₁ conducting DT _s , in other words, the non-conducting time of a main switch is (1-D) T _s , the magnetizing inductance L _m The cross voltage V _Lm is equal to the negative cross voltage V _Cc of the clamp capacitor (in other words, V _Lm =-V _Cc ).

Since at steady state, the inductor will satisfy the volt-second balance principle, that is, the average voltage of the inductor in the switching period T _s is zero, therefore,

…式四

...Form four

After finishing, the clamping capacitor voltage V _Cc is

…式五

...Form five

In the linear circuit diagram of the first stage (as shown in FIG. 5), it can be seen that the voltage across the first winding V _N1 of the coupled inductor is

…式六

…Form 6

At the same time, the voltage across the first lifting capacitor V _C3 and the voltage across the second lifting capacitor V _C4 in the voltage lifting unit 2 can be determined by the voltage across the first winding of the coupling inductor The cross voltage V _N2 reflected from _N1 to the second winding is derived. The cross voltage V _C3 of the first lifting capacitor and the cross voltage V _C4 of the second lifting capacitor are

…式七

...Form seven

On the other hand, the cross voltage V _C2 of the second superposition capacitor in the voltage superposition unit 3 is

…式八

…Form 8

In the linear circuit of the sixth stage (as shown in FIG. 10), it can be seen that the cross-voltage V _N1 of the first winding N ₁ of the coupled inductor is

…式九

...Form nine

The cross voltage V _C1 of the first superposition capacitor in the voltage superposition unit 3 is

…式十

...Form ten

Substituting equation 5 into equation 10, the voltage V _C1 of the first superimposed capacitor is

…式十一

...Form eleven

On the other hand, in the linear circuit of the sixth stage (as shown in Fig. 10), using Kirchhoff's voltage law, the cross-voltage V _C0 of the output capacitor can be obtained as

…式十二

...Form twelve

Substituting Equation 7 and Equation 9 into Equation 12, the voltage across the output capacitor V _C0 is

…式十三

…Form XIII

After finishing, the expression of the voltage across the output capacitor V _C0 is

…式十四

...Form fourteen

Because the output voltage _Vo is the sum of the voltages of the three capacitors, so

…式十五

… Formula fifteen

After finishing, the output voltage V _o can be expressed as

…式十六

...Style sixteen

Therefore, a voltage gain M of the high boost DC converter of the present invention can be expressed as

…式十七

…Form XVII

It can be seen from the above formula that the voltage gain has two design degrees of freedom, the coupling inductance turns ratio n and the conduction ratio D. The high boost DC converter of the present invention can achieve a high boost ratio by properly designing the coupling inductance turns ratio n, and does not need to operate at a very large conduction ratio D.

Referring to FIG. 16, it is a voltage gain curve corresponding to the turns ratio n of the coupled inductor and the conduction ratio D. When the conduction ratio D is equal to 0.6 and the turns ratio n of the coupled inductor is equal to 1, the voltage gain M is 5.5, When the conduction ratio D is equal to 0.6 and the coupled inductor turns ratio n is equal to 3, the voltage gain M is 20.5.

Switching element voltage stress analysis:

From the first stage, the voltage stress of the auxiliary switch S ₂ is

…式十八

…Form 18

Similarly, from the sixth stage, the voltage stress of the main switch S ₁ is

…式十九

…Form 19

The present invention is a high voltage stress switching boost converter DC output voltage V _o is only a 1 / (1 + 3n-nD ) times, with the coupled inductors turns ratio increased n, the switch voltage stress is greatly reduced, far It is lower than the output voltage V _o , so a metal oxide semiconductor field effect transistor (MOSFET) with a low on-state resistance and a low on-resistance _{Rds (ON)} can be used as a switch to reduce the switch conduction loss and improve the converter Overall efficiency.

Diode voltage stress analysis:

From the first stage of circuit operation analysis, the voltage stress of the first superimposed diode D ₁ is

…式二十

...Form twenty

The voltage stress of the output diode D ₀ is

…式二十一

… Formula 21

From the sixth stage of circuit operation analysis, the voltage stress of the first lifting diode D ₃ is

…式二十二

… Formula 22

The voltage stress of the second lifting diode D ₄ is

…式二十三

… Formula 23

The voltage stress of the second superimposed diode D ₂ is

…式二十四

… Formula 24

From the above formula 20 to formula 24, and the voltage gain M (formula 17), it can be seen that the first superimposed diode D ₁ , the second superimposed diode D ₂ , and the first lift two The diode D ₃ , the second lifting diode D ₄ , and the output diode D ₀ all have a low voltage stress far lower than the output voltage V _o , so the diode can choose a low rated withstand voltage Schottky diodes with low turn-on voltage drop reduce conduction losses and improve overall converter efficiency.

Experimental simulation verification:

Referring to Figure 17, first verify that the steady-state characteristic of the converter, when the full 400 watts (W), the input voltage V _in is equal to 24 volts (V), and the output voltage V _o is equal to 380 volts, respectively for controlling the main switch S voltages v ₁ and a first pulse modulation signal S ₂ of the auxiliary switch voltage V _GS1 and a second pulse modulation signal _gs2, the present invention is a high-DC converter of the boost voltage gain of approximately 15.8 M Times, according to Equation 17, when the conduction ratio D is 0.52, the conduction ratio M of the simulation result conforms to the analysis result. It is verified that the high-boost DC converter of the present invention has a high voltage gain but does not have to operate at a very large turn-on ratio.

Referring to Figure 18, when the full 400 watts, respectively, of the main control switch S ₁ is the first voltage v _GS1 pulse modulation signal of the auxiliary switch S _2, and voltage v of the second pulse modulation signal _GS2, which The voltage across the main switch v _ds1 and the voltage across the auxiliary switch v _{ds2 are} about 57 volts based on the analysis of the voltage stress of the switching element. The voltage stress of the analog waveform of the switching element is about 59 volts. voltage stress of only about one-sixth of the output voltage V _o. The simulation results are roughly in line with the analysis results, verifying that the power switch of the high-boost DC converter of the present invention has the advantage of low voltage stress, and can use a metal oxide semiconductor field effect with a low on-voltage resistance and a low on-resistance R _{ds (ON)} Transistor to reduce the switch conduction loss and improve the overall efficiency of the converter.

Referring to FIG. 19, it is the zero-voltage switching waveform of the main switch S ₁ and the auxiliary switch S ₂ at a full load of 400 watt-hours. It can be seen that the main switch S ₁ and an auxiliary switch S ₂ before the switch is turned on, the main switch _Both the cross-over voltage v _{ds1 of} S ₁ and the cross-over voltage v _{ds2 of} the auxiliary switch S ₂ have been reduced to zero, indeed reaching zero voltage switching operation, reducing switching losses.

Referring to FIG. 20, for a full load of 400 watt hours, flowing through the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first hoisted diode D ₃ , the second hoisted diode The body D ₄ and the current waveform of the output diode D ₀ can be analyzed to find that the leakage inductance L _k can alleviate the rate of decrease of the diode current. It can be seen from the figure that after the diode current drops to zero, there is almost no reverse recovery current, so the diode reverse recovery loss can be reduced.

Referring to FIG. 21, for a full load of 400 watt hours, the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first lifted diode D ₃ , and the second lifted diode D ₄ , and the voltage stress waveform of the output diode _D0 . It can be seen from the figure that the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first lifted diode D ₃ , the second lifted diode D ₄ , and the output two The maximum voltage across the pole body D ₀ , that is, the voltage stress is much lower than the output voltage of 380 volts, the simulation results are consistent with the analysis results.

In summary, the above embodiments have the following advantages:

1. The turns ratio of the coupled inductor composed of the first to third windings N ₁ ~N ₃ increases the design freedom of the voltage gain M, so the main switch S ₁ does not need to operate at a maximum The turn-on ratio.

2. Since the clamping capacitor C _c and the auxiliary switch S ₂ form an active clamping circuit, both the main switch S ₁ and the auxiliary switch S ₂ can achieve the soft cut performance of zero voltage switching, so the switching can be reduced loss.

3. Since the voltage stress of the main switch S ₁ and the auxiliary switch S ₂ is much lower than the output voltage V _o , a metal oxide semiconductor field with a low on-state resistance and a low on-resistance R _{ds (ON)} can be used The effect transistor is implemented to reduce its conduction loss.

4. The leakage inductance of the coupled inductor can effectively ease the first superimposed diode D ₁ , the second superimposed diode D ₂ , the first hoisted diode D ₃ , the second hoisted diode Body D ₄ , and the reverse recovery current of the output diode D ₀ .

5. The leakage inductance energy can be recovered and reused, which not only improves the efficiency, but also avoids the voltage surge problem caused when the main switch S ₁ and the auxiliary switch S _{2 are} switched off.

However, the above are only examples of the present invention, and the scope of implementation of the present invention cannot be limited by this, any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as Within the scope of the invention patent.

2: Voltage lifting unit 3: Voltage superposition unit 4: Control unit N ₁ : First winding N ₂ : Second winding N ₃ : Third winding S ₁ : Main switch S ₂ : Auxiliary switch C _r : Clamp capacitor C _c: the clamp capacitor C _0: main switch parasitic capacitance C _1: superimposing a first capacitor C _2: superimposing a second capacitor C _3: a first lifting capacitance C _4: lifting the second capacitor D _0: output diode D ₁ : First superimposed diode D ₂ : Second superimposed diode D ₃ : First lifted diode D ₄ : Second lifted diode R _o : Output load V _in : Input voltage V _o : Output voltage L _m : Magnetizing inductance L _k : Leakage inductance V _Cr : Parasitic capacitance across voltage V _Cc : Clamp capacitance across voltage V _C0 : Output capacitance across voltage V _C1 : First overlay capacitance across voltage V _C2 : Cross-voltage V _{C3 of the} second superimposed capacitor: Cross-voltage V _{C4 of the} first lifting capacitor: Cross-voltage V _{gs1 of the} second lifting capacitor: Voltage of the first pulse modulation signal v _gs2 : Second pulse modulation Voltage of variable signal v _ds1 : Overvoltage of main switch v _ds2 : Overvoltage of auxiliary switch T _s : Switching period t: Time t0~t10: First start time ~ Eleventh start time t11: Eleventh end time i _In : input current i _o : output current i _S1 : on-current of the main switch i _S2 : on-current of the auxiliary switch i _D0 : on-current of the output diode i _D1 : on-current of the first superimposed diode i _D2 : On-state current i _{D3 of the} second superimposed diode: On-state current i of the first lifting diode _D4 : On-state current i of the second lifting diode i _Lm : Current i of the magnetizing inductor i _Lk : Current n of the leakage inductor : Turn ratio of coupled inductance

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, in which: FIG. 1 is a circuit diagram of a conventional boost converter; FIG. 2 is a high boost DC converter of the present invention. A circuit diagram of an embodiment; FIG. 3 is an equivalent circuit diagram of the embodiment; FIG. 4 is an operation timing diagram of the embodiment; FIG. 5 is a circuit diagram of the embodiment in the first stage of operation; FIG. 6 is the circuit diagram of the embodiment A circuit diagram of the embodiment operating in the second stage; FIG. 7 is a circuit diagram of the embodiment operating in the third stage; FIG. 8 is a circuit diagram of the embodiment operating in the fourth stage; FIG. 9 is a circuit diagram of the embodiment operating in the A circuit diagram of five stages; FIG. 10 is a circuit diagram of the embodiment operating in the sixth stage; FIG. 11 is a circuit diagram of the embodiment operating in the seventh stage; FIG. 12 is a circuit diagram of the embodiment operating in the eighth stage FIG. 13 is a circuit diagram of the embodiment operating in the ninth stage; FIG. 14 is a circuit diagram of the embodiment operating in the tenth stage; FIG. 15 is a circuit diagram of the embodiment operating in the eleventh stage; FIG. 16 is A voltage gain curve diagram of the turns ratio and conduction ratio of the coupled inductor; FIG. 17 is a waveform diagram of the drive signal, input voltage and output voltage of the switch; FIG. 18 is a waveform diagram of the voltage across the drive signal of the switch and the switch; 19 is another waveform diagram of the switch driving signal and the cross voltage of the switch; FIG. 20 is a current waveform diagram of the diode; and FIG. 21 is a waveform diagram of the diode voltage.

2: Voltage lifting unit

3: Voltage superposition unit

4: control unit

N ₁ : first winding

N ₂ : second winding

N ₃ : third winding

S ₁ : Main switch

S ₂ : auxiliary switch

C ₂ : second superposition capacitor

C ₃ : First lifting capacitor

C ₄ : Second lifting capacitor

D ₀ : output diode

D ₁ : first superimposed diode

D ₂ : Second superimposed diode

D ₃ : First lift diode

D ₄ : Second lift diode

C _c : clamping capacitance

C ₀ : output capacitance

C ₁ : the first superimposed capacitor

R _o : output load

V _in : input voltage

V _o : output voltage

Claims (8)

A high-boost DC converter includes: a first winding having a first end electrically connected to an anode of an input voltage, and a second end electrically connected to a first common contact; a main The switch has a first end electrically connected to the first common contact and a second end grounded, and the main switch is controlled to switch between a conducting state and a non-conducting state; an auxiliary switch has a first And a second terminal electrically connected to the first common contact, and the auxiliary switch is controlled to switch between a conducting state and a non-conducting state; a clamping capacitor has a first end electrically connected to the auxiliary switch The first end of the power supply, and a second end of the anode electrically connected to the input voltage; a voltage lifting unit having a lifting input terminal electrically connected to the first common contact, and a lifting output terminal An induced voltage from the first winding is boosted, and a lifting voltage is generated and output from its lifting output terminal. The voltage lifting unit includes a first lifting capacitor with a first electrically connected to the lifting input terminal End and a second end; a second winding with a first end electrically connected to the second end of the first lifting capacitor and a second end; a second lifting capacitor with an electrically connected second winding The first end of the second end, and a second end electrically connected to the lifting output end; a first lifting diode having an anode electrically connected to the first end of the second winding, and an electrically connected to the The cathode of the lifting output; and a second lifting diode with an anode electrically connected to the lifting input, and a cathode electrically connected to the second end of the second winding; an output diode with an electric An anode connected to the second end of the lifting output, and a cathode electrically connected to a second common contact; an output capacitor having a first end electrically connected to the second common contact, and a grounded second Terminal, when the output diode is turned on, receiving charging from the lifting voltage to generate a capacitor voltage proportional to the lifting voltage; and a voltage superimposing unit, electrically connected to the second common contact to be connected in series to the output A capacitor, and boosting the induced voltage from the first winding to generate a superimposed voltage, the superimposed voltage and the capacitor voltage are added to generate an output voltage, the voltage superimposing unit includes a first superimposed diode , Has an anode and a cathode electrically connected to the second common contact; a third winding has a first end and a second end electrically connected to the cathode of the first superposed diode; a first superposed capacitor With a first end electrically connected to the second end of the third winding, and a second end electrically connected to the second common contact; a second superimposed diode with an electrically connected to the first superimposed diode An anode of the body cathode and a cathode; and a second superimposed capacitor having a first end electrically connected to the cathode of the second superimposed diode and a second end electrically connected to the first end of the first superimposed capacitor end. The high-boost DC converter according to claim 1, wherein the first end of the first winding is a dotted end, and the second end of the first winding is a non-dotted end. The high-boost DC converter according to claim 1, wherein the first end of the second winding is a dotted end, and the second end of the second winding is a non-dotted end. The high-boost DC converter according to claim 1, wherein the first end of the third winding is a dotted end, and the second end of the third winding is a non-dotted end. The high-boost DC converter according to claim 1, wherein the main switch is an N-type power semiconductor transistor, and the first end of the main switch is a drain, and the second end of the main switch is a source . The high-boost DC converter according to claim 1, wherein the auxiliary switch is an N-type power semiconductor transistor, and the first end of the auxiliary switch is a drain, and the second end of the auxiliary switch is a source . The high-boost DC converter according to claim 1 further includes a control unit that generates a first pulse modulation signal that switches the main switch and a second pulse modulation signal that switches the auxiliary switch . The high-boost DC converter according to claim 7, wherein the on-time of the main switch does not overlap with the on-time of the auxiliary switch.

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