TW202010086A - 暫態電壓抑制裝置 - Google Patents

暫態電壓抑制裝置 Download PDF

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TW202010086A
TW202010086A TW108124991A TW108124991A TW202010086A TW 202010086 A TW202010086 A TW 202010086A TW 108124991 A TW108124991 A TW 108124991A TW 108124991 A TW108124991 A TW 108124991A TW 202010086 A TW202010086 A TW 202010086A
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doped
transient voltage
semiconductor structure
suppression device
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林昆賢
陳子平
莊哲豪
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晶焱科技股份有限公司
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Abstract

本發明係揭露一種暫態電壓抑制裝置，包含一輕摻雜半導體結構、一第一摻雜井區、一第一重摻雜區、一第一埋區與一第二重摻雜區。輕摻雜半導體結構屬於第一導電型。第一摻雜井區屬於第二導電型，並設於輕摻雜半導體結構中。第一重摻雜區屬於第二導電型，並設於第一摻雜井區中。第一埋區屬於第一導電型，並設於輕摻雜半導體結構中，且位於第一埋區之下方。第一埋區鄰接第一摻雜井區。第二重摻雜區屬於第二導電型，並設於輕摻雜半導體結構中。

Description

暫態電壓抑制裝置
本發明係關於一種抑制裝置，且特別關於一種能較深之崩潰接面之暫態電壓抑制裝置。
由於積體電路(Integrated Circuit)的製作已進入納米級的工藝水準，晶片內部電晶體的尺寸能夠愈做愈小，然而這些晶片確很容易受到靜電放電（ESD）的衝擊而損傷，再加上一些消費性電子產品，如筆記型電腦或手機亦作的比以前更加輕薄短小，對ESD衝擊的承受能力更為降低。對於這些電子產品，若沒有利用適當的ESD保護裝置來進行保護，則電子產品很容易受到ESD的衝擊，而造成電子產品發生系統重新啟動，甚至硬體受到傷害而無法復原的問題。目前，所有的電子產品都被要求能通過IEC 61000-4-2標準之ESD測試需求。對於電子產品的ESD問題，使用暫態電壓抑制器（TVS）是較為有效的解決方法，讓ESD能量快速透過TVS予以釋放，避免電子產品受到ESD的衝擊而造成傷害。TVS的工作原理如第1圖所示，在印刷電路板（PCB）上，暫態電壓抑制器10並聯欲保護電路12，當ESD情況發生時，暫態電壓抑制器10係瞬間被觸發，同時，暫態電壓抑制器10亦可提供一低電阻路徑，以供暫態之ESD電流進行放電，讓ESD暫態電流之能量透過暫態電壓抑制器10得以釋放。
在美國專利案號7875933中，第3圖顯示一半導體裝置，其係形成於一半導體基底中。半導體基底包含單晶矽。舉例來說，半導體基底為P型基板。半導體裝置包含一橫向雙載子電晶體，其係由二N型摻雜區於P型基板上所形成。N型摻雜區由一隔離區域分隔，例如由淺溝渠隔離結構(STI)分隔。摻雜區形成集極與射極，半導體基底形成基極，基底電性連接附近的基板接點。有一個離子摻雜區位於作為集極之摻雜區的下方，以調整集基介面的崩潰電壓。在此例中，崩潰接面形成在離子摻雜區與作為集極之摻雜區之間。如第2圖之虛線所示，崩潰接面之深度相距半導體基底之表面約為0.1-0.2微米，使功率消耗不佳。此外，半導體裝置之崩潰電壓僅由離子摻雜區之摻雜濃度決定，因此崩潰電壓之可調範圍較窄。
因此，本發明係在針對上述的困擾，提出一種暫態電壓抑制裝置，以解決習知所產生的問題。
本發明的主要目的，在於提供一種暫態電壓抑制裝置，其係形成一位於摻雜井區下方的埋區，以形成較深之崩潰接面，進而提升功率消耗、湧浪及靜電放電效能與崩潰電壓之可調範圍。
為達上述目的，本發明提供一種暫態電壓抑制裝置，其係包含一輕摻雜半導體結構、一第一摻雜井區、一第一重摻雜區、一第一埋區與一第二重摻雜區。輕摻雜半導體結構屬於第一導電型，第一摻雜井區屬於第二導電型，第一重摻雜區屬於第二導電型，第一埋區屬於第一導電型，第二重摻雜區屬於第二導電型。第一摻雜井區設於輕摻雜半導體結構，第一重摻雜區設於第一摻雜井區中，第一埋區設於輕摻雜半導體結構中，並位於第一摻雜井區之下方，第一埋區鄰接第一摻雜井區，第二重摻雜區設於輕摻雜半導體結構中。
在本發明之一實施例中，輕摻雜半導體結構為浮接。
在本發明之一實施例中，暫態電壓抑制裝置更包含一第二摻雜井區與一第二埋區。第二摻雜井區屬於第二導電型，第二摻雜井區設於輕摻雜半導體結構中，第二重摻雜區設於第二摻雜井區中。第二埋區屬於第一導電型，第二埋區設於輕摻雜半導體結構中，並位於第二摻雜井區之下方，第二埋區鄰接第二摻雜井區。
在本發明之一實施例中，暫態電壓抑制裝置更包含一第三重摻雜區，其係屬於第一導電型，第三重摻雜區設於輕摻雜半導體結構中。
在本發明之一實施例中，暫態電壓抑制裝置更包含至少二隔離結構，其係設於輕摻雜半導體結構上，至少二隔離結構之其中一者設於第二重摻雜區與第一摻雜井區之間，至少二隔離結構之另一者設於第二重摻雜區與第三重摻雜區之間。
在本發明之一實施例中，暫態電壓抑制裝置更包含至少一隔離結構，其係設於輕摻雜半導體結構上，並設於第一摻雜井區與第二重摻雜區之間。
茲為使　貴審查委員對本發明的結構特徵及所達成的功效更有進一步的瞭解與認識，謹佐以較佳的實施例圖及配合詳細的說明，說明如後：
本發明之實施例將藉由下文配合相關圖式進一步加以解說。盡可能的，於圖式與說明書中，相同標號係代表相同或相似構件。於圖式中，基於簡化與方便標示，形狀與厚度可能經過誇大表示。可以理解的是，未特別顯示於圖式中或描述於說明書中之元件，為所屬技術領域中具有通常技術者所知之形態。本領域之通常技術者可依據本發明之內容而進行多種之改變與修改。
以下請參閱第3圖。以下介紹本發明之暫態電壓抑制裝置之第一實施例，其係包含一輕摻雜半導體結構14、一第一摻雜井區16、一第一重摻雜區18、一第一埋區20與一第二重摻雜區22。輕摻雜半導體結構14屬於第一導電型，第一摻雜井區16屬於第二導電型。第一摻雜井區16設於輕摻雜半導體結構14中。第一重摻雜區18屬於第二導電型，第一重摻雜區18設於第一摻雜井區16中。第一埋區20屬於第一導電型，第一埋區20設於輕摻雜半導體結構14中，並位於第一摻雜井區16之下方，第一埋區20鄰接第一摻雜井區16。第二重摻雜區22屬於第二導電型，第二重摻雜區22設於輕摻雜半導體結構14中。輕摻雜半導體結構14為浮接。第一重摻雜區18與第二重摻雜區22分別電性連接一第一接腳與一第二接腳。在第一實施例中，輕摻雜半導體結構14為輕摻雜半導體基板。此外，第一導電型為P型，第二導電型為N型。或者，第一導電型為N型，第二導電型為P型。
本發明之第一實施例更包含至少一隔離結構23，其係設於輕摻雜半導體結構14上，並設於第一摻雜井區16與第二重摻雜區22之間。隔離結構23包含場氧化層(field oxide)或淺溝渠隔離結構(shallow trench isolation)。隔離結構23亦可從第一實施例省略。
請參閱第3圖與第4圖。當第一導電型為P型，第二導電型為N型時，輕摻雜半導體結構14、第一摻雜井區16、第一重摻雜區18與第一埋區20之摻雜濃度分布如第4圖所示。在第4圖中，第一摻雜井區16與第一重摻雜區18之間的介面深度距離輕摻雜半導體結構14之表面為0.1-0.2微米。第一摻雜井區16與第一埋區20之間的崩潰接面之深度距離輕摻雜半導體結構14之表面為0.3-0.4微米。因此，本發明利用第一埋區20形成較深之崩潰接面，以提升功率消耗、湧浪及靜電放電效能。此外，因為崩潰接面之崩潰電壓由第一摻雜井區16與第一埋區20之摻雜濃度所決定，故崩潰電壓之可調範圍得以變寬。以此類推，當第一導電型為N型，第二導電型為P型時，暫態電壓抑制裝置亦增加功率消耗、湧浪及靜電放電效能與崩潰電壓之可調範圍。
請參閱第3圖與第5圖。當第一導電型為P型，第二導電型為N型時，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14與第二重摻雜區22形成一NPN雙載子接面電晶體24，其中第一重摻雜區18、輕摻雜半導體結構14與第二重摻雜區22分別作為NPN雙載子接面電晶體24之集極、基極與射極。請參閱第3圖與第6圖。當第一導電型為N型，第二導電型為P型時，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14與第二重摻雜區22形成一PNP雙載子接面電晶體26，其中第一重摻雜區18、輕摻雜半導體結構14與第二重摻雜區22分別作為PNP雙載子接面電晶體26之集極、基極與射極。
請參閱第7圖，以介紹本發明之暫態電壓抑制裝置之第二實施例。第二實施例與第一實施例差別在於輕摻雜半導體結構14。在第二實施例中，暫態電壓抑制裝置更包含一半導體基板28，且輕摻雜半導體結構14為一輕摻雜井區，其係設於半導體基板28中。當第一導電型為P型，第二導電型為N型時，半導體基板28為N型基板。當第一導電型為N型，第二導電型為P型時，半導體基板28為P型基板。第二實施例之等效電路與第一實施例之等效電路相同，於此不再贅述。
請參閱第8圖，以介紹本發明之暫態電壓抑制裝置之第三實施例。第三實施例與第一實施例差別在於第三實施例更包含一第二摻雜井區30與一第二埋區32。第三實施例為雙向暫態電壓抑制裝置。第二摻雜井區30屬於第二導電型，第二摻雜井區30設於輕摻雜半導體結構14中，第二重摻雜區22設於第二摻雜井區30中。第二埋區32屬於第一導電型，第二埋區32設於輕摻雜半導體結構14中，並位於第二摻雜井區30之下方，第二埋區32鄰接第二摻雜井區30。第二摻雜井區30及第二埋區32之功能與第一摻雜井區16及第一埋區20之功能相同。因此，本發明利用第二埋區32形成較深之崩潰接面，以提升功率消耗、湧浪及靜電放電效能。此外，因為崩潰接面之崩潰電壓由第二摻雜井區30及第二埋區32之摻雜濃度所決定，故崩潰電壓之可調範圍得以變寬。
本發明之第三實施例更包含至少一隔離結構23，其係設於輕摻雜半導體結構14上，並設於第一摻雜井區16與第二摻雜井區30之間。隔離結構23包含場氧化層(field oxide)或淺溝渠隔離結構(shallow trench isolation)。隔離結構23亦可從第三實施例省略。
請參閱第8圖與第9圖。當第一導電型為P型，第二導電型為N型時，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14、第二摻雜井區30、第二埋區32與第二重摻雜區22形成二NPN雙載子接面電晶體24、34，其中第一重摻雜區18、輕摻雜半導體結構14與第二重摻雜區22分別作為NPN雙載子接面電晶體24之集極、基極與射極，第二重摻雜區22、輕摻雜半導體結構14與第一重摻雜區18分別作為NPN雙載子接面電晶體34之集極、基極與射極。
請參閱第8圖與第10圖。當第一導電型為N型，第二導電型為P型時，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14、第二摻雜井區30、第二埋區32與第二重摻雜區22形成二PNP雙載子接面電晶體26、36，其中第一重摻雜區18、輕摻雜半導體結構14與第二重摻雜區22分別作為PNP雙載子接面電晶體26之集極、基極與射極，第二重摻雜區22、輕摻雜半導體結構14與第一重摻雜區18分別作為PNP雙載子接面電晶體36之集極、基極與射極。
請參閱第11圖，以介紹本發明之暫態電壓抑制裝置之第四實施例。第四實施例與第三實施例差別在於輕摻雜半導體結構14。在第四實施例中，暫態電壓抑制裝置更包含一半導體基板28，且輕摻雜半導體結構14為一輕摻雜井區，其係設於半導體基板28中。當第一導電型為P型，第二導電型為N型時，半導體基板28為N型基板。當第一導電型為N型，第二導電型為P型時，半導體基板28為P型基板。第四實施例之等效電路與第三實施例之等效電路相同，於此不再贅述。
請參閱第12圖，以介紹本發明之暫態電壓抑制裝置之第五實施例。第五實施例與第一實施例差別在於第五實施例更包含一第三重摻雜區38，其係屬於第一導電型，並設於輕摻雜半導體結構14中，且電性連接第二接腳。第五實施例為單向暫態電壓抑制裝置。
請參閱第12圖與第13圖。當第一導電型為P型，第二導電型為N型時，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14與第二重摻雜區22形成一NPN雙載子接面電晶體24，其中第一重摻雜區18、輕摻雜半導體結構14與第二重摻雜區22分別作為NPN雙載子接面電晶體24之集極、基極與射極。此外，輕摻雜半導體結構14形成一電阻40，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14與第三重摻雜區38形成一二極體42。
請參閱第12圖與第14圖。當第一導電型為N型，第二導電型為P型時，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14與第二重摻雜區22形成一PNP雙載子接面電晶體26，其中第一重摻雜區18、輕摻雜半導體結構14與第二重摻雜區22分別作為PNP雙載子接面電晶體26之集極、基極與射極。此外，輕摻雜半導體結構14形成一電阻44，第一重摻雜區18、第一摻雜井區16、第一埋區20、輕摻雜半導體結構14與第三重摻雜區38形成一二極體46。
請參閱第15圖，以介紹本發明之暫態電壓抑制裝置之第六實施例。第六實施例與第五實施例差別在於輕摻雜半導體結構14。在第六實施例中，暫態電壓抑制裝置更包含一半導體基板28，且輕摻雜半導體結構14為一輕摻雜井區，其係設於半導體基板28中。當第一導電型為P型，第二導電型為N型時，半導體基板28為N型基板。當第一導電型為N型，第二導電型為P型時，半導體基板28為P型基板。第六實施例之等效電路與第五實施例之等效電路相同，於此不再贅述。
請參閱第16圖，以介紹本發明之暫態電壓抑制裝置之第七實施例。第七實施例與第五實施例差別在於第七實施例更包含至少二隔離結構48，其係設於輕摻雜半導體結構14上，隔離結構48包含場氧化層或淺溝渠隔離結構。二隔離結構48之其中一者設於第二重摻雜區22與第一摻雜井區16之間，二隔離結構48之另一者設於第二重摻雜區22與第三重摻雜區18之間。第七實施例為以互補金氧半導體(CMOS)製程製作的單向暫態抑制裝置。第七實施例之等效電路與第五實施例之等效電路相同，於此不再贅述。
請參閱第17圖，以介紹本發明之暫態電壓抑制裝置之第八實施例。第八實施例與第七實施例差別在於輕摻雜半導體結構14。在第八實施例中，暫態電壓抑制裝置更包含一半導體基板28，且輕摻雜半導體結構14為一輕摻雜井區，其係設於半導體基板28中。當第一導電型為P型，第二導電型為N型時，半導體基板28為N型基板。當第一導電型為N型，第二導電型為P型時，半導體基板28為P型基板。第八實施例之等效電路與第七實施例之等效電路相同，於此不再贅述。
綜上所述，本發明形成一位於摻雜井區下方的埋區，以形成較深之崩潰接面，進而提升功率消耗、湧浪及靜電放電效能與崩潰電壓之可調範圍。
以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
10‧‧‧暫態電壓抑制器 12‧‧‧欲保護電路 14‧‧‧輕摻雜半導體結構 16‧‧‧第一摻雜井區 18‧‧‧第一重摻雜區 20‧‧‧第一埋區 22‧‧‧第二重摻雜區 23‧‧‧隔離結構 24‧‧‧NPN雙載子接面電晶體 26‧‧‧PNP雙載子接面電晶體 28‧‧‧半導體基板 30‧‧‧第二摻雜井區 32‧‧‧第二埋區 34‧‧‧NPN雙載子接面電晶體 36‧‧‧PNP雙載子接面電晶體 38‧‧‧第三重摻雜區 40‧‧‧電阻 42‧‧‧二極體 44‧‧‧電阻 46‧‧‧二極體
第1圖為先前技術之與欲保護電路連接之暫態電壓抑制器的電路方塊圖。 第2圖為先前技術之摻雜濃度與接面深度之曲線圖。 第3圖為本發明之暫態電壓抑制裝置之第一實施例之結構剖視圖。 第4圖為本發明之摻雜濃度與接面深度之曲線圖。 第5圖為本發明之第3圖之一等效電路圖。 第6圖為本發明之第3圖之另一等效電路圖。 第7圖為本發明之暫態電壓抑制裝置之第二實施例之結構剖視圖。 第8圖為本發明之暫態電壓抑制裝置之第三實施例之結構剖視圖。 第9圖為本發明之第8圖之一等效電路圖。 第10圖為本發明之第8圖之另一等效電路圖。 第11圖為本發明之暫態電壓抑制裝置之第四實施例之結構剖視圖。 第12圖為本發明之暫態電壓抑制裝置之第五實施例之結構剖視圖。 第13圖為本發明之第12圖之一等效電路圖。 第14圖為本發明之第12圖之另一等效電路圖。 第15圖為本發明之暫態電壓抑制裝置之第六實施例之結構剖視圖。 第16圖為本發明之暫態電壓抑制裝置之第七實施例之結構剖視圖。 第17圖為本發明之暫態電壓抑制裝置之第八實施例之結構剖視圖。
14‧‧‧輕摻雜半導體結構
16‧‧‧第一摻雜井區
18‧‧‧第一重摻雜區
20‧‧‧第一埋區
22‧‧‧第二重摻雜區
23‧‧‧隔離結構

Claims (18)

  1. 一種暫態電壓抑制裝置，包含： 一輕摻雜半導體結構，屬於第一導電型； 一第一摻雜井區，屬於第二導電型，該第一摻雜井區設於該輕摻雜半導體結構； 一第一重摻雜區，屬於該第二導電型，該第一重摻雜區設於該第一摻雜井區中； 一第一埋區，屬於該第一導電型，該第一埋區設於該輕摻雜半導體結構中，並位於該第一摻雜井區之下方，該第一埋區鄰接該第一摻雜井區；以及 一第二重摻雜區，屬於該第二導電型，該第二重摻雜區設於該輕摻雜半導體結構中。
  2. 如請求項1所述之暫態電壓抑制裝置，其中該第一導電型為N型，該第二導電型為P型。
  3. 如請求項2所述之暫態電壓抑制裝置，更包含一P型基板，該輕摻雜半導體結構為輕摻雜井區，其係設於該P型基板中。
  4. 如請求項2所述之暫態電壓抑制裝置，其中該輕摻雜半導體結構為輕摻雜半導體基板。
  5. 如請求項1所述之暫態電壓抑制裝置，其中該第一導電型為P型，該第二導電型為N型。
  6. 如請求項5所述之暫態電壓抑制裝置，更包含一N型基板，該輕摻雜半導體結構為輕摻雜井區，其係設於該N型基板中。
  7. 如請求項5所述之暫態電壓抑制裝置，其中該輕摻雜半導體結構為輕摻雜半導體基板。
  8. 如請求項1所述之暫態電壓抑制裝置，其中該輕摻雜半導體結構為浮接。
  9. 如請求項1所述之暫態電壓抑制裝置，更包含： 一第二摻雜井區，屬於該第二導電型，該第二摻雜井區設於該輕摻雜半導體結構中，該第二重摻雜區設於該第二摻雜井區中；以及 一第二埋區，屬於該第一導電型，該第二埋區設於該輕摻雜半導體結構中，並位於該第二摻雜井區之下方，該第二埋區鄰接該第二摻雜井區。
  10. 如請求項1所述之暫態電壓抑制裝置，更包含一第三重摻雜區，其係屬於該第一導電型，該第三重摻雜區設於該輕摻雜半導體結構中。
  11. 如請求項10所述之暫態電壓抑制裝置，更包含至少二隔離結構，其係設於該輕摻雜半導體結構上，該至少二隔離結構之其中一者設於該第二重摻雜區與該第一摻雜井區之間，該至少二隔離結構之另一者設於該第二重摻雜區與該第三重摻雜區之間。
  12. 如請求項11所述之暫態電壓抑制裝置，其中該至少二隔離結構包含場氧化層(field oxide)或淺溝渠隔離結構(shallow trench isolations)。
  13. 如請求項10所述之暫態電壓抑制裝置，其中該第一重摻雜區與該第二重摻雜區分別電性連接一第一接腳與一第二接腳，該第二接腳電性連接該第三重摻雜區。
  14. 如請求項1所述之暫態電壓抑制裝置，其中該第一重摻雜區與該第二重摻雜區分別電性連接一第一接腳與一第二接腳。
  15. 如請求項1所述之暫態電壓抑制裝置，更包含至少一隔離結構，其係設於該輕摻雜半導體結構上，並設於該第一摻雜井區與該第二重摻雜區之間。
  16. 如請求項15所述之暫態電壓抑制裝置，其中該至少一隔離結構包含場氧化層(field oxide)或淺溝渠隔離結構(shallow trench isolation)。
  17. 如請求項9所述之暫態電壓抑制裝置，更包含至少一隔離結構，其係設於該輕摻雜半導體結構上，並設於該第一摻雜井區與該第二摻雜井區之間。
  18. 如請求項17所述之暫態電壓抑制裝置，其中該至少一隔離結構包含場氧化層(field oxide)或淺溝渠隔離結構(shallow trench isolation)。
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US9748346B2 (en) 2014-11-25 2017-08-29 Alpha And Omega Semiconductor Incorporated Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
US8193560B2 (en) 2009-06-18 2012-06-05 Freescale Semiconductor, Inc. Voltage limiting devices
US8513774B2 (en) 2010-10-06 2013-08-20 Macronix International Co., Ltd. Low-voltage structure for high-voltage electrostatic discharge protection
US20120139013A1 (en) * 2010-12-03 2012-06-07 Sandeep Bahl Static induction transistor with dielectric carrier separation layer
US8847332B2 (en) * 2011-04-20 2014-09-30 Vanguard International Semiconductor Corporation Laterally diffused metal oxide semiconductor device having halo or pocket implant region
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US8982518B2 (en) 2013-03-14 2015-03-17 The Boeing Company Methods and apparatus to provide transient event protection for circuits
CN104377244A (zh) * 2013-08-15 2015-02-25 无锡华润上华半导体有限公司 一种降低ldmos导通电阻的器件结构
US20150097269A1 (en) * 2013-10-08 2015-04-09 Richtek Technology Corporation Transient voltage suppression device and manufacturing method thereof
US9184165B2 (en) * 2014-02-06 2015-11-10 Globalfoundries Singapore Pte. Ltd. 1t sram/dram
CN106558543B (zh) 2016-08-11 2023-09-01 南京矽力微电子技术有限公司 静电释放保护器件的半导体结构以及制造方法
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