CN109256381B - 瞬时电压抑制装置 - Google Patents

瞬时电压抑制装置 Download PDF

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CN109256381B
CN109256381B CN201811173780.4A CN201811173780A CN109256381B CN 109256381 B CN109256381 B CN 109256381B CN 201811173780 A CN201811173780 A CN 201811173780A CN 109256381 B CN109256381 B CN 109256381B
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doped
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CN109256381A (zh
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林昆贤
陈子平
庄哲豪
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Amazing Microelectronic Corp
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    • H—ELECTRICITY
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Abstract

本发明公开了一种瞬时电压抑制装置，包含一轻掺杂半导体结构、一第一掺杂井区、一第一重掺杂区、一第一埋区与一第二重掺杂区。轻掺杂半导体结构属于第一导电型。第一掺杂井区属于第二导电型，并设于轻掺杂半导体结构中。第一重掺杂区属于第二导电型，并设于第一掺杂井区中。第一埋区属于第一导电型，并设于轻掺杂半导体结构中，且位于第一埋区的下方。第一埋区邻接第一掺杂井区。第二重掺杂区属于第二导电型，并设于轻掺杂半导体结构中。

Description

瞬时电压抑制装置
技术领域
本发明涉及一种抑制装置，且特别关于一种能较深的崩溃接面的瞬时电压抑制装置。
背景技术
由于集成电路(Integrated Circuit)的制作已进入纳米级的工艺水平，芯片内部电晶体的尺寸能够愈做愈小，然而这些芯片确很容易受到静电放电(ESD)的冲击而损伤，再加上一些消费性电子产品，如笔记本电脑或手机亦作的比以前更加轻薄短小，对ESD冲击的承受能力更为降低。对于这些电子产品，若没有利用适当的ESD保护装置来进行保护，则电子产品很容易受到ESD的冲击，而造成电子产品发生统重新启动，甚至硬件受到伤害而无法复原的问题。目前，所有的电子产品都被要求能通过IEC 61000-4-2标准的ESD测试需求。对于电子产品的ESD问题，使用瞬时电压抑制器(TVS)是较为有效的解决方法，让ESD能量快速通过TVS予以释放，避免电子产品受到ESD的冲击而造成伤害。TVS的工作原理如图1所示，在印刷电路板(PCB)上，瞬时电压抑制器10并联欲保护电路12，当ESD情况发生时，瞬时电压抑制器10瞬间被触发，同时，瞬时电压抑制器10亦可提供一低电阻路径，以供瞬时的ESD电流进行放电，让ESD瞬时电流的能量通过瞬时电压抑制器10得以释放。
在美国专利案号7875933中，图3显示一半导体装置，其形成于一半导体基底中。半导体基底包含单晶硅。举例来说，半导体基底为P型基板。半导体装置包含一横向双载子晶体管，其是由两个N型掺杂区于P型基板上所形成。N型掺杂区由一隔离区域分隔，例如由浅沟渠隔离结构(STI)分隔。掺杂区形成集极与射极，半导体基底形成基极，基底电性连接附近的基板接点。有一个离子掺杂区位于作为集极的掺杂区的下方，以调整集基接口的崩溃电压。在此例中，崩溃接面形成在离子掺杂区与作为集极的掺杂区之间。如图2的虚线所示，崩溃接面的深度相距半导体基底的表面约为0.1-0.2微米，使功率消耗不佳。此外，半导体装置的崩溃电压仅由离子掺杂区的掺杂浓度决定，因此崩溃电压的可调范围较窄。
因此，本发明针对上述困扰，提出一种瞬时电压抑制装置，以解决存在的问题。
发明内容
本发明的主要目的，在于提供一种瞬时电压抑制装置，其形成一位于掺杂井区下方的埋区，以形成较深的崩溃接面，进而提升功率消耗、涌浪及静电放电效能与崩溃电压的可调范围。
为达上述目的，本发明提供一种瞬时电压抑制装置，其包含一轻掺杂半导体结构、一第一掺杂井区、一第一重掺杂区、一第一埋区与一第二重掺杂区。轻掺杂半导体结构属于第一导电型，第一掺杂井区属于第二导电型，第一重掺杂区属于第二导电型，第一埋区属于第一导电型，第二重掺杂区属于第二导电型。第一掺杂井区设于轻掺杂半导体结构，第一重掺杂区设于第一掺杂井区中，第一埋区设于轻掺杂半导体结构中，并位于第一掺杂井区的下方，第一埋区邻接第一掺杂井区，第二重掺杂区设于轻掺杂半导体结构中。
在本发明的一实施例中，轻掺杂半导体结构为浮接。
在本发明的一实施例中，瞬时电压抑制装置更包含一第二掺杂井区与一第二埋区。第二掺杂井区属于第二导电型，第二掺杂井区设于轻掺杂半导体结构中，第二重掺杂区设于第二掺杂井区中。第二埋区属于第一导电型，第二埋区设于轻掺杂半导体结构中，并位于第二掺杂井区的下方，第二埋区邻接第二掺杂井区。
在本发明的一实施例中，瞬时电压抑制装置更包含一第三重掺杂区，其属于第一导电型，第三重掺杂区设于轻掺杂半导体结构中。
在本发明的一实施例中，瞬时电压抑制装置更包含至少两个隔离结构，其设于轻掺杂半导体结构上，至少两个隔离结构的其中一者设于第二重掺杂区与第一掺杂井区之间，至少两个隔离结构的另一者设于第二重掺杂区与第三重掺杂区之间。
在本发明的一实施例中，瞬时电压抑制装置更包含至少一隔离结构，其设于轻掺杂半导体结构上，并设于第一掺杂井区与第二重掺杂区之间。
附图说明
图1为现有技术中的与欲保护电路连接的瞬时电压抑制器的电路方块图。
图2为现有技术的掺杂浓度与接面深度的曲线图。
图3为本发明的瞬时电压抑制装置的第一实施例的结构剖视图。
图4为本发明的掺杂浓度与接面深度的曲线图。
图5为本发明的图3的一等效电路图。
图6为本发明的图3的另一等效电路图。
图7为本发明的瞬时电压抑制装置的第二实施例的结构剖视图。
图8为本发明的瞬时电压抑制装置的第三实施例的结构剖视图。
图9为本发明的图8的一等效电路图。
图10为本发明的图8的另一等效电路图。
图11为本发明的瞬时电压抑制装置的第四实施例的结构剖视图。
图12为本发明的瞬时电压抑制装置的第五实施例的结构剖视图。
图13为本发明的图12的一等效电路图。
图14为本发明的图12的另一等效电路图。
图15为本发明的瞬时电压抑制装置的第六实施例的结构剖视图。
图16为本发明的瞬时电压抑制装置的第七实施例的结构剖视图。
图17为本发明的瞬时电压抑制装置的第八实施例的结构剖视图。
附图标记说明：10-瞬时电压抑制器；12-欲保护电路；14-轻掺杂半导体结构；16-第一掺杂井区；18-第一重掺杂区；20-第一埋区；22-第二重掺杂区；23-隔离结构；24-NPN双载子接面晶体管；26-PNP双载子接面晶体管；28-半导体基板；30-第二掺杂井区；32-第二埋区；34-NPN双载子接面晶体管；36-PNP双载子接面晶体管；38-第三重掺杂区；40-电阻；42-二极管；44-电阻；46-二极管。
具体实施方式
本发明的实施例将藉由下文配合相关图式进一步加以解说。尽可能的，于图式与说明书中，相同标号代表相同或相似构件。于图式中，基于简化与方便标示，形状与厚度可能经过夸大表示。可以理解的是，未特别显示于图式中或描述于说明书中的组件，为所属技术领域中具有通常技术者所知的形态。本领域的通常技术者可依据本发明的内容而进行多种的改变与修改。
以下请参阅图3。以下介绍本发明的瞬时电压抑制装置的第一实施例，其包含一轻掺杂半导体结构14、一第一掺杂井区16、一第一重掺杂区18、一第一埋区20与一第二重掺杂区22。轻掺杂半导体结构14属于第一导电型，第一掺杂井区16属于第二导电型。第一掺杂井区16设于轻掺杂半导体结构14中。第一重掺杂区18属于第二导电型，第一重掺杂区18设于第一掺杂井区16中。第一埋区20属于第一导电型，第一埋区20设于轻掺杂半导体结构14中，并位于第一掺杂井区16的下方，第一埋区20邻接第一掺杂井区16。第二重掺杂区22属于第二导电型，第二重掺杂区22设于轻掺杂半导体结构14中。轻掺杂半导体结构14为浮接。第一重掺杂区18与第二重掺杂区22分别电性连接一第一接脚与一第二接脚。在第一实施例中，轻掺杂半导体结构14为轻掺杂半导体基板。此外，第一导电型为P型，第二导电型为N型。或者，第一导电型为N型，第二导电型为P型。
本发明的第一实施例更包含至少一隔离结构23，其设于轻掺杂半导体结构14上，并设于第一掺杂井区16与第二重掺杂区22之间。隔离结构23包含场氧化层(field oxide)或浅沟渠隔离结构(shallow trench isolation)。隔离结构23亦可从第一实施例省略。
请参阅图3与图4。当第一导电型为P型，第二导电型为N型时，轻掺杂半导体结构14、第一掺杂井区16、第一重掺杂区18与第一埋区20的掺杂浓度分布如图4所示。在图4中，第一掺杂井区16与第一重掺杂区18之间的接口深度距离轻掺杂半导体结构14的表面为0.1-0.2微米。第一掺杂井区16与第一埋区20之间的崩溃接面的深度距离轻掺杂半导体结构14的表面为0.3-0.4微米。因此，本发明利用第一埋区20形成较深的崩溃接面，以提升功率消耗、涌浪及静电放电效能。此外，因为崩溃接面的崩溃电压由第一掺杂井区16与第一埋区20的掺杂浓度所决定，故崩溃电压的可调范围得以变宽。以此类推，当第一导电型为N型，第二导电型为P型时，瞬时电压抑制装置亦增加功率消耗、涌浪及静电放电效能与崩溃电压的可调范围。
请参阅图3与图5。当第一导电型为P型，第二导电型为N型时，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14与第二重掺杂区22形成一NPN双载子接面晶体管24，其中第一重掺杂区18、轻掺杂半导体结构14与第二重掺杂区22分别作为NPN双载子接面晶体管24的集极、基极与射极。请参阅图3与图6。当第一导电型为N型，第二导电型为P型时，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14与第二重掺杂区22形成一PNP双载子接面晶体管26，其中第一重掺杂区18、轻掺杂半导体结构14与第二重掺杂区22分别作为PNP双载子接面晶体管26的集极、基极与射极。
请参阅图7，以介绍本发明的瞬时电压抑制装置的第二实施例。第二实施例与第一实施例差别在于轻掺杂半导体结构14。在第二实施例中，瞬时电压抑制装置更包含一半导体基板28，且轻掺杂半导体结构14为一轻掺杂井区，其设于半导体基板28中。当第一导电型为P型，第二导电型为N型时，半导体基板28为N型基板。当第一导电型为N型，第二导电型为P型时，半导体基板28为P型基板。第二实施例的等效电路与第一实施例的等效电路相同，于此不再赘述。
请参阅图8，以介绍本发明的瞬时电压抑制装置的第三实施例。第三实施例与第一实施例差别在于第三实施例更包含一第二掺杂井区30与一第二埋区32。第三实施例为双向瞬时电压抑制装置。第二掺杂井区30属于第二导电型，第二掺杂井区30设于轻掺杂半导体结构14中，第二重掺杂区22设于第二掺杂井区30中。第二埋区32属于第一导电型，第二埋区32设于轻掺杂半导体结构14中，并位于第二掺杂井区30的下方，第二埋区32邻接第二掺杂井区30。第二掺杂井区30及第二埋区32的功能与第一掺杂井区16及第一埋区20的功能相同。因此，本发明利用第二埋区32形成较深的崩溃接面，以提升功率消耗、涌浪及静电放电效能。此外，因为崩溃接面的崩溃电压由第二掺杂井区30及第二埋区32的掺杂浓度所决定，故崩溃电压的可调范围得以变宽。
本发明的第三实施例更包含至少一隔离结构23，其设于轻掺杂半导体结构14上，并设于第一掺杂井区16与第二掺杂井区30之间。隔离结构23包含场氧化层(field oxide)或浅沟渠隔离结构(shallow trench isolation)。隔离结构23亦可从第三实施例省略。
请参阅图8与图9。当第一导电型为P型，第二导电型为N型时，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14、第二掺杂井区30、第二埋区32与第二重掺杂区22形成二NPN双载子接面晶体管24、34，其中第一重掺杂区18、轻掺杂半导体结构14与第二重掺杂区22分别作为NPN双载子接面晶体管24的集极、基极与射极，第二重掺杂区22、轻掺杂半导体结构14与第一重掺杂区18分别作为NPN双载子接面晶体管34的集极、基极与射极。
请参阅图8与图10。当第一导电型为N型，第二导电型为P型时，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14、第二掺杂井区30、第二埋区32与第二重掺杂区22形成二PNP双载子接面晶体管26、36，其中第一重掺杂区18、轻掺杂半导体结构14与第二重掺杂区22分别作为PNP双载子接面晶体管26的集极、基极与射极，第二重掺杂区22、轻掺杂半导体结构14与第一重掺杂区18分别作为PNP双载子接面晶体管36的集极、基极与射极。
请参阅图11，以介绍本发明的瞬时电压抑制装置的第四实施例。第四实施例与第三实施例差别在于轻掺杂半导体结构14。在第四实施例中，瞬时电压抑制装置更包含一半导体基板28，且轻掺杂半导体结构14为一轻掺杂井区，其设于半导体基板28中。当第一导电型为P型，第二导电型为N型时，半导体基板28为N型基板。当第一导电型为N型，第二导电型为P型时，半导体基板28为P型基板。第四实施例的等效电路与第三实施例的等效电路相同，于此不再赘述。
请参阅图12，以介绍本发明的瞬时电压抑制装置的第五实施例。第五实施例与第一实施例差别在于第五实施例更包含一第三重掺杂区38，其属于第一导电型，并设于轻掺杂半导体结构14中，且电性连接第二接脚。第五实施例为单向瞬时电压抑制装置。
请参阅图12与图13。当第一导电型为P型，第二导电型为N型时，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14与第二重掺杂区22形成一NPN双载子接面晶体管24，其中第一重掺杂区18、轻掺杂半导体结构14与第二重掺杂区22分别作为NPN双载子接面晶体管24的集极、基极与射极。此外，轻掺杂半导体结构14形成一电阻40，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14与第三重掺杂区38形成一二极管42。
请参阅图12与图14。当第一导电型为N型，第二导电型为P型时，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14与第二重掺杂区22形成一PNP双载子接面晶体管26，其中第一重掺杂区18、轻掺杂半导体结构14与第二重掺杂区22分别作为PNP双载子接面晶体管26的集极、基极与射极。此外，轻掺杂半导体结构14形成一电阻44，第一重掺杂区18、第一掺杂井区16、第一埋区20、轻掺杂半导体结构14与第三重掺杂区38形成一二极管46。
请参阅图15，以介绍本发明的瞬时电压抑制装置的第六实施例。第六实施例与第五实施例差别在于轻掺杂半导体结构14。在第六实施例中，瞬时电压抑制装置更包含一半导体基板28，且轻掺杂半导体结构14为一轻掺杂井区，其设于半导体基板28中。当第一导电型为P型，第二导电型为N型时，半导体基板28为N型基板。当第一导电型为N型，第二导电型为P型时，半导体基板28为P型基板。第六实施例的等效电路与第五实施例的等效电路相同，于此不再赘述。
请参阅图16，以介绍本发明的瞬时电压抑制装置的第七实施例。第七实施例与第五实施例差别在于第七实施例更包含至少两个隔离结构48，其设于轻掺杂半导体结构14上，隔离结构48包含场氧化层或浅沟渠隔离结构。二隔离结构48的其中一者设于第二重掺杂区22与第一掺杂井区16之间，二隔离结构48的另一者设于第二重掺杂区22与第三重掺杂区18之间。第七实施例为以互补金氧半导体(CMOS)制程制作的单向瞬时抑制装置。第七实施例的等效电路与第五实施例的等效电路相同，于此不再赘述。
请参阅图17，以介绍本发明的瞬时电压抑制装置的第八实施例。第八实施例与第七实施例差别在于轻掺杂半导体结构14。在第八实施例中，瞬时电压抑制装置更包含一半导体基板28，且轻掺杂半导体结构14为一轻掺杂井区，其设于半导体基板28中。当第一导电型为P型，第二导电型为N型时，半导体基板28为N型基板。当第一导电型为N型，第二导电型为P型时，半导体基板28为P型基板。第八实施例的等效电路与第七实施例的等效电路相同，于此不再赘述。
综上所述，本发明形成一位于掺杂井区下方的埋区，以形成较深的崩溃接面，进而提升功率消耗、涌浪及静电放电效能与崩溃电压的可调范围。
以上所述仅为本发明一较佳实施例而已，并非用来限定本发明实施的范围，故举凡依本发明权利要求范围所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的保护范围内。

Claims (8)

1.一种瞬时电压抑制装置，其特征在于，包含：
一轻掺杂半导体结构，属于第一导电型；
一第一掺杂井区，属于第二导电型，该第一掺杂井区设于该轻掺杂半导体结构；
一第一重掺杂区，属于该第二导电型，该第一重掺杂区设于该第一掺杂井区中；
一第一埋区，属于该第一导电型，该第一埋区设于该轻掺杂半导体结构中，并位于该第一掺杂井区的下方，该第一埋区邻接该第一掺杂井区；
一第二重掺杂区，属于该第二导电型，该第二重掺杂区设于该轻掺杂半导体结构中；以及
至少一隔离结构，其设于该轻掺杂半导体结构上，并设于该第一掺杂井区与该第二重掺杂区之间，其中该至少一隔离结构的深度浅于该第一掺杂井区的深度；
其中该第一埋区与该第一掺杂井区之间为无结构设置，该第一埋区与该第一掺杂井区形成崩溃介面；
其中在该第一导电型为N型时，该第二导电型为P型；
其中在该第一导电型为P型时，该第二导电型为N型；
其中该轻掺杂半导体结构、该第一掺杂井区、该第一重掺杂区、该第一埋区与该第二重掺杂区形成双载子接面晶体管，该第一重掺杂区与该第一掺杂井区作为该双载子接面晶体管的集极，该第一埋区与该轻掺杂半导体结构作为该双载子接面晶体管的基极，该第二重掺杂区作为该双载子接面晶体管的射极；
其中该第一重掺杂区与该第二重掺杂区分别电性连接一第一接脚与一第二接脚。
2.如权利要求1所述的瞬时电压抑制装置，其特征在于，更包含一P型基板，且该第一导电型为N型，该第二导电型为P型，该轻掺杂半导体结构为轻掺杂井区，其设于该P型基板中。
3.如权利要求1所述的瞬时电压抑制装置，其特征在于，该轻掺杂半导体结构为轻掺杂半导体基板。
4.如权利要求1所述的瞬时电压抑制装置，其特征在于，更包含一N型基板，且该第一导电型为P型，该第二导电型为N型，该轻掺杂半导体结构为轻掺杂井区，其设于该N型基板中。
5.如权利要求1所述的瞬时电压抑制装置，其特征在于，该轻掺杂半导体结构为浮接。
6.如权利要求1所述的瞬时电压抑制装置，其特征在于，更包含一第三重掺杂区，其属于该第一导电型，该第三重掺杂区设于该轻掺杂半导体结构中。
7.如权利要求6所述的瞬时电压抑制装置，其特征在于，该第二接脚电性连接该第三重掺杂区。
8.如权利要求1所述的瞬时电压抑制装置，其特征在于，该至少一隔离结构包含场氧化层或浅沟渠隔离结构。
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