TW202004974A - 晶粒鋪設技術 - Google Patents

晶粒鋪設技術 Download PDF

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TW202004974A
TW202004974A TW108105811A TW108105811A TW202004974A TW 202004974 A TW202004974 A TW 202004974A TW 108105811 A TW108105811 A TW 108105811A TW 108105811 A TW108105811 A TW 108105811A TW 202004974 A TW202004974 A TW 202004974A
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die
base
base die
chip package
terminal
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TW108105811A
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TWI797260B (zh
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斯里尼斯 佩安巴恩
剛 段
迪帕克 庫卡尼
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美商英特爾股份有限公司
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Abstract

提供用於精細節點異質晶片封裝之技術。於一範例中，一種製造異質晶片封裝之方法可包括使用矽橋以耦合第一基礎晶粒之第一側的電終端至第二基礎晶粒之第一側的電終端，形成有機基底在該矽橋周圍並鄰接該等第一基礎晶粒和第二基礎晶粒之該等第一側，及耦合精細節點晶粒至該第一基礎晶粒或該第二基礎晶粒之至少一者的第二側。

Description

晶粒鋪設技術
此文件一般地有關於(但非以限制之方式)晶粒互連，而更特別地有關於提供使用集成晶粒橋之大型異質晶粒封裝。
傳統晶粒製造技術正被推向其針對單石晶粒之大小的限制，而應用正盼望其可能用於使用最近科技(諸如7nm閘極長度)之大尺寸積體電路的能力。隨著單石晶粒已變得更大，其可能針對較小晶粒被忽略的小差異無法被補償且經常可能顯著地減少產量。最近的解決方案可能涉及使用與半導體插入器互連的或者與矽橋集成的更小積體電路，該等矽橋被組合入矽基底以提供異質晶片封裝。然而，用以製造半導體強加器或基底的傳統技術限制了異質晶片封裝之大小。
及
以下描述及圖形充分地闡明用以致使那些熟悉此技藝人士來施行的特定實施例。其他實施例可結合結構、邏輯、電氣、製程、及其他改變。某些實施例之部分及特徵可被包括於(或取代)其他實施例之那些部分及特徵。申請專利範圍中所提出之實施例係涵蓋那些申請專利範圍之所有可能的同等物。
用以在單一解決方案中使用多數異質晶粒的封裝技術可能需要數個晶粒至晶粒連接。雖然是一種相當新的科技，針對此挑戰之傳統解決方案(其可被稱為2.5D解決方案)可利用矽插入器及穿越矽通孔(TSV)來以所謂的矽互連速度連接晶粒在最小足跡中。其結果是越來越複雜的佈局及製造技術，其可能延遲下線(tape-outs)並抑制生產率。例如，某些使用矽插入器之技術限制了異質晶片封裝之大小。一個限制是其矽插入器被限制於製造程序之微影標線片大小。第二個限制可能是用以生產可接受封裝之組裝程序的能力。例如，組裝程序可包括將精細節點晶粒(或先進節點晶粒)安裝至矽插入器並接著將矽插入器裝附至基底(諸如有機基底)。將插入器裝附至基底可涉及熱連接接合(TCB)程序，其可能使大型插入器變形且不容許強韌的電連接。
圖1一般性地繪示依據本請求標的之異質晶片封裝100的至少一部分之範例。於某些範例中，異質晶片封裝100可包括基底101、複數基礎晶粒102、一或更多矽橋103及一或更多精細節點晶片104。基底101可為有機基底且可包括用以將異質晶片封裝100連接至另一裝置(諸如印刷電路板或更大電子裝置之某其他組件)之終端或互連105。各基礎晶粒102可提供互連106以供精細節點晶片104連接於其上、以及介於基礎晶粒102的第一側與基礎晶粒102的第二側之間的一些穿越互連107。於某些範例中，基礎晶粒102是被動的且可或可不僅包括被動電路元件，諸如電阻、電容、電感、二極體(等等)，以支援精細節點晶片。於某些範例中，基礎晶粒102可包括主動組件以支援精細節點晶片。於某些範例中，基礎晶粒102可包括被動組件及主動組件兩者以支援精細節點晶片104之操作或異質晶片封裝100之操作。基礎晶粒102之電路可包括(但不限定於)電壓轉換器、位準移位器、緩衝器、時鐘電路，等等。於某些範例中，基礎晶粒電路之大小可由用於製造基礎晶粒102之微影設備的標線片大小所限制。於某些範例中，基礎晶粒102可包括額外互連108，用以經由矽橋103而耦合至其他基礎晶粒。
矽橋103可使用其用以製造基礎晶粒102或精細節點晶片104之相同的晶圓製造程序來製造。於某些形態中，矽橋可由其小尺寸、薄度及精細路由所特徵化。例如，矽橋之長度及寬度可為2mm、4mm、6mm及甚至更大者之組合，於某些情況下。矽橋可具有2微米(um)寬度及2 um間隔之軌線路由。矽橋通常具有介於35um與150um之間的厚度但可根據應用而為更厚。於某些範例中，矽橋可包括導電材料之至少兩個接地層及導電材料之兩個路由層。矽橋103可提供介於基礎晶粒102的小節點間隔之間的互連109並可容許異質晶片封裝100之總大小變為相當的大而同時提供其利用傳統組裝的異質晶片封裝(其包括精細節點晶片)所無法得到的產量。精細節點晶片104可包括12nm、10nm、7nm及更細者之等級的節點間隔，但不限於此。隨著電晶體節距科技發展以處理小於7nm之節點長度，本請求標的預期容許其不受可用於製造單石插入器或基礎晶粒102之標線片面積所限制的異質晶片封裝之製造或組裝。因此，使用精細節點晶片之大型異質晶片封裝可使用花費不多的、大型面板的、有機基底為基的處理來製造出以健全的產量。於某些範例中，利用7nm精細節點晶片之異質晶片封裝的互連基礎晶粒可界定具有25mm、50mm、75mm或更長的寬度、長度、或其組合之最終封裝，且仍維持高產量。
圖2A至2G繪示一種依據本請求標的以製造異質晶片封裝100的方法。圖2A顯示種晶層210，其係裝附至可移除的製造基底211、或製造載體。於某些範例中，種晶層210可被沈積於脫模劑(release agent)或可釋黏著劑212上。種晶層210可被用以建立金屬柱213，其可作用為用以準確地將二或更多基礎晶粒102放置於該等柱213之間的基準。柱213可使用傳統方法來製造。於某些範例中，金屬柱可提供介於異質晶片封裝100的主表面之間的功能性連接，例如，用以堆疊異質晶片封裝100與其他組件。
基礎晶粒102可使用傳統方法而被置放並裝附至種晶層210。於某些範例中，基礎晶粒102可使用第二黏著劑214而被裝附至種晶層。於某些範例中，製造基底211為尺寸穩定基底，諸如玻璃。如以上所討論，各基礎晶粒102可提供第一互連215以供精細節點晶片104連接於其上、以及介於基礎晶粒102的第一側與基礎晶粒102的第二側之間的一些穿越連接216。
在圖2B上，在基礎晶粒102被放置於種晶層210後，電介質材料217可被製造(諸如藉由模製)以覆蓋基礎晶粒102。電介質材料217可接著被接地或蝕刻以顯露各基礎晶粒102之第一側上的連接。在圖2C上，矽橋103可被安裝或電連接於兩個基礎晶粒102之間。矽橋103可提供介於基礎晶粒102之間的互連。在該程序之極初始階段中的尺寸穩定載體或製造基底211(諸如玻璃)之使用、及矽橋103之裝附可提供相較於傳統矽橋嵌入程序(其中橋是於基底處理之最終階段放置且是在尺寸上較不穩定的多層有機基底上)顯著地更高的放置準確度及互連穩定度之機會。
在圖2D上，基底101(諸如有機基底)可被製造以包封矽橋103之暴露側並提供基礎晶粒102之外部連接。在圖2E上，製造基底211可連同可釋黏著劑212被移除，種晶層210可被蝕刻或移除，而第二黏著劑214可被蝕刻或鑽孔以暴露基礎晶粒102之第二側上的終端。於某些範例中，異質晶片之中間組裝可被翻轉在移除製造基底211之前或之後。
在圖2F上，精細節點晶粒104可被裝附至各基礎晶粒102。於某些範例中，精細節點晶粒104被電連接(經由製造的互連220)至各基礎晶粒102之第二側上的終端並接著下填218。在圖2G上，第二電介質219可被製造以覆蓋精細節點晶粒104。第二電介質219可被研磨以暴露用於散熱之精細節點晶粒104的背側。於某些範例中，可裝附集成散熱片(IHS)(未顯示)以利提升的散熱。於某些範例中，第二電介質219可被鑽孔以暴露基準柱213之一或更多者的終端。額外的製造可涉及沈積導電材料以形成墊或凸塊來容許異質晶片封裝被電連接至另一組件，諸如(但不限定於)印刷電路板。於某些範例中，圖2A-2G繪示具有兩個基礎晶粒及單一矽橋之異質晶片的製造。於某些範例中，圖2A-2G繪示更大型異質晶片封裝之部分的製造。應理解：使用上述方法之異質晶片封裝可包括多更多的基礎晶粒及矽橋而不背離本請求標的之範圍。
圖3繪示一種用以製造異質晶片封裝之方法300的流程圖。在301，矽橋可被裝附至兩個基礎晶粒以協助介於基礎晶粒之間的電互連。於某些範例中，橋晶粒可為具有耦合外部終端之軌線的極薄矽晶粒，諸如具有等級55微米、35微米、未來更小的節距(諸如10微米)、或其組合之外部微凸塊終端。在302，基底可被製造以包封矽橋並覆蓋基礎晶粒之相應表面。如文中所使用，製造該基底不包括以經組裝的基礎晶粒及矽橋來組裝預先製作的基底。此實例中(以及相關於圖2D)之製造包括將材料之一或更多層沈積於基礎晶粒與橋晶粒之組合上以使得：隨著基底被製造，基底係符合其耦合至矽橋之基礎晶粒的表面之形貌並符合矽橋之暴露部分的拓撲。於某些範例中，於基底之完成時，矽橋可被包封於基底內，除了其耦合至基礎晶粒之橋晶粒的表面以外。於某些範例中，基底可為有機基底。於某些範例中，可於多層中完成該基底之製造以容許導電層及通孔被製造及形成。該基底之導電層及通孔可容許基礎晶粒之節距被扇出至針對異質晶片封裝之外部終端的可接受節距。
於某些範例中，方法300可包括製造基準標記於穩定製造基底上。此等標記可被用以相對於彼此地定位基礎晶粒以使得基礎晶粒之外部連接係針對橋晶粒之互連通孔而被適當地定位。於某些範例中，基準標記可由金屬所形成於一裝附至穩定製造基底之種晶層上。於某些範例中，基準標記可為垂直於製造基底而延伸的金屬柱。於某些範例中，在製造橋晶粒上方之基底以及基礎晶粒之相應表面時，製造基底可被移除，且(在303)精細節點晶粒之節點可被裝附至相反於該矽橋所裝附至之基礎晶粒的表面之基礎晶粒的表面上之基礎晶粒的相應節點。
圖4繪示範例機器400之方塊圖，於該範例機器上可履行文中所討論的技術(例如，方法)之任何一或更多者。於替代實施例中，機器400可操作為獨立裝置或者可被連接(例如，網路連接)至其他機器。於網路連接的部署中，機器400可作為伺服器-客戶網路環境中之伺服器機器、客戶機器、或兩者來操作。於一範例中，機器400可作用為點對點(或其他分散式)網路環境中之同級機器。如文中所使用，點對點指的是直接地介於兩個裝置之間的資料鏈結(例如，其並非軸輻式(hub-and spoke)拓撲)。因此，點對點網路連接為針對使用點對點資料鏈結之一組機器的網路連接。機器400可為單板電腦、積體電路封裝、系統單晶片(SOC)、個人電腦(PC)、輸入板PC、機上盒(STB)、個人數位助理(PDA)、行動電話、網路器具、網路路由器、或者能夠執行其指明應由該機器所採取之行動的指令(序列或其他)的其他機器。再者，雖僅顯示單一機器，但術語「機器」亦應被視為包括其獨立地或聯合地執行一組(或多組)用來履行文中所討論之任何一或更多方法的指令之機器的任何集合，諸如雲端計算、軟體即服務(SaaS)、其他計算叢集組態。
範例(如文中所述者)可包括(或可由以下所操作)邏輯或數個組件、或者機制。電路為其包括硬體之有形單體中所實施之電路的集合(例如，簡單電路、閘、邏輯，等等)。電路構件可隨著時間經過而有彈性且構成硬體變化性之基礎。電路包括其可(單獨地或結合地)履行指定操作(當操作時)之構件。於一範例中，電路之硬體可永遠不變地被設計以執行特定操作(例如，硬線連接的)。於一範例中，電路之硬體可包括可變地連接的實體組件(例如，執行單元、電晶體、簡單電路，等等)，包括電腦可讀取媒體，其被實體地修改(例如，不變性群集的粒子之磁性地、電地、可移動放置，等等)以編碼特定操作之指令。於連接實體組件時，硬體構件之基本電性質被改變(例如)自絕緣體至導體(或反之亦然)。該等指令係致能嵌入式硬體(例如，執行單元或載入機制)經由可變連接而以硬體方式產生硬體中的電路之構件來執行特定操作之部分(當操作時)。因此，電腦可讀取媒體係通訊地耦合至電路之其他組件，當裝置正操作時。於一範例中，實體組件之任一者可被使用於多於一個電路之多於一個構件中。例如，於操作時，執行單元可在一個時點被使用於第一電路系統之第一電路中，且在不同時間被該第一電路系統中之第二電路、或者被第二電路系統中之第三電路所再使用。
機器(例如，電腦系統)400可包括硬體處理器402(例如，中央處理單元(CPU)、圖形處理單元(GPU)、硬體處理器核心、異質晶片封裝、或其任何組合)、主記憶體404及靜態記憶體406，其部分或全部可經由互連(例如，匯流排)408而彼此通訊。機器400可進一步包括顯示單元410、文數輸入裝置412(例如，鍵盤)、及使用者介面(UI)導航裝置414(例如，滑鼠)。於一範例中，顯示單元410、輸入裝置412及UI導航裝置414可為觸控螢幕顯示。機器400可額外地包括儲存裝置(例如，驅動單元)416、信號產生裝置418(例如，揚聲器)、網路介面裝置420、及一或更多感應器421，諸如全球定位系統(GPS)感應器、羅盤、加速計、或其他感應器。機器400可包括輸出控制器428，諸如串列(例如，通用串列匯流排(USB))、平行、或者其他有線或無線(例如，紅外線(IR)、近場通訊(NFC)等等)連接，以通連或控制一或更多周邊裝置(例如，印表機、讀卡機，等等)。
儲存裝置416可包括機器可讀取媒體422，於其上儲存一或更多組資料結構或指令424(例如，軟體)，該等資料結構或指令係實現文中所述之技術或功能的任何一或更多者或者由文中所述之技術或功能的任何一或更多者所利用。指令424亦可駐存(完全地或至少部分地)、於主記憶體404內、於靜態記憶體406內、或者於硬體處理器402內，在藉由機器400之其執行期間。於一範例中，硬體處理器402、主記憶體404、靜態記憶體406、異質晶片封裝、或儲存裝置416之一者或任何組合可構成機器可讀取媒體。於某些範例中，諸如(但不限定於)伺服器機器，異質晶片封裝可包括機器400或上述組件402之任何組合。
雖然機器可讀取媒體422被顯示為單一媒體，但術語「機器可讀取媒體」可包括單一媒體或多重媒體(例如，集中式或分散式資料庫、及/或相關快取及伺服器)，其係組態成儲存一或更多指令集424。
術語「機器可讀取媒體」可包括任何媒體，其能夠儲存、編碼、或攜載指令以供由機器400所執行且其致使機器400履行本發明之技術的任何一或更多者，或者其能夠儲存、編碼或攜載由此等指令所使用的(或者與此等指令關聯的)資料結構。非限制性機器可讀取媒體範例可包括固態記憶體、及光和磁媒體。於一範例中，群集機器可讀取媒體包含具有複數含不變(例如，靜止)質量之粒子的機器可讀取媒體。因此，群集機器可讀取媒體並非暫態傳播信號。群集機器可讀取媒體之特定範例可包括：非揮發性記憶體，諸如半導體記憶體裝置(例如，電可編程唯讀記憶體(EPROM)、電可抹除可編程唯讀記憶體(EEPROM))及快閃記憶體裝置；磁碟，諸如內部硬碟及可移除碟；磁光碟；及CD-ROM和DVD-ROM碟片。
指令424可進一步透過使用傳輸媒體之通訊網路426來傳輸或接收，經由網路介面裝置420，利用數個轉移協定之任一者(例如，框中繼、網際網路協定(IP)、傳輸控制協定(TCP)、使用者資料報協定(UDP)、超文件轉移協定(HTTP)，等等)。範例通訊網路可包括區域網路(LAN)、廣域網路(WAN)、封包資料網路(例如，網際網路)、行動電話網路(例如，胞狀網路)、簡易老式電話(POTS)網路、及無線資料網路(例如，已知為Wi-Fi®的電機電子工程師學會(IEEE)802.11標準系列、已知為WiMax®的IEEE 802.16標準系列)、IEEE 802.15.4標準系列、點對點(P2P)網路，以及其他。於一範例中，網路介面裝置420可包括一或更多實體插口(例如，乙太網路、同軸、或電話插口)或者一或更多天線以供連接至通訊網路426。於一範例中，網路介面裝置420可包括用以無線地通訊之複數天線，使用以下之至少一者：單輸入多輸出(SIMO)、多輸入多輸出(MIMO)、或多輸入單輸出(MISO)技術。術語「傳輸媒體」應被視為包括任何能夠儲存、編碼或攜載指令以供由機器400所執行的無形媒體，且包括用以協助此等軟體之通訊的數位或類比通訊信號或其他無形媒體。
圖5繪示系統位準圖，其係描繪一種包括如本發明中所描述之異質晶片封裝的電子裝置(例如，系統)的例子。於一實施例中，系統500包括(但不限定於)桌上型電腦、膝上型電腦、小筆電、平板、筆記型電腦、個人數位助理(PDA)、伺服器、工作站、行動電話、行動計算裝置、智慧型手機、網際網路器具或任何其他類型的計算裝置。於某些實施例中，系統500為系統單晶片(SOC)系統。
於一實施例中，處理器510具有一或更多處理器核心512及512N，其中512N代表處理器510內部的第N個處理器核心，其中N為正整數。於一實施例中，系統500包括多數處理器(包括510及505)，其中處理器505具有類似於或相同於處理器510之邏輯的邏輯。於某些實施例中，處理核心512包括(但不限定於)預提取邏輯(用以提取指令)、解碼邏輯(用以解碼指令)、執行邏輯(用以執行指令)，等等。於某些實施例中，處理器510具有用以快取系統500之指令及/或資料的快取記憶體516。快取記憶體516可被組織成包括一或更多階快取記憶體的階層結構。
於某些實施例中，處理器510包括記憶體控制器514，其係可操作以履行致能處理器存取及通訊與記憶體530(包括揮發性記憶體532及/或非揮發性記憶體534)之功能。於某些實施例中，處理器510係與記憶體530及晶片組520耦合。處理器510亦可耦合至無線天線578以與任何組態成傳輸及/或接收無線信號之裝置通訊。於一實施例中，無線天線578之介面係依據(但不限定於)IEEE 802.11標準及其相關系列(家用插塞(Home Plug)AV (HPAV)、超寬頻帶(UWB)、藍牙、WiMax、或任何形式的無線通訊協定)而操作。
於某些實施例中，揮發性記憶體532包括(但不限定於)同步動態隨機存取記憶體(SDRAM)、動態隨機存取記憶體(DRAM)、RAMBUS動態隨機存取記憶體(RDRAM)、及/或任何其他類型的隨機存取記憶體裝置。非揮發性記憶體534包括(但不限定於)快閃記憶體、相變記憶體(PCM)、唯讀記憶體(ROM)、電可抹除可編程唯讀記憶體(EEPROM)、或任何其他類型的非揮發性記憶體裝置。
記憶體530係儲存將由處理器510所執行的資訊及指令。於一實施例中，記憶體530亦可儲存暫時變數或其他中間資訊，在當處理器510正執行指令時。於所示的實施例中，晶片組520係經由點對點(PtP或P-P)介面517及522而與處理器510連接。晶片組520致能處理器510連接至系統500中之其他元件。於範例系統之某些實施例中，介面517及522係依據PtP通訊協定(諸如Intel® QuickPath Interconnect (QPI)等等)而操作。於其他實施例中，不同的互連可被使用。於某些範例中，異質晶片封裝(如以上參考圖1、2A-2g及3所討論)可包括處理器510、記憶體530、晶片組520、介面517、介面522、或其組合。
於某些實施例中，晶片組520係可操作以與以下通訊：處理器510、505N、顯示裝置540、及其他裝置，包括匯流排橋572、智慧型TV 576、I/O裝置574、非揮發性記憶體560、儲存媒體(諸如一或更多大量儲存裝置)562、鍵盤/滑鼠564、網路介面566、及各種形式的消費者電子設備577(諸如PDA、智慧型手機、平板等等)，等等。於一實施例中，晶片組520係透過介面524而與這些裝置耦合。晶片組520亦可耦合至無線天線578以與任何組態成傳輸及/或接收無線信號之裝置通訊。
晶片組520經由介面526而連接至顯示裝置540。顯示540可為(例如)液晶顯示(LCD)、電漿顯示、陰極射線管(CRT)顯示、或任何其他形式的視覺顯示裝置。於範例系統之某些實施例中，處理器510與晶片組520被合併成單一SOC。此外，晶片組520連接至一或更多匯流排550及555，其係互連各種系統元件，諸如I/O裝置574、非揮發性記憶體560、儲存媒體562、鍵盤/滑鼠564、及網路介面566。匯流排550及555係經由匯流排橋572而被互連在一起。
於一實施例中，大量儲存裝置562包括(但不限定於)固態驅動、硬碟驅動、通用串列匯流排快閃記憶體驅動、或任何其他形式的電腦資料儲存媒體。於一實施例中，網路介面566係藉由任何類型的眾所周知網路介面標準來實施，包括(但不限定於)乙太網路介面、通用串列匯流排(USB)介面、快速周邊組件互連(PCI)介面、無線介面及/或任何其他適當類型的介面。於一實施例中，無線介面係依據(但不限定於)IEEE 802.11標準及其相關系列(家用插塞(Home Plug)AV (HPAV)、超寬頻帶(UWB)、藍牙、WiMax、或任何形式的無線通訊協定)而操作。
雖然圖5中所示之模組被描繪為系統500內之分離的區塊，但由這些區塊之部分所履行的功能可被集成於單一半導體電路內或者可使用二或更多分離的積體電路來實施。例如，雖然快取記憶體516被描繪為處理器510內之分離的區塊，但快取記憶體516(或516之選定的形態)可被結合入處理器核心512內。額外重點
於第一範例(範例1)中，一種形成異質晶片封裝之方法可包括使用矽橋以耦合第一基礎晶粒之第一側的電終端至第二基礎晶粒之第一側的電終端，形成有機基底在該矽橋周圍並鄰接該等第一基礎晶粒和第二基礎晶粒之該等第一側，及耦合先進節點晶粒至該第一基礎晶粒或該第二基礎晶粒之至少一者的第二側。
於範例2中，申請專利範圍第1項之方法選擇性地包括：在使用該矽橋以耦合該第一基礎晶粒之該第一側的該等電終端至該第二基礎晶粒之該第一側的該等電終端以前，裝附該第一基礎晶粒之該第二側至載體，及裝附該第二基礎晶粒之該第二側至該載體。
於範例3中，範例1-2之任何一或更多者的該載體選擇性地為玻璃為基的載體。
於範例4中，範例1-3之任何一或更多者的方法選擇性地包括：在放置該第一基礎晶粒或該第二基礎晶粒之任一者於該載體上以前，製造基準標記於該載體上以協助該第一基礎晶粒及該第二基礎晶粒之放置。
於範例5中，製造範例1-4之任何一或更多者的該等基準標記選擇性地包括沈積種晶層於該載體上，及製造該等基準標記於該種晶層上。
於範例6中，範例1-5之任何一或更多者的該等基準標記選擇性地組態成協助多於兩個基礎晶粒之放置於該載體上。
於範例7中，範例1-6之任何一或更多者的方法選擇性地包括：在使用該矽橋以耦合該第一基礎晶粒之該第一側的該等電終端至該第二基礎晶粒之該第一側的該等電終端以前，以電介質材料覆蓋模製該第一基礎晶粒及該第二基礎晶粒。
於範例8中，範例1-2之任何一或更多者的方法選擇性地包括研磨該電介質材料以暴露該第一基礎晶粒之該第一側的該等電終端。
於範例9中，範例1-8之任何一或更多者的方法選擇性地包括研磨該電介質材料以暴露該第二基礎晶粒之該第一側的該等電終端。
於範例10中，範例1-2之任何一或更多者的方法選擇性地包括在形成該有機基底後移除該載體。
於範例11中，範例1-2之任何一或更多者的方法選擇性地包括蝕刻其鄰接該第一基礎晶粒之該第二側及該第二基礎晶粒之第二側的黏著劑以暴露該第一基礎晶粒之該第二側的電終端並暴露該第二基礎晶粒之該第二側的電終端。
於範例12中，範例1-11之任何一或更多者的方法選擇性地包括下填該先進節點晶粒。
於範例13中，範例1-2之任何一或更多者的方法選擇性地包括覆蓋模製該先進節點晶粒。
於範例14中，一種異質晶片封裝可包括第一基礎晶粒、第二基礎晶粒、組態成耦合該第一基礎晶粒之第一側的終端與該第二基礎晶粒之第一側的終端之矽橋、配置於該矽橋周圍並鄰接該第一基礎晶粒與該第二基礎晶粒之該第一側的有機基底，該有機基底組態成提供用以耦合該異質晶片封裝至電路之電終端、及耦合至該第一基礎晶粒或該第二基礎晶粒之一的第二側之電連接的先進節點晶粒。
於範例15中，範例1-14之任何一或更多者的該第一基礎晶粒選擇性地組態成連接該第一基礎晶粒之該第一側的第二終端與該第一基礎晶粒之該第二側的第二終端。
於範例16中，範例1-15之任何一或更多者的該第二基礎晶粒選擇性地組態成連接該第二基礎晶粒之該第一側的第二終端與該第二基礎晶粒之該第二側的第二終端。
於範例17中，範例1-16之任何一或更多者的該異質晶片封裝之足跡的面積選擇性地係大於700 mm2 ，而該先進節點晶粒包括7nm技術。
於範例18中，範例1-17之任何一或更多者的該異質晶片封裝選擇性地包括大於50mm之長度尺寸。
於範例19中，範例1-18之任何一或更多者的該異質晶片封裝選擇性地包括大於50mm之寬度尺寸。
於範例20中，範例1-19之任何一或更多者的該異質晶片封裝選擇性地包括支援額外精細節點晶粒之連接的額外基礎晶粒，該額外基礎晶粒係經由第一額外矽橋而彼此互連並經由第二額外矽橋而與該第一基礎晶粒及該第二基礎晶粒互連。
以上詳細描述包括對於附圖之參考，該等附圖係形成詳細描述之一部分。該等圖形係顯示(藉由繪示之方式)其中可實現本發明的特定實施例。這些實施例於文中亦稱為「範例」。此等範例可包括除了那些已顯示或已描述者之外的元件。然而，本案發明人亦考量僅提供了那些已顯示或已描述之元件的範例。此外，本案發明人亦考量使用那些已顯示或已描述之元件(或其一或更多形態)的任何組合或排列之範例，無論是針對特定範例(或其一或更多形態)，或者是針對其他範例(或其一或更多形態)，如文中所述者。
於此文件中，使用了術語「一(a)」或「一(an)」(如專利文件中所常見者)以包括一個或多於一個，無關於「至少一」或「一或更多」之任何其他實例或使用。於此文件中，使用了術語「或」以指稱非排他的或，以使得「A或B」包括了「A但非B」、「B但非A」、及「A與B」，除非另有指示。於此文件中，術語「包括」及「其中」被使用為個別術語「包含」及「其中」的一般英文同語詞。同時，於以下申請專利範圍中，術語「包括」及「包含」為開放式的，亦即，一種包括在申請專利範圍中之此一術語後所列出之那些以外的元件之系統、裝置、物件、組成、成分、或製程仍被視為落入該項申請專利範圍之範圍內。此外，於以下申請專利範圍中，術語「第一」、「第二」、及「第三」等等僅被使用為標籤，而不是為了要加諸數字的要求於其目標上。
上述描述係為了說明性，而非限制性。例如，上述範例(或其一或更多形態)可彼此結合地使用。於閱讀以上描述後其他實施例可被使用，諸如由本技術領域中具有通常知識者。提供了摘要以符合37 C.F.R. §1.72(b)，來容許讀者快速地確認技術內容之本質。應理解摘要的提交不應被用來解讀或限制申請專利範圍之範圍或意義。同時，於以上詳細描述中，各種特徵可被群集在一起以簡化本發明。此不應被解讀為認為其未納入申請專利範圍之已揭露特徵為任何申請專利範圍之基本必要的。反之，具發明性的請求標的可存在於比特定已揭露實施例之所有特徵還少的特徵內。因此，以下申請專利範圍藉此被併入詳細描述，以各申請專利範圍獨立為分離的實施例，已考量其此等實施例可以各種結合或排列方式來彼此結合。本發明之範圍應參考後附申請專利範圍(連同此等申請專利範圍合法有權主張之同等物的完整範圍)來判定。
100‧‧‧異質晶片封裝 101‧‧‧基底 102‧‧‧基礎晶粒 103‧‧‧矽橋 104‧‧‧精細節點晶片 105‧‧‧終端或互連 106‧‧‧互連 107‧‧‧互連 108‧‧‧額外互連 109‧‧‧互連 210‧‧‧種晶層 211‧‧‧製造基底 212‧‧‧可釋黏著劑 213‧‧‧金屬柱 214‧‧‧第二黏著劑 215‧‧‧第一互連 216‧‧‧穿越連接 217‧‧‧電介質材料 218‧‧‧下填 219‧‧‧第二電介質 220‧‧‧互連 400‧‧‧機器 402‧‧‧硬體處理器 404‧‧‧主記憶體 406‧‧‧靜態記憶體 408‧‧‧互連 410‧‧‧顯示單元 412‧‧‧文數輸入裝置 414‧‧‧使用者介面(UI)導航裝置 416‧‧‧儲存裝置 418‧‧‧信號產生裝置 420‧‧‧網路介面裝置 421‧‧‧感應器 422‧‧‧機器可讀取媒體 424‧‧‧資料結構或指令 426‧‧‧通訊網路 428‧‧‧輸出控制器 500‧‧‧系統 505‧‧‧處理器 510‧‧‧處理器 512、512N‧‧‧處理器核心 514‧‧‧記憶體控制器 516‧‧‧快取記憶體 517‧‧‧介面 520‧‧‧晶片組 522‧‧‧介面 524‧‧‧介面 526‧‧‧介面 530‧‧‧記憶體 532‧‧‧揮發性記憶體 534‧‧‧非揮發性記憶體 540‧‧‧顯示裝置 550、555‧‧‧匯流排 560‧‧‧非揮發性記憶體 562‧‧‧儲存媒體 564‧‧‧鍵盤/滑鼠 566‧‧‧網路介面 572‧‧‧匯流排橋 574‧‧‧I/O裝置 576‧‧‧智慧型TV 577‧‧‧消費者電子設備 578‧‧‧無線天線
於圖形(其不一定依比例繪製)中，類似的數字可描述不同視圖中之類似的組件。具有不同文字字尾之類似數字可代表類似組件之不同實例。某些實施例係藉由範例來闡明(而非限制)於附圖之圖示中，其中：
圖1一般性地繪示依據本請求標的之異質晶片封裝100的至少一部分之範例。
圖2A至2G繪示一種依據本請求標的以製造異質晶片封裝100的方法。
圖3繪示一種用以製造異質晶片封裝之方法300的流程圖。
圖4繪示範例機器400之方塊圖，於該範例機器上可履行文中所討論的技術(例如，方法)之任何一或更多者。
圖5繪示系統位準圖，其係描繪一種包括如本發明中所描述之異質晶片封裝的電子裝置(例如，系統)的例子。

Claims (20)

  1. 一種形成異質晶片封裝之方法，該方法包含： 使用矽橋以耦合第一基礎晶粒之第一側的電終端至第二基礎晶粒之第一側的電終端； 形成有機基底在該矽橋周圍並鄰接該等第一基礎晶粒和第二基礎晶粒之該等第一側；及 耦合先進節點晶粒至該第一基礎晶粒或該第二基礎晶粒之至少一者的第二側。
  2. 如申請專利範圍第1項之方法，包括在使用該矽橋以耦合該第一基礎晶粒之該第一側的該等電終端至該第二基礎晶粒之該第一側的該等電終端以前： 裝附該第一基礎晶粒之該第二側至載體；及 裝附該第二基礎晶粒之該第二側至該載體。
  3. 如申請專利範圍第2項之方法，其中該載體是玻璃為基的載體。
  4. 如申請專利範圍第2項之方法，包括：在放置該第一基礎晶粒或該第二基礎晶粒之任一者於該載體上以前，製造基準標記於該載體上以協助該第一基礎晶粒及該第二基礎晶粒之放置。
  5. 如申請專利範圍第4項之方法，其中製造該等基準標記包括沈積種晶層於該載體上，及製造該等基準標記於該種晶層上。
  6. 如申請專利範圍第4項之方法，其中該等基準標記組態成協助多於兩個基礎晶粒之放置於該載體上。
  7. 如申請專利範圍第2項之方法，包括：在使用該矽橋以耦合該第一基礎晶粒之該第一側的該等電終端至該第二基礎晶粒之該第一側的該等電終端以前，以電介質材料覆蓋模製該第一基礎晶粒及該第二基礎晶粒。
  8. 如申請專利範圍第7項之方法，包括研磨該電介質材料以暴露該第一基礎晶粒之該第一側的該等電終端。
  9. 如申請專利範圍第7項之方法，包括研磨該電介質材料以暴露該第二基礎晶粒之該第一側的該等電終端。
  10. 如申請專利範圍第2項之方法，包括在形成該有機基底後移除該載體。
  11. 如申請專利範圍第10項之方法，包括蝕刻其鄰接該第一基礎晶粒之該第二側及該第二基礎晶粒之第二側的黏著劑以暴露該第一基礎晶粒之該第二側的電終端並暴露該第二基礎晶粒之該第二側的電終端。
  12. 如申請專利範圍第1項之方法，包括下填該先進節點晶粒。
  13. 如申請專利範圍第12項之方法，包括覆蓋模製該先進節點晶粒。
  14. 一種異質晶片封裝，包含： 第一基礎晶粒； 第二基礎晶粒； 組態成耦合該第一基礎晶粒之第一側的終端與該第二基礎晶粒之第一側的終端之矽橋； 配置於該矽橋周圍並鄰接該第一基礎晶粒與該第二基礎晶粒之該第一側的有機基底，該有機基底組態成提供用以耦合該異質晶片封裝至電路之電終端；及 耦合至該第一基礎晶粒或該第二基礎晶粒之一的第二側之電連接的先進節點晶粒。
  15. 如申請專利範圍第14項之異質晶片封裝，其中該第一基礎晶粒組態成連接該第一基礎晶粒之該第一側的第二終端與該第一基礎晶粒之該第二側的第二終端。
  16. 如申請專利範圍第14項之異質晶片封裝，其中該第二基礎晶粒組態成連接該第二基礎晶粒之該第一側的第二終端與該第二基礎晶粒之該第二側的第二終端。
  17. 如申請專利範圍第14項之異質晶片封裝，其中該異質晶片封裝之足跡的面積係大於700 mm2 ，而該先進節點晶粒包括7nm技術。
  18. 如申請專利範圍第14項之異質晶片封裝，其中該異質晶片封裝包括大於50mm之長度尺寸。
  19. 如申請專利範圍第14項之異質晶片封裝，其中該異質晶片封裝包括大於50mm之寬度尺寸。
  20. 如申請專利範圍第14項之異質晶片封裝，包括支援額外精細節點晶粒之連接的額外基礎晶粒，該額外基礎晶粒係經由第一額外矽橋而彼此互連並經由第二額外矽橋而與該第一基礎晶粒及該第二基礎晶粒互連。
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