TW202003895A - 用於銅金屬化的阻障層以及形成方法 - Google Patents

用於銅金屬化的阻障層以及形成方法 Download PDF

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TW202003895A
TW202003895A TW108115526A TW108115526A TW202003895A TW 202003895 A TW202003895 A TW 202003895A TW 108115526 A TW108115526 A TW 108115526A TW 108115526 A TW108115526 A TW 108115526A TW 202003895 A TW202003895 A TW 202003895A
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barrier layer
layer
aluminum
thickness
substrate
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沙謝德利 甘古利
尚澔 柳
陳璐
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美商應用材料股份有限公司
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Abstract

本案描述一種具有阻障層之電子元件和方法及形成該阻障層之方法。可將基板暴露於金屬前驅物（例如，鉭前驅物）、反應物（例如，氨氣）及可選電漿以形成第一厚度之阻障層。可選鋁膜可形成於第一阻障層上且第二阻障層形成於該第一阻障層上以形成具有鋁間層之阻障層。

Description

用於銅金屬化的阻障層以及形成方法
本揭示案之實施例係關於阻障層及其形成方法。更特定而言，本揭示案之實施例涉及用於銅金屬化之共形阻障層及形成共形阻障層之方法。
半導體及電子加工工業持續爭取更大之產品良率，同時增大沉積於具有更大表面積之基板上的層之均勻性。與新材料結合之此等相同因素亦提供單位面積基板更高之電路系統整合。隨著電路系統整合增大，對更高均勻性及關於層厚度之製程控制之需要增加。因此，已經發展各種技術以經濟有效地方式將層沉積於基板上，同時維持對層之特徵的控制。
隨著正在生產之節點元件愈來愈小，當前物理氣相沉積(physical vapor deposition; PVD)阻障層之階梯覆蓋不夠充分且需要共形阻障層。然而，共形阻障層具有高電阻率且通孔電阻高於PVD阻障層。當前沉積製程使用製程腔室解決方案以沉積共形膜，隨後在另一處理腔室中進行PVD處理。此舉為耗時且費錢的製程，需要在兩個處理腔室之間移動且使用兩個處理腔室。
因此，在本領域中需要阻障層及製備阻障層之方法，其允許更高產量、更低通孔電阻及/或更容易之製造處理。
本揭示案之一或多個實施例涉及形成阻障層之方法。將基板表面暴露於鉭前驅物及反應物以形成具有第一厚度之第一氮化鉭膜。將氮化鉭膜暴露於鋁前驅物以在第一氮化鉭膜上形成鋁膜。將基板表面暴露於鉭前驅物及反應物以形成具有第二厚度之第二氮化鉭膜以形成具有鋁間層之阻障層，該鋁間層具有阻障層厚度。
本揭示案之附加實施例涉及包括提供具有金屬表面及介電表面之基板的處理方法。在一溫度下，藉由將基板暴露於鉭前驅物及反應物以形成未處理之TaN層，而選擇性地生成第一TaN層。將未處理之TaN層暴露於電漿以生成第一TaN層。在與第一TaN層約相同之溫度下藉由將基板暴露於鋁前驅物，而在第一TaN層上形成鋁膜。在一溫度下，藉由將基板暴露於鉭前驅物及反應物以形成未處理TaN，且將未處理TaN層暴露於電漿以生成第二TaN層，而形成第二TaN層。
本揭示案之另外實施例涉及包括具有第一金屬層及介電層之基板的半導體元件。包括具有鋁間層之TaN的阻障層形成於介電層上。鋁間層為不連續的且阻障層包括約1至約3原子% Al。
本揭示案之實施例涉及阻障層及形成阻障層之方法。本揭示案之一些實施例有利地提供形成具有通孔電阻之共形阻障層之方法，其等效於當前PVD基線法。這可以使用相對於純金屬表面選擇性沉積於氧化物/金屬氧化物/碳化物/氮化物表面上之前驅物來實現。在一些實施例中，鋁夾在兩層阻障膜之間，藉由吸收擴散金屬（例如，銅）原子而有利地改善了阻障性質。
本揭示案之一些實施例有利地提供沉積共形膜之方法，該共形膜之通孔電阻等效於藉由習用物理氣相沉積製程沉積的膜。一些實施例有利地提供使用一個製程腔室之形成阻障層的方法。
如本文使用的「基板表面」，指任意基板部分或在基板上形成的材料表面部分，對該基板執行膜處理。例如，在其上可執行處理的基板表面根據應用包括材料，諸如矽、氧化矽、氮化矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石，以及任意其他材料，諸如金屬、金屬氮化物、金屬合金，以及其他導電材料。基板包括但不限於半導體晶圓。基板可暴露於預處理製程以研磨、蝕刻、還原、氧化、羥基化、退火、UV固化、電子束固化、及/或烘烤基板表面。除了直接在基板本身的表面上的膜處理外，在本發明中，所揭示之膜處理步驟的任一步也可在基板上形成的下層上執行，如下文更詳細地說明，且術語「基板表面」意欲包括上下文指出的此種下層。因此，例如，在膜/層或部分膜/層已經沉積在基板表面上的情況下，新沉積的膜/層的暴露表面變成基板表面。基板可具有不同尺寸，諸如200 mm或300 mm直徑晶圓，以及矩形或正方形窗格。在一些實施例中，基板包括剛性離散材料。
如本文使用「原子層沉積」或「循環沉積」指順序暴露兩種或更多種反應化合物以在基板表面上沉積材料層。如在本說明書及隨附申請專利範圍中使用，術語「反應化合物」、「反應氣體」、「反應物質」、「前驅物」、「製程氣體」等等可互換使用以意味具有在表面反應（例如，化學吸附、氧化、還原）中能夠與基板表面或基板表面上之材料反應的物種的物質。將基板、或基板部分順序暴露於引入處理腔室之反應區中的兩種或更多種反應化合物。在時域ALD製程中，暴露於每種反應化合物之步驟藉由時間延遲來分隔以允許每種化合物黏附及/或起反應於基板表面上且隨後從處理腔室淨化。在空間ALD製程中，基板表面之不同部分、或基板表面上之材料，同時暴露於兩種或更多種反應化合物，以便基板上之任意已知點實質上並不同時暴露於多於一種反應化合物。如本說明書及隨附申請專利範圍中使用，此方面使用之術語「實質上」意味著本領域彼等技術人員所理解之存在由於擴散導致的基板之小部分同時暴露於多種反應氣體之可能性，且該同時暴露為非故意的。
在時域ALD製程之一個態樣中，將第一反應氣體（即，第一前驅物或化合物A）脈衝進反應區中，隨後為第一時間延遲。接下來，將第二前驅物或化合物B脈衝進反應區，隨後為第二延遲。在每次時間延遲期間，將淨化氣體（諸如氬氣）引入處理腔室中以淨化反應區或以另外方式從反應區去除任何剩餘反應化合物或反應副產物。或者，淨化氣體可在整個沉積製程中連續地流動，以便在反應化合物之脈衝之間的時間延遲期間僅有淨化氣體流動。交替地脈衝反應化合物直到在基板表面上形成要求膜或膜厚度。在任一種情景中，脈衝化合物A、淨化氣體、化合物B及淨化氣體之ALD製程為一循環。循環可從化合物A或化合物B開始，並且繼續各個循環之序列直到實現具有預定厚度之膜。
在空間ALD製程之實施例中，第一反應氣體及第二反應氣體同時輸送至反應區但由惰性氣體幕及/或真空幕分隔。相對於氣體輸送設備移動基板，以便基板上之任意已知點順序地暴露於第一反應氣體及第二反應氣體。
在本揭示案之一些實施例中，阻障膜藉由原子層沉積而沉積。例如，藉由交替暴露於鉭前驅物及氮氣反應物，隨後利用電漿（例如，40 MHz Ar / H2 ）處理，而形成膜(約5 A)。可重複膜形成製程以獲得具有預定厚度之膜。在一些實施例中，電漿處理降低膜電阻率。在一些實施例中，電漿處理減少膜之碳含量。在一些實施例中，電漿處理改善膜之阻障性質。
第1A圖至第1E圖圖示根據第2圖中描述之方法100的一或多個實施例處理的電子元件10。參照圖式，本揭示案之一或多個實施例涉及形成電子元件10之方法100。在一些實施例中，方法100被描述為在基板20上形成阻障層50。在105處，基板20經提供用於處理。以此方式使用之術語「經提供用於」意味將基板置於一位置（即，處理腔室）中以執行至少一個方法製程，或用於形成基板本身之製程。
在一些實施例中，基板20具有第一材料30及第二材料40，第一材料30具有第一表面31，第二材料40具有第二表面41。在一些實施例中，第一材料30包括介電質（例如，SiO2 ）。在一些實施例中，第二材料40包括導電材料（例如，銅(Cu)）。在一些實施例中，第一材料包括導電材料，及第二材料包括介電質。在一些實施例中，如第1A圖至第1E圖圖示，將第二材料40凹成低於第一材料30之水平，以便第二表面41低於第一表面31。換言之，在一些實施例中，第一材料30具有從基板20量測之大於第二材料40之厚度。第一材料與第二材料之交錯高度形成至少一個特徵（例如，溝槽）。溝槽可具有由第二材料40之第二表面41形成之底部及由第一材料30形成之側壁。
如第1B圖圖示，形成阻障層50之步驟開始於形成第一阻障層51。第一阻障層51可形成為共形膜，如圖所示，或相對於第二材料40之第二表面41選擇性地形成於第一材料30之第一表面31上。如本說明書及隨附申請專利範圍中使用，「共形」膜在特徵之頂部、中間及底部具有實質上均勻之厚度。實質上均勻之厚度相對於平均厚度變化不超過10%、5%、2%或1%。
本揭示案之各種實施例在本文關於氮化鉭(TaN)阻障層50之形成來描述。熟習此項技術者將認識到本揭示案不限於TaN阻障層，且其他材料落在本揭示案之範疇內。在一或多個實施例中，如110處圖示，在一溫度下，藉由將基板暴露於金屬前驅物112（例如，鉭前驅物）及反應物114以形成未處理的第一阻障層，而選擇性地形成第一阻障層51。將金屬前驅物及反應物同時或按順序地暴露於基板。在一些實施例中，將未處理阻障層暴露於可選電漿處理116以生成第一阻障層51。
金屬前驅物可為形成阻障層之熟習此項技術者已知的任何適當金屬前驅物。在一些實施例中，金屬前驅物包括鉭前驅物。在一些實施例中，鉭前驅物包括具有通式M(NR2 )3L之化合物，見結構(I)，
Figure 02_image001
其中M包括金屬原子，每個R獨立地從由H及C1 - C5烷基組成之群組中選出，且L為具有至少三個碳原子及雙鍵或三鍵（即，具有金屬原子之η鍵）的有機配位體。如以此方式使用，η鍵指經由至少兩個鄰近原子與金屬原子配位之配位體。
在一些實施例中，金屬原子(M)包括坦、基本上由坦組成或由坦組成。在一些實施例中，術語「基本上由...組成」意味以原子計，大於或等於約95%、98%、99%或99.5%金屬原子為所述物種。
在一些實施例中，配位體L經由其中兩個鄰近原子與金屬原子配位之η2 鍵而配位至金屬原子。在一些實施例中，配位體L包括約3至約18個碳原子。在一些實施例中，配位體L包括具有雙鍵之大於或等於三個碳原子。在一些實施例中，配位體L包括具有三鍵之大於或等於三個碳原子。在一些實施例中，配位體L包括鍵接至非封端原子之至少一個雙鍵及/或三鍵。如以此方式使用，非封端原子意味形成原子鏈末尾之任何原子，除氫原子外。例如，在第二碳原子與第三碳原子之間具有雙鍵之丁烯為非封端的，其中在第一碳原子與第二碳原子之間的鍵為封端鍵。在一些實施例中，配位體L具有低於NR2 基團之每一者的鍵能。在一些實施例中，配位體L包括丁烯、丁炔、戊烯、戊炔、己烷、己炔、庚烷、庚炔、辛烯、辛炔、壬烯、壬炔、癸烯或癸炔之一或多者。
在一些實施例中，配位體L鍵接至金屬表面以阻止沉積於金屬表面上，從而增大沉積製程在介電表面上之選擇性。電漿處理可去除鍵接至金屬表面之任何配位體L，以便下一次前驅物暴露幾乎沒有或完全沒有成核延遲。
反應物114可為與吸附至基板上之金屬前驅物反應之任何適當反應物。適當的反應物包括但不限於氮氣、氨氣、肼、氧化氮、氧化亞氮、其組合或電漿。在一些實施例中，反應物包括氨氣、基本上由氨氣組成或由氨氣組成。稀釋劑、載體或惰性氣體不包括在反應物之組成物之計算內。在一些實施例中，在無電漿之熱製程中將反應物暴露於基板。
在與反應物反應之後，可將基板暴露於可選電漿116。電漿暴露可改變第一阻障層51之性質、從金屬表面去除殘餘配位體、及/或活化表面以進行進一步沉積。在一些實施例中，電漿包括惰性氣體及氫氣(H2 )。一些實施例中之電漿包括約10%至約90%之氫含量。在一些實施例中，惰性氣體包括氦氣(He)、氖氣(Ne)、氬氣(Ar)、氪氣(Kr)或氙氣(Xe)之一或多種。在一些實施例中，惰性氣體包括氬氣、基本上由氬氣組成或由氬氣組成。在一些實施例中，電漿包括氬氣及氫氣，其中Ar:H2 比率在約1:1至約1:10之範圍中，或在約1:2至約1:8之範圍中，或在約1:3至約1:5之範圍中。在一些實施例中，電漿包括以莫耳計大於或等於約50%、55%、60%、65%、70%、75%、80%或85%氫氣。在一些實施例中，電漿包括以莫耳計小於或等於約90%、85%、80%、75%或70%氫氣。
在一些實施例中，可在每次連續暴露於金屬前驅物及反應物之後進行電漿處理。在一些實施例中，在已經形成預定厚度之金屬氮化物膜之後進行電漿處理。例如，在每次形成4-5Å TaN之後可進行電漿處理。
第一阻障層51之沉積可在任何適當溫度下進行。在一些實施例中，沉積溫度在約100℃至約500℃之範圍中，或在約200℃至約400℃之範圍中，或在約300℃至約350℃之範圍中。
在暴露於金屬前驅物、反應物及可選電漿之每個循環之後，方法到達判定點120。若第一阻障層51已經形成至預定厚度，則方法從第一阻障層110沉積繼續前進。若第一阻障層51尚未到達預定厚度，則重複第一阻障層110沉積。
在通過判定點120之後，在第一阻障膜51上形成可選鋁膜52，如第1C圖示出。鋁膜52可藉由熟習此項技術者已知之任何適當製程而形成。在一些實施例中，鋁膜52選擇性地形成於第一阻障層51上。在與第一阻障層51形成約相同之溫度下藉由將基板暴露於鋁前驅物，而形成一些實施例之鋁層。一些實施例之鋁前驅物包括參(第三丁基)鋁、由參(第三丁基)鋁基本上組成或由參(第三丁基)鋁組成。在一些實施例中，鋁間層藉由適當鋁前驅物之熱分解而形成。
在一些實施例中，將鋁膜52沉積至一厚度以便鋁膜52為不連續的。換言之，鋁膜52可為間斷的。如以此方式使用，術語「不為連續的」或「間斷的」意味鋁膜52具有暴露之第一阻障層51之區域，以便小於或等於約90%、80%、70%、60%、50%、40%、30%、20%或10%之第一阻障層的表面積具有形成於其上之鋁膜。在一些實施例中，鋁膜具有以原子計小於或等於約5%、4%、3%或2%之碳含量。
在形成鋁膜52之後，方法100移動至第二阻障層140形成製程。如第1D圖示出，在與第一阻障層51及鋁膜52約相同溫度下，第二阻障層形成於第一阻障層51及鋁膜52上。可藉由與第一阻障層51相同之製程、或藉由不同製程，而進行第二阻障層之形成。在一些實施例中，藉由將基板暴露於結構(I)之鉭前驅物，而形成第一阻障層及第二阻障層。
在一些實施例中，相對於第一材料30，第一阻障層51選擇性地形成於第二材料40上。第3圖圖示阻障層50選擇性地形成於第二材料40上之實施例。
第4圖圖示具有鋁間層52之阻障層50。所示之阻障層50包括第一阻障層51、鋁膜52及第二阻障層53。第一阻障層51形成至厚度T1 及第二阻障層53形成至厚度T2 。在一些實施例中，第一厚度T1 大於或等於第二厚度T2 。在一些實施例中，第一厚度在約5Å至約15Å之範圍中，在約6Å至約14Å之範圍中，或在約7Å至約13Å之範圍中，或在約8Å至約12Å之範圍中，或在約9Å至約11Å之範圍中，或在約9Å至約10Å之範圍中。在一些實施例中，第二厚度T2 在約2Å至約10Å之範圍中，或在約3Å至約8Å之範圍中，或在約4Å至約5Å之範圍中。在一些實施例中，第一厚度T1 與第二厚度T2 之比率在約1:1至約10:1之範圍中，或在約2:1至約7:1之範圍中。在一些實施例中，阻障層50（包括鋁膜52）之總厚度在約10Å至約30Å之範圍中，或在約12Å至約25Å之範圍中，或在約15Å至約20Å之範圍中。在一些實施例中，阻障層50具有約20Å之厚度，其由約10Å之第一阻障層51、約10Å之鋁間層及第二阻障層53組成。因為鋁間層為間斷的，由此層貢獻之厚度不應視為將填充第二阻障層之膜中的縫隙。在一些實施例中，阻障層具有約15Å之厚度，其由約9-10Å之第一阻障層、鋁間層、約5-6Å之第二阻障層組成。
在一些實施例中，阻障層50包括具有鋁含量之氮化鉭。在一些實施例中，鋁含量以原子計在約0.5%至約10%之範圍中，或在約1%至約5%之範圍中，或在約1%至約3%之範圍中。
在一些實施例中，方法包括將基板表面暴露於鉭前驅物及反應物以形成具有第一厚度之第一氮化鉭膜的步驟。隨後將第一氮化鉭膜暴露於鋁前驅物以在第一氮化鉭膜上形成鋁膜。隨後將基板表面暴露於鉭前驅物及反應物以形成具有第二厚度之第二氮化鉭膜以形成具有鋁間層之阻障層，該鋁間層具有阻障層厚度。
回頭參看第1E圖及第2圖，在形成阻障層50之後，方法100選擇性地進行至金屬沉積製程160。在一些實施例中，第二材料40為導電材料，及金屬層60（例如，鈷）沉積於第二材料40上。
製備TaN阻障層之樣品並比較通孔電阻(約32 nm)。藉由習用物理氣相沉積製程將比較實例沉積至約40Å之厚度。此比較樣品具有8.09歐姆之通孔電阻。在約325℃之溫度下，將TaN膜沉積至約20Å之厚度，其中鉭前驅物具有η鍵配位體（9.15歐姆）或五(二甲基胺基)鉭(PDMAT)（pentakis(dimethylamino)tantalum; 37.16歐姆）。
儘管已經參考特定實施例描述了本文揭示內容，但應理解，此等實施例僅為說明本揭示案之原理及應用。對於熟習此項技術者而言顯而易見地為，在不脫離本揭示案之精神及範疇的情況下，可對本揭示案之方法及設備進行各種修改及變化。因此，本揭示案意欲覆蓋此種修改及變化，只要它們落入所附申請專利範圍及其等同物之範圍內。
10‧‧‧電子元件 20‧‧‧基板 30‧‧‧第一材料 31‧‧‧第一表面 40‧‧‧第二材料 41‧‧‧第二表面 50‧‧‧阻障層 51‧‧‧第一阻障層 52‧‧‧鋁膜 53‧‧‧第二阻障層 60‧‧‧金屬層 100‧‧‧方法 105‧‧‧步驟 110‧‧‧第一阻障層 112‧‧‧金屬前驅物 114‧‧‧反應物 116‧‧‧電漿處理 120‧‧‧判定點 130‧‧‧鋁膜 140‧‧‧第二阻障層 142‧‧‧金屬前驅物 144‧‧‧反應物 146‧‧‧電漿處理 150‧‧‧判定點 160‧‧‧金屬沉積製程
因此，為了能夠詳細理解本揭示案之上述特徵結構所用方式，上文所簡要概述的本揭示案之更具體的描述可以參考各個實施例進行，該等實施例中的一些示出於附圖中。然而，應注意，附圖僅示出本揭示案之典型實施例並因此不應視為對本揭示案範圍的限制，因為本揭示案可承認其他同等有效的實施例。
第1A圖至第1E圖示出根據本揭示案之一或多個實施例形成之電子元件的示意表示；
第2圖圖示根據本揭示案之一或多個實施例的形成電子元件的方法；
第3圖圖示根據本揭示案之一或多個實施例形成的電子元件的示意表示；以及
第4圖圖示根據本揭示案之一或多個實施例的具有鋁間層之阻障層。
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無
10‧‧‧電子元件
20‧‧‧基板
30‧‧‧第一材料
40‧‧‧第二材料
50‧‧‧阻障層
52‧‧‧鋁膜
60‧‧‧金屬層

Claims (20)

  1. 一種形成一阻障層之方法，該方法包括以下步驟： 將一基板表面暴露於一鉭前驅物及一反應物以形成具有一第一厚度之一第一氮化鉭膜； 將該氮化鉭膜暴露於一鋁前驅物以在該第一氮化鉭膜上形成一鋁膜；以及 將該基板表面暴露於該鉭前驅物及該反應物以形成具有一第二厚度之一第二氮化鉭膜以形成具有一鋁間層之一阻障層，該阻障層具有一阻障層厚度。
  2. 如請求項1所述之方法，其中該鉭前驅物包括具有通式M(NR2 )3 L之一化合物，其中M包括鉭，每個R獨立地從由H及C1-C5烷基組成之群組中選出，且L為具有至少三個碳原子及與M η鍵合的雙鍵或三鍵之一有機配位體。
  3. 如請求項2所述之方法，其中L具有低於-NR2 基團之每一者的一鍵能。
  4. 如請求項1所述之方法，其中該反應物包括氨氣。
  5. 如請求項4所述之方法，其中該反應物不為一電漿。
  6. 如請求項1所述之方法，該第一厚度在約7Å至約11Å之範圍中。
  7. 如請求項6所述之方法，其中該第二厚度在約3Å至約6Å之範圍中。
  8. 如請求項1所述之方法，其中該阻障層厚度在約10Å至約30Å之範圍中。
  9. 如請求項8所述之方法，其中該阻障層具有以原子計約1%至約3%之範圍中的一鋁含量。
  10. 如請求項8所述之方法，其中該鋁膜不為連續的。
  11. 如請求項8所述之方法，其中該鋁膜具有以原子計小於或等於約5%之一碳含量。
  12. 如請求項1所述之方法，其中形成該第一氮化鉭膜及該第二氮化鉭膜之步驟包括以下步驟：將該基板順序暴露於該鉭前驅物及該反應物以形成具有在約3.5Å至約6Å之範圍中的一厚度的一膜，及隨後以包括一惰性氣體及氫氣(H2 )之一電漿處理該膜，該電漿具有在約10%至約90%之範圍中的一氫含量。
  13. 如請求項12所述之方法，其中該惰性氣體包括氬氣，其中Ar:H2 比率在約1:1至約1:10之範圍中。
  14. 如請求項2所述之方法，其中該基板表面包括一金屬表面及一介電質表面，且該阻障層選擇性地形成於該介電質表面上。
  15. 如請求項14所述之方法，其中該配位體L鍵接至該金屬表面，從而阻止沉積於金屬表面上。
  16. 一種處理方法，包括以下步驟： 提供具有一金屬表面及一介電質表面之一基板； 在一溫度下，藉由將該基板暴露於一鉭前驅物及一反應物以形成一未處理之TaN層，且將該未處理之TaN層暴露於一電漿以生成一第一TaN層，而選擇性地形成一第一厚度之一第一TaN層； 在與該第一TaN層約相同之溫度下藉由將該基板暴露於一鋁前驅物，在該第一TaN層上形成一鋁膜；以及 在該溫度下，藉由將該基板暴露於該鉭前驅物及該反應物以形成一未處理TaN層，且將該未處理之TaN層暴露於一電漿以生成該第二TaN層，而選擇性地形成一第二厚度之一第二TaN層，該第一TaN層、該鋁膜及該第二TaN層形成具有一鋁間層之一阻障層，該阻障層具有一阻障層厚度。
  17. 如請求項16所述之方法，其中該鉭前驅物包括具有通式M(NR2 )3 L之一化合物，其中M包括鉭，每個R獨立地從由H及C1-C5烷基組成之群組中選出，且L為具有至少三個碳原子及與M η鍵合之一雙鍵或三鍵之一有機配位體，且L具有低於-NR2 基團之每一者的鍵能，該反應物包括氨氣，及形成該TaN層之步驟以一熱原子層沉積製程進行。
  18. 如請求項16所述之方法，其中該第一厚度在約7Å至約11Å之範圍中，該第二厚度在約3Å至約6Å之範圍中，該阻障層具有以原子計在約1%至約3%範圍中之一鋁含量。
  19. 如請求項16所述之方法，其中該鋁膜不為連續的且具有以原子計小於或等於約5%之一碳含量。
  20. 一種半導體元件，包括： 一基板，具有一第一金屬層及一介電層；以及 一阻障層，包括具有形成於該介電層上之一鋁間層之TaN，該鋁間層為不連續的且該阻障層包括約1至約3原子%Al。
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