TW202002307A - 具有超接面及肖特基二極體的功率裝置 - Google Patents

具有超接面及肖特基二極體的功率裝置 Download PDF

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TW202002307A
TW202002307A TW108117801A TW108117801A TW202002307A TW 202002307 A TW202002307 A TW 202002307A TW 108117801 A TW108117801 A TW 108117801A TW 108117801 A TW108117801 A TW 108117801A TW 202002307 A TW202002307 A TW 202002307A
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trench
layer
electrode
pillar
well
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TW108117801A
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李元華
蓋瑞 Ｈ 羅卻特
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美商半導體組件工業公司
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Abstract

一種功率半導體裝置包括具有一第一導電性類型的一半導體層。一渠溝界定在該半導體層內，該渠溝具有一開口、一側壁、及一基部。一柱經提供在該渠溝下方，且該柱具有不同於該第一導電性類型的一第二導電性類型。一金屬層經提供在該渠溝之該側壁上方，該金屬層在該渠溝之該側壁處接觸該半導體層，以形成一肖特基二極體之一肖特基界面。一第一電極經提供在該半導體層之一第一側上方。一第二電極經提供在該半導體層之一第二側上方。

Description

具有超接面及肖特基二極體的功率裝置
本揭露係關於一種功率半導體裝置，特別係關於一種具有超接面(super junction)結構及肖特基二極體的功率裝置。
功率半導體裝置係用在許多不同的產業中。一些此等產業，諸如通訊、計算及充電系統，正在迅速發展。此等產業將得益於經改良的半導體裝置特性，包括可靠性、切換速度、及小型化(miniaturization)。
最近對於改良功率半導體裝置特性的努力包括建立與電晶體區分開的一肖特基障壁區(Schottky barrier region)。分開的肖特基障壁區減少漏電流並改良反向恢復(reverse recovery)特性。然而，功率半導體裝置之結構仍有改良的空間，以便透過較低的順向電壓(VF )、更快的反向恢復性能、及新興技術之更好的可靠性來滿足更高的系統效率之需求。
本申請案之實施例係關於一種功率半導體裝置，該功率半導體裝置具有一超接面及一肖特基二極體，其中該肖特基二極體經整合至該功率裝置之單位晶格。相較於習知功率裝置，該裝置具有較低的順向電壓(VF )及減少之反向恢復時間。
在一實施例中，一種功率半導體裝置包括具有一第一導電性類型的一半導體層。一渠溝界定在該半導體層內，該渠溝具有一開口、一側壁、及一基部。一柱經提供在該渠溝下方，且該柱具有不同於該第一導電性類型的一第二導電性類型。一金屬層經提供在該渠溝之該側壁上方，該金屬層在該渠溝之該側壁處接觸該半導體層，以形成一肖特基二極體之一肖特基界面。一第一電極經提供在該半導體層之一第一側上方。一第二電極經提供在該半導體層之一第二側上方。
在上述裝置之一實施例中，該功率半導體裝置進一步包括經提供在該半導體層上方的一閘極電極、具有該第二導電性類型且經提供在該柱上方並與該柱間隔開的一井、及界定介於該井與該柱之間的一距離的一間隙，該間隙對應於該肖特基界面。該第一電極經提供在鄰近該閘極處，該閘極延伸至該渠溝中並電耦接至該金屬層，且該第二電極經提供在該柱下方。該半導體層提供介於該第一電極與該第二電極之間的一垂直電流路徑，且該第一導電性係一N型導電性且該第二導電性係一P型導電性。
在上述裝置之一實施例中，該功率半導體裝置進一步包括一增強區，該增強區在該半導體層內且介於該井與該柱之間。該增強區具有該第一導電性類型及大於該半導體層之摻雜濃度的一摻雜濃度。
在上述裝置之一實施例中，該渠溝延伸至該柱之一上部部分中，使得該渠溝之該基部經提供在該柱之內部。該功率半導體裝置進一步包括一歐姆接觸區(Ohmic contact region)，該歐姆接觸區經提供在該渠溝之該基部下方且在該柱內。
在上述裝置之一實施例中，該功率半導體裝置進一步包括具有該第二導電性類型且經提供在該柱上方並與該柱間隔開的一井以及界定介於該井與該柱之間的一距離的一間隙，該間隙對應於該肖特基界面。
在一實施例中，一種功率半導體裝置包括一基材，該基材具有一上側及一下側。一第一電極經設置於該基材之該上側上方。一第二電極經設置於該基材之該下側下方。一磊晶層經形成於該基材上方且介於該第一電極及該第二電極之間，該磊晶層具有一柱及一井，該柱及該井界定一間隙。一渠溝經設置於該柱上方且具有一側壁及一基部，該渠溝之該基部係凹入該柱中。一金屬接觸層經設置於該渠溝之該基部及該側壁上方，該金屬接觸層在由該井及該柱所界定的該間隙處接觸該磊晶層，從而在該間隙處界定一肖特基界面。
在上述裝置之一實施例中，該功率半導體裝置進一步包括一增強區，該增強區經提供在該井與該柱之間且鄰近於該肖特基界面。該功率半導體裝置進一步包括一歐姆接觸區，該歐姆接觸區經提供在該渠溝下方，使得該金屬接觸層與該歐姆接觸區形成一歐姆接觸。
在一實施例中，一種形成一功率半導體裝置之方法包括在一基材上提供一磊晶層；在該磊晶層之一上部部分處形成一井；在該井下方形成一柱且使該柱與該井間隔開，以界定一肖特基接觸區；將一渠溝蝕刻入該磊晶層中，該渠溝具有一側壁及一基部，該渠溝之該側壁之一部分對應於該肖特基接觸區；在該渠溝之該側壁及該基部上方形成一金屬接觸層，該金屬接觸層在該肖特基接觸區處與該磊晶層形成一肖特基界面；及形成一閘極電極及第一電極及第二電極。
在上述方法之一實施例中，該方法進一步包括在該渠溝上方形成一絕緣層，該絕緣層覆蓋該渠溝之該側壁及該基部；蝕刻該絕緣層以移除該絕緣層覆於該渠溝之該基部的一部分，但留下該絕緣層覆於該渠溝之該側壁的一部分，從而暴露該柱之一部分；及將離子植入至該柱之該暴露部分中，以形成一歐姆接觸區。該金屬接觸層與該歐姆接觸區作出歐姆接觸，且該絕緣在該渠溝之該側壁上剩餘的該部分用於保護該渠溝之該側壁免於在該植入步驟期間之散射離子。
在上述方法之一實施例中，該方法進一步包括在該井與該柱之間以及鄰近該渠溝之該側壁處形成一增強區。
[相關申請案的交叉參照]
本揭露主張於2018年6月15日提出申請之美國非臨時專利申請案第16/009,484號之優先權，其係針對所有目的以引用方式併入本文中。
本申請案之實施例係關於一種具有超接面結構及肖特基二極體的功率半導體裝置。肖特基二極體經整合至該功率裝置之單位晶格，使得肖特基二極體不佔用任何較該功率裝置之單位晶格更多的區域。肖特基二極體在超接面柱(super junction pillar)與功率裝置之源極/射極之間亦提供良好的電流路徑，以在高電流崩潰下最小化動態切換問題及毀滅性故障。肖特基二極體亦可具有適當的屏蔽（例如，相鄰於肖特基接觸區（或肖特基界面）的高摻雜區），以減少逆向偏壓下的電流溢漏。在一實施例中，功率裝置經組態以具有低磊晶電阻率及處理高崩潰電壓，例如，大於300伏特、或大於500伏特、或大於700伏特。
下文連同隨附圖式提供實施例之詳細描述。本揭露之範疇僅受限於申請專利範圍，並涵蓋數個替代物、修改物、及等效物。儘管以給定順序呈現各種程序之步驟，實施例不必然限於以所列順序執行。在一些實施例中，某些操作可同時執行、以所描述的順序以外的順序執行、或根本不執行。
數個特定細節於下列說明中提出。此等細節經提供以促進對本揭露之範疇的徹底理解，且無須此等特定細節之一些即可根據申請專利範圍來實行實施例。因此，本揭露之特定實施例係例示性的，且並非意圖為具排他性或限制性。為了清楚的目的，與本揭露有關之在本技術領域中所知的技術材料未經詳細描述，使得本揭露不以不必要之方式而模糊。
圖1繪示根據本揭露之一實施例之功率半導體裝置100。在本實施例中，功率裝置100係具有超接面結構（或柱）之功率金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor, MOSFET)裝置。在其他實施例中，功率裝置100可係其他功率裝置，諸如絕緣閘雙極電晶體(insulated gate bipolar transistor, IGBT)裝置。若功率裝置100係一IGBT，則其將具有額外的P+基材或層，如所屬技術領域中具有通常知識者應所理解。
功率裝置100包括半導體基材102，例如矽基材。磊晶層104（或磊晶層）經提供在基材102之第一側上，且第一電極106經提供在基材102之第二側上或上方。在一實施例中，磊晶層104具有N型導電性。第二電極108經提供在磊晶層104上方。複數個閘極結構110經提供在磊晶層104上方，且鄰近於第二電極108。當閘極結構110經導通時，磊晶層104提供用於第一電極106與第二電極108的電流路徑。在本實施例中，功率裝置100係功率MOSFET，且第一電極106及第二電極108分別係汲極電極及源極電極。在另一實施例中，該功率裝置係一IGBT，且第一電極106及第二電極108可分別係集極電極及射極電極。
閘極結構110之各者包括閘極電極112、閘極氧化物114、及閘極間隔物116。複數個井118經提供在磊晶層中，介於閘極結構110之間。井118之深度可取決於功率裝置100之特性。在一實施例中，井之深度介於約1微米至約2微米之間的範圍，或至多可達5微米。在一實施例中，井118具有P導電性，且形成具有磊晶層104的本體二極體。P井118之摻雜濃度係約介於1.2 × 1016 原子/cm3 與8.0 × 1017 原子/cm3 之間。複數個N+區120經提供在P井118內，且鄰近於閘極電極112。在一實施例中，N+區120係源極區。
複數個柱122（或超接面結構）經設置於磊晶層104中。各柱與P井118間隔開，取決於實施方案而界定1微米至5微米、或自2微米至3微米的間隙123。此垂直之間隙123界定肖特基二極體區，且取決於實施方案其大小可變化。在一實施例中，柱122具有P型導電性，且具有約1016 原子/cm3 的摻雜濃度。在一實施例中，柱122具有至少20微米或至少25微米之垂直尺寸。在另一實施例中，柱122取決於實施方案可具有約30微米至約60微米之垂直尺寸。例如，在一實施方案中，對於600 V至650 V的裝置，該等柱具有約45微米至50微米的垂直尺寸。
在一實施例中，複數個N+增強區124經提供在由P井及該等柱所界定的間隙123中。N+增強區124經提供以減少本體二極體之順向電壓降並減少逆向偏壓下的電流溢漏。在一實施例中，N+增強區124係以交替的方式提供，如圖1B所示，其顯示N+增強區124及P井118之俯視圖。在另一實施例中，間隙123可僅存在於有對應的N+增強區124處而在其他處不存在，如圖1C所示。在此實施例中，P井118及P柱122在沒有N+增強區124的區域中重疊。在又另一實施例中，未提供N+增強區124。
複數個渠溝126從磊晶層104之上表面延伸並進入至P柱122之上部部分中。渠溝126延伸通過N+源極區120且部分地進入至P井118中，使得渠溝之基部或底部留駐在P柱122中。在一實施例中，渠溝126延伸至P柱中約1微米至約8微米。
複數個歐姆接觸區128經提供在渠溝126之基部下方。在一實施例中，歐姆接觸區128係藉由將額外的P型雜質（例如，硼）提供至P柱122之上部部分而形成。在一實施例中，歐姆接觸區128具有較P柱122之摻雜濃度顯著更高的摻雜濃度。例如，P柱具有約1016 原子/cm3 的摻雜濃度，且歐姆接觸區128具有約1019 原子/cm3 的摻雜濃度，其係P柱122之摻雜濃度量值的3倍。
肖特基接觸層130經設置在渠溝126之表面上方。肖特基接觸層130包括上部部分130a、側部分130b、及底部部分（或基部）130c。肖特基接觸層130之上部部分130a延伸超過渠溝及閘極結構110之毗連側。肖特基接觸層130之側部分130b接觸由P井118及P柱122所界定的間隙123，從而界定肖特基接觸（肖特基界面）。此等肖特基接觸界定一肖特基二極體，其中陽極經連接至（或對應於）源極電極108，且陰極經連接至（或對應於）汲極電極106。肖特基二極體減少功率裝置100之順向電壓(VF )及反向恢復時間。由於肖特基接觸係形成於P井118與P柱122之間，因此肖特基二極體經整合至功率裝置100之單位晶格。因此，肖特基二極體所佔用的區域不比功率裝置100之單位晶格更多。
此外，肖特基接觸層130之底部部分130c與歐姆接觸區128作出歐姆接觸。歐姆接觸導致柱122與第二電極108（例如，源極電極）之間良好的電流路徑，其在高電流崩潰的情況下降低動態切換問題及毀滅性故障的可能性。
形成肖特基二極體的肖特基接觸層130可包括金屬材料，諸如鉬(Mo)、鉑(Pt)、釩(V)、鈦(Ti)、鈀(Pd)、等。在另一實施例中，肖特基接觸層130係矽化物材料，諸如矽化鉑或矽化鈀。
如上所解釋，具有肖特基二極體的功率裝置100具有某些優點。圖2繪示流過兩功率裝置之隨源極-汲極電壓VSD 而變動的電流波形：「SJ MOS」代表習知超接面MOSFET裝置(super junction MOSFET device)，且「具有肖特基二極體的超接面」代表功率裝置100。在實驗中，已發現具有肖特基二極體的超接面（或功率裝置100）之源極-汲極電壓VSD 低於習知超接面MOSFET之源極-汲極電壓，尤其是在低於15 A的電流位準處。例如，當習知超接面MOSFET於1 A處具有0.68V之源極-汲極電壓VSD 時，功率裝置100之源極-汲極電壓VSD 於1 A處係0.46V，其較習知超接面MOSFET之源極-汲極電壓低約30%。據信，由於肖特基二極體具有較PN二極體低的順向電壓，因此肖特基二極體降低功率裝置100之源極-汲極電壓VSD 。
類似地，當習知超接面MOSFET於5 A處具有0.74V之源極-汲極電壓VSD 時，具有垂直肖特基二極體的超接面MOSFET（或功率裝置100）於5A處係0.66V，其較習知超接面MOSFET之源極-汲極電壓低約11%。由於在功率裝置100中的肖特基二極體具有較建置於習知超接面MOSFET中的PN接面二極體低的順向電壓降，因此功率裝置100具有較習知MOSFET低的源極-汲極電壓VSD （例如，0.2V ~ 0.5V比上0.7 V）。因此，具有肖特基二極體的功率裝置100具有較習知超接面MOSFET小的本體二極體傳導損耗，從而增加包括反相器及DC-DC功率轉換的應用中的功率效率。
圖3繪示習知超接面MOSFET裝置中的PN接面二極體及超接面MOSFET裝置（例如，功率裝置100）中的垂直肖特基二極體之本體二極體反向恢復電流的波形。垂直肖特基二極體之反向恢復電流顯著小於習知超接面MOSFET裝置中的PN接面二極體之反向恢復電流。例如，當只有肖特基二極體導通時，功率裝置100之垂直肖特基二極體之反向恢復電流可於汲極電流值小於6 A時低至零。由於反向恢復電流在具有電感負載的橋接電路中會引起MOSFET開關中的額外損失，因此當具有垂直肖特基二極體的功率裝置100係使用在此橋接電路中時，功率裝置100的導通損耗將小於習知超接面MOSFET開關的導通損耗。另外，橋接電路中的閘極-源極電壓振盪可經降低並預防MOSFET故障。
圖4A至圖4S繪示根據本揭露之實施例之形成半導體功率裝置200的方法之態樣。
在圖4A中，半導體層204係形成在半導體基材202上方。層204可由磊晶生長程序形成。在一實施例中，基材202係矽，且各磊晶生長步驟形成具有約2.5微米至3.2微米的磊晶層。在其他實施例中，基材202可係其他半導體材料，諸如第IV族半導體基材、第III至V族化合物半導體基材、或第II至VI族氧化物半導體基材。例如，第IV族半導體基材可包括矽基材、鍺基材、或矽鍺基材。
基材202可包括磊晶層。在一實施例中，基材202可係N+摻雜層，其中功率裝置係MOSFET。在一實施例中，基材202可係P+摻雜層，其中功率裝置係IGBT。將N型雜質植入層204（圖4B），以將層204轉換為N型導電性。可執行退火以促進雜質之擴散。在一實施例中，層204可與N型雜質一起形成，使得植入步驟可跳過。
半導體層206係形成在層204上（圖4C）。將N型雜質植入層206，產生具有兩個N層的結構。接下來，在層206上形成圖案化之光阻劑207（圖4D），暴露層206之選定部分。將P型雜質（或離子）選擇性地植入層206之暴露部分。層206之此等暴露部分將用於形成柱（參見圖1A中的元件符號122）。P型雜質具有足夠的濃度，以將暴露部分轉變成複數個P區208。移除光阻劑207（圖4E）。重複上述步驟（例如，13至20次），以獲得具有複數個柱208'的層206'（圖4F）。層206'包括多個磊晶層。在一實施例中，柱208'從頂部至基部的總深度（或垂直尺寸）係大於20微米，例如，在約30微米至60微米的範圍內。退火程序可在將離子植入至各磊晶層上之後執行，以促進摻雜物擴散。
接下來，半導體層210形成在整個結構上方且摻雜有N雜質（圖4G）。層210根據實施方案可係單一磊晶層或多個磊晶層。層210係形成為具有2微米至4微米的深度。層210具有足夠的深度，以形成一間隙，隨後肖特基接觸將形成於該間隙上。層210摻雜有N型雜質。經圖案化之光阻劑212經形成以暴露層210之部分。
在一實施例中，於層210之選定部分處執行額外的N摻雜以提供更高的N型濃度，從而形成複數個N+增強區214（圖4H）。N+增強區214對應於圖1中的N+增強區124。N+增強區214中的摻雜濃度可係例如約1.2 × 1016 至5 × 1017 。N+增強區214經形成以減少在其他原因下的逆向偏壓之電流溢漏。在P柱208'與隨後形成的P井之間不存在著間隙且沒有N+增強區214的情況中（圖1C），可藉由額外之光罩及植入的步驟達成P柱208'及隨後形成的P井之重疊，在該步驟中橋接植入區係僅形成於N+增強區214外的區域。替代地，橋接植入區可於N+增強區214存在處形成，並允許N+增強區214反摻雜P柱208'，以形成用於肖特基二極體之所欲的間隙。根據實施方案，可形成或不形成N+增強區214。
圖4I根據一實施例顯示顯示N+增強區214及柱208'的俯視圖。N+增強區214之圖案可描述為於柱208'上方之棋盤圖案。換句話說，裝置之各鄰接的柱208'可具有沿其長度的N+增強區214及N本體摻雜區之交替圖案，而N+增強區214之圖案係於各相鄰的柱208'間偏移。N+增強區214及N本體摻雜區之寬度可係相同的或類似的，使得N+增強區214及N本體摻雜區係在柱208'上方以交替的矩陣、或棋盤圖案而設置。雖然圖4I中的N+增強區214之形狀係矩形，但實施例並不限於此特定形狀。例如，N+增強區214之形狀可係圓形、六邊形、或其他形狀。
在一實施例中，設置在相鄰的柱208'上方的N+增強區214在相關於閘極軸方向或圖式（參見圖4I）之頂部至底部方向上彼此不重疊。在其他實施例中，相鄰的柱208'之N+增強區214在相關於閘極軸方向上彼此重疊。在又另一實施例中，一或多個N+增強區214可延伸於整個P柱210之上。
參照圖4J，藉由使用上述步驟執行一或多個磊晶生長步驟來在N+增強區214上方形成另一個層216。層216取決於實施方案具有約1微米至3微米的深度，或具有足夠的厚度以隨後在其中形成P井。閘極氧化物層218係形成於層216上方。閘極電極層220係形成於閘極氧化物層218上方。在一實施例中，閘極電極層係N摻雜多晶矽，但根據實施方案可係其他導電材料。
使用技術領域中所熟知的微影蝕刻方法來蝕刻閘極電極層220，以形成複數個閘極電極220'（圖4K）。雖然圖4K在相鄰的閘極電極220'之間的空間顯示完整的閘極氧化物層218，一些實施例可包括將提供在閘極電極220'之間的閘極氧化物材料移除。使用閘極電極220'作為遮罩將P型摻雜物植入層216中，以形成複數個P井222。可執行退火以促進摻雜物之擴散。P井222經形成為與柱208'間隔開，從而提供間隙223。亦即，在一實施例中，P井222之底部及柱208'之頂部界定間隙223，以具有至少1微米的垂直尺寸。在另一實施例中，間隙223係2微米至4微米、或2微米至3微米。間隙之尺寸界定用於肖特基二極體之肖特基接觸（或肖特基界面），因此其尺寸可根據實施方案而變化。
使用閘極電極220'作為遮罩，將N型雜質選擇性地植入P井222之頂部（圖4L）。替代地，可使用光阻劑遮罩來圖案化植入物。控制N摻雜以產生複數個N+區224。在一實施例中，N+區係源極區。
參照圖4M，閘極介電質層（未圖示）係形成於閘極電極220'及N+源極區224上方。可藉由沉積一或多個介電質層於裝置之上表面的上方來形成閘極介電質層。介電質層可包括氮化物層、氧化物層、或其他介電質材料。在一實施例中，介電質層係氮化物層。介電質層經選擇性地蝕刻以移除設置在閘極電極220'之間的介電質材料之部分，從而產生複數個閘極間隔物226。閘極間隔物226界定複數個閘極結構228。閘極結構228包括閘極氧化物218'、閘極電極220'、及閘極間隔物226。
複數個渠溝230形成於柱208'上方並延伸通過P井222（圖4N）。該等渠溝係使用已知的微影蝕刻及各向異性蝕刻程序來形成。在一實施例中，渠溝230延伸至柱208'中達1微米至8微米。
氧化物層232形成於渠溝230上方（圖4O）。氧化物層232可使用沉積程序或熱氧化程序來形成，且可具有50埃至600埃的厚度。在一實施例中，氧化物層232全面形成於整個結構上，包括閘極結構228上方。氮化物層234係形成於氧化物層232上方。在一實施例中，氮化物層234具有1000埃至2500埃的厚度。
執行各向異性蝕刻以暴露柱208'（圖4P）。該蝕刻水平地移除氮化物層234及氧化物層232之暴露部分，包括氮化物層234及氧化物層232之設置於渠溝230之底部表面上方的底部部分。然而，氮化物層234及氧化物層232仍留在渠溝230及閘極結構228的側壁上。在一些實施例中，氧化物層232之薄部分可留在渠溝230之底部表面上。剩餘的氮化物層及氧化物層用作側壁間隔物236，該側壁間隔物236保護該等渠溝之側壁免於隨後的植入步驟，其將於下文解釋。在一實施例中，在各向異性蝕刻之前於閘極結構228上形成光阻遮罩以保護閘極結構。
執行離子植入步驟以在渠溝230之底部處形成歐姆接觸區238（圖4Q），其中柱208'之部分係藉由上述之各向異性蝕刻而暴露。在一實施例中，歐姆接觸區摻雜有至少1019 原子/cm3 之濃度的P型摻雜物。歐姆接觸區238具有較柱208'之本體高的導電性，其具有約1016 原子/cm3 的濃度。
側壁間隔物236保護渠溝230之側壁免於在植入步驟期間可能散射的離子（或摻雜物）。在一實施例中，相對低的植入能量，諸如3 keV至25 keV，可用於植入步驟，使得散射離子不具足夠的能量來穿透間隔物236及經植入渠溝230之側壁中。此外，若需要，可使用較重的植入物種來取代硼，諸如BF2 ，以減小植入物的投射範圍。替代地，可增加間隔物236之厚度，以防止散射離子穿透渠溝230之側壁。或者可調整植入能量及間隔物236之厚度兩者，以防止散射之離子穿透至渠溝230之側壁。若P型摻雜物經植入至渠溝之側壁中，此等摻雜物可稀釋側壁之N型導電性（隨後此處將形成肖特基接觸），其將會降低肖特基二極體之性能。
在離子植入步驟之後，移除在閘極結構228及渠溝230上剩餘的氮化物層234及氧化物層232（圖4R）。在一實施例中，氮化物層234及氧化物層232係使用濕式蝕刻步驟來移除。濕式蝕刻係選定用以溶解在氮化物層下層的氧化物層232。因此，氮化物層從該結構上起離。在此實施例中，使用氮化物層閘形成閘極間隔物226，以保護閘極結構。
肖特基接觸層240形成於渠溝230之暴露表面上方（圖4R）。肖特基接觸層240可藉由遮罩及選擇性形成肖特基金屬材料來形成，諸如鉬(Mo)、鉑(Pt)、釩(V)、鈦(Ti)、鈀(Pd)、等。在一實施例中，肖特基接觸層係藉由形成矽化物材料，諸如鉑或矽化鈀，來形成。肖特基接觸層240亦可係金屬材料及矽化物材料之組合。在一實施例中，肖特基接觸層240係適形地形成於渠溝230之表面上。在一實施例中，雖然未圖示，但可在肖特基材料層之表面上方形成屏蔽金屬材料，諸如氮化鈦。肖特基接觸層240在由P井222及P柱208'所界定的間隙223處作出肖特基接觸，以形成肖特基二極體。肖特基接觸層240之底部部分與歐姆接觸區238作出歐姆接觸。此歐姆接觸促進流過其中的電流。
第一電極242係藉由在基材202上方沉積導電材料，諸如鋁，而形成。在一實施例中，第一電極242係一汲極電極（圖4S）。第二電極244係藉由在閘極結構228上方及渠溝230中沉積導電材料，諸如鋁，而形成。在一實施例中，第二電極係一源極電極。所得之裝置係與圖1中的功率裝置100對應的功率半導體裝置200。根據實施方案，功率裝置200可係功率MOSFET、IGBT、或類似者。
A1. 本揭露之一實施例包括一種功率半導體裝置，其包含： 一半導體層，其具有一第一導電性類型； 一渠溝，其界定在該半導體層內，該渠溝具有一開口、一側壁、及一基部； 一柱，其經提供在該渠溝下方且具有不同於該第一導電性類型的一第二導電性類型； 一金屬層，其經提供在該渠溝之該側壁上方，該金屬層在該渠溝之該側壁處接觸該半導體層，以形成一肖特基二極體之一肖特基界面； 一第一電極，其經提供在該半導體層之一第一側上方；及 一第二電極，其經提供在該半導體層之一第二側上方。
A2. 如A1之裝置，其中該半導體層提供介於該第一電極及該第二電極之間的一垂直電流路徑，且該第一電極作為該肖特基二極體之一陽極且該第二電極作為該肖特基二極體之一陰極，且 其中該半導體層係形成於一基材上方的一磊晶層。
A3. 如A2之裝置，其中該基材包括一磊晶層。
A4. 如A3之裝置，其中該功率裝置係一MOSFET，且該第一電極及該第二電極分別係源極電極及汲極電極，且該柱係具有至少25微米之深度的一超接面柱。
A5. 如A4之裝置，其中該渠溝延伸至該柱之一上部部分中，使得該渠溝之該基部經提供在該柱之內部。
A6. 本揭露之一實施例包括一種功率半導體裝置，其包含： 一基材，其具有一上側及一下側； 一第一電極，其設置於該基材之該上側上方； 一第二電極，其設置於該基材之該下側下方； 一磊晶層，其形成於該基材上方且介於該第一電極及該第二電極之間，該磊晶層具有一柱及一井，該柱及該井界定一間隙； 一渠溝，其設置於該柱上方且具有一側壁及一基部，該渠溝之該基部係凹入該柱中；及 一金屬接觸層，其設置於該渠溝之該基部及該側壁上方，該金屬接觸層在由該柱及該井所界定的該間隙處接觸該磊晶層，從而在該間隙處界定一肖特基界面。
A7. 如A6之裝置，其進一步包含： 一歐姆接觸區，其經提供在該渠溝下方，使得該金屬接觸層與該歐姆接觸區形成一歐姆接觸， 其中一肖特基二極體係由該磊晶層及該金屬接觸層所界定，且 其中該第一電極對應於該肖特基二極體之一陽極，且該第二電極對應於該肖特基二極體之一陰極。
A8. 如A6之裝置，其中該功率半導體裝置係一MOSFET。
A9. 如A6之裝置，其中該功率半導體裝置係一IGBT。
A10. 本揭露之一實施例包括一種形成一功率半導體裝置之方法，該方法包含： 在一基材上提供一磊晶層； 在該磊晶層之一上部部分處形成一井； 在該井下方形成一柱且使該柱與該井間隔開，以界定一肖特基接觸區； 將一渠溝蝕刻入該磊晶層中，該渠溝具有一側壁及一基部，側渠溝之該側壁之一部分對應於該肖特基接觸區； 於該渠溝之該側壁及該基部上方形成一金屬接觸層，該金屬接觸層在該肖特基接觸區處與該磊晶層形成一肖特基界面；及 形成一閘極電極及第一電極及第二電極。
A11. 如A10之方法，其進一步包含： 在該渠溝上方形成一絕緣層，該絕緣層覆蓋該渠溝之該側壁及該基部； 蝕刻該絕緣層以移除該絕緣層覆於該渠溝之該基部的一部分，但留下該絕緣層覆於該渠溝之該側壁的一部分，從而暴露該柱之一部分；及 將離子植入至該柱之該暴露部分中，以形成一歐姆接觸區， 其中該金屬接觸層與該歐姆接觸區作出一歐姆接觸，且該絕緣在該渠溝之該側壁上剩餘的該部分用於保護該渠溝之該側壁免於在該植入步驟期間散射離子。
A12. 如A11之方法，其進一步包含： 在該井與該柱之間以及鄰近該渠溝之該側壁處形成一增強區。
A13. 如A12之方法，其中該功率半導體裝置係一MOSFET，且該柱係一超接面柱。
A14. 如A11之方法，其中該離子係以一能量位準來植入，該能量位準不足以穿透剩餘在該渠溝之該側壁上的該絕緣層。
本揭露之若干態樣已結合經提議為實例之本揭露特定實施例來描述。可製作本文中前述的多項實施例之數個的替代方式、修改和變化，而不致悖離如後述申請專利範圍的範疇。例如，在另一實施例中，P柱可藉由包括下列的程序來形成：形成交替的磊晶半導體層及阻擋層(blocking layers)、將雜質植入至該等阻擋層中、及使雜質從該等阻擋層擴散至該等磊晶半導體層中，如美國專利申請案第15/454,861號所描述，其以引用方式併入本文中。替代地，該等P柱可藉由一種完全不同的方法來形成，諸如蝕刻一深渠溝、將一P型摻雜物併入該渠溝中、及以一些材料（諸如單晶矽）填充該渠溝。再者，併入P型摻雜物的方法可包括在該深渠溝內部生長經摻雜之磊晶矽、有角度的離子植入、電漿離子摻雜、來自固態源的擴散、原子層沉積、或一些其他摻雜技術。類似地，雖然在前述實施例中使用一平面閘極結構，但其他類型之閘極結構仍係可能的。具體而言，可使用渠渠溝閘極結構取代平面閘極結構。因此，本文中所陳述的實施例屬說明意圖為說明性質而非限制性。
100‧‧‧功率半導體裝置/功率裝置 102‧‧‧半導體基材/基材 104‧‧‧磊晶層 106‧‧‧第一電極/汲極電極 108‧‧‧第二電極/源極電極 110‧‧‧閘極結構 112‧‧‧閘極電極 114‧‧‧閘極氧化物 116‧‧‧閘極間隔物 118‧‧‧井/P井 120‧‧‧N+區/N+源極區 122‧‧‧柱/P柱 123‧‧‧間隙 124‧‧‧N+増強區 126‧‧‧渠溝 128‧‧‧歐姆接觸區 130‧‧‧肖特基接觸層 130a‧‧‧上部部分 130b‧‧‧側部分 130c‧‧‧底部部分/基部 200‧‧‧半導體功率裝置/功率裝置 202‧‧‧半導體基材/基材 204‧‧‧半導體層/層 206‧‧‧半導體層/層 206’‧‧‧層 207‧‧‧光阻劑 208‧‧‧P區 208’‧‧‧柱/P柱 210‧‧‧半導體層/層/P柱 212‧‧‧光阻劑 214‧‧‧N+増強區 216‧‧‧層 218‧‧‧閘極氧化物層 218’‧‧‧閘極氧化物 220‧‧‧閘極電極層 220’‧‧‧閘極 222‧‧‧P井 223‧‧‧間隙 224‧‧‧N+區/N+源極區 226‧‧‧閘極間隔物 228‧‧‧閘極結構 230‧‧‧渠溝 232‧‧‧氧化物層 234‧‧‧氮化物層 236‧‧‧側壁間隔物/間隔物 238‧‧‧歐姆接觸區 240‧‧‧肖特基接觸層 242‧‧‧第一電極 244‧‧‧第二電極
圖1A至圖1C繪示根據一實施例之具有超接面結構及肖特基二極體的功率半導體裝置。 圖2繪示根據一實施例之習知功率裝置與功率裝置之間在傳導損耗上的比較。 圖3繪示根據一實施例之習知超接面功率裝置及功率裝置在本體二極體反向恢復電流上的比較。 圖4A至圖4S繪示根據一實施例之形成功率半導體裝置之程序。
100‧‧‧功率半導體裝置/功率裝置
102‧‧‧半導體基材/基材
104‧‧‧磊晶層
106‧‧‧第一電極/汲極電極
108‧‧‧第二電極/源極電極
110‧‧‧閘極結構
112‧‧‧閘極電極
114‧‧‧閘極氧化物
116‧‧‧閘極間隔物
118‧‧‧井/P井
120‧‧‧N+區/N+源極區
122‧‧‧柱/P柱
123‧‧‧間隙
124‧‧‧N+増強區
126‧‧‧渠溝
128‧‧‧歐姆接觸區
130‧‧‧肖特基接觸層
130a‧‧‧上部部分
130b‧‧‧側部分
130c‧‧‧底部部分/基部

Claims (10)

  1. 一種功率半導體裝置，其包含： 一半導體層，其具有一第一導電性類型； 一渠溝，其界定在該半導體層內，該渠溝具有一開口、一側壁、及一基部； 一柱，其經提供在該渠溝下方且具有不同於該第一導電性類型的一第二導電性類型； 一金屬層，其經提供在該渠溝之該側壁上方，該金屬層在該渠溝之該側壁處接觸該半導體層，以形成一肖特基二極體之一肖特基界面； 一第一電極，其經提供在該半導體層之一第一側上方；及 一第二電極，其經提供在該半導體層之一第二側上方。
  2. 如請求項1之功率半導體裝置，其進一步包含： 一閘極電極，其經提供在該半導體層上方； 一井，其具有該第二導電性類型且經提供在該柱上方並與該柱間隔開；及 一間隙，其界定介於該井與該柱之間的一距離，該間隙對應於該肖特基界面， 其中該第一電極經提供在鄰近該閘極處，該閘極延伸至該渠溝中並電耦接至該金屬層，且該第二電極經提供在該柱下方，且 其中該半導體層提供介於該第一電極與該第二電極之間的一垂直電流路徑，並且該第一導電性係一N型導電性且該第二導電性係一P型導電性。
  3. 如請求項2之功率半導體裝置，其進一步包含： 一增強區，其係在該半導體層內且介於該井與該柱之間，該增強區具有該第一導電性類型及大於該半導體層之摻雜濃度的一摻雜濃度。
  4. 如請求項2之功率半導體裝置，其中該渠溝延伸至該柱之一上部部分中，使得該渠溝之該基部經提供在該柱之內部，其中該功率半導體裝置進一步包含： 一歐姆接觸區，其經提供在該渠溝之該基部下方且在該柱內。
  5. 如請求項1之功率半導體裝置，其進一步包含： 一井，其具有該第二導電性類型且經提供在該柱上方並與該柱間隔開；及 一間隙，其界定介於該井與該柱之間的一距離，該間隙對應於該肖特基界面。
  6. 一種功率半導體裝置，其包含： 一基材，其具有一上側及一下側； 一第一電極，其設置於該基材之該上側上方； 一第二電極，其設置於該基材之該下側下方； 一磊晶層，其形成於該基材上方且介於該第一電極與該第二電極之間，該磊晶層具有一柱及一井，該柱及該井界定一間隙； 一渠溝，其設置於該柱上方且具有一側壁及一基部，該渠溝之該基部係凹入該柱中；及 一金屬接觸層，其設置於該渠溝之該基部及該側壁上方，該金屬接觸層在由該柱及該井所界定的該間隙處接觸該磊晶層，從而在該間隙處界定一肖特基界面。
  7. 如請求項6之功率半導體裝置，其進一步包含： 一增強區，其經提供在該井與該柱之間且鄰近於該肖特基界面；及 一歐姆接觸區，其經提供在該渠溝下方，使得該金屬接觸層與該歐姆接觸區形成一歐姆接觸。
  8. 一種形成一功率半導體裝置之方法，該方法包含： 在一基材上提供一磊晶層； 在該磊晶層之一上部部分處形成一井； 在該井下方形成一柱且使該柱與該井間隔開，以界定一肖特基接觸區； 將一渠溝蝕刻入該磊晶層中，該渠溝具有一側壁及一基部，該渠溝之該側壁之一部分對應於該肖特基接觸區； 於該渠溝之該側壁及該基部上方形成一金屬接觸層，該金屬接觸層在該肖特基接觸區處與該磊晶層形成一肖特基界面；及 形成一閘極電極及第一電極及第二電極。
  9. 如請求項8之方法，其進一步包含： 在該渠溝上方形成一絕緣層，該絕緣層覆蓋該渠溝之該側壁及該基部； 蝕刻該絕緣層以移除該絕緣層覆於該渠溝之該基部的一部分，但留下該絕緣層覆於該渠溝之該側壁的一部分，從而暴露該柱之一部分；及 將離子植入至該柱之該暴露部分中，以形成一歐姆接觸區， 其中該金屬接觸層與該歐姆接觸區作出一歐姆接觸，且該絕緣層在該渠溝之該側壁上剩餘的該部分用於保護該渠溝之該側壁免於在該植入步驟期間散射離子。
  10. 如請求項9之方法，其進一步包含： 在該井與該柱之間以及鄰近該渠溝之該側壁處形成一增強區。
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US20200273981A1 (en) 2020-08-27
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CN110610981A (zh) 2019-12-24
US11652166B2 (en) 2023-05-16

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