TW201947772A - 混合半導體電晶體結構與製造方法 - Google Patents

混合半導體電晶體結構與製造方法 Download PDF

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TW201947772A
TW201947772A TW107136779A TW107136779A TW201947772A TW 201947772 A TW201947772 A TW 201947772A TW 107136779 A TW107136779 A TW 107136779A TW 107136779 A TW107136779 A TW 107136779A TW 201947772 A TW201947772 A TW 201947772A
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transistor
taken along
layer
sectional
fin
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TW107136779A
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TWI772540B (zh
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江宏禮
陳奕升
陳自強
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台灣積體電路製造股份有限公司
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    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Abstract

本揭露提供一種混合半導體電晶體結構，其包含：一基板；一第一電晶體，其在該基板上，該第一電晶體之一通道包含一鰭片且具有一第一通道高度；一第二電晶體，其相鄰於該第一電晶體，該第二電晶體之一通道包含一奈米線；及一離距，其橫向隔開該鰭片與該奈米線。該第一通道高度大於該離距。本揭露亦提供一種用於製造該混合半導體電晶體結構之方法。

Description

混合半導體電晶體結構與製造方法
本發明實施例係有關混合半導體電晶體結構與製造方法。
為達成積體電路之電路密度之一增大，已減小此等積體電路內之半導體裝置(諸如場效電晶體)之大小。然而，減小一半導體裝置之大小可導致半導體裝置之一通道之長度之一減小。減小通道長度可導致半導體裝置之一源極區及一汲極區更靠近彼此，此可允許源極及汲極區對通道或甚至對通道內之載子施加不當影響(通常稱為短通道效應)。因此，經受短通道效應之一半導體裝置之一閘極已減少對通道之控制，此尤其抑制閘極控制半導體裝置之接通及/或關斷狀態之能力。
根據本發明的一實施例，一種混合半導體電晶體結構包括：一基板；一第一電晶體，其在該基板上，該第一電晶體之一通道包括一鰭片且具有一第一通道高度；一第二電晶體，其相鄰於該第一電晶體，該第二電晶體之一通道包括一奈米線；及一離距，其橫向隔開該鰭片與該奈米線，其中該第一通道高度大於該離距。
根據本發明的一實施例，一種用於形成一混合半導體電晶體結構之方法包括：提供一基板；在該基板上方磊晶地形成交替堆疊膜；在一第一電晶體區上方之該等交替堆疊膜中形成一溝槽；及圖案化一第二電晶體區上方之該等交替堆疊膜以獲得一交替堆疊鰭片。
根據本發明的一實施例，一種用於形成一混合半導體電晶體結構之方法包括：提供一基板；在該基板上方及一p型電晶體區及一n型電晶體區中磊晶地形成交替堆疊膜；在該p型電晶體區中之該等交替堆疊膜中形成一溝槽；及圖案化該n型電晶體區上方之該等交替堆疊膜以獲得一交替堆疊鰭片。
在下文詳細論述本揭露之實施例之製造及使用。然而，應瞭解，實施例提供可在廣泛多種特定內容背景中體現之許多可應用發明概念。所討論之特定實施例僅繪示製造及使用實施例之特定方式且不限制本揭露之範疇。貫穿各種視圖及闡釋性實施例，相似元件符號用來指定相似元件。現將詳細參考隨附圖式中繪示之例示性實施例。在任何可能之情況下，在圖式及描述中使用相同元件符號以指代相同或相似元件。在圖式中，形狀及厚度可為清楚及方便起見而放大。此描述尤其係關於形成根據本揭露之一設備之部分或與該設備更直接協作之元件。應瞭解，未特定展示或描述之元件可採用各種形式。貫穿本說明書對「一項實施例」或「一實施例」之引用意謂結合實施例描述之一特定構件、結構或特性包含於至少一項實施例中。因此，在貫穿本說明書之各處出現之片語「在一項實施例中」或「在一實施例中」未必皆指代相同實施例。此外，在一或多項實施例中可以任何適合方式組合特定構件、結構或特性。應瞭解，下圖不按比例繪製；實情係，此等圖僅旨在用於圖解。
此外，為便於描述，可在本文中使用諸如「在…下面」、「在…下方」、「下」、「在…上方」、「上」及類似物之空間相對術語來描述一個元件或構件與另一(些)元件或構件之關係，如在圖中繪示。空間相對術語旨在涵蓋除在圖中描繪之定向以外的使用或操作中之裝置之不同定向。設備可以其他方式定向(旋轉90度或按其他定向)且因此可同樣解釋本文中使用之空間相對描述符。
半導體裝置用於各種電子應用中，諸如個人電腦、蜂巢式電話、數位相機及其他電子設備。通常藉由以下步驟製造半導體裝置：在一半導體基板上方循序沉積絕緣或介電層、導電層及半導電材料層；及使用微影術圖案化各種材料層以在其上形成電路組件及元件。通常在一單一半導體晶圓上製造許多積體電路，且藉由沿著一切割道在積體電路之間鋸切而單粒化晶圓上之個別晶粒。
多個閘極場效電晶體(MuGFET)係半導體技術的最近發展，其通常係將一個以上閘極併入至一單一裝置中之金屬氧化物半導體FET (MOSFET)。一種類型之MuGFET稱為一FinFET，其係具有垂直凸起遠離一積體電路之一基板之一鰭狀半導體通道之一電晶體結構。FinFET之最近設計係一環繞式閘極(GAA) FinFET，其具有在所有側上包圍一通道區之一閘極材料。
可藉由任何適合方法圖案化環繞式閘極(GAA)電晶體結構。例如，可使用一或多個光微影製程(包含雙重圖案化或多重圖案化製程)圖案化結構。一般言之，雙重圖案化或多重圖案化製程組合光微影與自對準製程，從而允許產生具有例如小於原本可使用一單一直接光微影製程獲得之間距之圖案。例如，在一項實施例中，在一基板上方形成一犧牲層且使用一光微影製程圖案化該犧牲層。使用一自對準製程與圖案化犧牲層並排形成間隔件。接著移除犧牲層，且接著可使用剩餘間隔件以圖案化GAA結構。
MuGFET之一混合設計包含一第一導電類型之一FET係一FinFET，且一第二導電類型之至少另一FET係一環繞式閘極結構。參考圖1，圖1展示處於一中間製造階段之一種類型之混合設計。一堆疊磊晶區101A與一相鄰堆疊磊晶區101B隔開。歸因於堆疊磊晶區101A及101B之任一者形成於從一基板100凹陷之一溝槽中之事實，所沉積磊晶膜將呈現溝槽之輪廓且顯現為一U形堆疊。例如，在後續操作中，由虛線包圍之區103變成一n-FET且由虛線包圍之區105變成一p-FET。可觀察到，n-FET與p-FET之間的間隔(其稱為一n/p邊界102)由磊晶膜之垂直堆疊或生長於溝槽之側壁上之磊晶膜佔據。圖1中繪示之混合結構面臨由n/p邊界102之存在所引起之面積損失之一問題。例如，圖1之n/p邊界102可為約相同於通道高度CH1之量值，諸如從約50 nm至約80 nm。無法藉由先進對準或微影技術緩和n/p邊界102減小，此係因為其受限於溝槽之幾何形狀。
本揭露提供MuGFET之一新混合設計，其解決由n/p邊界引起之面積損失。參考圖2A，圖2A展示根據本揭露之一些實施例之處於一中間製造階段之一種類型之混合設計。在圖2A中，在形成堆疊磊晶201之前未在基板200中形成凹槽，因此可獲得堆疊磊晶201之一水平輪廓。在堆疊磊晶201中重新生長具有從頂部至底部之實質上相等寬度之一FinFET井207。例如，在後續操作中，由虛線包圍之區203變成一n-FET且由虛線包圍之區205變成一p-FET。n-FET與p-FET之間的間隔或n/p邊界202可減小至光微影限制所指示之一程度。例如，在本實施例中，n/p邊界202可為通道高度CH2之約四分之一至五分之一，諸如從約10 nm至約20 nm。在一些實施例中，重新生長之FinFET井可放置於一混合設計之一n-FET中。
參考圖3，圖3展示根據本揭露之一些實施例之處於一中間製造階段之一種類型之混合設計。在圖3中，在形成堆疊磊晶301之前未在基板300中形成凹槽，因此可獲得堆疊磊晶301之一水平輪廓。在堆疊磊晶301中重新生長具有朝向基板300漸縮之一形狀(即，具有一較寬頂部及一較窄底部)之一FinFET井307。可在FinFET井307及下伏基板300之材料具有不同晶格常數且因此引發失配應力時採用FinFET井307之錐形形狀。FinFET井307之錐形形狀可促進晶格失配介面處之鬆弛且因此獲得一無應變FinFET井307。在後續操作中，由虛線包圍之區303變成一n-FET且由虛線包圍之區305變成一p-FET。n-FET與p-FET之間的間隔或n/p邊界302可減小至光微影限制所指示之一程度。例如，在本實施例中，n/p邊界302可為通道高度CH3之約四分之一至五分之一，諸如從約10 nm至約20 nm。在一些實施例中，重新生長之FinFET井可放置於一混合設計之一n-FET中。
參考圖2B，圖2B係根據本揭露之一些實施例之在一混合半導體電晶體結構20之一閘極區處剖開之一剖面。如圖2B中展示，結構20包含一基板200及至少一第一電晶體200A及一第二電晶體200B。第一電晶體200A具有在從一隔離209突出之一第一鰭片208A之一部分處量測之一第一通道高度H1。第二電晶體200B具有在一第二鰭片208B之一奈米線部分處量測之一第二通道高度H2。可在圖2B中繪示之剖面中觀察到橫向隔開從一隔離209突出之一第一鰭片208A之部分與一第二鰭片208B之奈米線部分之一離距S。在一些實施例中，第一通道高度H1大於離距S之2倍、3倍或4倍。在一些實施例中，第二通道高度H2實質上相同於第一通道高度且大於離距S。在一些實施例中，例如，在5 nm技術節點及以上技術節點下，第一通道高度H1係至少約50 nm至約80 nm，且離距S小於約10 nm至20 nm。
如圖2B中展示，從隔離209突出之第一鰭片208A之部分可由與由隔離209包圍之第一鰭片208A之部分之材料不同之材料組成。類似地，從隔離209突出之第一鰭片208A之部分可由與基板200之材料不同之材料組成。在一些實施例中，取決於裝置之效能要求，基板200及由隔離209包圍之第一鰭片208A由矽組成，而從隔離209突出之第一鰭片208A之部分可由矽鍺或其他III-V族化合物組成。在一些實施例中，從隔離209突出之第一鰭片208A之部分由Six Ge1-x 組成，其中X小於0.6。可由隨後在本揭露之圖10A至圖10D或圖20A至圖20D中描繪之鍺冷凝操作獲得此高鍺含量。
在圖2B中，第二鰭片208B之奈米線部分可由相同於由隔離209包圍之第二鰭片208B之部分之材料或相同於基板200之材料組成。
在一些實施例中，第一電晶體200A係一p-FET，此係因為電洞遷移率未隨著橫向尺寸減小而降級，且p-FET之通道區可保持具有減小鰭片寬度W1之一鰭片形狀。相比之下，第二電晶體200B係具有環繞式閘極通道之一n-FET，此係因為電洞遷移率對橫向尺寸之減小更敏感，且n-FET之通道區由具有大於鰭片寬度W1之一直徑W2之奈米線取代。相較於擁有具有一鰭片寬度W2之一鰭片通道，擁有具有一直徑W2之一奈米線通道大幅減少洩漏電流且緩和短通道效應。在一些實施例中，鰭片寬度W1可小於6 nm且直徑W2可大於或等於6 nm。在一些實施例中，鰭片寬度W1係約4 nm且直徑W2係約6 nm。
參考圖4，圖4展示電子遷移率與矽鰭片寬度之間的一關係。應明白，用於保持電子遷移率之一最佳值係具有約6 nm之一鰭片寬度。如先前論述，可藉由將一鰭片幾何形狀改變為一奈米線幾何形狀而減少洩漏電流，在判定一n-FET之最佳鰭片寬度時減小洩漏電流之權重。
參考圖5，圖5展示電洞遷移率與矽鍺鰭片寬度之間的一關係。在不具有矽罩蓋之條件下(此係指一無應變狀態)，電洞遷移率處於約180 cm2 /V-s之一平均值，在鰭片寬度從8 nm減小至4 nm時稍微減小。在具有矽罩蓋之條件下(此係指一應變狀態)，電洞遷移率處於約300 cm2 /V-s之一平均值，在鰭片寬度從8 nm減小至4 nm時減小。應變狀態更佳地描述FinFET之最終產物，此係因為鰭片上方之鈍化層產生適量應力。考量足夠高電洞遷移率之保持以及減少洩漏電流，p-FET之最佳鰭片寬度處於約4 nm。
應注意，在MuGFET之技術中，當前已知包含III族及V族材料之若干材料系統且其等應涵蓋於本揭露之預期範疇內。例如，在一矽基板上，通常採用用於n-FET之Si奈米線及用於p-FET之SiGe奈米線。在一GaAs基板上，通常採用用於n-FET之GaAs奈米線及用於p-FET 之InGaAs奈米線。在一Ge/GaAs基板上，通常採用用於n-FET之Ge奈米線及用於p-FET之GaAs奈米線。出於簡潔目的，本揭露僅提供Si奈米線及SiGe奈米線材料系統之圖解及以下詳細描述。相同發明概念可應用於所處置之不同半導體材料系統上。
圖6A至圖25D繪示本文中描述之混合半導體結構之中間製造階段中之不同透視圖。
參考圖6A至圖6C，在基板600上方形成一堆疊磊晶1023。在一些實施例中，堆疊磊晶1023包含交替地放置於基板600上方之一或多個矽(Si)層及一或多個矽鍺(SiGe)層。圖6A係一透視圖，圖6B係一Y切割剖面圖，且圖6C係一X切割剖面圖。例如，堆疊磊晶1023包含一第一矽鍺層1023A'、一第一矽層1023A、一第二矽鍺層1023B'、一第二矽層1023B、一第三矽鍺層1023C'、一第三矽層1023C、一第四矽鍺層1023D'及一第四矽層1023D。應瞭解，可形成任何數目個矽層或矽鍺層。
參考圖7A至圖7D，基板600包含一第一電晶體區600A及一第二電晶體區600B。移除第一電晶體區600A內之堆疊磊晶1023，因此在堆疊磊晶1023中形成一溝槽600A'，且曝露下伏基板600。在一些實施例中，溝槽600A'可具有如先前在圖2A中描述之一垂直側壁。在一些其他實施例中，溝槽600A'可具有如先前在圖3中描述之朝向基板600漸縮之一側壁。在一些實施例中，第一電晶體區600A係p型電晶體區，且第二電晶體區600B係n型電晶體區。圖7A係一透視圖，圖7B係一Y切割剖面圖，圖7C係第二電晶體區600B處之一X切割剖面圖，且圖7D係第一電晶體區600A處之一X切割剖面圖。
在圖8A至圖8D中，將一第一層1024填充至堆疊磊晶1023之溝槽600A'中。圖8A係一透視圖，圖8B係一Y切割剖面圖，圖8C係第二電晶體區600B處之一X切割剖面圖，且圖8D係第一電晶體區600A處之一X切割剖面圖。第一層1024之一材料不同於基板600之材料。例如，基板600可由矽組成，且第一層1024可由矽鍺(SiGe)組成。在一些實施例中，堆疊磊晶1023可包含第一層1024之一材料，然而，第一層1024之材料組合物(例如，一複合材料中之原子百分比)可或可不相同於堆疊磊晶1023中之材料組合物。
在圖9A至圖9D中，圖案化第一層1024及基板600之一部分以形成從基板600突出之一第一鰭片。第一鰭片之一上部係一第一層鰭片1024'。堆疊磊晶1023及基板600之一部分經圖案化以形成從基板600突出之一第二鰭片。第二鰭片之一上部係一堆疊鰭片1023'。圖9A係一透視圖，圖9B係一Y切割剖面圖，圖9C係第二電晶體區600B處之一X切割剖面圖，且圖9D係第一電晶體區600A處之一X切割剖面圖。在一些實施例中，在一個微影操作下同時圖案化第一層鰭片1024'及堆疊鰭片1023'。如圖案化之第一層鰭片1024'之一寬度及堆疊鰭片1023'之一寬度可相同。在一些實施例中，第一層鰭片1024'可為一矽鍺鰭片。在一些實施例中，第一層鰭片1024'可隨後形成一P型電晶體之一通道。在一些實施例中，堆疊鰭片1023'可由矽及矽鍺組成。在一些實施例中，堆疊鰭片1023'可形成一N型電晶體之一通道。隨後在第一鰭片與第二鰭片之下部之間形成一淺溝槽隔離(STI) 199。
在圖10A至圖10D中，在第一層鰭片1024'及堆疊鰭片1023'上方毯覆式形成一第一虛設氧化物層1003。圖10A係一透視圖，圖10B係一Y切割剖面圖，圖10C係第二電晶體區600B處之一X切割剖面圖，且圖10D係第一電晶體區600A處之一X切割剖面圖。視情況執行一退火操作以將具有一剛沉積厚度之第一虛設氧化物層1003變換為具有一退火厚度W之一第二虛設氧化物層1003'。在退火操作期間，第一虛設氧化物層1003與第一層鰭片1024'及堆疊鰭片1023'反應，從而使第一層鰭片1024'及堆疊鰭片1023'之材料氧化。因此，第二虛設氧化物層1003'之退火厚度W大於第一虛設氧化物層1003之剛沉積厚度。在圖21A至圖21D中繪示之後續操作中，移除第二虛設氧化物層1003'，從而曝露具有窄於剛圖案化對應物之寬度之一退火後第一層鰭片1024'及一退火後堆疊鰭片1023'。
在一些實施例中，當組成矽鍺之剛圖案化第一層鰭片1024'具有一第一鍺濃度時，經退火第一層鰭片1024'則將歸因於氧化製程消耗矽之一速率比鍺快而組成具有大於第一鍺濃度之一第二鍺濃度之矽鍺，第一層鰭片1024'之表面處之鍺接著被排出且集中於第一層鰭片1024'之未氧化部分中。可視情況執行前述鍺冷凝操作以增大剛圖案化第一層鰭片1024'中之鍺濃度。
參考圖11A至圖11D，在形成第一虛設氧化物層1003之後，藉由一後續圖案化操作使用一硬遮罩1033在第一層鰭片1024'及堆疊鰭片1023'之一通道區上方正交地形成一虛設閘極1030。圖11A係一透視圖，圖11B係一Y切割剖面圖，圖11C係第二電晶體區600B處之一X切割剖面圖，且圖11D係第一電晶體區600A處之一X切割剖面圖。在圖11A至圖11D之圖解中，未執行先前論述之鍺冷凝操作。虛設閘極1030係一犧牲閘極，諸如由一圖案化技術形成之一多閘極(polygate)。如圖11A中展示，虛設閘極1030未直接接觸第一層鰭片1024'及堆疊鰭片1023'但直接接觸第一虛設氧化物層1003。
在圖12A至圖12D中，將一虛設閘極間隔件1069保形地沉積於硬遮罩1033、第一虛設氧化物層1003上方以及沉積至虛設閘極1030及硬遮罩1033上。圖12A係一透視圖，圖12B係一Y切割剖面圖，圖12C係第二電晶體區600B處之一X切割剖面圖，且圖12D係第一電晶體區600A處之一X切割剖面圖。在一些實施例中，藉由一蝕刻操作移除硬遮罩1033之頂表面及第一虛設氧化物層1003之頂表面上方之虛設閘極間隔件1069。在一些實施例中，隨後移除未由虛設閘極1030遮蔽之第一虛設氧化物層1003，而在氧化物蝕刻操作之後僅保留第一虛設氧化物層1003在虛設閘極103下方之部分。
參考圖13A至圖13D，在第一電晶體區600A上方圖案化一遮蔽層1055以覆蓋第一層鰭片1024'而曝露第二電晶體600A及堆疊鰭片1023'。圖13A係一透視圖，圖13B係一Y切割剖面圖，圖13C係第二電晶體區600B處之一X切割剖面圖，且圖13D係第一電晶體區600A處之一X切割剖面圖。遮蔽層1055可在源極/汲極區中之後續奈米線釋放操作中保護第一層鰭片1024'。
在圖14A至圖14D中，執行一選擇性蝕刻以部分移除例如堆疊鰭片1023'中之鍺層1023A'、1023B'、1023C'及1023D'，同時維持極少移除或不移除矽層1023A、1023B、1023C及1023D。因此，在源極/汲極區處從堆疊鰭片1023'釋放一Si奈米線結構1023''，而堆疊鰭片之通道區處之SiGe堆疊在虛設閘極1030及虛設閘極間隔件1069下方受到保護。
圖14A係一透視圖，圖14B係一Y切割剖面圖，圖14C係第二電晶體區600B處之一X切割剖面圖，且圖14D係第一電晶體區600A處之一X切割剖面圖。Si奈米線結構1023''內之矽堆疊之釋放部分因此相對於彼此獨立。隨後，將一內間隔件106橫向沉積至通道區內之剩餘SiGe堆疊之一刻面表面上。在圖15A至圖15D中，透過一磊晶生長技術在所曝露Si奈米線結構1023''周圍以及上方形成一第一源極/汲極105。圖15A係一透視圖，圖15B係一Y切割剖面圖，圖15C係第二電晶體區600B處之一X切割剖面圖，且圖15D係第一電晶體區600A處之一X切割剖面圖。在一些實施例中，形成第一源極/汲極105以產生一Si奈米線NFET。在一些實施例中，第一源極/汲極105由SiP或類似物組成。移除遮蔽層1055以曝露第一層鰭片1024'以用於後續操作。
參考圖16A至圖16D，在第二電晶體區600B上方圖案化一遮蔽層1055以覆蓋源極/汲極區處之Si奈米線結構。遮蔽層1055可在隨後在第一層鰭片1024'處形成源極/汲極時保護源極/汲極區處之所曝露Si奈米線結構1023''。在圖17A至圖17D中，在第一層鰭片1024'上方保形地形成一第二源極/汲極區1039。在一些實施例中，透過一磊晶生長技術形成第二源極/汲極1039以產生一矽鍺奈米線PFET。在一些實施例中，第二源極/汲極1039由摻雜硼之SiGe (SiGeB)組成。
參考圖18A至圖18D，在第一電晶體區600A及第二電晶體區600B上方形成一層間介電質(ILD) 109以覆蓋第一源極/汲極105及第二源極/汲極1039。隨後執行一化學機械平坦化(CMP)操作以移除硬遮罩1033且使虛設閘極1030、虛設閘極間隔件1069及ILD 109共同平坦化。在一些實施例中，CMP操作在第一源極/汲極105及第二源極汲極1039兩者上方之一位置處停止。在圖19A至圖19D中，移除虛設閘極1030，從而曝露如先前在圖10A至圖10D中繪示般沉積之第一虛設氧化物層1003。
在圖20A至圖20D中，圖20A係一透視圖，圖20B係一Y切割剖面圖，圖20C係第二電晶體區600B處之一X切割剖面圖，且圖20D係第一電晶體區600A處之一X切割剖面圖。視情況執行一退火操作以將具有一剛沉積厚度之第一虛設氧化物層1003變換為具有一退火厚度W之一第二虛設氧化物層1003'。在退火操作期間，第一虛設氧化物層1003與第一層鰭片1024'及堆疊鰭片1023'反應，從而使第一層鰭片1024'及堆疊鰭片1023'之材料氧化。因此，第二虛設氧化物層1003'之退火厚度W大於第一虛設氧化物層1003之剛沉積厚度。在圖21A至圖21D中繪示之後續操作中，移除第二虛設氧化物層1003'，從而曝露具有窄於剛圖案化對應物之寬度之一退火後第一層鰭片1024'及一退火後堆疊鰭片1023'。
在一些實施例中，當組成矽鍺之剛圖案化第一層鰭片1024'具有一第一鍺濃度時，經退火第一層鰭片1024'則將歸因於氧化製程消耗矽之一速率比鍺快而組成具有大於第一鍺濃度之一第二鍺濃度之矽鍺，第一層鰭片1024'之表面處之鍺接著被排出且集中於第一層鰭片1024'之未氧化部分中。可視情況執行前述鍺冷凝操作以增大剛圖案化第一層鰭片1024'中之鍺濃度。
圖20A與圖10A之間的差異在於，藉由在圖20A中繪示之階段進行退火或氧化操作，在僅通道區曝露至氧化物時發生第一虛設氧化物層1003至第二虛設氧化物層1003'之轉換，然而，藉由在圖10A中繪示之階段進行退火或氧化操作，在僅源極/汲極區曝露至氧化物時發生第一虛設氧化物層1003至第二虛設氧化物層1003'之轉換。在一些實施例中，在前述階段之一者中進行退火或氧化操作。
在圖22A至圖22D中，在第一電晶體區600A上方圖案化一遮蔽層1055以覆蓋第一層鰭片1024'以用於通道區處之後續Si奈米線釋放操作。應注意，圖22A、圖23A、圖24A及圖25A藉由在通道區處剖開而繪示混合半導體結構之透視圖以便更佳展示前述中間階段期間的通道區處之鰭片結構。
在圖23A至圖23D中，第二電晶體區600B之通道區中之堆疊鰭片1023'中之矽鍺經移除且第二電晶體區600B之通道區中之Si奈米線經釋放且其等相對於彼此獨立。在釋放第二電晶體區600A之通道區中之Si奈米線之後，移除覆蓋第一電晶體區600B之遮蔽層1055。在圖24A至圖24D中，在第一電晶體區600A及第二電晶體區600B上方保形地沉積一高k/層間介電質1077以用於後續替換閘極操作。在圖25A至圖25D中，將金屬閘極材料1087填充於通道區及相鄰經釋放奈米線之間的空間中。隨後藉由一CMP操作平坦化閘極材料1087。在一些實施例中，閘極材料可包含可形成在通道區內之複數個經釋放Si奈米線周圍以及上方之氮化鈦罩蓋層、功函數金屬層、鎢閘極金屬或類似物。
本揭露之一些實施例提供一種混合半導體電晶體結構，其包含：一基板；一第一電晶體，其在該基板上；該第一電晶體之一通道，其包含一鰭片且具有一第一通道高度；一第二電晶體，其相鄰於該第一電晶體；該第二電晶體之一通道，其包含一奈米線；及一離距，其橫向隔開該鰭片與該奈米線。該第一通道高度大於該離距。
本揭露之一些實施例提供一種用於製造一半導體結構之方法，其包含：(1)提供一基板；(2)在該基板上方磊晶地形成交替堆疊膜；(3)在一第一電晶體區上方之該等交替堆疊膜中形成一溝槽；及(4)圖案化一第二電晶體區上方之該等交替堆疊膜以獲得一交替堆疊鰭片。
本揭露之一些實施例提供一種用於製造一半導體結構之方法，其包含：(1)提供一基板；(2)在該基板上方及一p型電晶體區及一n型電晶體區中磊晶地形成交替堆疊膜；(3)在該p型電晶體區中之該等交替堆疊膜中形成一溝槽；及(4)圖案化該n型電晶體區上方之該等交替堆疊膜以獲得一交替堆疊鰭片。
儘管已詳細描述本揭露及其優點，但應理解，可在不脫離如由隨附發明申請專利範圍定義之本揭露之精神及範疇之情況下在本文中做出各種改變、替代及更改。例如，上文論述之許多製程可以不同方法實施且由其他製程或其等之一組合取代。
再者，本申請案之範疇並不旨在限於說明書中描述之製程、機器、製造、物質組合物、構件、方法及步驟之特定實施例。一般技術者將容易從本揭露之揭露內容瞭解，可根據本揭露利用執行與本文描述之對應實施例實質上相同之功能或達成與其等實質上相同之結果之當前現有或稍後開發之製程、機器、製造、物質組合物、構件、方法或步驟。因此，隨附發明申請專利範圍旨在將此等製程、機器、製造、物質組合物、構件、方法或步驟包含於其等範疇內。
20‧‧‧混合半導體電晶體結構
100‧‧‧基板
101A‧‧‧堆疊磊晶區
101B‧‧‧堆疊磊晶區
102‧‧‧n/p邊界
103‧‧‧區
105‧‧‧區/第一源極/汲極
106‧‧‧內部間隔件
109‧‧‧層間介電質(ILD)
199‧‧‧淺溝槽隔離(STI)
200‧‧‧基板
200A‧‧‧第一電晶體
200B‧‧‧第二電晶體
201‧‧‧堆疊磊晶
202‧‧‧n/p邊界
203‧‧‧區
205‧‧‧區
207‧‧‧FinFET井
208A‧‧‧第一鰭片
208B‧‧‧第二鰭片
209‧‧‧隔離
300‧‧‧基板
301‧‧‧堆疊磊晶
302‧‧‧n/p邊界
303‧‧‧區
305‧‧‧區
307‧‧‧FinFET井
600‧‧‧基板
600A‧‧‧第一電晶體區
600A'‧‧‧溝槽
600B‧‧‧第二電晶體區
1003‧‧‧第一虛設氧化物層
1003'‧‧‧第二虛設氧化物層
1023‧‧‧堆疊磊晶
1023'‧‧‧堆疊鰭片
1023''‧‧‧Si奈米線結構
1023A‧‧‧第一矽層
1023A'‧‧‧第一矽鍺層
1023B‧‧‧第二矽層
1023B'‧‧‧第二矽鍺層
1023C‧‧‧第三矽層
1023C'‧‧‧第三矽鍺層
1023D‧‧‧第四矽層
1023D'‧‧‧第四矽鍺層
1024‧‧‧第一層
1024'‧‧‧第一層鰭片
1030‧‧‧虛設閘極
1033‧‧‧硬遮罩
1039‧‧‧第二源極/汲極區/第二源極/汲極
1055‧‧‧遮蔽層
1069‧‧‧虛設閘極間隔件
1077‧‧‧高k/層間介電質
1087‧‧‧金屬閘極材料
CH1‧‧‧通道高度
CH2‧‧‧通道高度
CH3‧‧‧通道高度
H1‧‧‧第一通道高度
H2‧‧‧第二通道高度
S‧‧‧離距
W‧‧‧退火厚度
W1‧‧‧鰭片寬度
W2‧‧‧直徑
在隨附圖式之圖中藉由實例且非限制性地繪示一或多項實施例，其中具有相同元件符號名稱之元件貫穿全文表示相似元件。除非另外揭示，否則圖式不按比例繪製。
圖1係展示處於一中間製造階段之一種類型之混合設計之一剖面圖。
圖2A係展示根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合設計半導體結構之一剖面圖。
圖2B係根據本揭露之一些實施例之一混合半導體電晶體區之一閘極區之一剖面圖。
圖3係展示根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合設計半導體結構之一剖面圖。
圖4係展示根據本揭露之一些實施例之電子遷移率與矽鰭片寬度之間的關係之一圖示。
圖5係展示根據本揭露之一些實施例之電洞遷移率與矽鰭片寬度之間的關係之一圖示。
圖6A至圖6C分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、沿著一Y方向剖開之一剖面圖及沿著一X方向剖開之一剖面圖。
圖7A至圖7D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖8A至圖8D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖9A至圖9D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖10A、圖10B、圖10B'、圖10C、圖10D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖11A、圖11B、圖11B'、圖11C、圖11D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖12A、圖12B、圖12B'、圖12C、圖12D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖13A、圖13B、圖13B'、圖13C、圖13D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖14A、圖14B、圖14B'、圖14C、圖14D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖15A、圖15B、圖15B'、圖15C、圖15D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖16A、圖16B、圖16B'、圖16C、圖16D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖17A、圖17B、圖17B'、圖17C、圖17D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖18A、圖18B、圖18B'、圖18C、圖18D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖19A、圖19B、圖19B'、圖19C、圖19D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖20A、圖20B、圖20B'、圖20C、圖20D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖21A、圖21B、圖21B'、圖21C、圖21D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖22A、圖22B、圖22B'、圖22C、圖22D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖23A、圖23B、圖23B'、圖23C、圖23D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖24A、圖24B、圖24B'、圖24C、圖24D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。
圖25A、圖25B、圖25B'、圖25C、圖25D分別係根據本揭露之一些實施例之在製造操作之一中間階段期間的一種類型之混合半導體結構之一3D透視圖、在閘極上沿著一Y方向剖開之一剖面圖、在源極/汲極區上沿著一Y方向剖開之一剖面圖、在N區處沿著一X方向剖開之一剖面圖及在P區處沿著一X方向剖開之一剖面圖。

Claims (1)

  1. 一種混合半導體電晶體結構，其包括： 一基板； 一第一電晶體，其在該基板上，該第一電晶體之一通道包括一鰭片且具有一第一通道高度； 一第二電晶體，其相鄰於該第一電晶體，該第二電晶體之一通道包括一奈米線；及 一離距，其橫向隔開該鰭片與該奈米線， 其中該第一通道高度大於該離距。
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US10756089B2 (en) 2020-08-25
US20230087836A1 (en) 2023-03-23
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US20200091151A1 (en) 2020-03-19
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US11515305B2 (en) 2022-11-29
US20190355724A1 (en) 2019-11-21

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