CN110504215B - 混合半导体晶体管结构与制造方法 - Google Patents

混合半导体晶体管结构与制造方法 Download PDF

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CN110504215B
CN110504215B CN201811248016.9A CN201811248016A CN110504215B CN 110504215 B CN110504215 B CN 110504215B CN 201811248016 A CN201811248016 A CN 201811248016A CN 110504215 B CN110504215 B CN 110504215B
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fin
over
transistor
fins
dummy gate
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CN110504215A (zh
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江宏礼
陈奕升
陈自强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露提供一种混合半导体晶体管结构，其包含：衬底；第一晶体管，其在所述衬底上，所述第一晶体管的沟道包含鳍片且具有第一沟道高度；第二晶体管，其相邻于所述第一晶体管，所述第二晶体管的沟道包含纳米线；和离距，其横向隔开所述鳍片与所述纳米线。所述第一沟道高度大于所述离距。本揭露还提供一种用于制造所述混合半导体晶体管结构的方法。

Description

混合半导体晶体管结构与制造方法
技术领域
本发明实施例涉及混合半导体晶体管结构与制造方法。
背景技术
为达成集成电路的电路密度的增大，已减小此些集成电路内的半导体装置(例如场效晶体管)的大小。然而，减小半导体装置的大小可导致半导体装置的沟道的长度的减小。减小沟道长度可导致半导体装置的源极区和漏极区更靠近彼此，此可允许源极和漏极区对沟道或甚至对沟道内的载子施加不当影响(通常称为短沟道效应)。因此，经受短沟道效应的半导体装置的栅极已减少对沟道的控制，此尤其抑制栅极控制半导体装置的接通和/或关断状态的能力。
发明内容
根据本发明的一实施例，一种混合半导体晶体管结构包括：衬底；第一晶体管，其在所述衬底上，所述第一晶体管的沟道包括鳍片且具有第一沟道高度；第二晶体管，其相邻于所述第一晶体管，所述第二晶体管的沟道包括纳米线；和离距，其横向隔开所述鳍片与所述纳米线，其中所述第一沟道高度大于所述离距。
根据本发明的一实施例，一种用于形成混合半导体晶体管结构的方法包括：提供衬底；在所述衬底上方外延地形成交替堆叠膜；在第一晶体管区上方的所述交替堆叠膜中形成沟槽；和图案化第二晶体管区上方的所述交替堆叠膜以获得交替堆叠鳍片。
根据本发明的一实施例，一种用于形成混合半导体晶体管结构的方法包括：提供衬底；在所述衬底上方以及p型晶体管区和n型晶体管区中外延地形成交替堆叠膜；在所述p型晶体管区中的所述交替堆叠膜中形成沟槽；和图案化所述n型晶体管区上方的所述交替堆叠膜以获得交替堆叠鳍片。
附图说明
在随附图式的图中通过实例且非限制性地说明一或多个实施例，其中具有相同元件符号名称的元件贯穿全文表示相似元件。除非另外公开，否则图式不按比例绘制。
图1是展示处于中间制造阶段的一种类型的混合设计的剖面图。
图2A是展示根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合设计半导体结构的剖面图。
图2B是根据本揭露的一些实施例的混合半导体晶体管区的栅极区的剖面图。
图3是展示根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合设计半导体结构的剖面图。
图4是展示根据本揭露的一些实施例的电子迁移率与硅鳍片宽度之间的关系的图示。
图5是展示根据本揭露的一些实施例的空穴迁移率与硅鳍片宽度之间的关系的图示。
图6A到6C分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、沿着Y方向剖开的剖面图和沿着X方向剖开的剖面图。
图7A到7D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图8A到8D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图9A到9D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图10A、10B、10B'、10C、10D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图11A、11B、11B'、11C、11D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图12A、12B、12B'、12C、12D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图13A、13B、13B'、13C、13D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图14A、14B、14B'、14C、14D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图15A、15B、15B'、15C、15D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图16A、16B、16B'、16C、16D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图17A、17B、17B'、17C、17D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图18A、18B、18B'、18C、18D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图19A、19B、19B'、19C、19D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图20A、20B、20B'、20C、20D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图21A、21B、21B'、21C、21D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图22A、22B、22B'、22C、22D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图23A、23B、23B'、23C、23D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图24A、24B、24B'、24C、24D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
图25A、25B、25B'、25C、25D分别为根据本揭露的一些实施例的在制造操作的中间阶段期间的一种类型的混合半导体结构的3D透视图、在栅极上沿着Y方向剖开的剖面图、在源极/漏极区上沿着Y方向剖开的剖面图、在N区处沿着X方向剖开的剖面图和在P区处沿着X方向剖开的剖面图。
具体实施方式
在下文详细论述本揭露的实施例的制造和使用。然而，应了解，实施例提供可在广泛多种特定内容背景中体现的许多可应用发明概念。所讨论的特定实施例仅说明制造和使用实施例的特定方式且不限制本揭露的范围。贯穿各种视图和阐释性实施例，相似元件符号用来指定相似元件。现将详细参考随附图式中说明的示范性实施例。在任何可能的情况下，在图式和描述中使用相同元件符号以指代相同或相似元件。在图式中，形状和厚度可为清楚和方便起见而放大。此描述尤其涉及形成根据本揭露的设备的部分或与所述设备更直接协作的元件。应了解，未特定展示或描述的元件可采用各种形式。贯穿本说明书对“一个实施例”或“一实施例”的引用意谓结合实施例描述的特定构件、结构或特性包含于至少一个实施例中。因此，在贯穿本说明书的各处出现的短语“在一个实施例中”或“在一实施例中”未必均指代相同实施例。此外，在一或多个实施例中可以任何适合方式组合特定构件、结构或特性。应了解，下图不按比例绘制；实情为，此些图仅旨在用于图解。
此外，为便于描述，可在本文中使用例如“在…下面”、“在…下方”、“下”、“在…上方”、“上”等等的空间相对术语来描述一个元件或构件与另一(些)元件或构件的关系，如在图中说明。空间相对术语旨在涵盖除在图中描绘的定向以外的使用或操作中的装置的不同定向。设备可以其它方式定向(旋转90度或按其它定向)且因此可同样解释本文中使用的空间相对描述符。
半导体装置用于各种电子应用中，例如个人计算机、蜂窝式电话、数码相机和其它电子设备。通常通过以下步骤制造半导体装置：在半导体衬底上方循序沉积绝缘或介电层、导电层和半导电材料层；和使用光刻术图案化各种材料层以在其上形成电路组件和元件。通常在单个半导体晶片上制造许多集成电路，且通过沿着切割道在集成电路之间锯切而单粒化晶片上的个别裸片。
多个栅极场效晶体管(MuGFET)是半导体技术的最近发展，其通常为将多于一个栅极并入到单个装置中的金属氧化物半导体FET(MOSFET)。一种类型的MuGFET称为FinFET，其是具有垂直凸起远离集成电路的衬底的鳍状半导体沟道的晶体管结构。FinFET的最近设计是环绕式栅极(GAA)FinFET，其具有在所有侧上包围沟道区的栅极材料。
可通过任何适合方法图案化环绕式栅极(GAA)晶体管结构。例如，可使用一或多个光刻工艺(包含双重图案化或多重图案化工艺)图案化结构。一般来说，双重图案化或多重图案化工艺组合光刻与自对准工艺，从而允许产生具有例如小于原本可使用单个直接光刻工艺获得的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层且使用光刻工艺图案化所述牺牲层。使用自对准工艺与图案化牺牲层并排形成间隔件。接着去除牺牲层，且接着可使用剩余间隔件以图案化GAA结构。
MuGFET的混合设计包含第一导电类型的FET是FinFET，且第二导电类型的至少另一FET是环绕式栅极结构。参考图1，图1展示处于中间制造阶段的一种类型的混合设计。堆叠外延区101A与相邻堆叠外延区101B隔开。归因于堆叠外延区101A和101B的任一个形成于从衬底100凹陷的沟槽中的事实，所沉积外延膜将呈现沟槽的轮廓且显现为U形堆叠。例如，在后续操作中，由虚线包围的区103变成n-FET且由虚线包围的区105变成p-FET。可观察到，n-FET与p-FET之间的间隔(其称为n/p边界102)由外延膜的垂直堆叠或生长于沟槽的侧壁上的外延膜占据。图1中说明的混合结构面临由n/p边界102的存在所引起的面积损失的问题。例如，图1的n/p边界102可为约相同于沟道高度CH1的量值，例如从约50nm到约80nm。无法通过先进对准或光刻技术缓和n/p边界102减小，这是因为其受限于沟槽的几何形状。
本揭露提供MuGFET的新混合设计，其解决由n/p边界引起的面积损失。参考图2A，图2A展示根据本揭露的一些实施例的处于中间制造阶段的一种类型的混合设计。在图2A中，在形成堆叠外延201之前未在衬底200中形成凹槽，因此可获得堆叠外延201的水平轮廓。在堆叠外延201中重新生长具有从顶部到底部的大体上相等宽度的FinFET井207。例如，在后续操作中，由虚线包围的区203变成n-FET且由虚线包围的区205变成p-FET。n-FET与p-FET之间的间隔或n/p边界202可减小到光刻限制所指示的程度。例如，在本实施例中，n/p边界202可为沟道高度CH2的约四分之一到五分之一，例如从约10nm到约20nm。在一些实施例中，重新生长的FinFET井可放置在混合设计的n-FET中。
参考图3，图3展示根据本揭露的一些实施例的处于中间制造阶段的一种类型的混合设计。在图3中，在形成堆叠外延301之前未在衬底300中形成凹槽，因此可获得堆叠外延301的水平轮廓。在堆叠外延301中重新生长具有朝向衬底300渐缩的形状(即，具有较宽顶部和较窄底部)的FinFET井307。可在FinFET井307和下伏衬底300的材料具有不同晶格常量且因此引发失配应力时采用FinFET井307的锥形形状。FinFET井307的锥形形状可促进晶格失配接口处的松弛且因此获得无应变FinFET井307。在后续操作中，由虚线包围的区303变成n-FET且由虚线包围的区305变成p-FET。n-FET与p-FET之间的间隔或n/p边界302可减小到光刻限制所指示的程度。例如，在本实施例中，n/p边界302可为沟道高度CH3的约四分之一到五分之一，例如从约10nm到约20nm。在一些实施例中，重新生长的FinFET井可放置在混合设计的n-FET中。
参考图2B，图2B是根据本揭露的一些实施例的在混合半导体晶体管结构20的栅极区处剖开的剖面。如图2B中展示，结构20包含衬底200和至少第一晶体管200A和第二晶体管200B。第一晶体管200A具有在从隔离209突出的第一鳍片208A的一部分处测量的第一沟道高度H1。第二晶体管200B具有在第二鳍片208B的纳米线部分处测量的第二沟道高度H2。可在图2B中说明的剖面中观察到横向隔开从隔离209突出的第一鳍片208A的部分与第二鳍片208B的纳米线部分的离距S。在一些实施例中，第一沟道高度H1大于离距S的2倍、3倍或4倍。在一些实施例中，第二沟道高度H2大体上相同于第一沟道高度且大于离距S。在一些实施例中，例如，在5nm技术节点和以上技术节点下，第一沟道高度H1为至少约50nm到约80nm，且离距S小于约10nm到20nm。
如图2B中展示，从隔离209突出的第一鳍片208A的部分可由与由隔离209包围的第一鳍片208A的部分的材料不同的材料组成。类似地，从隔离209突出的第一鳍片208A的部分可由与衬底200的材料不同的材料组成。在一些实施例中，取决于装置的性能要求，衬底200和由隔离209包围的第一鳍片208A由硅组成，而从隔离209突出的第一鳍片208A的部分可由硅锗或其它III-V族化合物组成。在一些实施例中，从隔离209突出的第一鳍片208A的部分由SixGe1-x组成，其中X小于0.6。可由随后在本揭露的图10A到10D或图20A到20D中描绘的锗浓缩操作获得此高锗含量。
在图2B中，第二鳍片208B的纳米线部分可由相同于由隔离209包围的第二鳍片208B的部分的材料或相同于衬底200的材料组成。
在一些实施例中，第一晶体管200A是p-FET，这是因为空穴迁移率未随着横向尺寸减小而降级，且p-FET的沟道区可保持具有减小鳍片宽度W1的鳍片形状。相比之下，第二晶体管200B是具有环绕式栅极沟道的n-FET，这是因为空穴迁移率对横向尺寸的减小更敏感，且n-FET的沟道区由具有大于鳍片宽度W1的直径W2的纳米线取代。相较于拥有具有鳍片宽度W2的鳍片沟道，拥有具有直径W2的纳米线沟道大幅减少泄漏电流且缓和短沟道效应。在一些实施例中，鳍片宽度W1可小于6nm且直径W2可大于或等于6nm。在一些实施例中，鳍片宽度W1为约4nm且直径W2为约6nm。
参考图4，图4展示电子迁移率与硅鳍片宽度之间的关系。应明白，用于保持电子迁移率的最优选值是具有约6nm的鳍片宽度。如先前论述，可通过将鳍片几何形状改变为纳米线几何形状而减少泄漏电流，在确定n-FET的最优选鳍片宽度时减小泄漏电流的权重。
参考图5，图5展示空穴迁移率与硅锗鳍片宽度之间的关系。在不具有硅罩盖的条件下(此是指无应变状态)，空穴迁移率处于约180cm2/V-s的平均值，在鳍片宽度从8nm减小到4nm时稍微减小。在具有硅罩盖的条件下(此是指应变状态)，空穴迁移率处于约300cm2/V-s的平均值，在鳍片宽度从8nm减小到4nm时减小。应变状态更佳地描述FinFET的最终产物，这是因为鳍片上方的钝化层产生适量应力。考量足够高空穴迁移率的保持以及减少泄漏电流，p-FET的最优选鳍片宽度处于约4nm。
应注意，在MuGFET的技术中，当前已知包含III族和V族材料的若干材料系统且其应涵盖在本揭露的预期范围内。例如，在硅衬底上，通常采用用于n-FET的Si纳米线和用于p-FET的SiGe纳米线。在GaAs衬底上，通常采用用于n-FET的GaAs纳米线和用于p-FET的InGaAs纳米线。在Ge/GaAs衬底上，通常采用用于n-FET的Ge纳米线和用于p-FET的GaAs纳米线。出于简洁目的，本揭露仅提供Si纳米线和SiGe纳米线材料系统的图解和以下详细描述。相同发明概念可应用于所处置的不同半导体材料系统上。
图6A到25D说明本文中描述的混合半导体结构的中间制造阶段中的不同透视图。
参考图6A到6C，在衬底600上方形成堆叠外延1023。在一些实施例中，堆叠外延1023包含交替地放置在衬底600上方的一或多个硅(Si)层和一或多个硅锗(SiGe)层。图6A是透视图，图6B是Y切割剖面图，且图6C是X切割剖面图。例如，堆叠外延1023包含第一硅锗层1023A'、第一硅层1023A、第二硅锗层1023B'、第二硅层1023B、第三硅锗层1023C'、第三硅层1023C、第四硅锗层1023D'和第四硅层1023D。应了解，可形成任何数目个硅层或硅锗层。
参考图7A到7D，衬底600包含第一晶体管区600A和第二晶体管区600B。去除第一晶体管区600A内的堆叠外延1023，因此在堆叠外延1023中形成沟槽600A'，且暴露下伏衬底600。在一些实施例中，沟槽600A'可具有如先前在图2A中描述的垂直侧壁。在一些其它实施例中，沟槽600A'可具有如先前在图3中描述的朝向衬底600渐缩的侧壁。在一些实施例中，第一晶体管区600A是p型晶体管区，且第二晶体管区600B是n型晶体管区。图7A是透视图，图7B是Y切割剖面图，图7C是第二晶体管区600B处的X切割剖面图，且图7D是第一晶体管区600A处的X切割剖面图。
在图8A到8D中，将第一层1024填充到堆叠外延1023的沟槽600A'中。图8A是透视图，图8B是Y切割剖面图，图8C是第二晶体管区600B处的X切割剖面图，且图8D是第一晶体管区600A处的X切割剖面图。第一层1024的材料不同于衬底600的材料。例如，衬底600可由硅组成，且第一层1024可由硅锗(SiGe)组成。在一些实施例中，堆叠外延1023可包含第一层1024的材料，然而，第一层1024的材料组合物(例如，复合材料中的原子百分比)可或可不相同于堆叠外延1023中的材料组合物。
在图9A到9D中，图案化第一层1024和衬底600的一部分以形成从衬底600突出的第一鳍片。第一鳍片的上部是第一层鳍片1024'。堆叠外延1023和衬底600的一部分经图案化以形成从衬底600突出的第二鳍片。第二鳍片的上部是堆叠鳍片1023'。图9A是透视图，图9B是Y切割剖面图，图9C是第二晶体管区600B处的X切割剖面图，且图9D是第一晶体管区600A处的X切割剖面图。在一些实施例中，在一个光刻操作下同时图案化第一层鳍片1024'和堆叠鳍片1023'。如图案化的第一层鳍片1024'的宽度和堆叠鳍片1023'的宽度可相同。在一些实施例中，第一层鳍片1024'可为硅锗鳍片。在一些实施例中，第一层鳍片1024'可随后形成P型晶体管的沟道。在一些实施例中，堆叠鳍片1023'可由硅和硅锗组成。在一些实施例中，堆叠鳍片1023'可形成N型晶体管的沟道。随后在第一鳍片与第二鳍片的下部之间形成浅沟槽隔离(STI)199。
在图10A到10D中，在第一层鳍片1024'和堆叠鳍片1023'上方毯覆式形成第一虚设氧化物层1003。图10A是透视图，图10B是Y切割剖面图，图10C是第二晶体管区600B处的X切割剖面图，且图10D是第一晶体管区600A处的X切割剖面图。任选地执行退火操作以将具有刚沉积厚度的第一虚设氧化物层1003变换为具有退火厚度W的第二虚设氧化物层1003'。在退火操作期间，第一虚设氧化物层1003与第一层鳍片1024'和堆叠鳍片1023'反应，从而使第一层鳍片1024'和堆叠鳍片1023'的材料氧化。因此，第二虚设氧化物层1003'的退火厚度W大于第一虚设氧化物层1003的刚沉积厚度。在图21A到21D中说明的后续操作中，去除第二虚设氧化物层1003'，从而暴露具有窄于刚图案化对应物的宽度的退火后第一层鳍片1024'和退火后堆叠鳍片1023'。
在一些实施例中，当组成硅锗的刚图案化第一层鳍片1024'具有第一锗浓度时，经退火第一层鳍片1024'则将归因于氧化工艺消耗硅的速率比锗快而组成具有大于第一锗浓度的第二锗浓度的硅锗，第一层鳍片1024'的表面处的锗接着被排出且集中于第一层鳍片1024'的未氧化部分中。可任选地执行前述锗浓缩操作以增大刚图案化第一层鳍片1024'中的锗浓度。
参考图11A到11D，在形成第一虚设氧化物层1003之后，通过后续图案化操作使用硬掩模1033在第一层鳍片1024'和堆叠鳍片1023'的沟道区上方正交地形成虚设栅极1030。图11A是透视图，图11B是Y切割剖面图，图11C是第二晶体管区600B处的X切割剖面图，且图11D是第一晶体管区600A处的X切割剖面图。在图11A到11D的图解中，未执行先前论述的锗浓缩操作。虚设栅极1030是牺牲栅极，例如由图案化技术形成的多栅极(polygate)。如图11A中展示，虚设栅极1030未直接接触第一层鳍片1024'和堆叠鳍片1023'但直接接触第一虚设氧化物层1003。
在图12A到12D中，将虚设栅极间隔件1069保形地沉积在硬掩模1033、第一虚设氧化物层1003上方以及沉积到虚设栅极1030和硬掩模1033上。图12A是透视图，图12B是Y切割剖面图，图12C是第二晶体管区600B处的X切割剖面图，且图12D是第一晶体管区600A处的X切割剖面图。在一些实施例中，通过蚀刻操作去除硬掩模1033的顶表面和第一虚设氧化物层1003的顶表面上方的虚设栅极间隔件1069。在一些实施例中，随后去除未由虚设栅极1030遮蔽的第一虚设氧化物层1003，而在氧化物蚀刻操作之后仅保留第一虚设氧化物层1003在虚设栅极103下方的部分。
参考图13A到13D，在第一晶体管区600A上方图案化遮蔽层1055以覆盖第一层鳍片1024'而暴露第二晶体管600A和堆叠鳍片1023'。图13A是透视图，图13B是Y切割剖面图，图13C是第二晶体管区600B处的X切割剖面图，且图13D是第一晶体管区600A处的X切割剖面图。遮蔽层1055可在源极/漏极区中的后续纳米线释放操作中保护第一层鳍片1024'。
在图14A到14D中，执行选择性蚀刻以部分去除例如堆叠鳍片1023'中的锗层1023A'、1023B'、1023C'和1023D'，同时维持极少去除或不去除硅层1023A、1023B、1023C和1023D。因此，在源极/漏极区处从堆叠鳍片1023'释放Si纳米线结构1023”，而堆叠鳍片的沟道区处的SiGe堆叠在虚设栅极1030和虚设栅极间隔件1069下方受到保护。
图14A是透视图，图14B是Y切割剖面图，图14C是第二晶体管区600B处的X切割剖面图，且图14D是第一晶体管区600A处的X切割剖面图。Si纳米线结构1023”内的硅堆叠的释放部分因此相对于彼此独立。随后，将内间隔件106横向沉积到沟道区内的剩余SiGe堆叠的刻面表面上。在图15A到15D中，透过外延生长技术在所暴露Si纳米线结构1023”周围以及上方形成第一源极/漏极105。图15A是透视图，图15B是Y切割剖面图，图15C是第二晶体管区600B处的X切割剖面图，且图15D是第一晶体管区600A处的X切割剖面图。在一些实施例中，形成第一源极/漏极105以产生Si纳米线NFET。在一些实施例中，第一源极/漏极105由SiP或类似物组成。去除遮蔽层1055以暴露第一层鳍片1024'以用于后续操作。
参考图16A到16D，在第二晶体管区600B上方图案化遮蔽层1055以覆盖源极/漏极区处的Si纳米线结构。遮蔽层1055可在随后在第一层鳍片1024'处形成源极/漏极时保护源极/漏极区处的所暴露Si纳米线结构1023”。在图17A到17D中，在第一层鳍片1024'上方保形地形成第二源极/漏极区1039。在一些实施例中，透过外延生长技术形成第二源极/漏极1039以产生硅锗纳米线PFET。在一些实施例中，第二源极/漏极1039由掺杂硼的SiGe(SiGeB)组成。
参考图18A到18D，在第一晶体管区600A和第二晶体管区600B上方形成层间介电质(ILD)109以覆盖第一源极/漏极105和第二源极/漏极1039。随后执行化学机械平坦化(CMP)操作以去除硬掩模1033且使虚设栅极1030、虚设栅极间隔件1069和ILD 109共同平坦化。在一些实施例中，CMP操作在第一源极/漏极105和第二源极漏极1039两者上方的位置处停止。在图19A到19D中，去除虚设栅极1030，从而暴露如先前在图10A到10D中说明般沉积的第一虚设氧化物层1003。
在图20A到20D中，图20A是透视图，图20B是Y切割剖面图，图20C是第二晶体管区600B处的X切割剖面图，且图20D是第一晶体管区600A处的X切割剖面图。任选地执行退火操作以将具有刚沉积厚度的第一虚设氧化物层1003变换为具有退火厚度W的第二虚设氧化物层1003'。在退火操作期间，第一虚设氧化物层1003与第一层鳍片1024'和堆叠鳍片1023'反应，从而使第一层鳍片1024'和堆叠鳍片1023'的材料氧化。因此，第二虚设氧化物层1003'的退火厚度W大于第一虚设氧化物层1003的刚沉积厚度。在图21A到21D中说明的后续操作中，去除第二虚设氧化物层1003'，从而暴露具有窄于刚图案化对应物的宽度的退火后第一层鳍片1024'和退火后堆叠鳍片1023'。
在一些实施例中，当组成硅锗的刚图案化第一层鳍片1024'具有第一锗浓度时，经退火第一层鳍片1024'则将归因于氧化工艺消耗硅的速率比锗快而组成具有大于第一锗浓度的第二锗浓度的硅锗，第一层鳍片1024'的表面处的锗接着被排出且集中于第一层鳍片1024'的未氧化部分中。可任选地执行前述锗浓缩操作以增大刚图案化第一层鳍片1024'中的锗浓度。
图20A与图10A之间的差异在于，通过在图20A中说明的阶段进行退火或氧化操作，在仅沟道区暴露到氧化物时发生第一虚设氧化物层1003到第二虚设氧化物层1003'的转换，然而，通过在图10A中说明的阶段进行退火或氧化操作，在仅源极/漏极区暴露到氧化物时发生第一虚设氧化物层1003到第二虚设氧化物层1003'的转换。在一些实施例中，在前述阶段的一个中进行退火或氧化操作。
在图22A到22D中，在第一晶体管区600A上方图案化遮蔽层1055以覆盖第一层鳍片1024'以用于沟道区处的后续Si纳米线释放操作。应注意，图22A、23A、24A和25A通过在沟道区处剖开而说明混合半导体结构的透视图以便更佳展示前述中间阶段期间的沟道区处的鳍片结构。
在图23A到23D中，第二晶体管区600B的沟道区中的堆叠鳍片1023'中的硅锗经去除且第二晶体管区600B的沟道区中的Si纳米线经释放且其相对于彼此独立。在释放第二晶体管区600A的沟道区中的Si纳米线之后，去除覆盖第一晶体管区600B的遮蔽层1055。在图24A到24D中，在第一晶体管区600A和第二晶体管区600B上方保形地沉积高k/层间介电质1077以用于后续替换栅极操作。在图25A到25D中，将金属栅极材料1087填充于沟道区和相邻经释放纳米线之间的空间中。随后通过CMP操作平坦化栅极材料1087。在一些实施例中，栅极材料可包含可形成在沟道区内的多个经释放Si纳米线周围以及上方的氮化钛罩盖层、功函数金属层、钨栅极金属或类似物。
本揭露的一些实施例提供一种混合半导体晶体管结构，其包含：衬底；第一晶体管，其在所述衬底上；所述第一晶体管的沟道，其包含鳍片且具有第一沟道高度；第二晶体管，其相邻于所述第一晶体管；所述第二晶体管的沟道，其包含纳米线；和离距，其横向隔开所述鳍片与所述纳米线。所述第一沟道高度大于所述离距。
本揭露的一些实施例提供一种用于制造半导体结构的方法，其包含：(1)提供衬底；(2)在所述衬底上方外延地形成交替堆叠膜；(3)在第一晶体管区上方的所述交替堆叠膜中形成沟槽；和(4)图案化第二晶体管区上方的所述交替堆叠膜以获得交替堆叠鳍片。
本揭露的一些实施例提供一种用于制造半导体结构的方法，其包含：(1)提供衬底；(2)在所述衬底上方以及p型晶体管区和n型晶体管区中外延地形成交替堆叠膜；(3)在所述p型晶体管区中的所述交替堆叠膜中形成沟槽；和(4)图案化所述n型晶体管区上方的所述交替堆叠膜以获得交替堆叠鳍片。
尽管已详细描述本揭露和其优点，但应理解，可在不脱离如由随附发明权利要求书定义的本揭露的精神和范围的情况下在本文中做出各种改变、替代和更改。例如，上文论述的许多工艺可以不同方法实施且由其它工艺或其组合取代。
而且，本申请案的范围并不旨在限于说明书中描述的工艺、机器、制造、物质组合物、构件、方法和步骤的特定实施例。一般技术人员将容易从本揭露的揭露内容了解，可根据本揭露利用执行与本文描述的对应实施例大体上相同的功能或达成与其大体上相同的结果的当前现有或稍后开发的工艺、机器、制造、物质组合物、构件、方法或步骤。因此，随附发明权利要求书旨在将此些工艺、机器、制造、物质组合物、构件、方法或步骤包含于其范围内。
符号说明
20       混合半导体晶体管结构
100      衬底
101A     堆叠外延区
101B     堆叠外延区
102      n/p边界
103      区
105      区/第一源极/漏极
106      内部间隔件
109      层间介电质(ILD)
199      浅沟槽隔离(STI)
200      衬底
200A     第一晶体管
200B     第二晶体管
201      堆叠外延
202      n/p边界
203      区
205      区
207      FinFET井
208A     第一鳍片
208B     第二鳍片
209      隔离
300      衬底
301      堆叠外延
302      n/p边界
303      区
305      区
307      FinFET井
600      衬底
600A     第一晶体管区
600A'    沟槽
600B     第二晶体管区
1003     第一虚设氧化物层
1003'    第二虚设氧化物层
1023     堆叠外延
1023'    堆叠鳍片
1023”    Si纳米线结构
1023A    第一硅层
1023A'   第一硅锗层
1023B    第二硅层
1023B'   第二硅锗层
1023C    第三硅层
1023C'   第三硅锗层
1023D    第四硅层
1023D'   第四硅锗层
1024     第一层
1024'    第一层鳍片
1030     虚设栅极
1033     硬掩模
1039     第二源极/漏极区/第二源极/漏极
1055     遮蔽层
1069     虚设栅极间隔件
1077     高k/层间介电质
1087     金属栅极材料
CH1      沟道高度
CH2      沟道高度
CH3      沟道高度
H1       第一沟道高度
H2       第二沟道高度
S        离距
W        退火厚度
W1       鳍片宽度
W2       直径

Claims (41)

1.一种混合半导体晶体管结构，其包括：
衬底；
第一晶体管，其在所述衬底上，所述第一晶体管的沟道包括鳍片且具有第一沟道高度，其中所述鳍片包括由隔离包围的第一部分和从所述隔离突出的第二部分，所述第一部分的材料不同于所述第二部分的材料，所述第一部分和所述第二部分分别由单一材料所组成，且所述第一部分的顶表面高于所述隔离的顶表面；
第二晶体管，其邻近于所述第一晶体管，所述第二晶体管的沟道包括纳米线；和
离距，其横向隔开所述鳍片与所述纳米线，
其中所述第一沟道高度大于所述离距。
2.根据权利要求1所述的结构，其中所述第二晶体管的所述沟道的第二沟道高度大体上等同于所述第一沟道高度。
3.根据权利要求1所述的结构，其中所述第一晶体管是p型晶体管，且所述第二晶体管是n型晶体管。
4.根据权利要求3所述的结构，其中所述鳍片的宽度小于所述纳米线的直径。
5.根据权利要求1所述的结构，其中所述第一晶体管的所述鳍片的所述第二部分的材料不同于所述衬底的材料。
6.根据权利要求5所述的结构，其中所述第一晶体管的所述鳍片的所述第二部分包括SixGe1-x，X小于0.6。
7.根据权利要求1所述的结构，其中所述第一沟道高度大于所述离距的2倍。
8.一种用于形成混合半导体晶体管结构的方法，其包括：
提供衬底；
在所述衬底上方外延地形成交替堆叠式膜；
在所述交替堆叠式膜中第一晶体管区上方形成沟槽；
在所述第一晶体管区上方用不同于所述衬底材料的材料填充所述沟槽，其中所述材料直接接触所述交替堆叠式膜；
在所述第一晶体管区上方用所述材料填充所述沟槽之后，在第二晶体管区上方图案化所述交替堆叠式膜，以获得交替堆叠式鳍片；
在所述第一晶体管区上方图案化所述材料以获得鳍片；及
在所述鳍片及所述交替堆叠式鳍片上方形成虚拟栅极，其中所述虚拟栅极连续地延伸跨过所述鳍片及所述交替堆叠式鳍片。
9.根据权利要求8所述的方法，其中在所述第二晶体管区上方所述图案化所述交替堆叠式膜和在所述第一晶体管区上方所述图案化所述材料同时进行。
10.根据权利要求8所述的方法，其进一步包括：
在所述第一晶体管区上方用硬掩模覆盖所述鳍片；
将纳米线从所述交替堆叠式鳍片释放；和
去除覆盖所述鳍片的所述硬掩模。
11.根据权利要求8所述的方法，其中所述形成所述沟槽包括形成竖直侧壁沟槽或朝向所述衬底逐渐变窄的锥形沟槽。
12.根据权利要求8所述的方法，其进一步包括：
在获得所述鳍片之后，在所述鳍片上方沉积第一虚拟氧化物层；和
使所述鳍片退火，以便在所述鳍片上方垂直形成所述虚拟栅极之前，将所述第一虚拟氧化物层转变成第二虚拟氧化物层。
13.根据权利要求8所述的方法，其进一步包括：
在获得所述鳍片之后，在所述鳍片上方沉积第一虚拟氧化物层；
去除所述鳍片上方的所述虚拟栅极以暴露所述第一虚拟氧化物层；
使所述鳍片退火，以便将所述第一虚拟氧化物层转变成第二虚拟氧化物层；和
去除所述第二虚拟氧化物层。
14.一种用于形成混合半导体晶体管结构的方法，其包括：
提供衬底；
在所述衬底上方且在p型晶体管区和n型晶体管区中外延地形成交替堆叠式膜；
在所述交替堆叠式膜中且在所述p型晶体管区中形成沟槽；
用硅锗填充所述p型晶体管区中的所述沟槽，其中所述硅锗直接接触所述交替堆叠式膜；
在所述p型晶体管区中的所述交替堆叠式膜中形成所述沟槽之后，在所述n型晶体管区上方图案化所述交替堆叠式膜，以获得交替堆叠式鳍片；
图案化所述硅锗以获得硅锗鳍片；及
在所述硅锗鳍片和所述交替堆叠式鳍片的沟道区上方垂直形成虚拟栅极，其中所述虚拟栅极连续地延伸跨过所述硅锗鳍片及所述交替堆叠式鳍片。
15.根据权利要求14所述的方法，其进一步包括：
去除所述硅锗鳍片和所述交替堆叠式鳍片的所述沟道区上方的所述虚拟栅极；和
从所述沟道区中的所述交替堆叠式鳍片释放硅纳米线。
16.根据权利要求15所述的方法，其进一步包括：
在获得所述硅锗鳍片之后，在所述硅锗鳍片上方沉积第一虚拟氧化物层；和
使所述硅锗鳍片退火，以便在所述硅锗鳍片上方垂直形成所述虚拟栅极之前，将所述第一虚拟氧化物层转变成第二虚拟氧化物层。
17.根据权利要求15所述的方法，其进一步包括：
在获得所述硅锗鳍片之后，在所述硅锗鳍片的所述沟道区上方沉积第一虚拟氧化物层；
去除所述硅锗鳍片上方的所述虚拟栅极以暴露所述第一虚拟氧化物层；
使所述硅锗鳍片退火，以便将所述第一虚拟氧化物层转变成第二虚拟氧化物层；和
去除所述第二虚拟氧化物层。
18.根据权利要求14所述的方法，其中形成所述沟槽包括形成竖直侧壁沟槽或朝向所述衬底逐渐变窄的锥形沟槽。
19.一种用于形成混合半导体晶体管结构的方法，其包括：
提供衬底；
在所述衬底上方外延地形成交替堆叠式膜；
在所述交替堆叠式膜中第一晶体管区上方形成沟槽；
用不同于所述衬底材料的材料填充所述沟槽，其中所述材料直接接触所述交替堆叠式膜；
在所述衬底上形成第一晶体管，其包括：
图案化所述材料，从而在所述第一晶体管区上方获得鳍片，其中所述鳍片由所述材料形成，所述第一晶体管具有第一沟道高度，所述鳍片从隔离突出，所述鳍片接触所述衬底的顶表面，且所述衬底的所述顶表面高于所述隔离的顶表面；和
在所述衬底上形成第二晶体管，其包括：
在第二晶体管区上方图案化所述交替堆叠式膜，从而获得交替堆叠式鳍片，其中所述第一沟道高度大于所述交替堆叠式鳍片与所述鳍片之间的离距。
20.根据权利要求19所述的方法，其中所述第二晶体管包括第二沟道高度，且所述第二沟道高度大体上等同于所述第一沟道高度。
21.根据权利要求19所述的方法，其中所述第一沟道高度大于所述离距的2倍。
22.根据权利要求19所述的方法，其中在所述衬底上所述形成所述第二晶体管包括从所述交替堆叠式鳍片释放纳米线。
23.根据权利要求19所述的方法，其中所述第一晶体管的所述鳍片包括SixGe1-x，X小于0.6。
24.根据权利要求19所述的方法，其中在所述第一晶体管区上方的所述交替堆叠式膜中所述形成所述沟槽包括去除所述交替堆叠式膜并获得具有锥形侧壁的所述沟槽。
25.一种混合半导体晶体管结构，其包括：
衬底；
在所述衬底上方的鳍片结构，其中所述鳍片结构具有沟道高度，所述鳍片结构从隔离突出，所述鳍片结构接触所述衬底的顶表面，且所述衬底的所述顶表面高于所述隔离的顶表面；
在所述衬底上方的纳米线的堆叠，其中所述沟道高度大于所述鳍片结构与所述纳米线的所述堆叠之间的横向距离；和
在所述纳米线上方的栅极堆叠，其中所述纳米线通过所述栅极堆叠的部分彼此分离。
26.根据权利要求25所述的结构，其中所述纳米线的所述堆叠的第二沟道高度大体上等于所述鳍片结构的所述沟道高度。
27.根据权利要求25所述的结构，其中所述鳍片结构是p型晶体管的部分，且所述纳米线的所述堆叠是n型晶体管的部分。
28.根据权利要求27所述的结构，其中所述鳍片结构的宽度小于所述纳米线中的一个的宽度。
29.根据权利要求25所述的结构，其中所述鳍片结构和所述衬底由不同材料制成。
30.根据权利要求29所述的结构，其中所述鳍片结构由SixGe1-x制成，X小于0.6。
31.根据权利要求25所述的结构，其中所述鳍片结构的所述沟道高度大于所述横向距离的2倍。
32.一种用于形成混合半导体晶体管结构的方法，其包括：
提供具有第一晶体管区和第二晶体管区的衬底；
在所述衬底上方外延地形成交替堆叠式膜；
在所述交替堆叠式膜中所述第一晶体管区上方形成沟槽；
在形成所述沟槽之后，在所述第二晶体管区上方图案化所述交替堆叠式膜以获得交替堆叠式鳍片；
在所述第一晶体管区上方用不同于所述衬底材料的材料填充所述沟槽；
在所述第一晶体管区上方图案化所述材料以获得鳍片；和
在所述鳍片和所述交替堆叠式鳍片上方形成虚拟栅极，其中所述虚拟栅极包括第一部分和第二部分，所述第一部分部分覆盖所述交替堆叠式鳍片，所述第二部分部分覆盖所述鳍片，且所述第一部分电连接至所述第二部分。
33.根据权利要求32所述的方法，其中在所述第二晶体管区上方所述图案化所述交替堆叠式膜和在所述第一晶体管区上方所述图案化所述材料同时进行。
34.根据权利要求32所述的方法，其进一步包括：
在所述第一晶体管区上方用掩模覆盖所述鳍片；
从所述交替堆叠式鳍片释放至少一个纳米线；和
在释放所述至少一个纳米线之后，去除覆盖所述鳍片的所述掩模。
35.根据权利要求32所述的方法，其中所述沟槽是朝向所述衬底逐渐变窄的锥形沟槽。
36.根据权利要求32所述的方法，其进一步包括：
在所述鳍片上方沉积第一虚拟栅极介电层；和
使所述鳍片退火，以便在所述鳍片上方形成所述虚拟栅极之前，将所述第一虚拟栅极介电层转变成第二虚拟栅极介电层，其中所述第二虚拟栅极介电层比所述第一虚拟栅极介电层厚。
37.根据权利要求32所述的方法，其进一步包括：
在所述鳍片上方沉积第一虚拟栅极介电层；
去除所述鳍片上方的所述虚拟栅极以暴露所述第一虚拟栅极介电层；
使所述鳍片退火，以便将所述第一虚拟栅极介电层转变成第二虚拟栅极介电层，其中所述第二虚拟栅极介电层比所述第一虚拟栅极介电层厚；和
去除所述第二虚拟栅极介电层。
38.一种用于形成混合半导体晶体管结构的方法，其包括：
提供具有第一晶体管区和第二晶体管区的衬底；
交替并依次沉积第一材料层和第二材料层，以在所述衬底的所述第一晶体管区和所述第二晶体管区上方形成交替堆叠式膜；
部分地去除所述交替堆叠式膜以在所述第一晶体管区上方形成沟槽；
在形成所述沟槽之后，在所述第二晶体管区上方图案化所述交替堆叠式膜以形成交替堆叠式鳍片；
用半导体材料填充所述沟槽；
图案化所述半导体材料以形成半导体鳍片；及
在所述半导体鳍片和所述交替堆叠式鳍片上方形成连续的虚拟栅极。
39.根据权利要求38所述的方法，其进一步包括：
形成介电层以环绕所述虚拟栅极；
在形成所述介电层之后去除所述虚拟栅极；和
在去除所述虚拟栅极之后，从所述交替堆叠式鳍片释放至少一个纳米线。
40.根据权利要求39所述的方法，其进一步包括：
在所述半导体鳍片上方沉积第一虚拟栅极介电层；和
使所述半导体鳍片退火，以便在所述形成所述虚拟栅极之前，将所述第一虚拟栅极介电层转变成第二虚拟栅极介电层，其中所述第二虚拟栅极介电层比所述第一虚拟栅极介电层厚。
41.根据权利要求39所述的方法，其进一步包括：
在所述半导体鳍片上方沉积第一虚拟栅极介电层；
去除所述虚拟栅极以暴露所述第一虚拟栅极介电层；
使所述半导体鳍片退火，以便将所述第一虚拟栅极介电层转变成第二虚拟栅极介电层，其中所述第二虚拟栅极介电层比所述第一虚拟栅极介电层厚；和
去除所述第二虚拟栅极介电层。
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