TW201946166A - 形成半導體元件的方法 - Google Patents
形成半導體元件的方法 Download PDFInfo
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- TW201946166A TW201946166A TW107132226A TW107132226A TW201946166A TW 201946166 A TW201946166 A TW 201946166A TW 107132226 A TW107132226 A TW 107132226A TW 107132226 A TW107132226 A TW 107132226A TW 201946166 A TW201946166 A TW 201946166A
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Abstract
一種方法包含:將裝置晶粒包封於包封材料中;在裝置晶粒以及包封材料上形成第一介電層;形成延伸至第一介電層內以電性耦接至裝置晶粒的第一重佈線;在第一介電層上形成對準標記,其中對準標記包含多個細長帶;在第一重佈線以及對準標記上形成第二介電層;以及形成延伸至第二介電層內以電性耦接至第一重佈線的第二重佈線。第二重佈線是使用對準標記來對準而形成。
Description
隨著半導體技術的發展,半導體晶片/晶粒正變得日益更小。同時,更多功能需要整合至半導體晶粒中。因此,半導體晶粒需要具有封裝於較小區中的日益更大數目個I/O襯墊,且I/O襯墊的密度隨時間推移而快速升高。結果,半導體晶粒的封裝變得較困難,此不利地影響封裝的良率。
習知封裝技術可劃分成兩個種類。在第一種類中,封裝晶圓上的晶粒,隨後進行鋸切。此封裝技術具有一些有利特徵,諸如,較大輸送量以及較低成本。另外,需要較少底填充料或模製化合物。然而,此封裝技術亦患有缺點。由於晶粒的大小正變得日益更小,且各別封裝體可僅為扇入型封裝體,其中每一晶粒的I/O襯墊限於在各別晶粒的表面正上方的區域。隨著晶粒的面積受限,I/O襯墊的數目歸因於I/O襯墊的間距限制而受到限制。若襯墊的間距將減小,則可能發生焊料橋接(solder bridge)。另外,在固定球大小要求下,焊球必須具有某一大小,此又限制可封裝於晶粒的表面上的焊球的數目。
在封裝的另一種類中,自晶圓鋸切出晶粒,隨後將其進行封裝。此封裝技術的有利特徵為形成扇出封裝體的可能性,此意謂可將晶粒上的I/O襯墊重新分佈至比晶粒大的區,且因此可增加封裝於晶粒的表面上的I/O襯墊的數目。此封裝技術的另一有利特徵為封裝「已知合格晶粒(known-good-die)」且拋棄有缺陷的晶粒,且因此不在有缺陷的晶粒上浪費成本以及精力。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。以下描述組件以及配置的具體實例以簡化本揭露內容。當然,此等僅為實例且並不意欲為限制性的。舉例而言,在以下描述中,第一特徵在第二特徵上方或上的形成可包含第一特徵以及第二特徵直接接觸地形成的實施例,且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露內容可在各種實例中重複參考數字及/或字母。此重複是出於簡單以及清晰起見,且本身並不規定所論述的各種實施例及/或組態之間的關係。
另外,為了易於描述,諸如「下伏」、「下方」、「下部」、「上覆」、「上部」以及類似者的空間相對術語可在本文中用以描述如在圖中說明的一個元件或特徵與另一元件或特徵的關係。除圖中所描繪的定向以外,空間相對術語意欲亦涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣地相應地進行解釋。
根據各種實施例提供包含具有格柵圖案的對準標記的積體扇出型(Integrated Fan-Out;InFO)封裝體以及其形成方法。根據一些實施例說明形成InFO封裝體的中間階段。論述一些實施例的一些變化。貫穿各視圖以及說明性實施例,相同的參考數字用以標明相似元件。
圖1至圖18說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。亦在圖30中繪示的製程流程300中示意性地說明圖1至圖18中繪示的步驟。
參看圖1,提供載體20,且在載體20上塗佈離型薄膜(release film)22。載體20由透明材料形成,且可為玻璃載體、陶瓷載體、有機載體或類似者。載體20可具有圓形俯視圖形狀,且可具有矽晶圓的大小。離型薄膜22與載體20的頂表面實體接觸。離型薄膜22可由光-熱轉換(Light-To-Heat-Conversion;LTHC)塗佈材料形成。離型薄膜22可經由塗佈而塗覆至載體20上。根據本揭露內容的一些實施例,LTHC塗佈材料在光/輻射(諸如,雷射束)的熱量下能夠分解,且因此可自其上形成的結構釋放載體20。
根據一些實施例,如亦在圖1中繪示,聚合物緩衝層24形成於LTHC塗佈材料22上。聚合物緩衝層24可由聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或另一可適用的聚合物形成。
圖2至圖4說明金屬柱32的形成。個別製程在圖30中所繪示的製程流程中說明為製程302。在通篇描述中,金屬柱32替代地被稱作穿孔32,這是由於金屬柱32穿透隨後施配的包封材料。
參看圖2,金屬晶種層25例如經由物理氣相沈積(Physical Vapor Deposition;PVD)形成。金屬晶種層25可與聚合物緩衝層24實體接觸。根據本揭露內容的一些實施例,金屬晶種層25包含鈦層以及在鈦層上的銅層。根據本揭露內容的替代性實施例,金屬晶種層25包含接觸緩衝介電層24的銅層。
如亦在圖2中繪示,光阻26形成於金屬晶種層25上。接著使用光微影罩幕(未繪示)對光阻26執行曝光。在隨後的顯影後,在光阻26中形成開口28。金屬晶種層25的一些部分經由開口28曝露。
接下來,如圖3中所繪示,藉由在開口28中電鍍金屬材料來形成金屬柱32。電鍍的金屬材料可為銅或銅合金。金屬柱32的頂表面低於光阻26的頂表面,使得金屬柱32由開口28限界。金屬柱32可具有實質上豎直且直的邊緣。替代地,金屬柱32在橫截面圖中可具有沙漏計時器形狀,其中金屬柱32的中間部分比各別頂部部分以及底部部分窄。
在後續步驟中,移除光阻26,且曝露金屬晶種層25的下伏部分。接著在蝕刻步驟中,例如在多個各向異性及/或各向同性蝕刻步驟中,移除金屬晶種層25的經曝露部分。剩餘晶種層25的邊緣因此實質上與金屬柱32的各別上覆部分共端。所得金屬柱32在圖4中說明。在通篇描述中,金屬晶種層25的剩餘部分被視為金屬柱32的部分,且不分開說明。金屬柱32的俯視圖形狀包含且不限於圓形形狀、矩形、六邊形、八邊形以及類似者。在形成金屬柱32之後,曝露聚合物緩衝層24。
圖5說明裝置晶粒36的置放/附著。個別製程在圖30中所繪示的製程流程中說明為製程304。裝置晶粒36經由為黏著膜的晶粒附著膜(Die-Attach Film;DAF)38附著至聚合物緩衝層24。DAF 38可預附著於裝置晶粒36,隨後將裝置晶粒36置放於聚合物緩衝層24上。因此,DAF 38與裝置晶粒36在附著至聚合物緩衝層24前組合成整合件。裝置晶粒36可包含具有與DAF 38實體接觸的背表面(面向下的表面)的半導體基底。裝置晶粒36可在半導體基底的前表面(面向上的表面)處包含積體電路裝置(諸如,主動裝置,其包含例如電晶體,未繪示)。根據本揭露內容的一些實施例,裝置晶粒36為邏輯晶粒,其可為中央處理單元(Central Processing Unit;CPU)晶粒、圖形處理單元(Graphic Processing Unit;GPU)晶粒、行動應用晶粒、微型控制單元(Micro Control Unit;MCU)晶粒、輸入輸出(input-output;IO)晶粒、基頻(BaseBand;BB)晶粒或應用程式處理器(Application processor;AP)晶粒。因為載體20處於晶圓級,所以儘管說明了一個裝置晶粒36,但多個相同的裝置晶粒36置放於聚合物緩衝層24上方,且可經分配為包含多列及多行的陣列。
根據一些實施例,金屬支柱42(諸如,銅支柱)預形成為裝置晶粒36的部分,且金屬支柱42電性耦接至積體電路裝置,諸如,裝置晶粒36中的電晶體(未繪示)。根據本揭露內容的一些實施例,諸如聚合物的介電材料填充相鄰金屬支柱42之間的間隙以形成頂部介電層44。頂部介電層44亦可包含覆蓋且保護金屬支柱42的部分。根據本揭露內容的一些實施例,聚合物層44可由PBO或聚醯亞胺形成。
接下來,將裝置晶粒36以及金屬柱32包封於包封材料48中,如圖6中所繪示。將個別製程在圖30中所繪示的製程流程中說明為製程306。包封材料48填充相鄰金屬柱32之間的間隙以及金屬柱32與裝置晶粒36之間的間隙。包封材料48可包含模製化合物、模製底填充料、環氧樹脂及/或樹脂。包封材料48的頂表面高於金屬支柱42的頂端。當由模製化合物形成時,包封材料48可包含基礎材料(其可為聚合物、樹脂、環氧樹脂或類似者),以及基礎材料中的填充劑粒子。填充劑粒子可為二氧化矽(SiO2
)、氧化鋁(Al2
O3
)、矽土(Silica)或類似者的介電粒子,且可具有球形形狀。又,球形填充劑粒子可具有多個不同的直徑。包封材料48中的填充劑粒子以及基礎材料皆可與聚合物緩衝層24實體接觸。
在後續步驟中,執行諸如化學機械拋光(Chemical Mechanical Polish;CMP)製程或機械研磨(Mechanical grinding)製程的平坦化製程以使包封材料48以及介電層44變薄,直至全部曝露金屬柱32以及金屬支柱42。將個別製程亦說明為圖30中繪示的製程流程中的製程306。歸因於平坦化製程,金屬柱32的頂端與金屬支柱42的頂表面實質上齊平(共面),且與包封材料48的頂表面實質上共面。在後續段落中,金屬柱32替代地被稱作穿孔32,這是由於其穿透包封材料48。
圖7至圖15說明前側重佈結構的形成。圖7至圖10說明第一重佈線(Redistribution Line;RDL)層、對準標記以及各別介電層的形成。參看圖7,形成介電層50。將個別製程說明為圖30中繪示的製程流程中的製程308。根據本揭露內容的一些實施例,介電層50由諸如PBO、聚醯亞胺或類似者的聚合物形成。所述形成方法包含以可流動形式塗佈介電層50,且接著固化介電層50。根據本揭露內容的替代性實施例,介電層50由諸如氮化矽、氧化矽或類似者的無機介電材料形成。形成方法可包含塗佈、化學氣相沈積(Chemical Vapor Deposition;CVD)、原子層沈積(Atomic Layer Deposition;ALD)、電漿增強型化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition;PECVD)或其他可適用的沈積法。接著形成通孔開口52。將個別製程亦說明為圖30中繪示的製程流程中的製程308。根據介電層50由諸如PBO或聚醯亞胺的光敏性材料形成的一些實施例,開口52的形成涉及使用微影罩幕(未繪示)以及顯影步驟的曝光。穿孔32以及金屬支柱42經由通孔開口52曝露。
接下來,參看圖8,沈積金屬晶種層54。根據本揭露內容的一些實施例,金屬晶種層54包含鈦層以及在鈦層上的銅層。形成方法可包含(例如)PVD。金屬晶種層54延伸至開口52內,且接觸穿孔32以及金屬支柱42。
圖9說明光阻56的形成以及圖案化。金屬晶種層54具有曝露於光阻56中的開口的一些部分。接著執行電鍍製程以形成金屬區域58。根據本揭露內容的一些實施例,金屬區域58包括銅或銅合金。電鍍可包含電化學電鍍或無電電鍍。
在後續製程中,移除光阻56,且曝露金屬晶種層54的下伏部分。接著執行蝕刻製程中的一個或多個以移除曝露的金屬晶種層54。根據一些實施例,執行第一蝕刻製程以蝕刻金屬晶種層54中的銅層,接著執行第二蝕刻製程以蝕刻金屬晶種層54中的鈦層。結果,形成RDL 60以及對準標記62,且所得結構繪示於圖10中。將個別製程說明為圖30中繪示的製程流程中的製程310。RDL 60以及對準標記62中的每一者包含金屬晶種層54的剩餘部分以及電鍍的金屬區域58的一部分。
RDL 60包含在介電層50中形成的通孔60A以連接至金屬支柱42或穿孔32,以及介電層50上的金屬跡線(金屬線)60B。雖未繪示,但金屬跡線60B自開口52(圖8)生長的部分的頂表面可凹陷低於金屬跡線60B直接上覆於介電層50的部分的頂表面。
對準標記62包含組合形成對準標記的多個格柵帶64。格柵帶64亦界定對準標記62的輪廓,且輪廓的形狀可用以識別對準標記62。對準標記62中的多個格柵帶64為電性浮動(electrically floating)。此外,對準標記62的帶64中的每一者可與其他導電性特徵充分隔離,惟對準標記62的其他部分除外。替代性地陳述,所有格柵帶64的頂表面、底表面以及側壁與介電材料或對準標記62的另一部分接觸。圖28A、圖28B、圖28C以及圖28D說明對準標記62的一些實例的俯視圖,所述對準標記各自包含多個細長金屬帶64。細長金屬帶64可彼此平行,其中每一者具有一致的寬度。細長金屬帶64可具有一致的節距,其中舉例而言,節距P1與P2彼此相等。根據本揭露內容的一些實施例,細長金屬帶64中的一些可具有與其他金屬帶64的節距不同的節距,例如,間距P1與P2彼此不同。
根據本揭露內容的一些實施例,對準標記62的寬度W1(以及W2)小,且可接近於對應的RDL的最小允許(或可形成的)寬度。舉例而言,寬度W1及/或W2可在最小寬度與最小寬度的約125%之間。最小寬度為金屬帶64的寬度,其為可使用對應的技術形成的對應的RDL的最小寬度,而不招致可靠性問題,諸如,金屬帶64與下伏介電層50(圖11)之間的分層(delamination),及/或金屬帶64與上覆介電層66(圖17)之間的分層。應瞭解,最小寬度與製程、生產工具以及金屬帶64與相鄰介電層的材料有關。舉例而言,對應的RDL的最小寬度可歸因於諸如光阻或微影製程的限制的製程因素。根據一些實施例,當金屬帶的寬度很小為約4 µm時,則觀測到分層。因此,寬度W3以及W4大於4 µm。根據一些實施例,寬度W3(以及W4)在約5 µm與約10 µm的範圍中。根據一些實施例,金屬帶64中的至少一些具有大於約5的長寬比。取決於對準標記62的大小,長寬比也可大於約10或更大,且對準標記62愈大,則長寬比可愈大。使帶64拉長允許使帶64的寬度最小化,而無分層方面的關注。否則,若對準標記62中的特徵64的長度與寬度兩者彼此接近,則需要使特徵64較大,以便無分層。根據本揭露內容的一些實施例,對準標記62的長度L1以及L2可在30 µm與約120 µm之間的範圍中,且對準標記62的寬度W1與W2可在20 µm與約120 µm的範圍中。
如圖28A中所繪示的對準標記62具有具特徵圖案的輪廓,在說明的實例中,所述特徵圖案具有字母「L」的形狀。對準標記62的特徵圖案可具有其他形狀,包含且不限於十字形、矩形、正方形或類似者。對準標記62的特徵圖案亦可具有其他字母的形狀,諸如,字母「H」、字母「A」、字母「C」等。為圖28A中的字母「L」的特徵圖案由金屬帶64的外輪廓界定。然而,格柵帶64自身不直接形成字母中的線。舉例而言,若字母「H」為特徵圖案,則由於H包含兩條豎直線以及連接兩條豎直線的水平線,因此兩條豎直線以及水平線中的每一者可包含多個離散格柵帶。
圖28B說明對準標記62的實例,其亦包含多個金屬帶64。為圖28B中的實例中的字母「L」的特徵圖案由金屬帶64中的空隙界定,其中金屬帶64不延伸至空隙內。替代性地陳述,如圖28B中所繪示的對準標記具有倒轉圖案,這是由於特徵圖案「L」由金屬帶64中的空隙而非金屬帶64界定。
圖28C說明連接金屬帶64以形成環的對準標記62。替代性地陳述,圖28C(以及圖28D)中的特徵圖案為具有沿著輪廓排列的格柵帶的中空圖案。在如所說明的實施例中,環完全閉合。根據其他實施例,環可部分閉合,例如,其中不形成說明的環中所說明的金屬帶64中的一個或兩個。圖28D說明連接金屬帶64以形成兩個環的對準標記62,其中外環圍住內環。根據本揭露內容的一些實施例,可存在並排置放的多個環(其中每一者類似於在圖28C中所繪示),且所述多個環組合形成對準標記62。可按任何方向、位置彼此相對地置放所述多個環。
圖29A-1、圖29A-2、圖29B-1、圖29B-2、圖29C-1及圖29C-2說明對準標記以及自對準標記量測的對應的信號的一些實例。圖29A-1、圖29B-1以及圖29C-1為對準標記。圖29A-2為自圖29A-1中繪示的對準標記獲得的亮度對比度的信號強度。圖29B-2為自圖29B-1中繪示的對準標記獲得的亮度對比度的信號強度。圖29C-2為自圖29C-1中繪示的對準標記獲得的亮度對比度的信號強度。亮度對比度的信號強度值表示當在圖29A-1、圖29A-1以及圖29C-1中的線110的位置自左至右掃描對準標記時亮度的對比度。因此,信號強度的最高峰值在對準標記的邊緣處。
參看圖29C-1,其說明塊狀對準標記,存在由線110穿過的兩個邊緣,其中一個在左側,且一個在右側。兩個邊緣的信號強度值在圖29C-2中反映為峰114。圖29C-1亦說明對準標記中的多個顆粒112。舉例而言,顆粒112可為銅顆粒。晶顆112和各別對準標記的周圍部分具有亮度差,此導致亮度的對比,且因此產生圖29C-2中的峰116。峰116低於峰114。峰114用以判定對準標記的邊界在何處,且峰116充當不利地影響對準標記邊界(因此,影像)的判定的雜訊。在製造過程中,可存在覆蓋對準標記的介電層(諸如,圖17中的層66、72以及76),從而使對準標記的影像模糊。因此將減小峰114與峰116的高度之間的差。此外,在某些製程步驟(諸如,圖22中繪示的步驟)中可損壞對準標記。此亦造成峰114與116的高度之間的差的減小。
參看圖29A-1,根據本揭露內容的一些實施例的金屬帶64具有小寬度,此意謂金屬帶64中的顆粒在窄金屬帶內部將受到限制。金屬帶64的粗糙度因此減小,且自晶界(而非金屬帶64的邊緣)產生的峰至少被降低,且可能被消除。圖29A-2示意性地說明自圖29A-1中繪示的對準標記62量測的信號強度的部分。觀測到,無峰自顆粒邊界產生,且因此自金屬帶的邊緣產生的信號更顯著,且更易於區分。此導致對準標記的成像的改良,這是由於對準標記的邊緣是經由亮度對比度的信號來辨識。
圖29B-2示意性地說明自具有倒轉圖案的圖29B-1中繪示的對準標記量測的亮度對比度的信號強度的部分。觀測到,自顆粒邊界產生的峰亦不存在,且因此自金屬帶的邊緣產生的信號更顯著,且更易於區分。
比較在圖29A-2、圖29B-2以及圖29C-2中繪示的信號,發現即使亮度對比度的信號因於較多上覆介電層及/或對準標記的損壞而比不上所繪示的清晰,圖29A-2以及圖29B-2中繪示的亮度對比度的信號用來判定對準標記的位置仍然比圖29C-2中繪示的信號容易得多。因此,具有格柵圖案的對準標記較諸如在圖29C-1中繪示的塊狀對準標記得以改良。
為了易於識別圖案,對準標記62可並非柵格圖案,所述柵格圖案包含第一多個平行帶以及與第一多個平行帶交叉且垂直的第二多個平行帶。柵格圖案使對準標記的區分更困難。
返回參看圖11,介電層66形成於圖10中繪示的結構上。將個別製程說明為在圖30中繪示的製程流程中的製程312。通孔開口68接著形成於介電層66中。將個別製程說明為在圖30中繪示的製程流程中的製程314。介電層66覆蓋對準標記62以及RDL 60。RDL 60的一些部分經由通孔開口曝露。介電層66可使用選自用於形成介電層50的相同候選材料群組的材料形成,所述材料可包含PBO、聚醯亞胺、BCB或其他有機或無機材料。
參看圖12,形成RDL 70。將個別製程亦說明為在圖30中繪示的製程流程中的製程314。RDL 70的形成製程可基本上與RDL 60的形成相同。RDL 70亦包含延伸至介電層66中的通孔開口內以接觸RDL 60的通孔部分,以及在介電層66正上方的金屬跡線部分。RDL 70的形成可包含形成金屬晶種層,形成經圖案化罩幕(諸如,光阻),電鍍RDL 70,以及接著移除經圖案化罩幕以及晶種層的不需要的部分。
在開口68(圖11)的形成以及RDL 70(圖12)的形成中,對準標記62用以將開口68的位置以及RDL 70的跡線部分對準至合乎需要的位置。在對準中,首先發現對準標記62,且接著基於對準標記62的位置判定開口68以及RDL 70的位置。應瞭解,在封裝體中可存在多個對準標記,其中每一個在各別晶粒的一側上。對準標記62是自頂部穿過透明(或至少部分透明)介電層66來檢視。藉由採用格柵圖案,對準標記62可清晰可見,且對準的準確度得以改良。
圖13說明介電層72在介電層66以及RDL 70上的形成。將個別製程說明為在圖30中繪示的製程流程中的製程316。接下來,通孔開口73形成於介電層72中。將個別製程說明為在圖30中繪示的製程流程中的製程318。介電層72可由選自用於形成介電層50以及66的相同候選材料群組的材料形成。
參看圖14,形成RDL 74。將個別製程亦說明為在圖30中繪示的製程流程中的製程318。RDL 74的形成製程可基本上與RDL 60的形成相同。RDL 74可由包含鋁、銅、鎢或其合金的金屬或金屬合金形成。應瞭解,雖然在實施例的說明的實例中,形成三個RDL層(60、70以及74),但封裝體可具有其他數目個RDL層,諸如,一個層、兩個層或多於三個層。
在RDL 74的形成中,對準標記62用以將RDL 74的位置(以及對應的通孔部分的位置)與RDL 70對準。對準標記62是自頂部穿過透明(或至少部分透明)介電層72以及66來檢視。藉由採用格柵圖案,對準標記62可穿過介電層72以及66而清晰可見(具有用於對準的量產工具所評定的高清晰度評分),且對準的準確度得以改良。作為比較,若採用諸如在圖29C-1中所繪示的塊狀圖案,則對準標記的判定較可能不合格。
圖15說明介電層76的形成。介電層76可由選自用於形成介電層50、66以及72的相同候選材料群組的材料形成。舉例而言,介電層76可使用PBO、聚醯亞胺或BCB形成。開口77形成於介電層76中以曝露為RDL 74的部分的下伏金屬襯墊。亦可使用用於對準的對準標記62來判定開口77的位置,穿過介電層76、72以及66,所述對準標記是可見的。
圖16說明根據一些實施例的凸塊下金屬層(Under-Bump Metallurgy;UBM)78的形成。將個別製程說明為在圖30中繪示的製程流程中的製程320。根據本揭露內容的一些實施例,UBM 78經形成以延伸至介電層76中的開口內以便接觸RDL 74中的金屬襯墊。UBM 78可由鎳、銅、鈦或其多層形成。根據一些實施例,UBM 78包含鈦層以及在鈦層上的銅層。
根據一些實施例,接著形成電連接器80。電連接器80的形成可包含將焊球置放於UBM 78的經曝露部分上,且接著回焊焊球。根據本揭露內容的替代性實施例,電連接器80的形成包含執行電鍍步驟以在UBM 78上方形成焊料層,且接著回焊焊料層。電連接器80亦可包含非焊料金屬柱,或金屬柱以及非焊料金屬柱上的焊蓋,其亦可經由電鍍形成。在通篇描述中,包含組合的介電緩衝層24以及上覆結構的結構被稱作封裝體100,其為包含多個裝置晶粒36的複合晶圓(且下文亦被稱作複合晶圓100)。
接下來,自載體20卸下複合晶圓100,例如,藉由將雷射束投影於離型薄膜22上。離型薄膜22在雷射束的熱量下分解。所得複合晶圓100說明於圖17中。接下來,在介電緩衝層24中形成開口82,例如,經由雷射鑽孔。當穿孔32在其底部包含鈦層且鈦層來自金屬晶種層25(圖2)時,可經由蝕刻移除鈦層,因此曝露穿孔32中的銅。
接著可在晶粒切割步驟中個體化複合晶圓100。將個別製程說明為在圖30中繪示的製程流程中的製程322。舉例而言,鋸片可將單獨的晶圓100的切割道84鋸穿成多個相同封裝體86,每一者具有如根據一些實例所說明的結構。晶粒切割可穿過對準標記62中的一些或所有。結果,所得封裝體86可包含對準標記62的部分,或不包含對準標記62的任何部分,這是由於已在晶粒切割中切割對準標記62。舉例而言,取決於切割,封裝體86可包含金屬帶64(圖28A至圖28D)中的一個或多個的全部,及/或可包含金屬帶64中的一個或多個的部分。舉例而言,在圖28A至圖28C中,可鋸切對準標記62的左部分,而對準標記62的右部分留在最終封裝體86中,或反之亦然。亦可能的是,鋸切對準標記62的上部部分,而對準標記62的下部部分留在最終封裝體86中,或反之亦然。對準標記62的鋸切百分比可為說明的部分的任一百分比。
圖18說明封裝體86經由焊料區域80結合至封裝體組件88。根據本揭露內容的一些實施例,封裝體組件88為封裝基底,其可為無芯基底或具有芯的基底。根據本揭露內容的其他實施例,封裝組件88是印刷電路板或封裝體。底填充料90可施配於封裝86與封裝組件88之間。封裝體86亦可經由焊料區域206結合至封裝體200。根據一些實施例,封裝體200包含裝置晶粒202以及基底204。晶粒202可為記憶體晶粒,諸如,動態隨機存取記憶體(Dynamic Random Access Memory;DRAM)晶粒。底填充料208可安置於封裝86與封裝200之間。圖18中的所得封裝被稱作封裝體220。
圖19至圖27說明根據本揭露內容的一些實施例的封裝體的形成中的中間階段的橫截面圖。除非另有指定,否則在此等實施例中的組件的材料以及形成方法基本上與由在圖1至圖18中繪示的實施例中的參考數字表示的相似組件相同。關於在圖19至圖27中繪示的組件的形成製程以及材料的細節可因此在圖1至圖18中繪示的實施例的論述中發現。
圖19以及圖20說明一些實施例。此等實施例類似於圖1至圖18中的實施例,惟介電層72以及76的部分開口以為了更清晰地檢視對準標記除外。所得封裝體86繪示於圖19中。封裝體86的形成製程類似於圖1至圖18中所繪示,惟形成開口94且開口94穿透介電層72以及76除外。開口94包含兩個部分,其中第一部分在介電層72中,且第二部分在介電層76中。在用於形成圖13中的開口73的相同製程中形成開口94的第一部分。修改微影罩幕使得當形成開口73時,形成開口94的下部部分。在用於形成圖15中的開口77的相同製程中形成開口94的第二部分。修改微影罩幕使得當形成開口77時,形成開口94的上部部分。由於介電層76將填充至開口94內,因此當形成開口94的上部部分時,亦移除介電層76中填充開口94的下部部分的部分。
圖20說明包含封裝體86以及結合至封裝體86的封裝體88以及200的封裝體220。底填充料90延伸至開口94的其餘口內(若留有任何者)。
圖21至圖27說明根據一些實施例的封裝體的形成中的中間階段。此等實施例類似於圖1至圖18中的實施例,惟介電層66、72以及76的在對準標記62正上方的部分皆開放以為了更清晰地檢視對準標記62除外。因此,當將對準標記62用於對準RDL 70、74與UBM 78的形成時,曝露對準標記62。
根據此等實施例的初始製程類似於在圖10中所繪示的製程。接下來,參看圖21,形成介電質66,接著形成開口68以及94。將對準標記62曝露於開口94。並且,介電層50的頂表面亦曝露於開口94。
圖22說明根據本揭露內容的一些實施例的金屬晶種層70A的形成,所述金屬晶種層可包含鈦層以及在鈦層上的銅層。金屬晶種層70A延伸至開口68以及94內。接下來,參看圖23,形成且接著圖案化光阻124。開口94全部由光阻124填充。
接下來,將金屬區域70B電鍍至光阻124中的開口內,接著移除光阻124。接著曝露金屬晶種層70A的一些部分。接著蝕刻金屬晶種層70A的經曝露部分,從而顯露下伏對準標記62。亦形成RDL 70,且其包含金屬晶種層70A以及金屬區域70B。在金屬晶種層70A的蝕刻中,對準標記62亦受到損壞。然而,藉由採用格柵圖案,對準標記62可仍然清晰地檢視到,甚至在有損壞的情況下亦如此。
圖25說明類似於圖16中所繪示的上覆結構的形成。在RDL 74以及UBM 78的形成期間,金屬晶種層(未繪示)亦可形成於對準標記62上且接著經蝕刻。對準標記62因此遭受進一步損壞。然而,藉由採用格柵圖案,對準標記62可仍然清晰地檢視到,甚至在有進一步損壞的情況下。圖26說明自各別載體20(圖25)卸下晶圓100,以及將晶圓100鋸切成封裝體86。所述鋸切穿過切割道84,且移除對準標記62中的一些或所有,如參看圖17所論述。圖27說明所得的封裝體220。
在實施例的以上說明的實例中,論述根據本揭露內容的一些實施例的製程以及特徵的一些實例。亦可包含其他特徵以及製程。舉例而言,可包含測試結構以輔助對3D封裝或3DIC裝置的驗證測試。測試結構可包含(例如)形成於重佈層中或基底上的測試襯墊,其允許測試3D封裝或3DIC、探針及/或探針卡的使用以及類似者。可對中間結構以及最終結構執行驗證測試。另外,本文中所揭露的結構以及方法可結合併有對已知合格晶粒的中間驗證的測試方法使用,以增大良率以及降低成本。
本揭露內容的實施例具有一些有利特徵。藉由採用格柵圖案以及形成用於對準標記的細長且更窄的帶,可易於區分對準標記。用於對準的量產工具可提供針對在封裝體的製造中檢視的對準標記的評分。評分範圍在0與100之間,其中評分0意謂無對準標記被發現,且評分100意謂完美的對準標記影像。具有超過70的評分的對準標記影像是可接受的。實驗結果揭示,當如29C-1中繪示的塊狀對準標記具有42或50的評分時(其意謂不可接受),當所有其他條件相同時,在圖29A-1以及圖29B-1中繪示的對準標記仍然具有高於約95的評分。並且,實驗結果揭示,即使在格柵對準標記上存在多個介電層,評分可仍然維持超過90。
根據本揭露內容的一些實施例,一種形成半導體元件的方法包含:將裝置晶粒包封於包封材料中;在裝置晶粒以及包封材料上形成第一介電層;形成延伸至第一介電層內以電性耦接至裝置晶粒的第一重佈線;在第一介電層上形成對準標記,其中對準標記包含多個細長帶;在第一重佈線以及對準標記上形成第二介電層;以及形成延伸至第二介電層內以電性耦接至第一重佈線的第二重佈線。第二重佈線是使用對準標記來對準而形成。在實施例中,形成第二重佈線包括在第二介電層中形成通孔開口,其中第一重佈線的部分曝露於通孔開口,且使用對準標記來對準而形成通孔開口。在實施例中,對準標記中的多個細長帶彼此平行,且彼此實體分開。在實施例中,對準標記中的多個細長帶互連以形成環。在實施例中,對準標記中的多個細長帶各自具有大於約5的長寬比。在實施例中,對準標記中的多個細長帶各自具有接近於對準標記的形成製程所允許的最小寬度的寬度。在實施例中,在共同形成製程中形成第一重佈線以及對準標記。在實施例中,在切割道中形成對準標記,且方法更包括切穿切割道以及對準標記。
根據本揭露內容的一些實施例,一種形成半導體元件的方法包含:在載體上形成穿孔;將裝置晶粒以及穿孔包封於包封材料中;形成在裝置晶粒、穿孔以及包封材料上且接觸裝置晶粒、穿孔以及包封材料的第一介電層;在第一介電層中形成第一通孔開口以顯露穿孔以及裝置晶粒的導電特徵;電鍍第一重佈線以及對準標記,其中第一重佈線包括延伸至第一通孔開口內的第一通孔部分,且對準標記包括彼此平行的第一多個細長帶;在第一介電層上形成第二介電層,其中對準標記以及第一重佈線的第一跡線部分內嵌於第二介電層中;在第二介電層中形成第二通孔開口以顯露第一重佈線,其中第二通孔開口是使用對準標記來對準而形成;以及電鍍第二重佈線,第二重佈線包括延伸至第二通孔開口內的第二通孔部分以及在第二介電層上的第二跡線部分。在實施例中,在形成第二通孔開口後,對準標記被第二介電層覆蓋。在實施例中,所述方法更包含:在第二介電層以及第二重佈線上形成第三介電層;在第三介電層中形成第三通孔開口以顯露第二重佈線,其中第三通孔開口是使用對準標記來對準而形成,且在形成第三通孔開口後,對準標記被第三介電層的一部分重疊;以及電鍍第三重佈線,第三重佈線包括延伸至第三通孔開口內的第三通孔部分以及在第三介電層上的第三跡線部分。在實施例中,在形成第二通孔開口後,再次顯露對準標記,且在電鍍第二重佈線中,形成接觸對準標記的用於電鍍第二重佈線的晶種層,且所述方法更包括蝕刻晶種層的與對準標記接觸的部分。在實施例中,所述方法更包含在第二介電層以及第二重佈線上形成第三介電層;在第三介電層中形成第三通孔開口以顯露第二重佈線,其中第三通孔開口是使用對準標記來對準而形成,且在形成第三通孔開口中,移除第三介電層在對準標記正上方的部分,且曝露第二介電層的頂表面;以及電鍍第三重佈線,第三重佈線包括延伸至第三通孔開口內的第三通孔部分以及在第三介電層上的第三跡線部分。在實施例中,對準標記更包括彼此平行的第二多個細長帶,且第一多個細長帶與第二多個細長帶連接以形成環。在實施例中,第一多個細長帶彼此分開且具有實質上一致的寬度。在實施例中,第一多個細長帶彼此分開且具有實質上一致的節距。
根據本揭露內容的一些實施例,一種形成半導體元件的方法包含:在第一介電層上電鍍對準標記,其中對準標記包括彼此平行的多個細長帶,且多個細長帶具有實質上一致的節距以及實質上一致的寬度;在第一介電層上形成多個重佈線,其中多個重佈線是使用對準標記來對準而形成;以及鋸穿第一介電層以及對準標記。在實施例中,形成對準標記包括:在第一介電層上形成晶種層;在晶種層上形成經圖案化罩幕,其中晶種層的部分經由經圖案化罩幕曝露;以及電鍍經圖案化罩幕中的對準標記的多個細長帶。在實施例中,對準標記隨著多個細長帶的一些中間部分被移除而具有空隙。在實施例中,多個細長帶包括具有第一長度的第一多個細長帶,以及具有大於第一長度的第二長度的第二多個細長帶。
前文概述若干實施例的特徵,使得熟習此項技術者可更佳地理解本揭露內容的態樣。熟習此項技術者應瞭解,其可易於使用本揭露內容作為設計或修改用於實現本文中所介紹的實施例的相同目的及/或達成相同優點的其他製程以及結構的基礎。熟習此項技術者亦應認識到,此類等效構造並不脫離本揭露內容的精神以及範疇,且熟習此項技術者可在不脫離本揭露內容的精神以及範疇的情況下在本文中進行各種改變、取代以及更改。
20‧‧‧載體
22‧‧‧離型薄膜/LTHC塗佈材料
24‧‧‧聚合物緩衝層
25‧‧‧金屬晶種層
26、124‧‧‧光阻
28、77、82、94‧‧‧開口
32‧‧‧金屬柱
36、202‧‧‧裝置晶粒
38‧‧‧晶粒貼合膜(DAF)
42‧‧‧金屬支柱
44‧‧‧頂部介電層
48‧‧‧包封材料
50、66、72、76‧‧‧介電層
52、68、73‧‧‧通孔開口
54、70A‧‧‧金屬晶種層
56‧‧‧光阻
58、70B‧‧‧金屬區域
60、70、74‧‧‧重佈線(RDL)
60A‧‧‧通孔
60B‧‧‧金屬跡線(金屬線)
62‧‧‧對準標記
64‧‧‧格柵帶
78‧‧‧凸塊下金屬層(UBM)
80‧‧‧電連接器
84‧‧‧切割道
86、200、220‧‧‧封裝體
88‧‧‧封裝體組件
90、208‧‧‧底填充料
100‧‧‧封裝體/複合晶圓
110‧‧‧線
112‧‧‧晶粒
114、116‧‧‧峰
204‧‧‧基底
206‧‧‧焊料區域
300‧‧‧製程流程
302-322‧‧‧步驟
L1、L2‧‧‧長度
W1、W2、W3、W4‧‧‧寬度
P1、P2‧‧‧節距
當結合附圖閱讀時,自以下詳細描述最佳地理解本揭露內容的態樣。應注意,根據行業中的標準實踐,各種特徵未按比例繪製。事實上,可出於論述清楚起見,而任意地增大或減小各種特徵的尺寸。 圖1至圖18說明根據一些實施例的封裝體的形成中的中間階段。 圖19以及圖20說明根據一些實施例的封裝體的形成中的中間階段。 圖21至圖27說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。 圖28A、圖28B、圖28C以及圖28D說明根據一些實施例的一些對準標記的俯視圖。 圖29A-1和圖29A-2說明分別根據一些實施例的對準標記以及對應的亮度對比度的信號強度。 圖29B-1以及圖29B-2說明分別根據一些實施例的對準標記以及對應的亮度對比度的信號強度。 圖29C-1以及圖29C-2說明分別根據一些實施例的具有倒轉圖案的對準標記以及對應的亮度對比度的信號強度。 圖30說明用於形成根據一些實施例的封裝體的製程流程。
Claims (20)
- 一種形成半導體元件的方法,包括: 將裝置晶粒包封於包封材料中; 在所述裝置晶粒以及所述包封材料上形成第一介電層; 形成延伸至所述第一介電層內以電性耦接至所述裝置晶粒的第一重佈線; 在所述第一介電層上形成對準標記,其中所述對準標記包括多個細長帶; 在所述第一重佈線以及所述對準標記上形成第二介電層;以及 形成延伸至所述第二介電層內以電性耦接至所述第一重佈線的第二重佈線,其中所述第二重佈線是使用所述對準標記來對準而形成。
- 如申請專利範圍第1項所述的方法,其中所述形成所述第二重佈線包括: 在所述第二介電層中形成通孔開口,其中所述第一重佈線的部分曝露於所述通孔開口,且所述通孔開口是使用所述對準標記來對準而形成。
- 如申請專利範圍第1項所述的方法,其中所述對準標記中的所述多個細長帶彼此平行,且彼此實體分開。
- 如申請專利範圍第1項所述的方法,其中所述對準標記中的所述多個細長帶互連以形成環。
- 如申請專利範圍第1項所述的方法,其中所述對準標記中的所述多個細長帶各自具有大於約5的長寬比。
- 如申請專利範圍第1項所述的方法,其中所述對準標記中的所述多個細長帶各自具有接近於所述對準標記的形成製程所允許的最小寬度的寬度。
- 如申請專利範圍第1項所述的方法,其中所述第一重佈線與所述對準標記是在共同形成製程中形成的。
- 如申請專利範圍第1項所述的方法,其中在切割道中形成所述對準標記,且所述方法更包括切穿所述切割道以及所述對準標記。
- 一種形成半導體元件的方法,包括: 在載體上形成穿孔; 將裝置晶粒以及所述穿孔包封於包封材料中; 形成在所述裝置晶粒、所述穿孔以及所述包封材料上且接觸所述裝置晶粒、所述穿孔以及所述包封材料的第一介電層; 在所述第一介電層中形成第一通孔開口以顯露所述穿孔以及所述裝置晶粒的導電特徵; 電鍍第一重佈線以及對準標記,其中所述第一重佈線包括延伸至所述第一通孔開口內的第一通孔部分,且所述對準標記包括彼此平行的第一多個細長帶; 在所述第一介電層上形成第二介電層,其中所述對準標記以及所述第一重佈線的第一跡線部分內嵌於所述第二介電層中; 在所述第二介電層中形成第二通孔開口以顯露所述第一重佈線,其中所述第二通孔開口是使用所述對準標記來對準而形成;以及 電鍍第二重佈線,所述第二重佈線包括延伸至所述第二通孔開口內的第二通孔部分以及在所述第二介電層上的第二跡線部分。
- 如申請專利範圍第9項所述的方法,其中在所述形成所述第二通孔開口後,所述對準標記被所述第二介電層覆蓋。
- 如申請專利範圍第9項所述的方法,更包括: 在所述第二介電層以及所述第二重佈線上形成第三介電層; 在所述第三介電層中形成第三通孔開口以顯露所述第二重佈線,其中所述第三通孔開口是使用所述對準標記來對準而形成,且在所述形成所述第三通孔開口後,所述對準標記被所述第三介電層的部分重疊;以及 電鍍第三重佈線,所述第三重佈線包括延伸至所述第三通孔開口內的第三通孔部分以及在所述第三介電層上的第三跡線部分。
- 如申請專利範圍第9項所述的方法,其中在所述形成所述第二通孔開口後,再次顯露所述對準標記,且在所述電鍍所述第二重佈線中,形成接觸所述對準標記的用於電鍍所述第二重佈線的晶種層,且所述方法更包括蝕刻所述晶種層的與所述對準標記接觸的部分。
- 如申請專利範圍第9項所述的方法,更包括: 在所述第二介電層以及所述第二重佈線上形成第三介電層; 在所述第三介電層中形成第三通孔開口以顯露所述第二重佈線,其中所述第三通孔開口是使用所述對準標記來對準而形成,且在所述形成所述第三通孔開口中,移除所述第三介電層在所述對準標記正上方的部分,且曝露所述第二介電層的頂表面;以及 電鍍第三重佈線,所述第三重佈線包括延伸至所述第三通孔開口內的第三通孔部分以及在所述第三介電層上的第三跡線部分。
- 如申請專利範圍第9項所述的方法,其中所述對準標記進一步包括彼此平行的第二多個細長帶,且所述第一多個細長帶與所述第二多個細長帶連接以形成環。
- 如申請專利範圍第9項所述的方法,其中所述第一多個細長帶彼此分開且具有實質上一致的寬度。
- 如申請專利範圍第9項所述的方法,其中所述第一多個細長帶彼此分開且具有實質上一致的節距。
- 一種形成半導體元件的方法,包括: 在第一介電層上電鍍對準標記,其中所述對準標記包括彼此平行的多個細長帶,且所述多個細長帶具有實質上一致的節距以及實質上一致的寬度; 在所述第一介電層上形成多個重佈線,其中所述多個重佈線是使用所述對準標記來對準而形成;以及 鋸穿所述第一介電層以及所述對準標記。
- 如申請專利範圍第17項所述的方法,其中所述形成所述對準標記包括: 在所述第一介電層上形成晶種層; 在所述晶種層上形成經圖案化罩幕,其中所述晶種層的部分經由所述經圖案化罩幕曝露;以及 電鍍所述經圖案化罩幕中的所述對準標記的所述多個細長帶。
- 如申請專利範圍第17項所述的方法,其中所述對準標記隨著所述多個細長帶的一些中間部分被移除而具有空隙。
- 如申請專利範圍第17項所述的方法,其中所述多個細長帶包括具有第一長度的第一多個細長帶以及具有大於所述第一長度的第二長度的第二多個細長帶。
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US11605597B2 (en) * | 2020-04-17 | 2023-03-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
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US11756871B2 (en) * | 2020-09-15 | 2023-09-12 | Sj Semiconductor (Jiangyin) Corporation | Fan-out packaging structure and method |
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TWI725901B (zh) * | 2019-12-31 | 2021-04-21 | 力成科技股份有限公司 | 封裝元件以及其製作方法 |
CN113130447A (zh) * | 2019-12-31 | 2021-07-16 | 力成科技股份有限公司 | 封装元件以及其制作方法 |
CN113130447B (zh) * | 2019-12-31 | 2024-04-05 | 力成科技股份有限公司 | 封装元件以及其制作方法 |
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TWI707413B (zh) | 2020-10-11 |
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