TW201943105A - Semiconductor device - Google Patents

Abstract

A semiconductor device includes: a semiconductor stack including a first region and a second region protruded from the first region and surrounded by the first region; a first contact structure disposed on the first region; and a first conductive structure including a first part and a second part connecting to the first part, wherein the first part is disposed on the first region and the second part is disposed on the second region, and the first conductive structure electrically connects to the first contact structure.

Description

Semiconductor element

The present application relates to a semiconductor device, and more particularly to a semiconductor device having a conductive structure.

The semiconductor element includes a compound semiconductor composed of III-V elements, such as gallium phosphide (GaP), gallium arsenide (GaAs), or gallium nitride (GaN). The semiconductor element may be an optoelectronic semiconductor element such as a light emitting diode (LED ), Laser, light detector, solar cell or power device. The structure of the light-emitting diode includes a p-type semiconductor layer, an n-type semiconductor layer, and an active layer. The active layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer, so that under an external electric field, n The electrons and holes provided by the p-type semiconductor layer and the p-type semiconductor layer are recombined in the active layer to convert electric energy into light energy. How to improve the photoelectric conversion efficiency of optoelectronic semiconductor components is really one of the focuses of R & D.

A semiconductor device includes: a semiconductor stack including a first region and a second region protruding from the first region, and the first region surrounds the second region; a first contact structure is disposed on the first region; and The first conductive structure includes a first portion and a second portion connected to the first portion, the first portion is provided on the first region, the second portion is provided on the second region, and the first conductive structure is electrically connected to the first portion One contact structure.

Please refer to FIGS. 1 to 3, which show a first embodiment of the semiconductor device 100 of the present application. The substrates 102 are not shown in FIGS. 2A to 2F. The semiconductor device 100 includes a substrate 102 and a semiconductor stack 103 formed on the substrate 102. The semiconductor stack 103 has a first semiconductor layer 104 on the substrate 102, an active structure 106 on the first semiconductor layer 104, and a second semiconductor layer 108 on the active structure 106. The first semiconductor layer 104 and the second semiconductor layer 108 respectively have a different first conductivity and a second conductivity to provide electrons and holes, or holes and electrons, respectively. The active structure 106 may include a single heterostructure, a double heterostructure, a multi-quantum well, or other structures. The semiconductor stack 103 has a first region 103a and a second region 103b that are different from the first region 103a. The second region 103b projects upward from the first region 103a and is connected by a sidewall region 103c to the first region 103a and the first region 103a. Two areas 103b. In detail, in this embodiment, the first region 103a includes the first semiconductor layer 104, and the second region 103b includes the first semiconductor layer 104, the active structure 106, and the second semiconductor layer 108, so that the height of the second region 103b is higher than An area 103a is high, as shown in FIG. In addition, as shown in FIGS. 1 and 2A, from a top view, the first region 103a of the semiconductor element 100 of this embodiment surrounds the second region 103b, and the semiconductor stack 103 is partially removed and the substrate is exposed. 102, so that the exposed surface of the substrate 102 surrounds the first region 103b. In detail, the first region 103 a may be formed by removing a portion of the second semiconductor layer 108 and the active structure 106 and exposing a portion of the first semiconductor layer 104. In the top view of the semiconductor device of the present application, the range of the first region is represented by a gray scale, thereby clearly defining the distribution positions of the first region and the second region.

The substrate 102 can support the semiconductor stack 103 and other layers or structures thereon. The substrate 102 can include an opaque material, a transparent material, a conductive material, a semiconductor material, or an insulating material. The semiconductor stack 103 can be grown on the substrate 102 or another growth substrate by an epitaxial method such as organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor epitaxy (HVPE). . If the semiconductor stack 103 is generated on a growth substrate, the semiconductor stack 103 can be bonded to the substrate 102 by a substrate transfer technology, and the growth substrate can be selectively removed. In the first embodiment, the semiconductor stack 103 is grown on a growth substrate, and then is bonded to the substrate 102 through an adhesive layer (not shown) through a substrate transfer technology. In this embodiment, the substrate 102 is, for example, a sapphire substrate, which is transparent to the light emitted by the active structure 106 as a light emitting structure. In addition, from a top perspective, the shape of the substrate 102 may be rectangular, square, diamond, circular, oval, or irregular. The substrate 102 of this embodiment is rectangular and has two long sides 102a and two short sides 102b. The intersection of each long side 102 a and each short side 102 b is a corner C of the substrate 102.

The materials of the first semiconductor layer 104, the second semiconductor layer 108, and the active structure 106 include Group III or Five compound semiconductors. For example, they can be: GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the examples disclosed in this disclosure, unless otherwise specified, the above chemical expressions include "chemically compliant compounds" and "non-chemically compliant compounds", where "chemically compliant compounds" are, for example, Group III elements The total element dose of is the same as the total element dose of the Group 5 element. On the contrary, the "non-chemically dosed compound" is, for example, that the total element dose of the Group 3 element is different from the total element dose of the Group 5 element. For example, the chemical formula is AlGaAs, which represents a total of three group elements (aluminum and / or gallium) and three group elements (aluminum and / or gallium). The elemental dose may be the same as or different from the total elemental dose of the five elements (arsenic). In addition, if each compound represented by the above chemical formula is a compound that meets the chemical dosage, AlGaAs represents Al _x1 Ga _(1-x1) As, where 0 ≦ x1 ≦ 1; AlInP represents Al _x2 In _{(1-x2 )} P, where 0 ≦ x2 ≦ 1; AlGaInP represents (Al _y1 Ga _(1-y1) ) _1-x3 In _x3 P, where 0 ≦ x3 ≦ 1, 0 ≦ y1 ≦ 1; AlGaN represents Al _x4 Ga _{( 1-x4)} N, where 0 ≦ x4 ≦ 1; AlAsSb stands for AlAs _x5 Sb _(1-x5) , where 0 ≦ x5 ≦ 1; InGaP stands for In _x Ga _1-x P, where 0 ≦ x6 ≦ 1 ; InGaAsP stands for In _x Ga _1-x6 As _1-y2 P _y2 , where 0 ≦ x6 ≦ 1, 0 ≦ y2 ≦ 1; InGaAsN stands for In _x Ga _1-x8 As _1-y3 N _y3 , where 0 ≦ x8 ≦ 1, 0 ≦ y3 ≦ 1; AlGaAsP stands for Al _x9 Ga _1-x9 As _1-y4 P _y4 , where 0 ≦ x9 ≦ 1, 0 ≦ y4 ≦ 1; InGaAs stands for In _x10 Ga _1-x10 As, where, 0 ≦ x10 ≦ 1. According to the material of the active structure 106, when the material of the semiconductor stack 100 is an AlGaInP series, the active structure 106 can emit infrared light having a peak wavelength between 700 and 1700 nm, and a wavelength between 610 nm and 700 nm. Red light, or yellow light with a peak wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 100 is an InGaN series, the active structure 106 can emit blue light, dark blue light with a peak wavelength between 400 nm and 490 nm, or green light with a peak wavelength between 490 nm and 550 nm. . When the semiconductor stack 100 is made of an AlGaN series, the active structure 106 can emit ultraviolet light having a peak wavelength between 250 nm and 400 nm.

In this embodiment, the material of the semiconductor stack 103 is an aluminum gallium indium phosphide series material. The semiconductor stack 103 is first formed on a gallium arsenide growth substrate (not shown) by epitaxial growth. The substrate 102 is connected to the first semiconductor layer 104 through a transparent adhesive layer (not shown), and finally the gallium arsenide growth substrate is removed. The first semiconductor layer 104 may be a p-type semiconductor layer, and the second semiconductor layer 108 may be an n-type semiconductor layer. In another embodiment, the substrate 102 is an epitaxial growth substrate, the first semiconductor layer 104 is an n-type nitride semiconductor layer, and the second semiconductor layer 108 is a p-type nitride semiconductor layer. The material of the substrate 102 can be selected. The material can be selected from sapphire, glass, silicon (Si), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs), phosphorous arsenide. Gallium (AsGaP), zinc selenide (ZnSe), zinc sulfide (ZnS), or silicon carbide (SiC).

In this embodiment, the semiconductor device 100 further includes a first contact structure 110 located on the first region 103 a of the semiconductor stack 103 and electrically connected to the first semiconductor layer 104. As shown in FIG. 1, the first contact structure 110 includes two first contact portions 1101 symmetrically located on the left and right sides of the second region 103 b to improve the uniform distribution of current, and the first contact portion 1101 is disposed adjacent to the substrate. 102's long side 102a. Each of the first contact portions 1101 in this embodiment includes a first end portion 1101a, a second end portion 1101b, and an intermediate portion 1101c located between the first end portion 1101a and the second end portion 1101b. The first end portion 1101a and the second end portion 1101b are closer to the corner C of the substrate 102 than the middle portion 1101c. In this embodiment, the first contact portion 1101 has an uneven width. Specifically, the first end portion 1101a of the first contact portion 1101 has a first width W1, and the middle portion 1101c has a second width W2. The first width W1, for example, each of the second end portion 1101b and the middle portion 110c has a second width W2 smaller than the first width W1. External current is injected into the first contact structure 110 through the first end portion 1101a, and the first end portion 1101a having a larger width can withstand a higher current density without being burned, thereby improving the durability of the semiconductor device 100. In another embodiment, the width of the first end portion 1101a and the second end portion 1101b is larger than the width of the middle portion 110c.

Referring to FIGS. 1 and 2C, the semiconductor device 100 of this embodiment further includes a second contact structure 112 located on the second region 103 b and formed on the second semiconductor layer 108. The second contact structure 112 is electrically connected to the second semiconductor layer 108 and is separated from the first contact structure 110. Viewed from the top, the second contact structure 112 and the second region 103b in this embodiment have similar outlines, and the second contact structure 112 is conformally formed on the second region 103b, and has a top-view area smaller than that of the first region 103b. One top view area of the two regions 103b. The second contact structure 112 in this embodiment is located between the two first contact portions 1101, and the first contact structure 110 is closer to the long side 102 a or the short side 102 b of the substrate 102 than the second contact structure 112. The second contact structure 112 of this embodiment is continuously formed on the second semiconductor layer 108. However, in another embodiment, as shown in FIG. 2C ′, the second contact structure 112 includes a plurality of second electrodes separated from each other. The contact portion 112a can further improve the current dispersion benefit. The materials of the first contact structure 110 and the second contact structure 112 are conductive, and the materials of the first contact structure 110 and the second contact structure 112 can be selected according to the material of the semiconductor stack 103, so that the first contact structure 110 and the first contact structure 110 and the second contact structure 112 are conductive. The two contact structures 112 form good electrical contacts with the first semiconductor layer 104 and the second semiconductor layer 108, such as ohmic contacts. For example, the first contact structure 110 may be selected from a beryllium gold alloy (BeAu), and the second contact structure 112 may be selected from a germanium gold alloy (GeAu). In this embodiment, the top-view area of the first contact structure 110 is smaller than the top-view area of the second contact structure 112, and the top-view area of the first contact structure 110 accounts for 5% of the top-view area of the second contact structure 112 ~ 30%, preferably 8% to 18%. The area ratio of the first contact structure 110 and the second contact structure 112 described above helps the semiconductor device 100 to achieve a better current dispersion effect.

Referring to FIG. 2D and FIG. 3, the semiconductor device 100 in this embodiment further includes a first protection structure 114 covering the first region 103 a, the second region 203 b, and the sidewall region 103 c of the semiconductor stack 103. The first protection structure 114 can protect the semiconductor stack 103 to increase the mechanical strength of the semiconductor device 100, and at the same time prevent the subsequent electrodes from making unexpected electrical connections with the semiconductor stack 103. The first protective structure 114 of this embodiment covers the semiconductor stack 103 and extends to the surface of the substrate 102, and a first opening 114a is formed on the first region 103a and a second opening 114b is formed on the second region 103b. The first opening 114 a exposes the first end portion 1101 a of the first contact structure 110 and the second opening 114 b exposes the second contact structure 112. The first protective structure 114 is a dielectric material and may optionally include magnesium oxide (MgO), SU8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), and acrylic resin ( Acrylic Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polymer Polyetherimide, Fluorocarbon Polymer, Glass, Ta ₂ O ₅ , Al ₂ O ₃ , Silicon Dioxide (SiO ₂ ), Titanium Oxide (TiO ₂ ), silicon nitride (SiN _x ), spin-on-glass (SOG), or tetraethoxy silicon (TEOS). In another embodiment, the first protection structure 114 includes a plurality of first dielectric layers and a plurality of second dielectric layers (not shown). Each of the first dielectric layers and the second dielectric layers overlap each other. The first dielectric layer and the second dielectric layer have different refractive indexes to form a distributed Bragg reflector structure, thereby increasing the mechanical strength of the first protective structure 114 to strengthen the semiconductor The protective property of the stack 103 is that when the semiconductor element 100 emits light from the direction of the substrate 102, the first protective structure 114 of the decentralized Bragg reflector structure also helps to reflect light to the light emitting surface, so as to increase the efficiency of the semiconductor element 100. For example, the first dielectric layer may be selected from silicon dioxide, the second dielectric layer may be selected from titanium dioxide, and the first protective structure 114 includes 10-50 layers of the first dielectric layer and the second dielectric layer overlapping each other. Layer, and the thickness of the first protective structure 114 is 3um-20um.

In this embodiment, the semiconductor device 100 further includes a first conductive structure 116. Please refer to FIGS. 1, 2E, and 3. The first conductive structure 116 is located on the semiconductor stack 103, extends from the first region 103 a to the second region 103 b, and covers the sidewall region 103 c of the semiconductor stack 103. Furthermore, the first conductive structure 116 is formed on the first protection structure 114 and is connected to the first contact structure 110 through the first opening 114 a of the first protection structure 114. The first conductive structure 116 is electrically connected to the first semiconductor layer 104 through the first end portion 1101 a of the first contact structure 110. In detail, the first conductive structure 116 includes a first portion 1161 and a second portion 1162 connected to the first portion 1161. The first portion 1161 is located on the first region 103a of the semiconductor stack 103 and is connected to the first contact structure 110 through the first opening 114a. The second portion 1162 is located on the second region 103 b of the semiconductor stack 103. In this embodiment, the first conductive structure 116 directly contacts the first end portion 1101a of the first contact structure 110, and the top view area of the first portion 1161 is smaller than the top view area of the second portion 1162. In this embodiment, the first conductive structure 116 includes a first conductive portion 116a and a first electrode portion 116b on the first conductive portion 116a, and each of the first conductive portion 116a and the second conductive portion 116b includes a plurality of layers. A metal stack of metal layers, and the shapes of the first conductive portion 116a and the first electrode portion 116b are defined through two photomasks respectively; or, in another embodiment, the first conductive structure 116 may include a plurality of metal layers A metal stack is formed on the semiconductor stack 103. The metal stack passes through a single photomask to define the shape of the first conductive structure 116. The first electrode portion 116b covers an upper surface 116a1 and a side surface 116a2 of the first conductive portion 116a, and the first electrode portion 116b and the first contact structure 110 are electrically connected to each other through the first conductive portion 116a. . In detail, as viewed from the top, as shown in FIG. 2E, the first conductive portion 116a has a first contour A1, and the first electrode portion 116b has a second contour B1 conformally formed outside the first contour A1. The second contour B1 surrounds the first contour A1, and the area of the first electrode portion 116b when viewed from above is larger than the area of the first conductive portion 116a from above. Covering the first conductive portion 116a by the first electrode portion 116b can increase the yield and durability of the semiconductor device 100. In detail, due to the height difference of the surface of the semiconductor element 100, the covering integrity of the first protective structure 114 in the sidewall region 103c of the semiconductor stack 103 is generally poor. Some gaps often exist in the first protective structure of the sidewall region 103c. In 114, when the semiconductor element is bonded to the carrier board (not shown in the figure), an adhesive or solder is drilled into the gap of the first protective structure 114, which causes electrical failure. The first conductive portion 116 a and the first electrode portion 116 b covering the first conductive portion 116 a in this embodiment can provide double protection to maintain the normal electrical properties of the semiconductor device 100. In more detail, since the first conductive portion 116a and the first electrode portion 116b are sequentially located on the sidewall region 103c covered with the first protection structure 114, when the subsequent semiconductor device 100 performs the flip-chip operation, the first electrode portion The barrier of 116b reduces the probability that the solder will damage the first conductive portion 116a and further penetrate into the gap of the first protective structure 114, thereby reducing the risk of failure of the device during the flip-chip operation, and improving the durability of the semiconductor device 100 ( reliability) and process yield (yield).

In this embodiment, the semiconductor device 100 further includes a second conductive structure 118. Referring to FIGS. 2E and 3, the second conductive structure 118 is located on the second region 103 b and is electrically connected to the second semiconductor layer 108 of the semiconductor stack 103. Similarly, the second conductive structure 118 may be formed through a single photomask or two photomasks, and its related description may refer to the description of the first conductive structure 116. In this embodiment, the second conductive structure 118 includes a second conductive portion 118a and a second electrode portion 118b on the second conductive portion 118a. The second electrode portion 118b covers an upper surface 118a1 and a side surface 118a2 of the second conductive portion 118a, and the second electrode portion 118b is electrically connected to the second conductive portion 118a. The second conductive portion 118a is electrically connected to the second contact structure 112 through the second opening 114b of the first protection structure 114. In detail, from a top perspective, as shown in FIG. 2E, the second conductive portion 118a has a third contour A2, and the second electrode portion 118b has a fourth contour B2 that is conformally located outside the third contour A2. That is, the fourth contour B2 surrounds the third contour A2, so that the area viewed from above of the second electrode portion 118b is larger than the area viewed from above of the second conductive portion 118a. The second conductive portion 118a and the second electrode portion 118b can increase the yield and durability of the semiconductor device 100. In this embodiment, the first conductive structure 116 and the second conductive structure 118 respectively have a first bonding surface F1 and a second bonding surface F2 far from the semiconductor stack 103, and the semiconductor element 100 passes through the first bonding surface F1 and the first bonding surface F1. The two bonding surfaces F2 are connected to the carrier board. During flip-chip bonding, the first bonding surface F1 and the second bonding surface F2 are in contact with a bonding agent or solder, so that the semiconductor element 100 is electrically connected to the carrier board by the bonding agent or solder, and light is directed from the direction of the substrate 102. Fire outward.

The above-mentioned first conductive structure 116 and second conductive structure 118 are separated from each other, so that the first conductive structure 116 and the second conductive structure 118 are electrically connected to the first semiconductor layer 104 and the second semiconductor layer 108, respectively, and the first conductive structure The structures 116 and the second conductive structures 118 have different top-view areas. The first conductive structure 116 in this embodiment has an area larger than that of the second conductive structure 118. . In this embodiment, the first conductive structure 116 and the second conductive structure 118 have different top-view shapes. For example, the first conductive structure 116 has an irregular top-view shape and includes two first portions 1161. The two portions 1162 extend toward the corner C, and the second conductive structure 118 has a substantially square shape when viewed from the top.

Referring to FIGS. 1 and 2F, the first conductive portion 116a and the second conductive portion 118a of this embodiment are separated, and both of them can be formed by a process at the same time, and then the first conductive portion is separated by a partial removal method. The portion 116a and the second conductive portion 118a. The first conductive portion 116a and the second conductive portion 118a have different top-view areas. The top-view area of the first conductive portion 116a in this embodiment is larger than the top-view area of the second conductive portion 118a. In addition, similarly, the first electrode portion 116b and the second electrode portion 118b are also separated from each other, and the two can be formed at the same time through a process, and then the first electrode portion 116b and the second electrode portion are separated by a partial removal method. Electrode section 118b. The first electrode portion 116b and the second electrode portion 118b have different top-view areas. The top-view area of the first electrode portion 116b in this embodiment is larger than the top-view area of the second electrode portion 118b. The first conductive portion 116a, the second conductive portion 118a, the first electrode portion 116b, and the second electrode portion 118b may have a single-layer or multi-layer structure. In one embodiment, the materials of the first electrode portion 116b and the second electrode portion 118b are different from the first conductive portion 116a and the second conductive portion 118a. For example, the first conductive portion 116a and the first electrode portion 116b have at least one difference. s material. The first conductive portion 116a and the second conductive portion 118a have substantially the same material, for example, a metal or an alloy, such as a metal such as titanium, gold, platinum, nickel, or an alloy of the foregoing metals, and the first conductive portion 116a and the second conductive portion 118a may be a laminated structure composed of a plurality of metal layers or alloy layers. The first electrode portion 116b and the second electrode portion 118b have substantially the same material, for example, a metal or an alloy, such as a metal such as gold, nickel, titanium, platinum, aluminum, tin, or an alloy of the foregoing metals, and the first electrode portion 116b The second electrode portion 118b may have a laminated structure composed of a plurality of metal layers or alloy layers.

As shown in FIG. 3, a distance D between the first conductive structure 116 and the second conductive structure 118 separated from each other is 10 mm to 90 mm to form a small-sized semiconductor element 100. There is a surface between the first conductive structure 116 and the second conductive structure 118, and the surface is a flat area F. The current semiconductor devices on the market are usually attached to a temporary film layer (such as a blue film), and then a thimble is applied to the temporary film layer during subsequent processing. The application point is roughly corresponding to the two electrodes of the semiconductor device ( For example: between the first conductive structure 116 and the second conductive structure 118), in this way, the semiconductor element is removed. In the semiconductor element 100 of the present invention, because there is a flat area between the first conductive structure 116 and the second conductive structure 118, when the semiconductor element 100 is removed using a thimble, the uneven force on the surface of the thimble due to fluctuations in the surface can be avoided. The risk of cracking the semiconductor element 100 is reduced. In addition, because the first protective structure 114 has a plurality of first dielectric layers and a plurality of second dielectric layers overlapping each other, it also helps to improve the thimble strength of the semiconductor stack 103.

In this embodiment, the first bonding surface F1 of the first electrode portion 116a and the second bonding surface F2 of the second electrode portion 118a are coplanar. Therefore, when the semiconductor device 100 is fixed on a carrier board in a flip-chip manner, the coplanar characteristics are favorable. In order to improve the joint yield of the semiconductor device 100 and the carrier.

In an embodiment, the sum of the top-view areas of the first conductive structure 116 and the second conductive structure 118 may account for more than 25% of the top-view area of the semiconductor stack 103, and more preferably 32% to 60%. The area of the first conductive structure 116 and the second conductive structure 118 effectively improves the yield and heat dissipation efficiency of the flip-chip bonding.

Referring to FIG. 2F and FIG. 3, the semiconductor device 100 may optionally include a second protective layer 124 covering the sidewall region 103c of the semiconductor stack 103, the surface of the first region 103a, and the surface of the second region 103b. . In detail, the second protective layer 124 covers the semiconductor stack 103, the first protective structure 114, the first conductive structure 116 and the second conductive structure 118. The second protective layer 124 has a third opening 124a to expose the first conductive structure 116, and a fourth opening 124b to expose the second conductive structure 118, so that the semiconductor device 100 can pass through the exposed first conductive structure 116 and the first The two conductive structures 118 are electrically connected to a carrier board (for example, a printed circuit board) having a circuit structure through solder.

In addition, the second protective layer 124 of this embodiment covers the edges of the first conductive structure 116 and the second conductive structure 118 to extend inwardly by a distance d, and the distance d is, for example, 3 to 10 μm to improve reliability. In this embodiment, the material and structure of the second protective layer 124 are different from those of the first protective structure 114. For example, the structure of the first protective structure 114 is a decentralized Bragg reflection structure, and the second protective structure 124 may be a single layer or Double layer. In addition, the material of the second protective structure 124 may include a dielectric material, such as silicon oxide, silicon nitride, or a combination of the two. In one embodiment, both the first protective structure 114 and the second protective structure 124 are decentralized Bragg reflective structures.

In one embodiment, the second protective structure 124 may be disposed between the first conductive portion 116a and the first electrode portion 116b, and between the second conductive portion 118a and the second electrode portion 118b, so that the first conductive portion 116a is located at Between the second protective layer 124 and the first protective layer 114. Compared with the second protective structure 124 formed on the first conductive structure 116 and the second conductive structure 118, when the second protective structure 124 is disposed between the first conductive portion 116a and the first electrode portion 116b, and the second conductive portion Between 118a and the second electrode portion 118b, the first bonding surface F1 and the second bonding surface F2 are completely exposed to increase the bonding area when bonding with the carrier plate and increase the bonding yield. In addition, the first protection structure 114 and the second protection structure 124 may have different top-view areas. For example, in one embodiment, the first protection structure 114 extends to the upper surface of the substrate 102 and contacts the substrate 102, and the second protection structure The edge of the structure 124 stays on the semiconductor stack 103 and does not extend to the substrate 102.

FIG. 4 is a schematic cross-sectional view of a second embodiment of the semiconductor device 200 of the present application. Each component of the semiconductor element 200 and its connection relationship are substantially the same as those of the semiconductor element 100 of the first embodiment. The number of each component in the second embodiment is changed from 1 to 2 in the first code of the corresponding component of the first embodiment. In detail, the semiconductor device 200 of this embodiment includes: a substrate 202 and a semiconductor stack 203 formed on the substrate 202. The semiconductor stack 203 has a first region 203a and a second region 203b different from the first region 203a. The semiconductor device 200 includes a first contact structure 210 on the first region 203a and a second contact structure 212 on the second region 203b. A first protection structure 214 covers the semiconductor stack 203 and a first conductive structure 216. A second conductive structure 218 is located on the semiconductor stack 203 and extends from the first region 203a to the second region 203b.

The main difference between this embodiment and the foregoing embodiment is that the semiconductor element 200 of this embodiment omits the first conductive portion and the second conductive electrical portion, in other words, the first conductive structure 216 includes only the first electrode equivalent to the first embodiment In the structure of the portion 116b, the second conductive structure 218 includes only the structure equivalent to the second electrode portion 118b in the first embodiment. The thickness of the first conductive structure 216 and the second conductive structure 218 is 1 to 5 um (for example, 1.5 um, 2 um, 3 um), so as to prevent solder from drilling into the gaps that may exist in the first protective structure 214 and to avoid short circuits. This happens during the flip-chip bonding process. In addition, in this embodiment, the second protection structure is omitted. When the first protection structure 214 is a Bragg reflection layer (DBR), a single first protection structure 214 may have high uniformity of coating and high structural strength. In order to save the process of forming the second protection structure.

FIG. 5 shows a top view of the semiconductor device 200 according to the second embodiment. 4 and 5, the second region 203b of the semiconductor stack 203 is surrounded by the first region 203a, and viewed from above, the second region 203b has a concave portion 203b1 and two convex portions 203b2 on both sides of the concave portion 203b1, The recessed portion 203b1 is separated from the long side 202a and the short side 202b of the substrate 202. The first contact structure 210 is located on the first region 203a, the second contact structure 212 is located on the second region 203b, and has a main body portion 2121 and two extension portions 2122 connected to the main body portion 2121. Each extension portion 2122 extends in a direction away from the main body portion 2121. The second contact structure 212 is closer to the edge of the substrate 202 than the first contact structure 210. The first protection structure 214 covers the semiconductor stack 203 and has a first opening 214a and a second opening 214b. The first opening 214a exposes the first contact structure 210 and the second opening 214b exposes the second contact structure 212, whereby the first conductive structure 216 and the second conductive structure 218 pass through the first opening 214a and the second opening 214b, respectively, and The first contact structure 210 and the second contact structure 212 are electrically connected. In the top view, the first opening 214 a has an area smaller than that of the first contact structure 210. Each of the first opening 214a and the second opening 214b has a first extension direction and a second extension direction. In this embodiment, the first extension direction is different from the second extension direction, and the first extension direction is parallel to that in FIG. 5. X axis, and the second extension direction is parallel to the Y axis, so that the first extension direction is perpendicular to the second extension direction; in other embodiments, the first extension direction is the same as the second extension direction.

FIG. 6 shows a top view of a third embodiment of the semiconductor device 300 of the present application. The cross-sectional view corresponding to FIG. 6 may be similar to FIG. 3 or FIG. 4. This embodiment is based on the first embodiment, and describes differences between this embodiment and the first embodiment.

The components of the semiconductor element 300 and their connection relationships in this embodiment are similar to those in the first embodiment, except that the second region 303b and the first contact structure 310 in this embodiment have special configurations. As shown in FIG. 6, viewed from above, the second region 303b has a stepped outline, and the width of the second region 303b can be gradually changed from one end to the other. For example, the second region 303b in this embodiment has The width of the three segments varies. In detail, viewed from above, the second region 303b has a first portion 303b1 having a first width D1, a second portion 303b2 has a second width D2, and a third portion 303b3 has a third width D3 And the second portion 303b2 is located between the first portion 303b1 and the third portion 303b3. The width of the second region 303b decreases or increases from the first portion 303b1 to the third portion 303b2, and the manner of reducing or increasing the width may be continuous or segmented. In this embodiment, the first width D1 is smaller than the second width D2, and the third width D3 is larger than the second width D2.

A first contact structure 310 is formed on the first region 303a, and the first contact structure 310 includes two first contact portions 3101 located symmetrically on the left and right sides of the second region 303b. Each first contact portion 3101 includes a first end portion. 3101a, a second end portion 3101b, and a middle portion 3101c are located between the first end portion 3101a and the second end portion 3101b. The width of the first end portion 3101a is larger than the second end portion 3101b and the middle portion 3101c, and the first end The portion 3101a is provided beside the first portion 303b1 of the second region 303b, and the middle portion 3101c and the second end portion 3101b are provided beside the second portion 303b2. In this embodiment, the first contact structure 310 does not extend to the left and right sides of the third portion 303b3, thereby retaining a larger area of the second semiconductor layer 308 to maintain the uniformity of current dispersion and increase the number of active structures. area. In addition, in the direction of the long side 302a of the substrate 302 (ie, along the Y-axis direction), the second region 303b has a first length L1, and the first contact portion 3101 of the first contact structure 310 has a second length L2 smaller than The first length L1 and the second length L2 are 30% to 60% of the first length L1, or the second length L2 is 35% to 50% of the first length L1. When the semiconductor element 300 is a light-emitting element and has a miniaturized size (for example, the long side is less than 10 mil), the semiconductor element 300 of this embodiment can have a relatively large thickness through the configuration design of the second region 303b and the first contact structure 310 described above. Large light emitting area while maintaining good current dispersion uniformity.

As in the first embodiment, the first conductive structure 316 in this embodiment includes a first conductive portion 316a having a first outline A1 and a first electrode portion 316b having a second outline A2, and the second outline B2 is conformable Ground is formed outside the first contour A1, and the second contour B1 surrounds the first contour A1. However, in another embodiment, as shown in the second embodiment, the first conductive structure 316 may define its pattern through a single photomask and be formed on the semiconductor stack 303, or may include only the first electrode portion 316b.

The present application further includes a light emitting module having the semiconductor element. The light-emitting module includes a plurality of semiconductor elements and a carrier board. The plurality of semiconductor elements may be arranged on the carrier board in a matrix manner, and the carrier board includes a circuit layer and is electrically connected to the plurality of semiconductor elements. Specifically, the light emitting module includes a plurality of packages disposed on a carrier board, and any package includes semiconductor elements having different emission wavelengths, such as a red light semiconductor element, a green light semiconductor element, and a blue light semiconductor element. And an encapsulant (such as silicon) for covering the semiconductor elements. The dominant wavelengths or peak wavelengths of the semiconductor devices of the respective colors are, for example, between 600 nm and 660 nm, between 515 nm and 575 nm, and between 430 nm and 490 nm to form a package that emits white light. And the light emitting module is used as a backlight module of a display, for example.

In another embodiment, the light emitting module can be directly used as a display panel of a display. The light emitting module has a plurality of pixels, and any pixel includes a plurality of semiconductor elements. For example, the pixel includes a red light semiconductor element, a green light semiconductor element, and a blue light semiconductor element.

However, the above are only the preferred embodiments of this application, and are not intended to limit the scope of implementation of this application. For example, all the shapes, structures, features and spirits described in the scope of the patent application for this application are equal Changes and modifications shall be included in the scope of patent application of this application.

100‧‧‧Semiconductor element

102‧‧‧ substrate

102a‧‧‧long side

102b‧‧‧short side

103‧‧‧Semiconductor stack

103a‧‧‧First Zone

103b‧‧‧Second Zone

103c‧‧‧Sidewall area

104‧‧‧First semiconductor layer

106‧‧‧ Luminous active layer structure

108‧‧‧Second semiconductor layer

110‧‧‧First contact structure

1101‧‧‧First contact

1101a‧‧‧First end

1101b‧‧‧Second end

1101c‧‧‧Middle

112‧‧‧Second contact structure

112a‧‧‧Second contact section

114‧‧‧first protective structure

114a‧‧‧First opening

114b‧‧‧Second opening

116‧‧‧first conductive structure

116a1‧‧‧ Top surface

116a2‧‧‧ side surface

1161‧‧‧Part I

1162‧‧‧Part Two

116a‧‧‧The first conductive part

116b‧‧‧First electrode section

118‧‧‧Second conductive structure

118a‧‧‧Second conductive section

118a1‧‧‧ Top surface

118a2‧‧‧ side surface

118b‧‧‧Second electrode section

124‧‧‧Second protective layer

124a‧‧‧Third opening

124b‧‧‧ Fourth opening

200‧‧‧Semiconductor

202‧‧‧ substrate

202a‧‧‧long side

202b‧‧‧short side

203‧‧‧Semiconductor Stack

203a‧‧‧First Zone

203b‧‧‧Second Zone

203c‧‧‧Sidewall area

203b1‧‧‧Concave

203b2‧‧‧ convex

204‧‧‧First semiconductor layer

205‧‧‧etching platform

206‧‧‧active structure

208‧‧‧Second semiconductor layer

210‧‧‧First contact structure

212‧‧‧Second contact structure

2121‧‧‧Main body

2122‧‧‧Extension

214‧‧‧first protective structure

214a‧‧‧First opening

214b‧‧‧Second opening

216‧‧‧First conductive structure

2161‧‧‧Part I

2162‧‧‧Part Two

218‧‧‧Second conductive structure

300‧‧‧Semiconductor

302‧‧‧ substrate

302a‧‧‧long side

302b‧‧‧short side

303a‧‧‧First Zone

303b‧‧‧Second Zone

303b1‧‧‧ the first part

303b2‧‧‧Second Part

303b3 ‧‧‧ third part

304‧‧‧First semiconductor layer

308‧‧‧Second semiconductor layer

310‧‧‧First contact structure

3101‧‧‧First contact

3101a‧‧‧first end

3101b‧‧‧Second end

3101c‧‧‧Middle

312‧‧‧Second contact structure

316‧‧‧first conductive structure

316a‧‧‧The first conductive part

316b‧‧‧First electrode section

3161‧‧‧ Part I

3162‧‧‧Part Two

318‧‧‧Second conductive structure

318a‧‧‧Second Conductive Section

318b‧‧‧Second electrode section

A1‧‧‧First contour

B1‧‧‧Second outline

A2‧‧‧ Third contour

B2‧‧‧ Fourth contour

C‧‧‧ Corner

W1‧‧‧first width

W2‧‧‧Second width

F‧‧‧ flat area

F1‧‧‧First joining surface

F2‧‧‧Second joint surface

D‧‧‧Pitch

d‧‧‧distance

D1‧‧‧first width

D2‧‧‧Second width

D3‧‧‧ Third width

L1‧‧‧first length

L2‧‧‧Second Length

FIG. 1 is a schematic top view of a first embodiment of a semiconductor device of the present application.

Figures 2A to 2F are manufacturing flowcharts of the semiconductor device disclosed in the first embodiment of the present application.

Fig. 3 is a side sectional view of Fig. 1 cut along the AA 'section line.

FIG. 4 is a side sectional view of a second embodiment of the semiconductor device of the present application.

FIG. 5 is a schematic top view of a second embodiment of a semiconductor device of the present application.

FIG. 6 is a schematic top view of a third embodiment of the semiconductor device of the present application.

(no)

(no)

Claims (20)

A semiconductor device includes: a semiconductor stack including a first region and a second region, the second region protruding from the first region, and the first region surrounding the second region; a first contact structure provided On the first area; and a first conductive structure includes a first portion and a second portion connected to the first portion, the first portion is provided on the first area, and the second portion is provided on the first area Two regions, and the first conductive structure is electrically connected to the first contact structure. A semiconductor device according to claim 1, wherein a top view area of the first portion of the first conductive structure is smaller than a top view area of the second portion. A semiconductor device according to claim 1, wherein the first conductive structure includes a first conductive portion and a first electrode portion on the first conductive portion. A semiconductor device according to claim 3, wherein the first electrode portion and the first contact structure are electrically connected by the first conductive portion. A semiconductor device according to claim 3, wherein a top-view area of the first electrode portion is larger than a top-view area of the first conductive portion. A semiconductor device according to claim 3, wherein the first electrode portion covers the first conductive portion. A semiconductor device according to claim 1, further comprising a second conductive structure separated from the first conductive structure, and a flat area between the first conductive structure and the second conductive structure. A semiconductor device according to claim 1, wherein the first contact structure includes two first contact portions that are symmetrical. A semiconductor device according to claim 1, further comprising a second contact structure located in the second region, and the second contact structure is separated from the first contact structure. A semiconductor device according to claim 9, wherein the second contact structure includes a plurality of second contact portions separated from each other. A semiconductor device according to claim 9, wherein a top-view area of the first contact structure is smaller than a top-view area of the second contact structure. A semiconductor device according to claim 9, wherein the top-view area of the first contact structure is 5% -30% of the top-view area of the second contact structure. A semiconductor device according to claim 1, further comprising a second conductive structure electrically connected to the second region of the semiconductor stack, and a top area of the first conductive structure is different from that of the second conductive structure. Looking up area. A semiconductor device according to claim 13, wherein a top-view area of the first conductive structure is larger than a top-view area of the second conductive structure. A semiconductor device according to claim 13, wherein a top view shape of the first conductive structure is different from a top view shape of the second current structure when viewed from above. A semiconductor device according to claim 1, further comprising a first protection structure located between the first contact structure and the first conductive structure, and the first protection structure includes an insulating material. A semiconductor device according to claim 16, wherein the first protection structure includes a plurality of first dielectric layers and a plurality of second dielectric layers that overlap each other. A semiconductor device according to claims 16 and 17, wherein the first protective structure covers the first region, the second region, and a sidewall between the first region and the second region of the semiconductor stack. region. A semiconductor device according to claim 1, wherein the second region has a gradual width. A semiconductor device according to claim 1 or 19, wherein the second region has a first length, the first contact structure has a second length, and the second length is 30% to the first length ~ 60%.