KR20230086645A - Light-emitting device - Google Patents

Abstract

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer positioned between the first semiconductor layer and the second semiconductor layer; a first bonding pad positioned on the semiconductor stack; a second bonding pad positioned on the semiconductor stack, spaced apart from the first bonding pad, and defining a region located between the first bonding pad and the second bonding pad on the semiconductor stack; and a plurality of holes penetrating the active layer to expose the first semiconductor layer, and on a plan view of the light emitting device, the first bonding pad and the second bonding pad are formed in regions other than the plurality of hole portions.

Description

Light emitting device {LIGHT-EMITTING DEVICE}

The present invention relates to a light emitting device, and more particularly, to a light emitting device including a semiconductor stack and a bonding pad positioned on the semiconductor stack.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting device, and its advantages are low power consumption, low heat energy generated, long operating life, vibration resistance, small volume, and fast reaction speed. It has good photoelectric properties (for example, a stable emission wavelength). Therefore, light emitting diodes are widely used in home appliances, equipment lamps, and photoelectric products.

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer positioned between the first semiconductor layer and the second semiconductor layer; a first bonding pad positioned on the semiconductor stack; a second bonding pad positioned on the semiconductor stack; A plurality of holes passing through the active layer to expose the first semiconductor layer, wherein the first bonding pad and the second bonding pad are separated from each other by a distance between the first bonding pad and the second bonding pad on the semiconductor stack. , and on a plan view of the light emitting device, the first bonding pad and the second bonding pad are formed in an area other than the plurality of hole positions.

The light emitting device includes a semiconductor stack, a first contact layer, a second contact layer, a first bonding pad, and a second bonding pad, wherein the semiconductor stack comprises a first semiconductor layer, a second semiconductor layer, and a first semiconductor layer and a second bonding pad. An active layer positioned between the semiconductor layers, the first contact layer being located on the second semiconductor layer and connected to the first semiconductor layer while surrounding sidewalls of the second semiconductor layer, the second contact layer is Located on the second semiconductor layer and connected to the second semiconductor layer, the first bonding pad is located on the semiconductor stack and connected to the first contact layer, the second bonding pad is located on the semiconductor stack and connected to the second contact layer, , The first bonding pad and the second bonding pad are spaced apart from each other to define a region located between the first bonding pad and the second bonding pad on the semiconductor stack, and on the plan view of the light emitting device, on the second semiconductor layer. The first contact layer positioned at surrounds the second contact layer.

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer positioned between the first semiconductor layer and the second semiconductor layer; a first bonding pad electrically connected to the first semiconductor layer; a second bonding pad electrically connected to the second semiconductor layer; and a metal layer located on the semiconductor stack, surrounding a plurality of sidewalls of the second bonding pad, and spaced apart from the second bonding pad at a distance.

The light emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer positioned between the first semiconductor layer and the second semiconductor layer; a first contact layer positioned on the semiconductor stack; a first bonding pad disposed on the first contact layer and including a side surface; a second bonding pad positioned on the semiconductor stack; An insulating layer including a first portion covered by the first bonding pad and a connection portion adjacent to a side of the first bonding pad, wherein the insulating layer exposes the first contact layer and the first portion and the connection portion. and an opening located between the first side of the first part and the side of the connecting portion, and the side of the first bonding pad is less than 100 μm from the first side of the first portion or the side of the connecting portion. separated by a small distance.

1A to 7C are diagrams illustrating a manufacturing method of a light emitting device 1 or a light emitting device 2 disclosed in an embodiment of the present invention.
8 is a plan view of a light emitting device 1 disclosed in one embodiment of the present invention.
9A is a cross-sectional view of a light emitting device 1 disclosed in one embodiment of the present invention.
9B is a cross-sectional view of a light emitting device 1 disclosed in one embodiment of the present invention.
10 is a plan view of a light emitting device 2 disclosed in one embodiment of the present invention.
11A is a cross-sectional view of a light emitting device 2 disclosed in one embodiment of the present invention.
11B is a cross-sectional view of a light emitting device 2 disclosed in one embodiment of the present invention.
12A to 18B are diagrams showing a manufacturing method of a light emitting device 3 or a light emitting device 4 disclosed in an embodiment of the present invention.
19 is a plan view of a light emitting device 3 disclosed in one embodiment of the present invention.
20 is a cross-sectional view of a light emitting device 3 disclosed in one embodiment of the present invention.
21 is a plan view of a light emitting device 4 disclosed in one embodiment of the present invention.
22 is a cross-sectional view of a light emitting device 4 disclosed in one embodiment of the present invention.
23 is a cross-sectional view of a light emitting device 5 disclosed in one embodiment of the present invention.
24 is a cross-sectional view of a light emitting device 6 disclosed in one embodiment of the present invention.
25 to 33b are diagrams illustrating a method of manufacturing a light emitting device 7 and a structure of the light emitting device 7 disclosed in an embodiment of the present invention.
34A is a plan view of a light emitting device 8 disclosed in one embodiment of the present invention.
34B is a cross-sectional view of a light emitting device 8 disclosed in one embodiment of the present invention.
35 is a structural schematic diagram of a light emitting device according to an embodiment of the present invention.
36 is a structural schematic diagram of a light emitting device according to an embodiment of the present invention.

In order to make the description of the present invention more detailed and complete, the description of the embodiments below is referred to and related drawings are combined. However, the following examples are only for exemplifying the light emitting device of the present invention, and are not intended to limit the present invention. In addition, the size, material, shape, relative arrangement, etc. of the constituent parts described in the embodiments of this specification do not limit the scope of the present invention unless otherwise specifically limited, and are merely descriptions. In addition, the size, positional relationship, etc. of the members shown in each figure may be exaggerated to make the explanation clearer. In the following description, the same names and symbols are used to appropriately omit detailed descriptions of components of the same or identical properties.

1A to 11B are diagrams illustrating a manufacturing method of a light emitting device 1 or a light emitting device 2 disclosed in an embodiment of the present invention.

As shown in FIG. 1B, which is a plan view of FIG. 1A and a cross-sectional view taken along the line AA' of FIG. 1A, the method of manufacturing the light emitting device 1 or the light emitting device 2 includes a platform forming step, and the platform is formed. The steps include providing a substrate 11a; and forming a semiconductor layer 10a on the substrate 11a, wherein the semiconductor layer 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, and a first semiconductor layer 101a. and an active layer 103a positioned between the second semiconductor layer 102a. The semiconductor stack 10a is patterned by lithography and etching to partially remove the second semiconductor layer 102a and the active layer 103a to form one or more semiconductor structures 1000a; and a surrounding portion 111a surrounding one or more semiconductor structures 1000a. The surrounding portion 111a exposes the first surface 1011a of the first semiconductor layer 101a. Each of the one or more semiconductor structures 1000a includes a first outer wall 1003a, a second outer wall 1001a, and an inner wall 1002a, the first outer wall 1003a comprising a first semiconductor layer 101a. , the second outer wall 1001a is a sidewall of the active layer 103a and/or the second semiconductor layer 102a, and one end of the second outer wall 1001a is the surface 102s of the second semiconductor layer 102a. is connected to, the other end of the second outer wall 1001a is connected to the first surface 1011a of the first semiconductor layer 101a, and one end of the inner wall 1002a is connected to the surface 102s of the second semiconductor layer 102a. ), the other end of the inner wall 1002a is connected to the second surface 1012a of the first semiconductor layer 101a, and the plurality of semiconductor structures 1000a are connected to each other by the first semiconductor layer 101a. do. As shown in FIG. 1B, the inner wall 1002a of the semiconductor structure 1000a and the second surface 1012a of the first semiconductor layer 101a form an obtuse angle, and the first outer wall 1003a of the semiconductor structure 1000a and The surface 11s of the substrate 11a forms an obtuse angle or a right angle, and the second outer wall 1001a of the semiconductor structure 1000a and the first surface 1011a of the first semiconductor layer 101a form an obtuse angle. The surrounding portion 111a surrounds the periphery of the semiconductor structure 1000a, and the surrounding portion 111a has a rectangular or polygonal shape in a plan view of the light emitting device 1 or the light emitting device 2.

In one embodiment of the present invention, the light emitting element 1 or the light emitting element 2 has a side length of less than 30 mils. When an external current is injected into the light emitting element 1 or the light emitting element 2, the surrounding portion 111a surrounds the semiconductor structure 1000a, so that the light emitting element 1 or the light emitting element 2 A light field distribution can be made uniform, and a forward voltage of a light emitting device can be reduced.

In one embodiment of the present invention, light emitting element 1 or light emitting element 2 has a side length greater than 30 mils. The semiconductor layer 10a is patterned by lithography and etching to partially remove the second semiconductor layer 102a and the active layer 103a, and at least one hole penetrating the second semiconductor layer 102a and the active layer 103a. 100a, and one or more holes 100a expose one or more second surfaces 1012a of the first semiconductor layer 101a. When an external current is injected into the light emitting element 1 or the light emitting element 2, the light emitting element 1 or the light emitting element 2 is lighted by the distributed arrangement of the surrounding part 111a and the plurality of hole parts 100a. The field distribution can be made uniform and the forward voltage of the light emitting device can be reduced.

In one embodiment of the present invention, the light emitting element 1 or the light emitting element 2 has a side length of less than 30 mil, and the light emitting element 1 or the light emitting element 2 is one to increase the light emitting area of the active layer The above hole portion 100a may not be included.

In one embodiment of the present invention, the opening shape of the one or more holes 100a includes circular, elliptical, rectangular, polygonal, or arbitrary shapes. The plurality of hole parts 100a may be arranged in a plurality of rows, and the hole parts 100a on two adjacent rows may be arranged side by side or offset from each other.

In one embodiment of the present invention, the substrate 11a is a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), a sapphire (Al2O3) wafer for growing indium gallium nitrogen (InGaN), or a gallium nitride (GaN). ) wafer or a growth substrate including a silicon carbide (SiC) wafer. Here, on the substrate 11a, using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial method (MBE), hydride vapor deposition (HVPE), evaporation or ion plating, light-emitting lamination, etc. A semiconductor stack 10a having photoelectric properties may be formed.

In one embodiment of the present invention, the first semiconductor layer 101a and the second semiconductor layer 102a are, for example, cladding layers or confinement layers, and both have different conductivity types and electrical characteristics. It can provide electrons or holes according to the element having quality, polarity or doping. For example, the first semiconductor layer 101a is an n-type semiconductor and the second semiconductor layer 102a is a p-type semiconductor. it is a semiconductor The active layer 103a is formed between the first semiconductor layer 101a and the second semiconductor layer 102a, and electrons and holes recombine in the active layer 103a under the driving of current, converting electrical energy into light energy and ray emits The wavelength of light emitted from the light emitting element 1 or the light emitting element 2 is controlled by changing the physical and chemical composition of a single layer or multiple layers of the semiconductor stack 10a. The material of the semiconductor stack 10a includes a III-V group semiconductor material, for example, AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0x,y1; (x+y)1. Depending on the material of the active layer 103a, when the material of the semiconductor layer 10a is an AlInGaP-based material, red light with a wavelength of 610 nm to 650 nm and green light with a wavelength of 530 nm to 570 nm can be emitted, When the material of (10a) is an InGaN-based material, blue light having a wavelength of 450 nm to 490 nm can be emitted, and when the material of the semiconductor layer 10a is an AlGaN-based material, a blue light having a wavelength of 400 nm to 250 nm can be emitted. It can emit external light. The active layer 103a is a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), multi-quantum well (MQW) ) can be. The material of the active layer 103a may be a semiconductor having neutral, p-type or n-type electrical characteristics.

Following the platform formation step, the manufacturing method of the light emitting device 1 or the light emitting device 2 is a first insulating layer, as shown in FIG. 2B, which is a plan view of FIG. Including the forming stage. The first insulating layer 20a may be formed on the semiconductor structure 1000a by evaporation or deposition, and the first surface 1011a of the surrounding portion 111a and the hole portion ( Lithography to cover the second surface 1012a of 100a, and to cover the second semiconductor layer 102a of the semiconductor structure 1000a, the second outer wall 1001a and the inner wall 1002a of the active layer 103a, Patterned by an etching method, the first insulating layer 20a covers the first surface 1011a of the first semiconductor layer 101a located in the surrounding portion 111a. a first insulating layer surrounding region 200a covering; a first group of first insulating layer cover regions 201a covering the hole portion 100a so as to cover the second surface 1012a of the first semiconductor layer 101a located in the hole portion 100a; and a second group of first insulating layer openings 202 exposing the surface 102s of the second semiconductor layer 102a. The first insulating layer cover regions 201a of the first group are separated from each other and each correspond to a plurality of hole portions 100a. The first insulating layer 20a may have a single-layer or multi-layer structure. When the first insulating layer 20a is a single-layer film, the first insulating layer 20a protects the sidewall of the semiconductor structure 1000a to prevent the active layer 103a from being damaged in a subsequent manufacturing process. When the first insulating layer 20a is a multilayer film, the first insulating layer 20a is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure, thereby selectively emitting light of a specific wavelength. can reflect The first insulating layer 20a is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, and organic materials such as fluorocarbon polymer, or silicone, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, following the first insulating layer forming step, the method of manufacturing the light emitting device 1 or the light emitting device 2 is a plan view of FIG. 3A and a cross-sectional view taken along line AA' of FIG. 3A. As shown in 3b, a transparent conductive layer forming step is included. The transparent conductive layer 30a may be formed in the first insulating layer opening 202a of the second group by evaporation or deposition or the like, and the outer edge 301a of the transparent conductive layer 30a and the first insulating layer 20a are spaced apart from each other to expose the surface 102s of the second semiconductor layer 102a. Since the transparent conductive layer 30a is formed on almost the entire surface of the second semiconductor layer 102a and contacts the second semiconductor layer 102a, the transparent conductive layer 30a allows current to pass through the entire surface of the second semiconductor layer 102a. can be spread evenly. The material of the transparent conductive layer 30a includes a material that is transparent to light emitted from the active layer 103a, and the transparent material is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer may be omitted, and the step of forming the transparent conductive layer may be directly performed.

In one embodiment of the present invention, the manufacturing method of the light emitting element 1 or the light emitting element 2 following the step of forming the transparent conductive layer is shown in a plan view of FIG. As shown in , a reflective structure forming step is included. The reflective structure includes a reflective layer 40a and/or a barrier layer 41a, and may be directly formed on the transparent conductive layer 30a by evaporation or deposition, and the reflective layer 40a is formed on the transparent conductive layer 30a. and the barrier layer 41a. In a plan view of the light emitting element 1 or the light emitting element 2, the outer edge 401a of the reflective layer 40a is provided inside or outside the outer edge 301a of the transparent conductive layer 30a, or the transparent conductive layer 30a ) May be overlapped and aligned with the outer edge 301a, and the outer edge 411a of the barrier layer 41a is installed on the inside or outside of the outer edge 401a of the reflective layer 40a, or the outer edge of the reflective layer 40a. It can be installed aligned while overlapping with (401a).

In another embodiment of the present invention, the step of forming the transparent conductive layer may be omitted, and the step of forming the reflective structure may be directly performed after the step of forming the platform or the step of forming the first insulating layer. For example, the reflective layer 40a and/or the barrier layer 41a is formed directly on the second semiconductor layer 102a, and the reflective layer 40a is positioned between the second semiconductor layer 102a and the barrier layer 41a.

The reflective layer 40a may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, a Bragg reflective structure. The material of the reflective layer 40a includes a metal material having a relatively high reflectance, and the metal material is, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh) or an alloy thereof. Here, having a relatively high reflectance means having a reflectance of 80% or more with respect to the wavelength of light emitted from the light emitting element 1 or the light emitting element 2 . In one embodiment of the present invention, the barrier layer 41a covers the reflective layer 40a to prevent the surface of the reflective layer 40a from being oxidized to deteriorate the reflectance of the reflective layer 40a. The material of the barrier layer 41a includes a metal material, for example, titanium (Ti), wolfram (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum ( Pt) and other metals or alloys thereof. The barrier layer 41a may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, titanium (Ti)/aluminum (Al) and/or titanium (Ti)/wolfram (W). In one embodiment of the present invention, the barrier layer 41a includes a stacked structure of titanium (Ti)/aluminum (Al) on one side away from the reflective layer 40a and has titanium (Ti) on one side close to the reflective layer 40a. / Includes a layered structure of wolfram (W). In one embodiment of the present invention, the material of the reflective layer 40a and the barrier layer 41a preferably includes a metal material other than gold or copper (Cu).

In one embodiment of the present invention, the manufacturing method of the light emitting device 1 or the light emitting device 2 following the step of forming the reflective structure is a plan view of FIG. 5A, a cross-sectional view taken along line AA' of FIG. 5A, and FIGS. 5B and 5A. As shown in FIG. 5C, which is a cross-sectional view taken along line BB' of , a second insulating layer forming step is included. The second insulating layer 50a is formed on the semiconductor structure 1000a by evaporation or evaporation, and also forms a first group of second insulating layer openings 501a to expose the first semiconductor layer 101a. and patterned by a lithography or etching method to form a second group of second insulating layer openings 502a to expose the reflective layer 40a or the barrier layer 41a. In the patterning process, the first insulating layer surrounding region 200a covered by the surrounding portion 111a in the above-described first insulating layer forming step and the first insulating layer covering region 201a of the first group in the hole portion 100a ) is partially etched and removed to expose the first semiconductor layer 101a, and the first group of first insulating layer openings 203a are formed in the hole 100a to expose the first semiconductor layer 101a. In this embodiment, on a cross-sectional view of the light emitting element 1 or the light emitting element 2, as shown in FIG. 5B, the first group of second insulating layer openings 501a and the second group of second insulating layer openings 502a has different widths and numbers. The opening shapes of the first group of second insulating layer openings 501a and second group of second insulating layer openings 502a include circular, elliptical, rectangular, polygonal or arbitrary shapes. In this embodiment, as shown in FIG. 5A , the second insulating layer openings 501a of the first group are separated from each other and are arranged in a plurality of rows, respectively forming a plurality of hole portions 100a and the first insulating layer openings 501a of the first group. Corresponding to the layer opening 203a, the second insulating layer openings 502a of the second group are all close to one side of the substrate 11a, for example, the left side or the right side of the center line of the substrate 11a, and the second group of the second insulating layer opening 502a The insulating layer openings 502a are located between the second insulating layer openings 501a of the first group of two rows adjacent to each other while being separated from each other. The second insulating layer 50a may have a single-layer or multi-layer structure. When the second insulating layer 50a is a single-layer film, the second insulating layer 50a protects the sidewall of the semiconductor structure 1000a to prevent the active layer 103a from being damaged in a subsequent manufacturing process. When the second insulating layer 50a is a multilayer film, the second insulating layer 50a is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure, thereby selectively emitting light of a specific wavelength. can reflect The second insulating layer 50a is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, following the second insulating layer forming step, the manufacturing method of the light emitting element 1 or the light emitting element 2 is a plan view of FIG. and forming a contact layer, as shown in FIG. 6C, which is a cross-sectional view taken along line BB' of FIG. 6A. The contact layer 60a may be formed on the first semiconductor layer 101a and the second semiconductor layer 102a by evaporation or deposition or the like, and one on the second insulating layer opening 502a of the second group. Lithography and etching are used to expose the reflective layer 40a or the barrier layer 41a by forming the above contact layer opening 602a and to define the fin region 600a at the geometric center of the light emitting device 1 or 2. patterned by the method of In the cross-sectional view of the light emitting element 1 or the light emitting element 2, the width of the contact layer opening 602a is larger than that of any one of the second insulating layer openings 502a of the second group. In a plan view of the light emitting element 1 or the light emitting element 2, the plurality of contact layer openings 602a are all close to one side of the substrate 11a, for example, to the left or right of the center line of the substrate 11a. The contact layer 60a may have a single-layer or multi-layer structure. In order to reduce the electrical resistance in contact with the first semiconductor layer 101a, the material of the contact layer 60a includes a metal material, such as chromium (Cr), titanium (Ti), or wolfram (W). , metals such as gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), and platinum (Pt) or alloys thereof. In one embodiment of the present invention, the material of the contact layer 60a is preferably a metal material other than gold (Au) and copper (Cu). In one embodiment of the present invention, the material of the contact layer 60a preferably includes a metal having a high reflectance such as aluminum (Al) or platinum (Pt). In one embodiment of the present invention, one side of the contact layer 60a in contact with the first semiconductor layer 101a is made of chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101a. It is preferable to include.

In one embodiment of the present invention, the contact layer 60a covers all the holes 100a and also extends to cover the second semiconductor layer 102a, and the contact layer 60a is the second insulating layer 50a It is insulated from the second semiconductor layer 102a through, and the contact layer 60a contacts the first semiconductor layer 101a through the hole 100a. When an external current is injected into the light emitting element 1 or the light emitting element 2, the current is conducted to the first semiconductor layer 101a through the plurality of holes 100a. In this embodiment, a first shortest distance is provided between two adjacent hole portions 100a located on the same column, and an arbitrary hole portion 100a adjacent to the edge of the light emitting device and the first semiconductor layer 101a have a first shortest distance. There is a second shortest distance between the outer walls 1003a, and the first shortest distance is greater than the second shortest distance.

In another embodiment of the present invention, the contact layer 60a covers the surrounding portion 111a and the hole portion 100a, and also extends to cover the second semiconductor layer 102a, and the contact layer 60a It is insulated from the second semiconductor layer 102a through the second insulating layer 50a, and the contact layer 60a contacts the first semiconductor layer 101a through the surrounding portion 111a and the hole portion 100a. When an external current is injected into the light emitting element 1 or the light emitting element 2, some of the current is conducted to the first semiconductor layer 101a by the surrounding portion 111a, and some of the current flows through the plurality of hole portions 100a. is conducted up to the first semiconductor layer 101a. In this embodiment, a first shortest distance is provided between two adjacent hole portions 100a located on the same column, and an arbitrary hole portion 100a adjacent to the edge of the light emitting device and the first semiconductor layer 101a have a first shortest distance. There is a second shortest distance between the outer walls 1003a, and the first shortest distance is equal to or smaller than the second shortest distance.

In another embodiment of the present invention, the plurality of hole parts 100a may be arranged in a first row and a second row, and a first shortest distance between two adjacent hole parts 100a located on the same row, A second shortest distance exists between the hole parts 100a on the first row and the hole parts 100a located on the second row, and the first shortest distance is greater than or smaller than the second shortest distance.

In one embodiment of the present invention, the plurality of hole parts 100a may be arranged in a first row, a second row, and a third row, and between the hole parts 100a on the first row and the hole parts 100a on the second row A first shortest distance is provided between the hole portion 100a positioned on the second column and the hole portion 100a positioned on the third column, and the first shortest distance is smaller than the second shortest distance.

In one embodiment of the present invention, the manufacturing method of the light emitting device 1 or the light emitting device 2 following the contact layer forming step as shown in FIGS. 6A, 6B and 6C includes a third insulating layer forming step. And, as shown in the plan view of FIG. 7A, the cross-sectional view taken along line A-A' in FIG. 7B, and the cross-sectional view taken along line BB' in FIG. 7C, the third insulating layer 70a is The first group of third insulating layer openings on the contact layer 60a may be formed on the semiconductor structure 1000a by evaporation or deposition, and expose the contact layer 60a shown in FIG. 701a), and forming a second group of third insulating layer openings 702a on the one or more contact layer openings 602a to expose the reflective layer 40a or barrier layer 41a shown in FIG. 6A. , lithography and etching, and the contact layer 60a positioned on the second semiconductor layer 102a is interposed between the second insulating layer 50a and the third insulating layer 70a, and The third insulating layer openings 701a of one group and the second insulating layer openings 501a of the first group are offset and do not overlap each other. The aforementioned pin region 600a is surrounded and covered by the third insulating layer. In this embodiment, as shown in Fig. 7A, the third insulating layer openings 701a of the first group are separated from each other and are offset from the plurality of hole portions 100a. The third insulating layer openings 702a of the second group are separated from each other and correspond to a plurality of contact layer openings 602a respectively. On the plan view of Fig. 7A, the first group of third insulating layer openings 701a is close to one side of the substrate 11a, for example, the right side, and the second group of third insulating layer openings 702a is on the substrate 11a. The other side, for example, is close to the left side of the center line of the substrate 11a. In the sectional view of the light emitting element 1 or the light emitting element 2, the width of any one second group of third insulating layer openings 702a is smaller than the width of any one contact layer opening 602a, and 3 The insulating layer 70a is filled along the contact layer opening 602a and covers the sidewall of the contact layer opening 602a while exposing the reflective layer 40a or the barrier layer 41a, and thus the third insulating layer of the second group. It constitutes the opening 702a. The third insulating layer 70a may have a single-layer or multi-layer structure. When the third insulating layer 70a is a multilayer film, the third insulating layer 70a is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure to selectively emit light of a specific wavelength. can reflect The third insulating layer 70a is formed of a non-conductive material, and is made of Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

Following the third insulating layer forming step, the manufacturing method of the light emitting device 1 or the light emitting device 2 includes a bonding pad forming step. As shown in the plan view of FIG. 8 , the first bonding pad 80a and the second bonding pad 90a may be formed on one or more semiconductor structures 1000a by electroplating, evaporation, or deposition, and It is patterned by lithography and etching methods. 8, the first bonding pad 80a is close to one side, for example, the right side of the center line of the substrate 11a, and the second bonding pad 90a is close to the other side, for example, the left side, of the center line of the substrate 11a. The first bonding pad 80a covers all the third insulating layer openings 701a of the first group so as to contact the contact layer 60a, and also covers the first semiconductor layer through the contact layer 60a and the hole 100a. (101a) and form an electrical connection. The second bonding pad 90a covers all the third insulating layer openings 702a of the second group and is in contact with the reflective layer 40a or the barrier layer 41a, and also covers the reflective layer 40a or the barrier layer 41a. Through this, an electrical connection with the second semiconductor layer 102a is formed. The first bonding pad 80a includes one or more first bonding pad openings 800a, a first side 802a, and a plurality of first bonding pads 802a extending in a direction away from the second bonding pad 90a. A first concave portion 804a is included. The second bonding pad 90a includes one or more second bonding pad openings 900a, a second side 902a, and a plurality of second bonding pads 902a extending in a direction away from the first bonding pad 80a. A second concave portion 904a is included. The position of the first bonding pad opening 800a and the position of the second bonding pad opening 900a substantially correspond to the position of the hole portion 100a, and the position of the first concave portion 804a and the second concave portion 904a The position of corresponds almost to the position of the hole portion 100a. In other words, the first bonding pad 80a and the second bonding pad 90a do not cover any hole portion 100a, and the first bonding pad 80a and the second bonding pad 90a cover the hole portion 100a. By being formed around the hole portion 100a while avoiding, the first bonding pad opening 800a or the second bonding pad opening 900a has a larger diameter than any hole portion 100a, and the first concave portion 804a or The second concave portion 904a has a larger width than the diameter of any hole portion 100a. In one embodiment of the present invention, the plurality of first concave portions 804a are substantially parallel to the plurality of second concave portions 904a in plan view. In another embodiment of the present invention, the plurality of first concave portions 804a are displaced from the plurality of second concave portions 904a in a plan view. In one embodiment of the present invention, on a plan view of the light emitting device 1 or the light emitting device 2, the shape of the first bonding pad 80a is the same as or different from that of the second bonding pad 90a.

9A is a cross-sectional view taken along line A-A' of FIG. 8, and FIG. 9B is a cross-sectional view taken along line BB' of FIG. The light emitting device 1 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting element 1 includes a substrate 11a; one or more semiconductor structures 1000a located on the substrate 11a; a surrounding portion 111a surrounding one or more semiconductor structures 1000a; and a first bonding pad 80a and a second bonding pad 90a positioned on the semiconductor stack 10a. Each of the one or more semiconductor structures 1000a includes a semiconductor stack 10a, wherein the semiconductor stack 10a includes a first semiconductor layer 101a, a second semiconductor layer 102a, a first semiconductor layer 101a, and a second semiconductor layer 101a. It includes an active layer 103a positioned between the semiconductor layers 102a. The plurality of semiconductor structures 1000a are connected to each other by the first semiconductor layer 101a. As shown in FIGS. 8, 9A, and 9B, the second semiconductor layer 102a and the active layer 103a around one or more semiconductor structures 1000a are removed so that the first surface of the first semiconductor layer 101a ( 1011a) is exposed. In other words, the surrounding portion 111a includes the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a.

The light emitting device 1 includes one or more holes 100a penetrating the second semiconductor layer 102a and the active layer 103a to expose one or more second surfaces 1012a of the first semiconductor layer 101a; and formed on the first surface 1011a of the first semiconductor layer 101a to surround the periphery of the semiconductor structure 1000a and contact the first semiconductor layer 101a to form an electrical connection; A contact layer 60a formed on one or more second surfaces 1012a of the layer 101a to form an electrical connection by contacting the first semiconductor layer 101a while covering the one or more holes 100a. do. In this embodiment, on a plan view of the light emitting element 1, the contact layer 60a has a total surface area larger than the total surface area of the active layer 103a, or the contact layer 60a has a length greater than the outer side of the active layer 103a. It has a large external length.

In one embodiment of the present invention, the first bonding pad 80a and/or the second bonding pad 90a covers a plurality of semiconductor structures 1000a.

In one embodiment of the present invention, the first bonding pad 80a includes one or more first bonding pad openings 800a, and the second bonding pad 90a includes one or more second bonding pad openings 900a. do. The formation position of the first bonding pad 80a and the second bonding pad 90a avoids the formation position of the hole portion 100a, thereby forming the first bonding pad opening 800a and the second bonding pad opening 900a. The position overlaps with the formation position of the hole portion 100a.

In one embodiment of the present invention, on a plan view of the light emitting device 1, the shape of the first bonding pad 80a is the same as that of the second bonding pad 90a, for example, the first bonding pad 80a and the second bonding pad 80a. 2 The shape of the bonding pad 90a is a comb shape, and as shown in FIG. 8 , the first bonding pad 80a is formed in an area other than the plurality of hole portions 100a. The radius of curvature of the first bonding pad opening 800a and the radius of curvature of the first concave portion 804a are each greater than the radius of curvature of the hole portion 100a. The curvature radius of the second bonding pad opening 900a and the curvature of the second concave portion 904a of the second bonding pad 90a so that the second bonding pad 90a is formed in an area other than the plurality of hole portions 100a. The radii are each greater than the curvature radius of the hole portion 100a.

In one embodiment of the present invention, on a plan view of the light emitting device 1, the shape of the first bonding pad 80a and the shape of the second bonding pad 90a are different. For example, when the first bonding pad 80a has a rectangular shape and the second bonding pad 90a has a comb shape, the first bonding pad 80a has a plurality of holes 100a. The second bonding pad 90a includes a first bonding pad opening 800a to be formed in an area other than the plurality of holes 100a, and the second bonding pad 90a includes a second concave portion so that the second bonding pad 90a is formed in an area other than the plurality of holes 100a. 904a or simultaneously includes the second concave portion 904a and the second bonding pad opening 900a.

In one embodiment of the present invention, the size of the first bonding pad 80a and the size of the second bonding pad 90a are different, for example, the area of the first bonding pad 80a is that of the second bonding pad 90a. larger than the area. The first bonding pad 80a and the second bonding pad 90a may have a single-layer or multi-layer structure including a metal material. The material of the first bonding pad 80a and the second bonding pad 90a includes a metal material, and the metal material includes, for example, chromium (Cr), titanium (Ti), wolfram (W), aluminum (Al), indium ( In), tin (Sn), nickel (Ni), platinum (Pt), or other metals or alloys thereof. When the first bonding pad 80a and the second bonding pad 90a have a multilayer structure, the first bonding pad 80a includes a first upper bonding pad 805a and a first lower bonding pad 807a, The second bonding pad 90a includes a second upper bonding pad 905a and a second lower bonding pad 907a. The upper bonding pad and the lower bonding pad each have different functions. The function of the upper layer bonding pad is mainly to form welding and lead wires. By means of the upper bonding pad, the light emitting device 1 is mounted on the package substrate in a flip chip format using solder or Au-Sn eutectic bonding. The specific metal material of the upper bonding pad is nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), wolfram (W), zirconium (Zr), molybdenum ( Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), etc. contains the material of The upper bonding pad may be a single layer, alloy or multilayer film of the above material. In one embodiment of the present invention, the material of the upper bonding pad preferably includes nickel (Ni) and/or gold (Au), and the upper bonding pad is single-layered or multi-layered. The function of the lower bonding pad is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, the interface bonding strength between the first lower bonding pad 807a and the contact layer 60a. or to improve the interfacial bonding strength between the second lower bonding pad 907a and the reflective layer 40a or the barrier layer 41a. Another function of the lower bonding pad is to prevent tin (Sn) from being diffused into the reflective structure during the solder or Au-Sn process and damaging the reflectance of the reflective structure. Therefore, the lower bonding pad is made of a material other than gold (Au) and copper (Cu), for example, nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), Molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), etc. It is preferable to include a metal material of, and the lower bonding pad may be a single layer, alloy or multilayer film of the above material. In one embodiment of the present invention, the lower bonding pad preferably includes a multilayer film of titanium (Ti) and aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

In one embodiment of the present invention, in a cross-sectional view of the light emitting device 1, a portion of the contact layer 60a connected to the first semiconductor layer 101a is positioned below the second bonding pad 90a.

In one embodiment of the present invention, in a cross-sectional view of the light emitting device 1, the portion of the contact layer 60a connected to the first semiconductor layer 101a is positioned above the reflective layer 40a and/or the barrier layer 41a. do.

In one embodiment of the present invention, on a plan view of the light emitting element 1, the hole portion 100a has a maximum width smaller than the maximum width of the first bonding pad opening 800a; and/or the hole portion 100a has a maximum width smaller than the maximum width of the second bonding pad opening 900a.

In one embodiment of the present invention, on a plan view of the light emitting device 1, the plurality of holes 100a are the plurality of first concave portions 804a of the first bonding pad 80a and the second bonding pad 90a, respectively. It is located in the plurality of second concave portions 904a of .

10 is a cross-sectional view of a light emitting device 2 disclosed in one embodiment of the present invention. Comparing the light emitting element 2 with the light emitting element 1 in the above embodiment, the light emitting element 2 has a first bumper pad positioned below the first bonding pad 80a and the second bonding pad 90a, respectively. 810a and the second bumper pad 910a, and since the light emitting device 2 and the light emitting device 1 have almost the same structure, the light emitting device 2 of FIG. 10 and the light emitting device 2 of FIG. Structures having the same names and symbols of the light emitting element 1 denote the same structures, have the same materials or have the same functions, and therefore descriptions are not appropriately omitted or described in detail. In this embodiment, the light emitting device 2 includes a first bumper pad 810a positioned between the first bonding pad 80a and the semiconductor layer 10a, and the second bonding pad 90a and the semiconductor layer 10a. It includes a second bumper pad 910a located therebetween, and the first bumper pad 810a and the second bumper pad 910a cover part or all of the hole 100a, and in this embodiment, the bonding pad ( Since the multi-layered insulating layer is included between the semiconductor layer 10a and the semiconductor layer 10a, the bonding pads 80a and 90a of the light emitting device 2 are bonded with solder or bonded due to stress generated during Au-Sn process bonding. Since cracks occur in (80a, 90a) and the insulating layer, the bumper pads (810a, 910a) are positioned between the bonding pads (80a, 90a) and the third insulating layer (70a), respectively, and the first bumper pads (810a and 910a) The second bumper pad 910a covers the entire hole portion 100a, and the formation positions of the first bonding pad 80a and the second bonding pad 90a avoid the formation position of the hole portion 100a, and the bumper pad By selecting the material and reducing the thickness, the generation of stress between the bonding pad and the insulating layer is reduced. In other words, the first bonding pad 80a and the second bonding pad 90a do not cover the hole 100a.

In one embodiment of the present invention, as shown in FIG. 10, on a plan view of the light emitting device 2, the shapes of the bumper pads 810a and 910a are the same as those of the bonding pads 80a and 90a, respectively, for example The shape of the first bumper pad 810a and the first bonding pad 80a is a comb shape.

In one embodiment of the present invention, on a plan view (not shown) of the light emitting device 2, the shapes of the bumper pads 810a and 910a are different from those of the bonding pads 80a and 90a, respectively, and, for example, the first bumper pads The shape of 810a is a rectangle, and the shape of the first bonding pad 80a is a comb shape.

In another embodiment of the present invention, the size of the bumper pads 810a and 910a is different from the size of the bonding pads 80a and 90a, respectively, and for example, the area of the first bumper pad 810a is equal to the first bonding pad 80a. , and the area of the second bumper pad 910a is greater than that of the second bonding pad 90a.

In another embodiment of the present invention, the distance between the first bonding pad 80a and the second bonding pad 90a is greater than the distance between the first bumper pad 810a and the second bumper pad 910a.

In another embodiment of the present invention, compared to the bonding pads 80a and 90a, the bumper pads 810a and 910a have a relatively large area to release pressure during die bonding of the bonding pads 80a and 90a. In the cross-sectional view of the light emitting device 2, the width of the first bumper pad 810a is 1.5 to 2.5 times, preferably twice the width of the first bonding pad 80a.

In another embodiment of the present invention, compared to the bonding pads 80a and 90a, the bumper pads 810a and 910a have a relatively large area to release pressure during die bonding of the bonding pads 80a and 90a. In a cross-sectional view of the light emitting element 2, the extension distance of the first bumper pad 810a is one or more times its own thickness, and preferably two times or more its own thickness.

In another embodiment of the present invention, the bonding pads 80a and 90a have a thickness of 1 to 100 μm, preferably 2 to 6 μm, and the bumper pads 810a and 910a are used for die bonding of the bonding pads 80a and 90a. It has a thickness greater than 0.5 μm, so as to release the pressure of the time.

In another embodiment of the present invention, the first bumper pad 810a and the second bumper pad 910a may have a single-layer or multi-layer structure including a metal material. The function of the first bumper pad 810a and the second bumper pad 910a is to form a stable interface with the contact layer 60a, the reflective layer 40a, or the barrier layer 41a, for example, the first bumper pad 810a The silver contact layer 60a is in contact, and the second bumper pad 910a is in contact with the reflective layer 40a or the barrier layer 41a. The bumper pads 810a and 910a are made of a metal material other than gold (Au) and copper (Cu), such as chromium (Cr) and nickel, to prevent diffusion of tin (Sn) into the light emitting device during the solder or Au-Sn process. (Ni), Cobalt (Co), Iron (Fe), Titanium (Ti), Wolfram (W), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os) are preferably included.

In another embodiment of the present invention, the first bumper pad 810a and/or the second bumper pad 910a includes a multilayer structure made of a metal material, and the multilayer structure is such that the bonding pads 80a and 90a are bonded to or bonded to solder. A high ductility layer and a low ductility layer are included to prevent cracks from occurring in the insulating layer between the bonding pads 80a and 90a and the semiconductor layer 10a due to stress generated during Au-Sn eutectic bonding. The high ductility layer and the low ductility layer include metals having different Young's modulus.

In another embodiment of the present invention, the high-flexibility layer of the first bumper pad 810a and the second bumper pad 910a has a thickness greater than or equal to the thickness of the low-flexibility layer.

In another embodiment of the present invention, the first bumper pad 810a and the second bumper pad 910a have a multilayer structure including a metal material, and the first bonding pad 80a and the second bonding pad 90a are made of metal. In the case of a multi-layer structure including a material, one surface in contact with the first bumper pad 810a and the first bonding pad 80a includes the same metal material, and the second bumper pad 910a and the second bonding pad 90a One side in contact with the same metal material (for example, chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt)) to improve the interfacial bonding strength of the bonding pad and the bumper pad.

As shown in FIGS. 11A and 11B , the fourth insulating layer 110a may be formed on the first bumper pad 810a and the second bumper pad 910a by evaporation or deposition, and lithography or etching. patterned by the method of, the first bonding pad 80a and the second bonding pad 90a are formed on the first bumper pad 810a and the second bumper pad 910a, respectively, in the above-described manner, and the 4 The insulating layer 110a surrounds sidewalls of the first bumper pad 810a and the second bumper pad 910a. The fourth insulating layer 110a may have a single-layer or multi-layer structure. When the fourth insulating layer 110a is a multilayer film, the fourth insulating layer 110a is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure, selectively emitting light of a specific wavelength. can reflect The material of the fourth insulating layer 110a is formed of a non-conductive material, and Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin Organic materials such as polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or silicone (Silicone) ), inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ) or magnesium fluoride (MgFx) do.

In one embodiment of the present invention, the manufacturing process of the first bonding pad 80a and the second bonding pad 90a may be immediately followed after the manufacturing process of the first bumper pad 810a and the second bumper pad 910a. . In another embodiment of the present invention, after the manufacturing process of the first bumper pad 810a and the second bumper pad 910a, first the fourth insulating layer 110a is formed, and then the first bonding pad ( 80a) and the manufacturing process of the second bonding pad 90a are performed.

12A to 22 are methods of manufacturing a light emitting device 3 or a light emitting device 4 disclosed in an embodiment of the present invention.

As shown in FIG. 12B, which is a plan view of FIG. 12A and a cross-sectional view taken along line A-A' of FIG. 12A, the method of manufacturing the light emitting device 3 or the light emitting device 4 includes a platform forming step, and the platform is formed. The steps include providing a substrate 11b; and forming a semiconductor layer 10b on the substrate 11b, wherein the semiconductor layer 10b includes a first semiconductor layer 101b, a second semiconductor layer 102b, and a first semiconductor layer 101b. and an active layer 103b positioned between the second semiconductor layer 102b. The semiconductor layer 10b is patterned by lithography and etching to partially remove the second semiconductor layer 102b and the active layer 103b, thereby forming one or more semiconductor structures 1000b; and a surrounding portion 111b surrounding one or more semiconductor structures 1000b. The surrounding portion 111b exposes the first surface 1011b of the first semiconductor layer 101b. Each of the one or more semiconductor structures 1000b includes a first outer wall 1003b, a second outer wall 1001b and an inner wall 1002b, the first outer wall 1003b comprising a first semiconductor layer 101b. , the second outer wall 1001b is the sidewall of the active layer 103b and/or the second semiconductor layer 102b, and one end of the second outer wall 1001b is the surface 102s of the second semiconductor layer 102b. And, the other end of the second outer wall 1001b is connected to the first surface 1011b of the first semiconductor layer 101b, and one end of the inner wall 1002b is connected to the surface 102s of the second semiconductor layer 102b. ), the other end of the inner wall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b, and the plurality of semiconductor structures 1000b are connected to each other by the first semiconductor layer 101b. do. As shown in FIG. 12B, the inner wall 1002b of the semiconductor structure 1000b and the second surface 1012b of the first semiconductor layer 101b form an obtuse angle, and the first outer wall 1003b of the semiconductor structure 1000b and The surface 11s of the substrate 11b forms an obtuse angle or a right angle, and the second outer wall 1001b of the semiconductor structure 1000b and the first surface 1011b of the first semiconductor layer 101b form an obtuse angle. The surrounding portion 111b surrounds the periphery of the semiconductor structure 1000b, and the surrounding portion 111b has a rectangular or polygonal shape in a plan view of the light emitting device 3 or the light emitting device 4.

In one embodiment of the present invention, light emitting element 3 or light emitting element 4 has a side length of less than 30 mils. When an external current is injected into the light emitting element 3 or the light emitting element 4, the surrounding portion 111b surrounds the semiconductor structure 1000b, so that the light emitting element 3 or the light emitting element 4 A light field distribution can be made uniform, and a forward voltage of a light emitting device can be reduced.

In one embodiment of the present invention, light emitting element 3 or light emitting element 4 has a side length greater than 30 mils. The semiconductor stack 10b is patterned by lithography and etching to partially remove the second semiconductor layer 102b and the active layer 103b, and at least one hole portion penetrating the second semiconductor layer 102b and the active layer 103b. 100b, and the one or more holes 100b expose one or more second surfaces 1012b of the first semiconductor layer 101b. When an external current is injected into the light emitting element 3 or the light emitting element 4, the light emitting element 3 or the light emitting element 4 is lighted by the distributed arrangement of the surrounding part 111b and the plurality of hole parts 100b. The field distribution can be made uniform and the forward voltage of the light emitting device can be reduced.

In one embodiment of the present invention, the opening shape of the one or more holes 100b includes circular, elliptical, rectangular, polygonal, or arbitrary shapes. The plurality of hole parts 100b may be arranged in a plurality of rows, and the hole parts 100b on two adjacent rows may be arranged side by side or offset from each other.

In one embodiment of the present invention, the substrate 11b is a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), a sapphire (Al2O3) wafer for growing indium gallium nitrogen (InGaN), or a gallium nitride (GaN) wafer. ) wafer or a growth substrate including a silicon carbide (SiC) wafer. Here, on the substrate 11b, photoelectricity such as light-emitting lamination is performed using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial method (MBE), hydride vapor deposition (HVPE), evaporation, or ion plating. A semiconductor stack 10b having characteristics can be formed.

In one embodiment of the present invention, the first semiconductor layer 101b and the second semiconductor layer 102b are, for example, a cladding layer or a confinement layer, and both have different conductivity types and electrical characteristics. , polarity, or can provide electrons or holes depending on the doped element. For example, the first semiconductor layer 101b is a semiconductor having n-type electrical characteristics, and the second semiconductor layer 102b has p-type electrical characteristics. it is a semiconductor The active layer 103b is formed between the first semiconductor layer 101b and the second semiconductor layer 102b, and electrons and holes recombine in the active layer 103b under current driving to convert electrical energy into light energy to generate light rays. emit The wavelength of light emitted from the light emitting element 3 or the light emitting element 4 is controlled by changing the physical and chemical composition of a single layer or multiple layers of the semiconductor stack 10b. The material of the semiconductor stack 10b includes a III-V group semiconductor material, for example AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0x,y1; (x+y)1. Depending on the material of the active layer 103b, when the material of the semiconductor layer 10b is an AlInGaP-based material, red light with a wavelength of 610 nm to 650 nm and green light with a wavelength of 530 nm to 570 nm can be emitted, When the material of (10b) is an InGaN-based material, blue light having a wavelength of 450 nm to 490 nm can be emitted, or when the material of the semiconductor layered material (10b) is an AlGaN-based material, a blue light having a wavelength of 400 nm to 250 nm can be emitted. It can emit external light. The active layer 103b is a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), multi-quantum well (MQW) ) can be. The material of the active layer 103b may be a semiconductor having neutral, p-type or n-type electrical characteristics.

Following the platform formation step, the manufacturing method of the light emitting element 3 or the light emitting element 4 is a first insulating layer, as shown in FIG. 13B, which is a plan view of FIG. Including the forming stage. The first insulating layer 20b may be formed on the semiconductor structure 1000b by evaporation or deposition, and may be formed on the first surface 1011b of the surrounding portion 111b and the second surface of the hole portion 100b. (1012b), the second semiconductor layer 102b of the semiconductor structure 1000b, and the second outer wall 1001b and inner wall 1002b of the active layer 103b are patterned by lithography and etching methods. The first insulating layer 20b is a first insulating layer covering the surrounding part 111b so as to cover the first surface 1011b of the first semiconductor layer 101b located in the surrounding part 111b. a rounding area 200b; a first group of first insulating layer cover regions 201b covering the hole portion 100b so as to cover the second surface 1012b of the first semiconductor layer 101b located in the hole portion 100b; and a second group of first insulating layer openings 202b exposing the surface 102s of the second semiconductor layer 102b. The first insulating layer cover regions 201b of the first group are separated from each other and each correspond to a plurality of hole portions 100b. The first insulating layer 20b may have a single-layer or multi-layer structure. When the first insulating layer 20b is a single-layer film, the first insulating layer 20b may protect the sidewall of the semiconductor structure 1000b to prevent the active layer 103b from being damaged in a subsequent process. When the first insulating layer 20b is a multi-layer film, the first insulating layer 20b is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure to selectively emit light of a specific wavelength. can reflect The first insulating layer 20b is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, following the first insulating layer forming step, the method for manufacturing the light emitting element 3 or the light emitting element 4 is a plan view of FIG. 14A and a cross-sectional view taken along line AA' of FIG. 14A. As shown in 14b, a transparent conductive layer forming step is included. The transparent conductive layer 30b may be formed on the semiconductor structure 1000b by evaporation or deposition, and is in contact with the second semiconductor layer 102b, and the transparent conductive layer 30b covers the hole 100b. I never do that. On a plan view of the light emitting element 3 or the light emitting element 4, the transparent conductive layer 30b is formed on almost the entire surface of the second semiconductor layer 102b. Specifically, the transparent conductive layer 30b may be formed in the opening 202b of the second group of the first insulating layer by evaporation or deposition, and the outer edge 301b of the transparent conductive layer 30b and the first insulating layer (20b) are spaced apart from each other to expose the surface (102s) of the second semiconductor layer (102b). the transparent conductive layer 30b includes one or more transparent conductive layer openings 300b respectively corresponding to the one or more hole portions 100b and/or respectively corresponding to the first insulating layer cover regions 201b of the first group; The outer edge 301b of the transparent conductive layer opening 300b is spaced apart from the outer edge of the inner wall 1002b and/or the hole portion 100b of the semiconductor structure 1000b at a distance from each other, and the outer edge of the transparent conductive layer opening 300b is the hole portion ( 100b) Surrounds the periphery or the first insulating layer cover area 201b of the first group. The material of the transparent conductive layer 30b includes a material that is transparent to light emitted from the active layer 103b, and the transparent material is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer may be omitted, and the step of forming the transparent conductive layer may be directly performed.

In one embodiment of the present invention, the manufacturing method of the light emitting element 3 or the light emitting element 4 following the step of forming the transparent conductive layer is shown in a plan view of FIG. 15A and a cross-sectional view taken along line AA' in FIG. As shown in , a reflective structure forming step is included. The reflective structure includes a reflective layer 40b and/or a barrier layer 41b, and may be directly formed on the transparent conductive layer 30b by evaporation or deposition, and the reflective layer 40b is formed on the transparent conductive layer 30b. and the barrier layer 41b. On a plan view of the light emitting element 3 or the light emitting element 4, the reflective layer 40b and/or the barrier layer 41b are formed on almost the entire surface of the second semiconductor layer 102b. The outer edge 401b of the reflective layer 40b may be installed inside or outside the outer edge 301b of the transparent conductive layer 30b, or may be installed aligned while overlapping with the outer edge 301b of the transparent conductive layer 30b, The outer edge 411b of the barrier layer 41b may be installed inside or outside the outer edge 401b of the reflective layer 40b, or may be installed aligned while overlapping with the outer edge 401b of the reflective layer 40b. The reflective layer 40b each includes one or more reflective layer openings 400b corresponding to the one or more hole portions 100b, and the barrier layer 41b includes one or more barrier layer openings 410b corresponding to the one or more hole portions 100b. include The transparent conductive layer opening 300b, the reflective layer opening 400b and the barrier layer opening 410b overlap each other. The outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b are spaced apart from the outer edge of the hole portion 100b by a distance, and the outer edge of the reflective layer opening 400b and/or the outer edge of the barrier layer opening 410b is the hole portion 100b. ) encloses the extension.

In another embodiment of the present invention, the step of forming the transparent conductive layer may be omitted, and the step of forming the reflective structure may be directly performed after the step of forming the platform or the step of forming the first insulating layer. For example, the reflective layer 40b and/or the barrier layer 41b is formed directly on the second semiconductor layer 102b, and the reflective layer 40b is positioned between the second semiconductor layer 102b and the barrier layer 41b. The reflective layer 40b may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, a Bragg reflective structure. The material of the reflective layer 40b includes a metal material having a relatively high reflectance, and the metal material is, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh) or an alloy thereof. Here, having a relatively high reflectance means having a reflectance of 80% or more with respect to the wavelength of light emitted from the light emitting element 3 . In one embodiment of the present invention, the barrier layer 41b covers the reflective layer 40b to prevent the surface of the reflective layer 40b from being oxidized to deteriorate the reflectance of the reflective layer 40b. The material of the barrier layer 41b includes a metal material, and the metal material includes, for example, titanium (Ti), wolfram (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum ( Pt) and other metals or alloys thereof. The barrier layer 41b may have a single-layer or multi-layer structure, and the multi-layer structure is, for example, titanium (Ti)/aluminum (Al) and/or titanium (Ti)/wolfram (W). In one embodiment of the present invention, the barrier layer 41b includes a stacked structure of titanium (Ti)/aluminum (Al) on one side away from the reflective layer 40b and titanium (Ti) on one side close to the reflective layer 40b. ) / Wolfram (W). In one embodiment of the present invention, the material of the reflective layer 40b and the barrier layer 41b is preferably a metal material other than gold (Au) or copper (Cu).

In one embodiment of the present invention, the manufacturing method of the light emitting element 3 or the light emitting element 4 following the step of forming the reflective structure is shown in a plan view of FIG. 16A and a cross-sectional view taken along line AA' in FIG. 16B. As shown, a second insulating layer forming step is included. The second insulating layer 50b may be formed on the semiconductor layer 10b by evaporation or evaporation, and the second insulating layer opening 501b of the first group to expose the first semiconductor layer 101b. patterned by a lithography or etching method to form a second insulating layer opening 502b of a second group to expose the reflective layer 40b or the barrier layer 41b, and the second insulating layer 50b In the patterning process, the first insulating layer surrounding region 200b covered by the surrounding portion 111b in the above-described first insulating layer forming step and the first insulating layer covering region of the first group in the hole portion 100b ( 201b) is etched and removed to expose the first semiconductor layer 101b, and a first group of first insulating layer openings 203b are formed in the hole 100b to expose the first semiconductor layer 101b. . In one embodiment of the present invention, as shown in FIG. 16A, the second insulating layer openings 501b of the first group are separated from each other and correspond to a plurality of hole portions 100b, respectively, and the second insulating layer openings 501b of the second group are separated from each other. The layer openings 502b are all close to one side of the substrate 11b, for example, to the left or right of the center line of the substrate 11b, and in one embodiment, the number of the second insulating layer openings 502b in the second group is one or more. In this embodiment, the second insulating layer openings 502b of the second group are connected to each other to form one annular opening 5020b in common, and the annular opening 5020b is a plan view of the light emitting element 3 It may be comb-shaped, rectangular, elliptical, circular, or polygonal in shape. In one embodiment of the present invention, the second insulating layer 50b may have a single-layer or multi-layer structure. When the second insulating layer 50b is a multilayer film, the second insulating layer 50b is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure to selectively emit light of a specific wavelength. can reflect The second insulating layer 50b is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the method of manufacturing the light emitting element 3 or the light emitting element 4 following the second insulating layer forming step, as shown in the plan view of FIG. 17A and the cross-sectional view of FIG. 17B, the contact layer is formed. Include steps. The contact layer 60b may be formed on the semiconductor stack 10b by evaporation or deposition, or may be patterned by lithography or etching to form the first contact layer 601b and the second contact layer 602b. get angry The first contact layer 601b covers all the second insulating layer openings 501b of the first group, fills one or more holes 100b to contact the first semiconductor layer 101b, and expands to form the second insulating layer 601b. It covers the insulating layer 50b and the second semiconductor layer 102b, and the first contact layer 601b is insulated from the second semiconductor layer 102b through the second insulating layer 50b. The second contact layer 602b is formed in the annular opening 5020b of the second insulating layer 50b to contact the reflective layer 40b and/or the barrier layer 41b, and the sidewall of the second contact layer 602b ( 6021b) and the sidewall 5021b of the annular opening 5020b are spaced apart from each other. The sidewall 6011b of the first contact layer 601b is spaced apart from the sidewall 6021b of the second contact layer 602b so that the first contact layer 601b is not connected to the second contact layer 602b. And, the first contact layer 601b and the second contact layer 602b are electrically insulated by a part of the second insulating layer 50b. In plan view, the first contact layer 601b covers the surrounding portion 111b of the semiconductor stack 10b so as to surround the second contact layer 602b. On the plan view of FIG. 17A, the second contact layer 602b is close to one side of the substrate 11b, for example, to the left or right of the center line of the substrate 11b. The contact layer 60b defines a fin region 600b at the geometric center of the semiconductor stack 10b. The pin area 600b is not connected to the first contact layer 601b and the second contact layer 602b and is electrically insulated from each other, and the pin area 600b is not connected to the first contact layer 601b and/or the second contact layer 602b. It includes the same material as the contact layer 602b. The fin region 600b is a structure that protects the epitaxial layer, and prevents the epitaxial layer from being damaged by a probe in subsequent manufacturing processes such as die separation, die test, and packaging. The contact layer 60b may have a single-layer or multi-layer structure. In order to reduce electrical resistance in contact with the first semiconductor layer 101b, the material of the contact layer 60b includes a metal material, such as chromium (Cr), titanium (Ti), wolfram (W), A metal such as gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt) or an alloy thereof. In one embodiment of the present invention, the material of the contact layer 60b preferably includes a metal material other than gold (Au) and copper (Cu). In one embodiment of the present invention, the material of the contact layer 60b preferably includes a metal having a high reflectance such as aluminum (Al) or platinum (Pt). In one embodiment of the present invention, one side of the contact layer 60b in contact with the first semiconductor layer 101b is made of chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer 101b. It is preferable to include

In one embodiment of the present invention, following the step of forming the contact layer shown in FIGS. 17A and 17B, the method of manufacturing the light emitting element 3 or the light emitting element 4 includes a third insulating layer forming step, as shown in FIG. 18A. As shown in the plan view and FIG. 18B, which is a cross-sectional view taken along the line AA' of FIG. 18A, the third insulating layer 70b may be formed on the semiconductor layer 10b by evaporation or deposition, and A third insulating layer opening 701b is formed on the first contact layer 601b to expose the first contact layer 601b shown in FIG. 17A, and the second contact layer 602b shown in FIG. 17A is exposed. A first contact patterned by a lithography or etching method and partially located on the second semiconductor layer 102b to form another third insulating layer opening 702b on the second contact layer 602b to The layer 601b is interposed between the second insulating layer 50b and the third insulating layer 70b. In this embodiment, as shown in Fig. 18A, the third insulating layer opening 701b and the other third insulating layer opening 702b avoid one or more hole portions 100b. In this embodiment, the third insulating layer opening 701b and/or the other third insulating layer opening 702b are annular openings, and the annular openings may be comb-shaped, rectangular, elliptical, circular, or polygonal in plan view. there is. In the plan view of FIG. 18A, the third insulating layer opening 701b is close to one side of the center line of the substrate 11b, for example, the right side, and the other third insulating layer opening 702b is close to the other side of the center line of the substrate 11b, for example, the left side. Close up. In cross-sectional view, the third insulating layer opening 701b has a width larger than that of the other third insulating layer openings 702b. The third insulating layer 70b may have a single-layer or multi-layer structure. When the third insulating layer 70b is a multilayer film, the third insulating layer 70b is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure, selectively emitting light of a specific wavelength. can reflect The third insulating layer 70b is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

Following the step of forming the third insulating layer, the manufacturing method of the light emitting element 3 or 4 includes a step of forming a bonding pad. As shown in the plan view of FIG. 19, the first bonding pad 80b and the second bonding pad 90b may be formed on the semiconductor layer 10b by a method such as electroplating, evaporation, or deposition, and may be formed by lithography, It is patterned by an etching method. 19, the first bonding pad 80b is close to one side, for example, the right side of the center line of the substrate 11b, and the second bonding pad 90b is close to the other side, for example, the left side of the center line of the substrate 11b. The first bonding pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. form The second bonding pad 90b is in contact with the reflective layer 40b and/or the barrier layer 41b through the third insulating layer opening 702b, and via the reflective layer 40b and/or the barrier layer 41b. An electrical connection is formed with the second semiconductor layer 102b. The first bonding pad 80b includes a plurality of first convex portions 801b and a plurality of first concave portions 802b that are alternately connected to each other. The second bonding pad 90b includes a plurality of second convex portions 901b and a plurality of second concave portions 902b that are alternately connected to each other. The position of the first concave portion 802b of the first bonding pad 80b and the position of the second concave portion 902b of the second bonding pad 90b substantially correspond to the position of the hole portion 100b. In other words, the first bonding pad 801b and the second bonding pad 802b do not cover any hole 100b, and the first concave portion 802b of the first bonding pad 80b and the second bonding pad ( The second concave portion 902b of 90b) is formed around the hole portion 100b while avoiding the hole portion 100b, so that the width of the first concave portion 802b of the first bonding pad 80b or the second bonding pad ( The width of the second concave portion 902b of 90b) is larger than the diameter of any hole portion 100b. In one embodiment of the present invention, the plurality of first concave portions 802b are substantially aligned with the plurality of second concave portions 902b in plan view. In another embodiment of the present invention, the plurality of first concave portions 802b are displaced from the plurality of second concave portions 902b in a plan view.

In one embodiment of the present invention, as shown in FIG. 19, the first bonding pad 80b is covered on the third insulating layer opening 701b, and the second bonding pad 90b is covered by another third insulating layer. Covered on the opening 702b, the third insulating layer opening 701b has a maximum width greater than the maximum width of the other third insulating layer opening 702b, so that the first bonding pad 80b is the second bonding pad. It has a maximum width greater than the maximum width of (90b). The first bonding pad 80b and the second bonding pad 90b of different sizes are convenient to distinguish the electrical characteristics of the correspondingly connected bonding pads during packaging welding, so that welding to bonding pads having different electrical characteristics occurs. prevent that

In one embodiment of the present invention, on a plan view of the light emitting device, the third insulating layer opening 701b has an area equal to or greater than that of the first bonding pad 80b.

In another embodiment of the present invention, the shortest distance between the first convex portion 801b and the second convex portion 901b is smaller than the maximum distance between the first concave portion 802b and the second concave portion 902b.

In another embodiment of the present invention, the first bonding pad 80b includes a first straight side 803b facing the first convex portion 801b and the first concave portion 802b, and the second bonding pad ( 90b) includes a second straight side 903b facing the second convex portion 901b and the second concave portion 902b. The maximum distance between the first straight side 803b of the first bonding pad 80b and the first convex portion 801b is greater than the shortest distance between the first convex portion 801b and the second convex portion 901b. . The maximum distance between the second straight side 903b of the second bonding pad 90b and the second convex portion 901b is greater than the shortest distance between the first convex portion 801b and the second convex portion 901b. .

In another embodiment of the present invention, the radius of curvature of the plurality of first concave portions 802b of the first bonding pad 80b is equal to the radius of curvature of the plurality of first convex portions 801b of the first bonding pad 80b. different, for example, the radius of curvature of the plurality of first concave portions 802b of the first bonding pad 80b is larger or smaller than the radius of curvature of the plurality of first convex portions 801b of the first bonding pad 80b. In another embodiment of the present invention, the radius of curvature of the plurality of second concave portions 902b of the second bonding pad 90b is greater than the radius of curvature of the plurality of second convex portions 901b of the second bonding pad 90b. Big or small.

In another embodiment of the present invention, the radius of curvature of the first convex portion 801b of the first bonding pad 80b is larger or smaller than the radius of curvature of the second convex portion 901b of the second bonding pad 90b.

In another embodiment of the present invention, the plurality of first concave portions 802b of the first bonding pad 80b face the plurality of second concave portions 902b of the second bonding pad 90b, and the plurality of second concave portions 902b of the second bonding pad 90b face each other. The radius of curvature of one concave portion 802b is larger or smaller than that of the plurality of second concave portions 902b.

In another embodiment of the present invention, the shape of the first bonding pad 80b and the shape of the second bonding pad 90b are different, for example, the shape of the first bonding pad 80b is a rectangle, and the shape of the second bonding pad ( The shape of 90b) is a comb shape.

In another embodiment of the present invention, the size of the first bonding pad 80b and the size of the second bonding pad 90b are different, for example, the area of the first bonding pad 80b is that of the second bonding pad 90b. larger than the area.

FIG. 20 is a cross-sectional view taken along line A-A' of FIG. 19 . The light emitting device 3 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting element 3 includes a substrate 11b; It is located on the substrate (11b) and includes a semiconductor stack (10b), the semiconductor stack (10b) is a first semiconductor layer (101b), a second semiconductor layer (102b) and the first semiconductor layer (101b) and the second semiconductor one or more semiconductor structures (1000b) including an active layer (103b) located between layers (102b) and connected to each other by a first semiconductor layer (101b); a surrounding portion 111b surrounding the one or more semiconductor structures 1000b and exposing the first surface 1011b of the first semiconductor layer 101b; and a first bonding pad 80b and a second bonding pad 90b positioned on the at least one semiconductor structure 1000b. 19 and 20, each of the one or more semiconductor structures 1000b includes a plurality of outer walls 1001b and a plurality of inner walls 1002b, and one end of the outer wall 1001b is a second semiconductor layer ( 102b), the other end of the outer wall 1001b is connected to the first surface 1011b of the first semiconductor layer 101b, and one end of the inner wall 1002b is connected to the second semiconductor layer 102b. ) is connected to the surface 102s, and the other end of the inner wall 1002b is connected to the second surface 1012b of the first semiconductor layer 101b.

In one embodiment of the present invention, when the light emitting element 3 has a side length greater than 30 mil, the light emitting element 3 exposes at least one second surface 1012b of the first semiconductor layer 101b. one or more holes 100b penetrating the second semiconductor layer 102b and the active layer 103b; And located on the first surface 1011b of the first semiconductor layer 101b to surround the periphery of one or more semiconductor structures 1000b and contact the first semiconductor layer 101b to form an electrical connection, and also a second 1 a contact layer 60b formed on one or more second surfaces 1012b of the semiconductor layer 101b to cover one or more holes 100b and contact the first semiconductor layer 101b to form an electrical connection; Further, the contact layer 60b includes a first contact layer 601b and a second contact layer 602b, the first contact layer 601b is located on the second semiconductor layer, and the second semiconductor layer It is connected to the first semiconductor layer while surrounding the sidewall, the second contact layer is located on the second semiconductor layer and connected to the second semiconductor layer, and the second contact layer 602b is on the first contact layer 601b. , and the first contact layer 601b and the second contact layer 602b do not overlap each other.

In one embodiment of the present invention, when the light emitting element 3 has a side length of less than 30 mil, in order to obtain a relatively large light emitting area, the light emitting element 3 may not include any hole 100b.

In one embodiment of the present invention, on a plan view of the light emitting element 3, the total surface area of the contact layer 60b is greater than the total surface area of the active layer 103b.

In one embodiment of the present invention, in a plan view of the light emitting element 3, the total length of the outer side of the contact layer 60b is greater than the total length of the outer side of the active layer 103b.

In one embodiment of the present invention, on a plan view of the light emitting element 3, the first contact layer 601b has an area larger than that of the second contact layer 602b.

In one embodiment of the present invention, the formation position of the first bonding pad 80b and the second bonding pad 90b is determined by the first bonding pad 80b or the second bonding pad 90b in any hole 100b. The hole portion 100b is avoided so as not to be covered.

In one embodiment of the present invention, in a cross-sectional view of the light emitting device 3, the first contact layer 601b connected to the first semiconductor layer 101b is not positioned below the second bonding pad 90b.

In one embodiment of the present invention, the minimum distance between the first bonding pad 80b and the second bonding pad 90b is greater than 50 μm.

In one embodiment of the present invention, the distance between the first bonding pad 80b and the second bonding pad 90b is smaller than 300 μm.

In one embodiment of the present invention, the first bonding pad 80b and the second bonding pad 90b may have a single-layer or multi-layer structure including a metal material. The material of the first bonding pad 80b and the second bonding pad 90b includes a metal material, and the metal material includes, for example, chromium (Cr), titanium (Ti), wolfram (W), aluminum (Al), indium ( In), tin (Sn), nickel (Ni), platinum (Pt), etc., or alloys thereof. When the first bonding pad 80b and the second bonding pad 90b have a multilayer structure, the first bonding pad 80b includes a first lower bonding pad (not shown) and a first upper bonding pad (not shown). And, the second bonding pad 90b includes a second lower bonding pad (not shown) and a second upper bonding pad (not shown). The upper bonding pad and the lower bonding pad each have different functions. The function of the upper bonding pad is mainly to weld and form lead wires, and by means of the upper bonding pad, the light emitting element 3 is mounted on the mounting substrate in a flip chip format using solder or Au-Sn eutectic bonding. The specific metal material of the upper bonding pad includes a material of high ductility, and the material of high ductility includes, for example, nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), and gold (Au). ), Wolfram (W), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), Palladium (Pd), Rhodium (Rh), Iridium (Ir) ), ruthenium (Ru), and osmium (Os). The upper bonding pad may be a single layer, alloy or multilayer film of the above material. In one embodiment of the present invention, the material of the upper bonding pad preferably includes nickel (Ni) and/or gold (Au), and the upper bonding pad is single-layered or multi-layered. The function of the lower bonding pad is to form a stable interface with the contact layer 60b, the reflective layer 40b, or the barrier layer 41b, for example, to improve the bonding strength of the interface between the first lower bonding pad and the contact layer 60b. or to improve the bonding strength of the interface between the second lower bonding pad and the reflective layer 40b and/or the barrier layer 41b. Another function of the lower bonding pad is to prevent tin (Sn) from being diffused into the reflective structure during a solder or Au-Sn process, thereby damaging the reflectance of the reflective structure. Therefore, the lower bonding pad is made of a material other than gold (Au) and copper (Cu), for example, nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), Molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), etc. It is preferable to include a metal material of, and the lower bonding pad may be a single layer, alloy or multilayer film of the above material. In one embodiment of the present invention, the lower bonding pad preferably includes a multilayer film of titanium (Ti) and aluminum (Al), or a multilayer film of chromium (Cr) and aluminum (Al).

In one embodiment of the present invention, when the light emitting device 3 is mounted on a package substrate in a flip chip format by solder, the height difference (H) between the first bonding pad 80b and the second bonding pad 90b is there may be As shown in FIG. 20, the second insulating layer 50b under the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second bonding pad 90b is Since the second insulating layer opening 502b is included to expose the reflective layer 40b or the barrier layer 41b, the first bonding pad 80b and the second bonding pad 90b are each a third insulating layer opening 701b. ) and the other third insulating layer opening 702b, comparing the uppermost surface 80s of the first bonding pad 80b and the uppermost surface 90s of the second bonding pad 90b, the first bonding pad ( The uppermost surface 80s of 80b) is higher than the uppermost surface 90s of the second bonding pad 90b. In other words, there is a height difference H between the top surface 80s of the first bonding pad 80b and the top surface 90s of the second bonding pad 90b, and the first bonding pad 80b and the second bonding pad The height difference (H) between (90b) is substantially equal to the thickness of the second insulating layer (50b). In one embodiment, the height difference between the first bonding pad 80b and the second bonding pad 90b may be 0.5 μm to 2.5 μm, for example, 1.5 μm. When the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the first bonding pad 80b is formed in the third insulating layer opening 701b. It contacts the first contact layer 601b by the insulating layer opening 701b, extends from the third insulating layer opening 701b and covers a part of the surface of the third insulating layer 70b, and the second bonding pad 90b ) is in contact with the second contact layer 602b by another third insulating layer opening 702b, and extends from the other third insulating layer opening 702b to cover a part of the surface of the third insulating layer 70b.

21 is a plan view of a light emitting device 4 disclosed in one embodiment of the present invention. 22 is a cross-sectional view of a light emitting device 4 disclosed in one embodiment of the present invention. When the light emitting element 4 is compared with the light emitting element 3 of the above embodiment, the light emitting element 4 and the light emitting element 3 are almost the same except for the structure of the first bonding pad and the second bonding pad being different. Since the light emitting element 4 has the same structure as the light emitting element 3 and includes an element with the same code, description thereof will be omitted. When the light emitting device 4 is mounted on a package substrate in a flip chip format by Au-Sn process bonding, the first bonding pad 80b and the second bonding pad 90b are used to increase the rigidity between the bonding pad and the package substrate. ), the smaller the difference in height, the better. 22, the second insulating layer 50b below the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b below the second bonding pad 90b covers the reflective layer 40b. A second insulating layer opening 502b is included to expose the reflective layer 40b or the barrier layer 41b. In this embodiment, in order to reduce the height difference between the top surface 80s of the first bonding pad 80b and the top surface 90s of the second bonding pad 90b, the third insulating layer opening 701b is 3 has a larger width than the width of the insulating layer opening 702b. When the first bonding pad 80b and the second bonding pad 90b are formed in the third insulating layer opening 701b and the other third insulating layer opening 702b, respectively, the first bonding pad 80b is formed in the third insulating layer opening 701b. It is entirely formed in the insulating layer opening 701b to contact the first contact layer 601b, and the second bonding pad 90b is formed in the other third insulating layer opening 702b to form the reflective layer 40b and/or the barrier layer. 41b and the second bonding pad 90b extends from the third insulating layer opening 702b and covers a part of the surface of the third insulating layer 70b. In other words, the third insulating layer is not formed below the first bonding pad 80b, but a part of the third insulating layer is formed below the second bonding pad 90b. In this embodiment, the difference in height between the first bonding pad 80b and the second bonding pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm.

23 is a cross-sectional view of a light emitting device 5 disclosed in one embodiment of the present invention. When the light emitting element 5 is compared to the light emitting element 3 and the light emitting element 4 of the above embodiment, except for the structure of the second bonding pad, the light emitting element 5 is the light emitting element 3, the light emitting element Since the light emitting element 5 has substantially the same structure as the element 4 and includes elements having the same reference numerals as the light emitting elements 3 and 4, the description thereof is omitted. When the light emitting device 5 is mounted on the package substrate in a flip chip format by Au-Sn process bonding, the first bonding pad 80b and the second bonding pad 90b are provided to increase the rigidity between the bonding pad and the package substrate. ), the smaller the difference in height, the better. As described above, in addition to forming part of the third insulating layer on the lower side of the second bonding pad 90b, the second bumper pad 910b is formed on the lower side of the second bonding pad 90b to form the first bonding pad. A difference in height between the upper surface of 80b and the upper surface of the second bonding pad 90b may be reduced. 23, the second insulating layer 50b under the first bonding pad 80b covers the reflective layer 40b, and the second insulating layer 50b under the second bonding pad 90b is A second insulating layer opening 502b is included to expose the reflective layer 40b or the barrier layer 41b. In this embodiment, the first bonding pad 80b is entirely formed within the third insulating layer opening 701b to contact the first contact layer 601b, and the second bonding pad 90b is formed entirely in the third insulating layer opening 701b. 702b is entirely formed and contacts the second contact layer 602b. In other words, the third insulating layer is not formed below the first bonding pad 80b and below the second bonding pad 90b. In this embodiment, the top surface of the first bonding pad 80b and the second bonding pad 90b are formed by the second bumper pad 910b positioned between the second bonding pad 90b and the second contact layer 602b. ), and the second bumper pad 910b is made of gold (Au) and copper (Cu) to prevent diffusion of tin (Sn) into the light emitting device 5 during the Au-Sn process. Other metal materials, such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta) , It is preferable to include metal materials such as aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), and osmium (Os). . In this embodiment, the height difference between the top surface of the first bonding pad 80b and the top surface of the second bonding pad 90b is less than 0.5 μm, preferably less than 0.1 μm, and more preferably less than 0.05 μm. . In this embodiment, the second bumper pad 910b has a thickness substantially equal to that of the second insulating layer 50b.

24 is a cross-sectional view of a light emitting device 6 disclosed in one embodiment of the present invention. The light emitting element 6 is a light emitting element when compared to the light emitting element 3 and the light emitting element 4 of the above embodiment, except that the structure of the third insulating layer 70b under the first bonding pad 80b is different. (6) has almost the same structure as the light emitting element 3 and the light emitting element 4, and the light emitting element 6 includes elements having substantially the same signs as the light emitting element 3 and the light emitting element 4, so description is omitted. omit As shown in FIG. 24, the third insulating layer 70b may be formed on the semiconductor layer 10b by evaporation or deposition, or patterned by lithography or etching, so that the first contact layer ( 601b) to expose the first contact layer 601b by forming a third insulating layer opening 701b, and forming another third insulating layer opening 702b on the second contact layer 602b to expose the second insulating layer opening 701b. The contact layer 602b is exposed. The first bonding pad 80b and the second bonding pad 90b may be formed on the semiconductor layer 10b by electroplating, evaporation, or deposition, or patterned by lithography or etching. The first bonding pad 80b is in contact with the first contact layer 601b through the third insulating layer opening 701b and is electrically connected to the first semiconductor layer 101b through the first contact layer 601b. form In the process of etching the third insulating layer opening 701b, the first contact layer 601b and the second insulating layer 50b below the first bonding pad 80b are over-etched when the third insulating layer 70b is etched. The third insulating layer opening ( 701b) is reduced so that the third insulating layer 70b of the first portion is located between the first bonding pad 80b and the first contact layer 601b, and is completely covered by the first bonding pad 80b. The third insulating layer 70b of the other second part is located around the first bonding pad 80b, and the distance between the third insulating layer 70b of the first part and the second part is 3 insulating layer openings 701b are formed. Specifically, the third insulating layer 70b of the first portion completely covered by the first bonding pad 80b has a width greater than the width of the third insulating layer opening 701b below the bonding pad 80b. . In this embodiment, on a plan view of the light emitting element, the third insulating layer opening 701b is an annular opening.

25 to 34b are diagrams illustrating a manufacturing method and structure of a light emitting device 7 disclosed in an embodiment of the present invention.

As shown in Fig. 25, the manufacturing method of the light emitting element 7 includes providing a substrate 11c; and forming a semiconductor stack 10c on the substrate 11c, wherein the semiconductor stack 10c includes the first semiconductor layer 101c, the second semiconductor layer 102c, and the first semiconductor layer 101c. An active layer 103c positioned between the second semiconductor layers 102c is included.

In one embodiment of the present invention, the substrate 11c is a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), a sapphire (Al2O3) wafer for growing indium gallium nitrogen (InGaN), or a gallium nitride (GaN). ) wafer or a growth substrate including a silicon carbide (SiC) wafer.

In one embodiment of the present invention, light emission on the substrate 11c by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial deposition (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating A semiconductor layer 10c having photoelectric properties such as a light-emitting layer is formed, and physical vapor deposition includes sputtering or evaporation. The first semiconductor layer 101c and the second semiconductor layer 102c may be a cladding layer or a confinement layer, and both have different conductivity types, electrical characteristics, polarities, or are doped Depending on the element, electrons or holes are provided. For example, the first semiconductor layer 101c is an n-type semiconductor and the second semiconductor layer 102c is a p-type semiconductor. The active layer 103c is formed between the first semiconductor layer 101c and the second semiconductor layer 102c, and electrons and holes are recombinated in the active layer 103c under current driving to convert electrical energy into light energy to generate light rays. emit By changing the physical and chemical composition of a single layer or multiple layers in the semiconductor stack 10c, the wavelength of light emitted from the light emitting element 7 is adjusted. The material of the semiconductor stack 10c includes a III-V group semiconductor material, for example AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0x,y1;(x+y)1. Depending on the material of the active layer 103c, when the material of the semiconductor layer 10c is an AlInGaP-based material, red light with a wavelength of 610 nm to 650 nm and green light with a wavelength of 530 nm to 570 nm can be emitted, When the material of (10c) is an InGaN-based material, blue light having a wavelength of 450 nm to 490 nm can be emitted, or when the material of the semiconductor layer 10c is an AlGaN-based or AlInGaN-based material, the wavelength is 400 nm to 490 nm. It can emit ultraviolet light of 250 nm. The active layer 103c is a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), multi-quantum well (MQW) ) can be. The material of the active layer 103c may be a semiconductor having neutral, p-type or n-type electrical characteristics.

In an embodiment of the present invention, PVD aluminum nitride (AlN), as a buffer layer, is formed between the semiconductor layer 10c and the substrate 11c to improve the epitaxial quality of the semiconductor layer 10c. In an embodiment, the target forming PVD aluminum nitride (AlN) is composed of aluminum nitride. Another embodiment uses a target composed of aluminum and reacts with the aluminum target to form aluminum nitride in the environment of a nitrogen source.

As shown in FIG. 26B, which is a plan view of FIG. 26A and a cross-sectional view taken along line A-A' of FIG. Including the platform formation step. By patterning the semiconductor layer 10c by lithography or etching, a portion of the second semiconductor layer 102c and the active layer 103c are removed, and at least one semiconductor structure 1000c and around the one or more semiconductor structures 1000c are removed. A surrounding portion 111c exposing the first surface 1011c of the first semiconductor layer 101c and one or more hole portions 100c exposing the second surface 1012c of the first semiconductor layer 101c are formed. .

In one embodiment of the present invention, the plurality of semiconductor structures 1000c are separated from each other to expose the surface 11s of the substrate 11c or connected to each other by the first semiconductor layer 101c. The one or more semiconductor structures 1000c each include a first outer sidewall 1003c, a second outer sidewall 1001c and one or more inner walls 1002c, the first outer sidewall 1003c being a sidewall of the first semiconductor layer 101c. The second outer wall 1001c is a sidewall of the active layer 103c and/or the second semiconductor layer 102c, and one end of the second outer wall 1001c is connected to the surface 102s of the second semiconductor layer 102c. The other end of the second outer wall 1001c is connected to the first surface 1011c of the first semiconductor layer 101c, and one end of the inner wall 1002c is connected to the surface 102s of the second semiconductor layer 102c. and the other end of the inner wall 1002c is connected to the second surface 1012c of the first semiconductor layer 101c. As shown in FIG. 26B, the inner wall 1002c of the semiconductor structure 1000c and the second surface 1012c of the first semiconductor layer 101c form an obtuse or right angle, and the first outer wall of the semiconductor structure 1000c forms an obtuse angle or a right angle. (1003c) and the surface 11s of the substrate 11c form an obtuse or right angle, and the second outer wall 1001c of the semiconductor structure 1000c and the first surface 1011c of the first semiconductor layer 101c form an obtuse or right angle. form a right angle

In one embodiment of the present invention, the surrounding portion 111c has a rectangular or polygonal annular shape when viewed from a plan view of the light emitting device 7 shown in FIG. 26A.

In one embodiment of the present invention, the opening shape of the hole portion 100c is circular, elliptical, rectangular, polygonal, or any other shape. The plurality of hole parts 100c may be arranged in a plurality of rows, and the hole parts 100c on any two adjacent rows or each of the two adjacent rows may be arranged side by side or offset from each other.

In one embodiment of the present invention, the plurality of hole parts 100c may be arranged in a first row and a second row, and a first shortest distance is between two adjacent hole parts 100c located on the same row, A second shortest distance exists between the hole parts 100c located on the first row and the hole parts 100c located on the second row, and the first shortest distance is greater than or less than the second shortest distance. When an external current is injected into the light emitting element 7, the light field distribution of the light emitting element 7 can be made uniform and the forward voltage of the light emitting element 7 can be reduced by distributing the plurality of hole portions 100c. can make it

In one embodiment of the present invention, the plurality of hole portions 100c may be arranged in a first column, a second column, and a third column, and the hole portion 100c located on the first column and the hole portion 100c located on the second column A first shortest distance is provided between the hole portions 100c, a second shortest distance is provided between the hole portions 100c located on the second column and the hole portions 100c located on the third column, and the first shortest distance is 2 is less than the shortest distance. When an external current is injected into the light emitting element 7, the light field distribution of the light emitting element 7 can be made uniform and the forward voltage of the light emitting element 7 can be reduced by distributing the plurality of hole portions 100c. can make it

In one embodiment of the present invention, when the light emitting element 7 has a side length greater than 30 mil, the light emitting element 7 includes a surrounding portion 111c and one or more hole portions 100c. A first shortest distance is between two adjacent hole portions 100c, a second shortest distance is between an arbitrary hole portion 100c and the first outer wall 1003c of the first semiconductor layer 101c, and the first shortest distance is The distance is smaller than the second shortest distance. When an external current is injected into the light emitting element 7, the light field distribution of the light emitting element 7 can be made uniform by the distributed arrangement of the surrounding part 111c and one or more hole parts 100c, and the light emitting element ( The forward voltage of 7) can be reduced.

In one embodiment of the present invention, when the light emitting element 7 has a side length of less than 30 mil, the light emitting element 7 includes a surrounding portion 111c to increase the area of the active layer capable of emitting light. , does not include the hole portion 100c. When an external current is injected into the light emitting element 7, the light field distribution of the light emitting element 7 can be made uniform by the structure in which the surrounding portion 111c surrounds the semiconductor structure 1000c, and the light emitting element The forward voltage of (7) can be reduced.

Following the platform forming step, the manufacturing method of the light emitting element 7 includes a first insulating layer forming step, as shown in FIG. 27B, which is a plan view of FIG. 27A and a cross-sectional view taken along line AA' of FIG. 27A. The first insulating layer 20c is formed on the semiconductor structure 1000c by a physical vapor deposition method or a chemical vapor deposition method, and the first insulating layer 20c is patterned by a lithography or etching method to form the surrounding portion. A first insulating layer surrounding region 200c is formed to cover a part of the first surface 1011c of the semiconductor structure 111c and also to cover the second outer wall 1001c of the semiconductor structure 1000c, A grouped first insulating layer cover region 201c is formed so as to cover the second surface 1012c and also cover the inner wall 1002c of the semiconductor structure 1000c, and also the surface of the second semiconductor layer 102c. A first insulating layer opening 202c is formed to expose 102s. The grouped first insulating layer cover regions 201c are separated from each other and correspond to a plurality of hole portions 100c, respectively. The first insulating layer 20c may have a single-layer or multilayer structure. When the first insulating layer 20c has a single-layer structure, the first insulating layer 20c protects the sidewall of the semiconductor structure 1000c to prevent the active layer 103c from being damaged by a subsequent manufacturing process. When the first insulating layer 20c has a laminated structure, the first insulating layer 20c can protect the semiconductor structure 1000c, and two or more materials having different refractive indices are alternately laminated to form a Bragg reflector ( DBR) structure to selectively reflect light of a specific wavelength. The first insulating layer 20c is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In one embodiment of the present invention, the manufacturing method of the light emitting element 7 following the first insulating layer forming step is as shown in FIG. 28B, which is a plan view of FIG. , and a step of forming a transparent conductive layer. A transparent conductive layer 30c is formed in the first insulating layer opening 202c by a physical vapor deposition method or a chemical vapor deposition method, and the outer edge 301c of the transparent conductive layer 30c and the first insulating layer 20c are separated by a distance. are spaced apart from each other to expose a partial surface 102s of the second semiconductor layer 102c. Since the transparent conductive layer 30c is formed on almost the entire surface of the second semiconductor layer 102c and contacts the second semiconductor layer 102c, current is passed through the second semiconductor layer 102c by the transparent conductive layer 30c. spread evenly throughout. The material of the transparent conductive layer 30c includes a material that is transparent to light emitted from the active layer 103c, and the transparent material is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

In another embodiment of the present invention, after the platform forming step, the transparent conductive layer forming step may be performed first, and then the first insulating layer forming step may be performed.

In another embodiment of the present invention, after the step of forming the platform, the step of forming the first insulating layer may be omitted, and the step of forming the transparent conductive layer may be directly performed.

In one embodiment of the present invention, the manufacturing method of the light emitting element 7 following the transparent conductive layer forming step is a plan view in FIG. 29A, a partially enlarged view of area B in FIG. 29B, a partially enlarged view of area C in FIG. 29C, and FIG. As shown in the partial enlarged view of the area E of FIG. 29D and FIG. 29E, which is a cross-sectional view taken along line A-A' in FIG. 29A, a reflective structure forming step is included. A reflective structure 400 is formed on the transparent conductive layer 30c by a physical vapor deposition method or a chemical vapor deposition method, the reflective structure 400 includes a reflective layer 40c and/or a barrier layer 41c, and the reflective layer (40c) is located between the transparent conductive layer (30c) and the barrier layer (41c). In one embodiment of the present invention, the outer edge 401c of the reflective layer 40c may be provided inside or outside the outer edge 301c of the transparent conductive layer 30c, or the outer edge 301c of the transparent conductive layer 30c. ), and the outer edge 411c of the barrier layer 41c is installed inside or outside the outer edge 401c of the reflective layer 40c, or overlaps with the outer edge 401c of the reflective layer 40c. Can be installed aligned. As shown in the partially enlarged views of FIGS. 29B and 29C and the partially enlarged view of FIG. 29E, the outer edge 401c of the reflective layer 40c does not overlap with the outer edge 301c of the transparent conductive layer 30c, and the transparent conductive layer 40c does not overlap with the transparent conductive layer 30c. The periphery 301c of the layer 30c is covered by the reflective layer 40c so that the barrier layer 41c is not connected to the transparent conductive layer 30c.

In another embodiment of the present invention, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure must be directly performed after the step of forming the platform or the step of forming the first insulating layer, for example, the reflective layer 40c and/or The barrier layer 41c is directly formed on the second semiconductor layer 102c, and the reflective layer 40c is positioned between the second semiconductor layer 102c and the barrier layer 41c.

The reflective layer 40c may have a single-layer or laminated structure, and the laminated structure is, for example, a Bragg reflective structure. The material of the reflective layer 40c includes a metal material having a relatively high reflectance, and the metal material is, for example, a metal such as silver (Ag), aluminum (Al), or rhodium (Rh) or an alloy thereof. Here, having a relatively high reflectance means having a reflectance of 80% or more with respect to the wavelength of light emitted from the light emitting element 7 . In one embodiment of the present invention, the barrier layer 41c covers the reflective layer 40c to prevent the surface of the reflective layer 40c from being oxidized and the reflectance of the reflective layer 40c to deteriorate. The material of the barrier layer 41c includes a metal material, for example, titanium (Ti), wolfram (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum ( Pt) and other metals or alloys thereof. The barrier layer 41c may have a single-layer or laminated structure, and the laminated structure is, for example, titanium (Ti)/aluminum (Al) and/or titanium (Ti)/wolfram (W). In one embodiment of the present invention, the barrier layer 41c includes a titanium (Ti) / wolfram (W) stacked structure on one side close to the reflective layer 40c, and titanium (Ti) on one side away from the reflective layer 40c. )/aluminum (Al) laminated structure. In one embodiment of the present invention, the material of the reflective layer 40c and the barrier layer 41c includes a metal material other than gold (Au) or copper (Cu). As a result, in the subsequent manufacturing process, metal such as tin (Sn) in the package solder is diffused into the light emitting element 7, and the metal material inside the light emitting element 7, such as gold (Au) or copper (Cu) and the process ( It is possible to prevent structural deformation of the light emitting element 7 by forming a negative electrode.

In one embodiment of the present invention, the manufacturing method of the light emitting element 7 following the forming step of the reflective structure, as shown in FIG. 30B, which is a plan view of FIG. A second insulating layer forming step is included. The first semiconductor layer is formed by forming a second insulating layer 50c on the semiconductor structure 1000c by a physical vapor deposition method or a chemical vapor deposition method, and patterning the second insulating layer 50c by a lithography or etching method. One or a first group of second insulating layer openings 501c are formed to expose 101c, and one or a second group of second insulating layer openings 501c are exposed to expose reflective layer 40c or barrier layer 41c. In the process of forming 502c and patterning the second insulating layer 50c, the first insulating layer surrounding region 200c covered by the surrounding part 111c in the first insulating layer forming step and the hole part ( The first insulating layer covering region 201c of the first group in 100c) is partially etched and removed to expose the first semiconductor layer 101c, and the first insulating layer opening 203c of the first group is formed in the hole 100c. is formed to expose the first semiconductor layer 101c.

In this embodiment, as shown in the plan view of FIG. 30A and the cross-sectional view of FIG. 30B , the second insulating layer openings 501c of the first group include a shape or number corresponding to the shape or number of the holes 100c. do. The second insulating layer opening 501c located on the first semiconductor layer 101c and the second insulating layer opening 502c located on the second semiconductor layer 102c include different shapes, widths, and numbers. The plan view opening shape of the second insulating layer openings 501c and 502c is an annular opening.

In this embodiment, as shown in FIG. 30A, the second insulating layer openings 501c positioned on the first semiconductor layer 101c are separated from each other and correspond to a plurality of hole portions 100c, and the second semiconductor layer 101c The second insulating layer opening 502c located on the layer 102c is close to one side of the substrate 11c, for example to the left or right of the center line C-C' of the substrate 11c. The second insulating layer 50c may have a single-layer or multilayer structure. When the second insulating layer 50c has a single-layer structure, the second insulating layer 50c protects the sidewall of the semiconductor structure 1000c to prevent the active layer 103c from being damaged by a subsequent manufacturing process. When the second insulating layer 50c has a laminated structure, the second insulating layer 50c is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure, selectively emitting light of a specific wavelength. can reflect. The second insulating layer 50c is made of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

In an embodiment of the present invention, the method of manufacturing the light emitting element 7 following the second insulating layer forming step, as shown in the plan view of FIG. 31A and the cross-sectional view taken along the line A-A' in FIG. A step of forming a contact layer is included. A contact layer 60c is formed on the semiconductor layer 10c by a physical vapor deposition method or a chemical vapor deposition method, and the contact layer 60c is patterned by lithography or etching to obtain a first contact layer 601c. , forming the second contact layer 602c and the fin region 600c. The first contact layer 601c fills in the hole 100c and covers the second insulating layer opening 501c to contact the first semiconductor layer 101c and expand to form the second insulating layer 50c and the second insulating layer 601c. The partial surface of the second semiconductor layer 102c is covered, and the first contact layer 601c is insulated from the second semiconductor layer 102c through the second insulating layer 50c. The second contact layer 602c is formed within the annular opening 502c of the second insulating layer 50c and contacts the partial reflective layer 40c and/or the barrier layer 41c.

In one embodiment of the present invention, the first contact layer 601c, the second contact layer 602c and the pin region 600c are spaced apart from each other. The second contact layer 602c is formed by partially extending into the annular opening 502c of the second insulating layer 50c, and the sidewall 6021c of the second contact layer 602c and the sidewall of the annular opening 502c ( 5021c) are spaced apart from each other, and the sidewall 6011c of the first contact layer 601c is spaced apart from the sidewall 6021c of the second contact layer 602c, so that the first contact layer 601c is the first contact layer 601c. The second contact layer 602c is not connected, and the first contact layer 601c and the second contact layer 602c are partially electrically insulated by the second insulating layer 50c. On a plan view of the light emitting element 7, the first contact layer 601c surrounds the plurality of sidewalls of the second contact layer 602c, so that the first contact layer 601c surrounds the semiconductor layer 10c ( 111c).

In one embodiment of the present invention, the first contact layer 601c is in contact with the first semiconductor layer 101c by the surrounding portion 111c and the hole portion 100c. When an external current is injected into the light emitting element 7, some of the current is conducted to the first semiconductor layer 101c by the surrounding portion 111c, and another portion of the current is transmitted to the first semiconductor layer by the plurality of hole portions 100c. It conducts to (101c).

As shown in FIG. 31A, the second contact layer 602c is adjacent to one side of the substrate 11c, for example, to the left or right of the center line C-C' of the substrate 11c. The fin region 600c is located at the geometric center of the semiconductor stack 10c. The pin region 600c is connected to the first contact layer 601c and the second contact layer 602c, and electrically insulated from the first contact layer 601c and the second contact layer 602c, and the fin region ( 600c) includes the same material as the first contact layer 601c and/or the second contact layer 602c. The fin region 600c is a structure that protects the epitaxial layer, and prevents the epitaxial layer from being damaged by an external force such as a probe or a pin in a subsequent manufacturing process such as die separation, die test, and packaging. The shape of the pin area 600c is rectangular, elliptical or circular.

In one embodiment of the present invention, the fin region 600c is located at the geometric center of the semiconductor stack 10c. The pin area 600c is connected to the first contact layer 601c or the second contact layer 602c, and the pin area 600c is connected to the first contact layer 601c and/or the second contact layer 602c. contain the same material.

In one embodiment of the present invention, the contact layer 60c may have a single-layer or laminated structure. In order to reduce electrical resistance in contact with the first semiconductor layer 101c, the material of the contact layer 60c includes a metal material, such as chromium (Cr), titanium (Ti), wolfram (W), A metal such as gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt) or an alloy thereof. The material of the contact layer 60c includes a metal material other than gold (Au) and copper (Cu), and accordingly, in a subsequent manufacturing process, metal such as tin (Sn) in the package solder is diffused into the light emitting element 7 , It is possible to prevent structural deformation of the light emitting element 7 by forming a process with a metal material such as gold (Au) or copper (Cu) in the light emitting element 7 .

In one embodiment of the present invention, the material of the contact layer 60c includes a metal having a high reflectance, for example, aluminum (Al) or platinum (Pt).

In one embodiment of the present invention, in order to increase the bonding strength between the contact layer 60c and the first semiconductor layer 101c, one side of the contact layer 60c in contact with the first semiconductor layer 101c is chromium (Cr). ) or titanium (Ti).

In the embodiment of the present invention, following the contact layer forming step of FIGS. 31A and 31B, the manufacturing method of the light emitting element 7 includes a third insulating layer forming step, and the plan view of FIG. 32A and A-A of FIG. 32A As shown in FIG. 32B, which is a cross-sectional view along the line, a third insulating layer 70c is formed on the semiconductor structure 1000c by a physical vapor deposition method or a chemical vapor deposition method, and a third insulating layer 70c is formed by lithography and etching. patterning the insulating layer 70c to form third insulating layer openings 701c and 702c so as to expose the first contact layer 601c and the second contact layer 602c, respectively; forming a first portion 7011c of the third insulating layer 70c surrounded by the third insulating layer opening 701c; forming a second portion 7022c of the third insulating layer 70c surrounded by the third insulating layer opening 702c; A connecting portion 7000c of the third insulating layer 70c is formed between the third insulating layer opening 701c and the third insulating layer opening 702c. As shown in FIG. 32A, the connection portion 7000c of the third insulating layer 70c surrounds the first portion 7011c and the second portion 7022c of the third insulating layer 70c, respectively. As shown in FIG. 32B, the connecting portion 7000c of the third insulating layer 70c is located on both sides of the first portion 7011c of the third insulating layer 70c, and the third insulating layer 70c is connected. Portion 7000c is located on both sides of second portion 7022c of third insulating layer 70c. The third insulating layer opening 701c is formed by the first side 70111 of the first portion 7011c of the third insulating layer 70c and the side 70001 of the connection portion 7000c of the third insulating layer 70c. The third insulating layer opening 702c is the second side 70222c of the second portion 7022c of the third insulating layer 70c and the other side of the connection portion 7000c of the third insulating layer 70c. (70002c).

In one embodiment of the present invention, the first contact layer 601c positioned on the second semiconductor layer 102c is interposed between the second insulating layer 50c and the third insulating layer 70c. The pin region 600c is surrounded and covered by the connection portion 7000c of the third insulating layer 70c.

In one embodiment of the present invention, as shown in FIG. 32A, the third insulating layer openings 701c and 702c and the plurality of hole portions 100c are staggered and do not overlap each other. In other words, the third insulating layer opening 701c and the second insulating layer opening 501c are crossed and do not overlap each other. The third insulating layer opening 702c may be surrounded by the second insulating layer opening 502c. 32A, the third insulating layer openings 701c and 702c are on both sides of the center line C-C' of the substrate 11c, for example, the third insulating layer opening 701c is on the right side of the center line C-C' of the substrate 11c. , and the third insulating layer opening 702c is located on the left side of the center line C-C' of the substrate 11c.

In one embodiment of the present invention, the third insulating layer opening 701c has a width smaller than the width of the second insulating layer opening 501c, and the third insulating layer opening 702c is the second insulating layer opening 502c. has a width less than the width of

In one embodiment of the present invention, the third insulating layer opening 701c has a width larger than that of the second insulating layer opening 501c, and the third insulating layer opening 702c is the second insulating layer opening 502c. has a width greater than the width of

The third insulating layer 70c may have a single-layer or multilayer structure. When the third insulating layer 70c has a laminated structure, the third insulating layer 70c is formed by alternately stacking two or more materials having different refractive indices to form a DBR structure, selectively emitting light of a specific wavelength. can reflect. The third insulating layer 70c is formed of a non-conductive material, and includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer ( COC), polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or organic materials such as silicon, It includes inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). .

Following the third insulating layer forming step, the manufacturing method of the light emitting device 7 includes a bonding pad forming step. As shown in FIG. 33B, which is a plan view of FIG. 33A and a cross-sectional view taken along line A-A' of FIG. 33A, first bonding is performed on one or more semiconductor structures 1000c by electroplating, physical vapor deposition, or chemical vapor deposition. A pad 80c and a second bonding pad 90c are formed. 33A, the first bonding pad 80c is close to one side of the substrate 11c, for example, to the right of the center line C-C' of the substrate 11c, and the second bonding pad 90c is adjacent to the substrate 11c. It is close to the other side, for example, to the left of the center line C-C' of the substrate 11c. The first bonding pad 80c covers the third insulating layer opening 701c to contact the first contact layer 601c, and through the first contact layer 601c and the hole 100c, the first semiconductor layer ( 101c) and form an electrical connection. The second bonding pad 90c covers the third insulating layer opening 702c, contacts the second contact layer 602c, and forms the second contact layer 602c, the reflective layer 40c or the barrier layer 41c. Through this, an electrical connection with the second semiconductor layer 102c is formed. As shown in FIG. 33A, the first bonding pad 80c and the second bonding pad 90c do not cover all the holes 100c, and the hole parts 100c are the first bonding pads 80c and the second bonding pads 90c. It is formed in an area other than the pad 90c.

In one embodiment of the present invention, the first bonding pad 80c has a size equal to or different from that of the second bonding pad 90c, and the corresponding size may be a width or an area.

In one embodiment of the present invention, as shown in FIG. 33B, the first bonding pad 80c includes a side 801c, and the side 801c of the first bonding pad 80c and the third insulating layer ( The first side 70111 of the first portion 7011c of 70c) or the side 70001 of the connection portion 7000c of the third insulating layer 70c is spaced apart from each other, and the distance is smaller than 100 μm. It is preferably smaller than 50 μm, more preferably smaller than 20 μm, and most preferably smaller than 20 μm. The second bonding pad 90c includes a side 902c, and the side 902c of the second bonding pad 90c is the second side 70222c of the second portion 7022c of the third insulating layer 70c. Alternatively, it is spaced apart from the other side 70002c of the connection portion 7000c of the third insulating layer 70c at a distance, and the distance is preferably smaller than 100 μm, more preferably smaller than 50 μm, and smaller than 20 μm. it is most preferable

In one embodiment of the present invention, on a plan view of the light emitting element 7, the side 801c of the first bonding pad 80c is disposed along the side 70001, 70111 of the third insulating layer opening 701c, The side 902c of the second bonding pad 90c is disposed along the side sides 70002c and 70222c of the third insulating layer opening 702c.

FIG. 33A is a plan view of the light emitting element 7, and FIG. 33B is a cross-sectional view of the light emitting element 7. The light emitting device 7 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting element 7 includes a substrate 11c; one or more semiconductor structures 1000c located on the substrate 11c; a surrounding portion 111c surrounding one or more semiconductor structures 1000c; and a first bonding pad 80c and a second bonding pad 90c positioned on the semiconductor stack 10c. Each of the one or more semiconductor structures 1000c includes a semiconductor stack 10c, wherein the semiconductor stack 10c includes a first semiconductor layer 101c, a second semiconductor layer 102c, a first semiconductor layer 101c, and a second semiconductor layer 101c. It includes an active layer 103c positioned between the semiconductor layers 102c.

As shown in FIGS. 33A and 33B , the periphery of one or more semiconductor structures 1000c is surrounded by a surrounding portion 111c. In one embodiment of the present invention, the plurality of semiconductor structures 1000c are connected to each other by the first semiconductor layer 101c, and the surrounding portion 111c surrounds the plurality of semiconductor structures 1000c. and a first surface 1011c of layer 101c. In another embodiment of the present invention, the plurality of semiconductor structures 1000c are separated from each other and spaced apart at a distance to expose the surface 11s of the substrate 11c.

The light emitting device 7 further includes one or more hole portions 100c penetrating the second semiconductor layer 102c and the active layer 103c to expose one or more second surfaces 1012c of the first semiconductor layer 101c. .

The light emitting element 7 is formed on the first surface 1011c of the first semiconductor layer 101c, surrounds the periphery of the semiconductor structure 1000c and contacts the first semiconductor layer 101c to form an electrical connection. In addition, the first contact layer formed on the one or more second surfaces 1012c of the first semiconductor layer 101c covers the one or more holes 100c and contacts the first semiconductor layer 101c to form an electrical connection. (601c); and a second contact layer 602c formed on the surface 102s of the second semiconductor layer 102c. In one embodiment of the present invention, as shown in FIG. 31A, which is a plan view of the light emitting device 7, the first contact layer 601c surrounds a plurality of sidewalls of the second contact layer 602c.

In one embodiment of the present invention, the first bonding pads 80c and/or the second bonding pads 90c cover a plurality of semiconductor structures 1000c.

In one embodiment of the present invention, the formation position of the first bonding pad 80c and the second bonding pad 90c avoids the formation position of the hole 100c, and the first bonding pad 80c and the second bonding pad 90c are formed. The formation position of (90c) does not overlap with the formation position of the hole part (100c).

In one embodiment of the present invention, on a plan view of the light emitting element 7, the shape of the first bonding pad 80c and the shape of the second bonding pad 90c are the same, and as shown in FIG. 33A, for example, The shapes of the first bonding pad 80c and the second bonding pad 90c are rectangular.

In one embodiment of the present invention, the size of the first bonding pad 80c and the size of the second bonding pad 90c are different, for example, the area of the first bonding pad 80c is the size of the second bonding pad 90c. area larger or smaller than The material of the first bonding pad 80c and the second bonding pad 90c includes a metal material, for example, chromium (Cr), titanium (Ti), wolfram (W), aluminum (Al), indium ( In), tin (Sn), nickel (Ni), platinum (Pt), or other metals or alloys thereof. The first bonding pad 80c and the second bonding pad 90c may have a single-layer or laminated structure. When the first bonding pad 80c and the second bonding pad 90c have a laminated structure, the first bonding pad 80c includes a first upper bonding pad and a first lower bonding pad, and the second bonding pad 90c ) includes a second upper bonding pad and a second lower bonding pad. The upper bonding pad and the lower bonding pad each have different functions.

In one embodiment of the present invention, the function of the upper layer bonding pad is mainly to weld and form lead wires. By means of the upper bonding pad, the light emitting device 7 is mounted on the package substrate in a flip chip format using solder or Au-Sn eutectic bonding. The metal material of the upper bonding pad includes a material of high ductility, and the material of high ductility is, for example, tin (Sn), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu) , Gold (Au), Wolfram (W), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), Palladium (Pd), Rhodium (Rh) , iridium (Ir), ruthenium (Ru), osmium (Os), and other metals or alloys thereof. The upper layer bonding pad may have a single layer or laminated structure of the above material. In an embodiment of the present invention, the material of the upper bonding pad includes nickel (Ni) and/or gold (Au), and the upper bonding pad has a single-layer or laminated structure.

In one embodiment of the present invention, the function of the lower bonding pad is to form a stable interface with the contact layer 60c, the reflective layer 40c, or the barrier layer 41c, for example, the first lower bonding pad and the first contact layer. The interfacial bonding strength of (601c) is improved or the interfacial bonding strength between the second lower layer bonding pad and the reflective layer 40c or the barrier layer 41c is improved. Another function of the lower bonding pad is to prevent tin (Sn) from being diffused into the reflective structure during solder or Au-Sn fixation and damaging the reflectance of the reflective structure. Therefore, the lower bonding pad is made of a metal material other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), and zirconium (Zr). , Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), Palladium (Pd), Rhodium (Rh), Iridium (Ir), Ruthenium (Ru), Osmium (Os) metals or alloys thereof, and the lower bonding pad may have a single layer or laminated structure of the above material. In one embodiment of the present invention, the lower bonding pad includes a titanium (Ti)/aluminum (Al) laminated structure or a chromium (Cr)/aluminum (Al) laminated structure.

In one embodiment of the present invention, it is to prevent tin (Sn) from being diffused into the reflective structure during the solder or Au-Sn process to damage the reflectance of the reflective structure. Accordingly, one side where the first contact layer 601c and the first bonding pad 80c are connected includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt). One side where the second contact layer 602c and the second bonding pad 90c are connected includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt).

34A is a plan view of the light emitting element 8 of the embodiment of the present invention, and FIG. 34B is a cross-sectional view of the light emitting element 8. When comparing the light emitting element 8 with the light emitting element 7 of the above embodiment, the light emitting element 8 is a metal layer (which surrounds a plurality of sidewalls of the first bonding pad 80d and/or the second bonding pad 90d) 900d), and a first electrode block 810d and a second electrode block 910d positioned above the first bonding pad 80d and the second bonding pad 90d, respectively. In addition, since the light emitting element 8 and the light emitting element 7 have almost the same structure, the light emitting element 8 of FIGS. 34A and 34B and the light emitting element 7 of FIGS. 33A and 33B have the same name and code. Since they have a structure, show the same structure, have the same material, or have the same function, explanations are not appropriately omitted or described here.

The light emitting device 8 disclosed in this embodiment is a flip chip type light emitting diode device. The light emitting element 8 includes a substrate 11c; one or more semiconductor structures 1000c located on the substrate 11c; a surrounding portion 111c surrounding one or more semiconductor structures 1000c; a first bonding pad 80d and a second bonding pad 90d positioned on the semiconductor stack 10c; and a first electrode block 810d and a second electrode block 910d positioned above the first bonding pad 80d and the second bonding pad 90d, respectively. Each of the one or more semiconductor structures 1000c includes a semiconductor stack 10c, wherein the semiconductor stack 10c includes a first semiconductor layer 101c, a second semiconductor layer 102c, a first semiconductor layer 101c, and a second semiconductor layer 101c. It includes an active layer 103c positioned between the semiconductor layers 102c.

As shown in FIGS. 34A and 34B , the periphery of one or more semiconductor structures 1000c is surrounded by a surrounding portion 111c. In one embodiment of the present invention, the plurality of semiconductor structures 1000c may be connected to each other by the first semiconductor layer 101c, and the surrounding portion 111c surrounds the plurality of semiconductor structures 1000c. It includes the first surface 1011c of the semiconductor layer 101c. In another embodiment of the present invention, the plurality of semiconductor structures 1000c are separated from each other and spaced apart from each other to expose the surface 11s of the substrate 11c.

The light emitting element 8 further includes one or more hole portions 100c penetrating the second semiconductor layer 102c and the active layer 103c to expose one or more second surfaces 1012c of the first semiconductor layer 101c. .

The light emitting element 8 is formed on the first surface 1011c of the first semiconductor layer 101c, surrounds the periphery of the semiconductor structure 1000c, and contacts the first semiconductor layer 101c to form an electrical connection. In addition, the first contact layer formed on the one or more second surfaces 1012c of the first semiconductor layer 101c covers the one or more holes 100c and contacts the first semiconductor layer 101c to form an electrical connection. (601c); and a second contact layer 602c formed on the surface 102s of the second semiconductor layer 102c to form an electrical connection with the second semiconductor layer 102c. In one embodiment of the present invention, on a plan view of the light emitting device 2, the first contact layer 601c surrounds a plurality of sidewalls of the second contact layer 602c, and the second contact layer 602c has a first It has a smaller size (eg area) than the size of the contact layer 601c.

In one embodiment of the present invention, the first bonding pad 80d partially or entirely covers the hole portion 100c and/or the second bonding pad 90d partially or entirely covers the hole portion 100c. As shown in FIG. 34A, the first bonding pad 80d covers the partial hole portion 100c, and the second bonding pad 90d does not cover all the hole portion 100c.

When a light emitting device is mounted on a package substrate in the form of a flip chip, the insulating layer on the surface of the light emitting device is easily damaged by a collision with an external force. into the interior, causing failure of the light emitting element. In one embodiment of the present invention, the light emitting element 8 includes a metal layer 900d positioned on the semiconductor stack 10c to protect the lower insulating layer, thereby preventing the insulating layer from being damaged by a collision of an external force. do. As shown in FIG. 34A, the metal layer 900d surrounds a plurality of sidewalls of the second bonding pad 90d, and the metal layer 900d and the second bonding pad 90d are spaced apart from each other. The metal layer 900d covers the partial hole 100c, and a portion of the first contact layer 601c is positioned below the metal layer 900d and insulated from the metal layer 900d by the third insulating layer 70c.

In one embodiment of the present invention, the first bonding pad 80d, the second bonding pad 90d and the metal layer 900d are spaced apart from each other and are not connected to each other.

In an embodiment of the present invention, the light emitting element 8 includes a third insulating layer 70c, and the third insulating layer 70c exposes the first contact layer 601c and the second contact layer 602c. It includes one or more openings 701c and 702c to expose a partial surface of the third insulating layer 70c, and there is a gap between the metal layer 900d and the second bonding pad 90d.

In one embodiment of the present invention, on a plan view of the light emitting element 8, the shape of the first bonding pad 80d and the shape of the second bonding pad 90d are different, for example, the shape of the first bonding pad 80d. is a rectangle, and the shape of the second bonding pad 90d is a comb shape.

In one embodiment of the present invention, on a plan view of the light emitting device 8, the first bonding pad 80d has a size (eg, area) different from that of the second bonding pad 90d.

In one embodiment of the present invention, the sizes of the first bonding pad 80d and the second bonding pad 90d are different from those of the first electrode block 810d and the second electrode block 910d, respectively. The area of one bonding pad 80d is larger than that of the first electrode block 810d, and the area of the second bonding pad 90d is larger than that of the second electrode block 910d.

In one embodiment of the present invention, the distance between the first bonding pad 80d and the second bonding pad 90d is smaller than the distance between the first electrode block 810d and the second electrode block 910d.

In one embodiment of the present invention, on a plan view of the light emitting element 8, the shape of the first electrode block 810d is similar to or the same as the shape of the second electrode block 910d, for example, the first electrode block 810d. And the shape of the second electrode block 910d is a comb shape, and as shown in FIG. 10C, the first electrode block 810d has a plurality of first convex portions 811d and a plurality of first concave portions alternately connected to each other. includes section 812d. The second electrode block 910d includes a plurality of second convex portions 911d and a plurality of second concave portions 912d alternately connected to each other. The location of the first concave portion 812d of the first electrode block 810d and the location of the second concave portion 912d of the second electrode block 910d substantially correspond to the location of the hole portion 100c. In other words, the width of the first concave portion 812d of the first electrode block 810d or the width of the second concave portion 912d of the second electrode block 910d is larger than the diameters of all the hole portions 100c, and The first electrode block 810d and the second electrode block 910d do not cover all the holes 100c, and the first concave portion 812d of the first electrode block 810d and the second electrode block 910d 2 concave portions 912d are formed around the hole portion 100c while avoiding the hole portion 100c. In one embodiment of the present invention, the plurality of first concave portions 812d are substantially aligned with the plurality of second concave portions 912d in a plan view. In another embodiment of the present invention, the plurality of first concave portions 812d are displaced from the plurality of second concave portions 912d in a plan view.

In one embodiment of the present invention, when the light emitting device 8 is mounted on a package substrate in a flip chip format, multi-layer insulation is provided between the first bonding pad 80d and the second bonding pad 90d and the semiconductor layer 10c. The first bonding pad 80d and the second bonding pad 90d of the light emitting device 8 are formed by external force, for example, by stress generated during solder or Au-Sn eutectic bonding. Since cracks occur in the first bonding pad 80d, the second bonding pad 90d, and the insulating layer, the light emitting element 8 is located above the first bonding pad 80d and the second bonding pad 90d, respectively. It includes a first electrode block 810d and a second electrode block 910d and is bonded to the outside by the first electrode block 810d and the second electrode block 910d, and the first electrode block 810d and the second electrode block 810d Since the formation position of the electrode block 910d avoids the formation position of the hole 100c, it is possible to reduce the occurrence of stress between the bonding pad and the insulating layer due to external force.

In another embodiment of the present invention, compared to the first electrode block 810d and the second electrode block 910d, the pressure during die bonding of the first electrode block 810d and the second electrode block 910d is reduced. To release, the first bonding pad 80d and the second bonding pad 90d have a relatively large area. In a cross-sectional view of the light emitting device 8, the first bonding pad 80d has a width that is 1.2 to 2.5 times, preferably twice the width of the first electrode block 810d.

In another embodiment of the present invention, compared to the first electrode block 810d and the second electrode block 910d, the pressure during die bonding of the first electrode block 810d and the second electrode block 910d is reduced. The first bonding pad 80d and the second bonding pad 90d have a relatively large area to emit light. In a cross-sectional view of the light emitting element 8, the extension distance of the first bonding pad 80d is one time or more of its own thickness, and preferably two times or more of its own thickness.

In another embodiment of the present invention, the first electrode block 810d and the second electrode block 910d have a thickness of 1 to 100 μm, preferably 1.5 to 6 μm, and the first electrode block 810d and the second electrode block 810d have a thickness of 1.5 to 6 μm. It is mounted on the package substrate in the form of a flip chip by 910d. The first bonding pad 80d and the second bonding pad 90d have a thickness greater than 0.2 μm to release the pressure when the first electrode block 810d and the second electrode block 910d are solidified, and preferably have a thickness greater than 0.2 μm. Larger than 0.5 μm, smaller than 1 μm.

In another embodiment of the present invention, the first bonding pad 80d, the second bonding pad 90d, and the metal layer 900d include the same metal material and/or the same metal laminate.

The first bonding pad 80d, the second bonding pad 90d, and the metal layer 900d may have a single-layer or stacked structure. The function of the first bonding pad 80d and the second bonding pad 90d is to form a stable interface with the first contact layer 601c, the reflective layer 40c, or the barrier layer 41c, for example, the first bonding pad 80d is in contact with the first contact layer 601c, and the second bonding pad 90d is in contact with the reflective layer 40c or the barrier layer 41c. The first bonding pad 80d and the second bonding pad 90d are formed by diffusion of tin (Sn) in the solder or Au-Sn process into the light emitting device 8, and the first bonding pad 80d and the second bonding pad ( 90d) metal materials other than gold (Au) and copper (Cu), such as chromium (Cr) and nickel, to prevent generation of eutectic metals such as gold (Au) and copper (Cu) included in (Ni), Cobalt (Co), Iron (Fe), Titanium (Ti), Wolfram (W), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), and the like, or alloys thereof. The metal layer 900d is made of a metal material other than gold (Au) and copper (Cu), for example, chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), wolfram (W), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Aluminum (Al), Silver (Ag), Platinum (Pt), Palladium (Pd), Rhodium (Rh), Iridium (Ir), Ruthenium (Ru), and metals such as osmium (Os) or alloys thereof. One side of the metal layer 900d connected to the third insulating layer 70c is made of chromium (Cr), nickel (Ni), or titanium (Ti) to improve interfacial bonding strength between the metal layer 900d and the third insulating layer 70c. , or platinum (Pt).

In another embodiment of the present invention, the first bonding pad 80d and/or the second bonding pad 90d have a laminated structure, and the laminated structure is generated when the bonding pads 80d and 90d are bonded with a solder or Au-Sn process. A high ductility layer and a low ductility layer are included to prevent cracks from occurring in the insulating layer between the bonding pads 80d and 90d and the semiconductor layer 10a due to stress caused by the applied stress. The high ductility layer and the low ductility layer include metals having different Young's modulus.

In another embodiment of the present invention, the high-flexibility layer of the first bonding pad 80d and/or the second bonding pad 90d has a thickness greater than or equal to the thickness of the low-flexibility layer.

In another embodiment of the present invention, the first bonding pad 80d and the second bonding pad 90d have a laminated structure, the first electrode block 810d and the second electrode block 910d have a laminated structure, and the first The surface where the bonding pad 80d and the first electrode block 810d are connected is made of the same metal material, and the surface where the second bonding pad 90d and the second electrode block 910d are connected is made of the same metal material (for example, By including chromium (Cr), nickel (Ni), titanium (Ti), or platinum (Pt)), the interfacial bonding strength between the bonding pad and the bumper pad is improved.

In another embodiment of the present invention, following the bonding pad forming step, the manufacturing method of the light emitting element 8 includes a fourth insulating layer forming step. A fourth insulating layer (not shown) is formed on the first bonding pad 80d and the second bonding pad 90d by physical vapor deposition or chemical vapor deposition, and the first electrode block 810d and the second electrode block are formed. 910d is formed on the first bonding pad 80d and the second bonding pad 90d, respectively, and the fourth insulating layer surrounds sidewalls of the first bonding pad 80d and the second bonding pad 90d. . The fourth insulating layer may have a single-layer or laminated structure. When the fourth insulating layer has a laminated structure, the fourth insulating layer may selectively reflect light of a specific wavelength by forming a DBR structure by alternately stacking two or more materials having different refractive indices. The material of the fourth insulating layer is made of a non-conductive material, and Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC) ), organic materials such as polymethyl methacrylic acid (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or silicone, glass Inorganic materials such as glass, or dielectric materials such as alumina (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ) or magnesium fluoride (MgF _x ).

In one embodiment of the present invention, the manufacturing process of the first electrode block 810d and the second electrode block 910d may immediately follow the manufacturing process of the first bonding pad 80d and the second bonding pad 90d. . In another embodiment of the present invention, after the manufacturing process of the first bonding pad 80d and the second bonding pad 90d, first the fourth insulating layer is formed, and then the first electrode block 810d and the second bonding pad 90d are formed. A manufacturing process of the two-electrode block 910d is performed.

35 is a schematic diagram of a light emitting device according to an embodiment of the present invention. The semiconductor light emitting device 1, light emitting device 2, light emitting device 3, light emitting device 4, light emitting device 5, light emitting device 6, light emitting device 7 or light emitting device of the above-described embodiments (8) is mounted on the first pad 511 and the second pad 512 of the package substrate 51 in a flip chip format. The first pad 511 and the second pad 512 are electrically insulated by an insulating portion 53 including an insulating material. When mounting the flip chip, one side of the growth substrates 11a and 11b facing the electrode formation surface is set as a main light extraction surface. In order to increase the light extraction effect of the light emitting device, a semiconductor light emitting device (1), a light emitting device (2), a light emitting device (3), a light emitting device (4), a light emitting device (5), a light emitting device (6), a light emitting device ( 7) Alternatively, a reflective structure 54 may be installed around the light emitting element 8.

36 is a schematic diagram of a light emitting device according to an embodiment of the present invention. The bulb 600 includes a lamp shade 602, a reflector 604, a light emitting module 610, a lamp holder 612, a heat sink 614, a connector 616, and an electrically connected element 618. include The light emitting module 610 includes a mounting unit 606 and a plurality of light emitting elements 608 positioned on the mounting unit 606, and the plurality of light emitting elements 608 are the semiconductor light emitting elements 1 of the above-described embodiments, It may be a light emitting element 2 , a light emitting element 3 , a light emitting element 4 , a light emitting element 5 , a light emitting element 6 , a light emitting element 7 , or a light emitting element 8 .

Each embodiment illustrated in the present invention is only for explaining the present invention, and is not intended to limit the scope of the present invention. Obvious modifications or changes made to the present invention by anyone do not depart from the spirit and scope of the present invention.

1, 2, 3, 4, 5, 6 light-emitting elements
11a, 11b substrate
10a, 10b semiconductor layer
101a, 101b first semiconductor layer
102a, 102b second semiconductor layer
103a, 103b active layer
100a, 100b holes
102s surface
1011a, 1011b first surface
1012a, 1012b second surface
110a fourth insulating layer
111a, 111b surrounding parts
20a, 20b first insulating layer
200a, 200b first insulating layer surrounding area
201a, 201b first insulating layer cover area
202a, 202b first insulating layer opening
203a, 203b first insulating layer opening
30a, 30b transparent conductive layer
300b transparent conductive layer opening
301a, 301b transparent conductive layer outer edge
40a, 40b reflective layer
400b reflective layer aperture
401a, 401b reflective layer outer edge
41a, 41b barrier layer
410b barrier layer opening
411a, 411b barrier layer outer edge
50a, 50b second insulating layer
501a, 501b second insulating layer opening
502a, 502b second insulating layer opening
5020b annular opening
5021b sidewall
60a, 60b contact layer
600a, 600b pin area
602a contact layer opening
601b first contact layer
6011b first contact layer sidewall
602b second contact layer
6021b second contact layer sidewall
70a, 70b third insulating layer
701a, 702a third insulating layer opening
701b, 702b third insulating layer opening
80a, 80b first bonding pad
90a, 90b second bonding pad
800a first bonding pad opening
801b first convex portion
802a first side
802b first recess
803b first flat
804a first recess
805a first upper layer bonding pad
807a first lower layer bonding pad
810a first bumper pad
900a second bonding pad opening
901b second convex portion
902a second side
902b second recess
903b second straight edge
904a second recess
905a second upper layer bonding pad
907a second lower layer bonding pad
910a, 910b Second bumper pad
1000a, 1000b semiconductor structure
1001a, 1001b second outer wall
1002a, 1002b inner wall
1003a, 1003b first outer wall
51 package substrate
511 first pad
512 second pad
53 insulation
54 Reflective structures
600 bulbs
602 lamp shade
604 reflector
606 mount
608 light emitting device
610 light emitting module
612 lamp holder
614 heatsink
616 connection
618 Electrically Connected Elements

Claims (10)

In the light emitting device,
A semiconductor laminate, a surrounding portion, a plurality of hole portions, a first contact layer, a second contact layer, a first bonding pad and a second bonding pad,
the semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer positioned between the first semiconductor layer and the second semiconductor layer;
the surrounding portion surrounds the semiconductor laminate and exposes a first surface of the first semiconductor layer;
the plurality of holes penetrate the active layer to expose the second surface of the first semiconductor layer;
the first contact layer covers the first semiconductor layer through the surrounding portion and the plurality of hole portions;
the second contact layer is located on the second semiconductor layer and is surrounded by the first contact layer;
the first bonding pad is located on the first contact layer;
The second bonding pad is located on the second contact layer, and in a plan view, the first bonding pad and the second bonding pad are formed in an area other than the plurality of hole portions. According to claim 1,
The plurality of hole parts include two adjacent hole parts located on the same column, a first shortest distance between the two adjacent hole parts, and the plurality of hole parts further include a hole adjacent to an edge of the light emitting device. and a second shortest distance between the hole and the first outer wall of the first semiconductor layer, and wherein the first shortest distance is greater than the second shortest distance. According to claim 1,
The plurality of hole parts include two adjacent hole parts located on the same column, a first shortest distance between the two adjacent hole parts, and the plurality of hole parts further include a hole adjacent to an edge of the light emitting device. and a second shortest distance between the hole and the first outer wall of the first semiconductor layer, and wherein the first shortest distance is smaller than the second shortest distance. According to claim 1,
The plurality of hole parts include two adjacent hole parts located on the same column, a first shortest distance between the two adjacent hole parts, and the plurality of hole parts further include a hole adjacent to an edge of the light emitting device. and a second shortest distance between the hole portion and the first outer wall of the first semiconductor layer, wherein the first shortest distance is equal to the second shortest distance. According to claim 1,
The light emitting device further comprises a first insulating layer covering a sidewall of the active layer, wherein the first insulating layer has a first insulating layer opening to expose the second semiconductor layer. According to claim 3,
Further comprising a transparent conductive layer positioned within the opening of the first insulating layer, wherein an outer edge of the transparent conductive layer is spaced apart from the first insulating layer at a distance. According to claim 1,
It further includes a reflective layer positioned on the second semiconductor layer and a barrier layer positioned on the reflective layer, wherein an outer edge of the barrier layer is located outside the outer edge of the reflective layer or positioned to overlap with the outer edge of the reflective layer. to be, a light-emitting device. According to claim 1,
The first contact layer is not located below the second bonding pad, and the first contact layer and the second contact layer do not overlap each other. According to claim 1,
An area included in the first contact layer is larger than an area included in the second contact layer. According to claim 1,
Wherein the first contact layer comprises a metal material other than alloy.

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