TWI758212B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes: a semiconductor stack including a first region and a second region protruded from the first region and surrounded by the first region, and the second region includes a first length; a first contact structure disposed on the first region and comprises a second length shorter than the first length. The first contact structure includes a first end part and a second end part. A first conductive structure covers the first region and the second region and connects to the first contact structure.

Description

semiconductor element

The present application relates to a semiconductor device, especially a semiconductor device with a conductive structure.

The semiconductor element includes compound semiconductors composed of III-V group elements, such as gallium phosphide (GaP), gallium arsenide (GaAs) or gallium nitride (GaN), and the semiconductor element can be an optoelectronic semiconductor element such as a light emitting diode (LED). ), lasers, photodetectors, solar cells, or Power Devices. The structure of the light-emitting diode includes a p-type semiconductor layer, an n-type semiconductor layer and an active layer, and the active layer is arranged between the p-type semiconductor layer and the n-type semiconductor layer, so that under the action of an external electric field, n The electrons and holes provided by the p-type semiconductor layer and the p-type semiconductor layer respectively recombine in the active layer to convert electrical energy into light energy. How to improve the photoelectric conversion efficiency of optoelectronic semiconductor components is actually one of the focuses of R&D personnel.

A semiconductor device, comprising: a semiconductor stack includes a first region and a second region, the second region protrudes from the first region and has a first length, and the first region surrounds the second region; a first region The contact structure is arranged on the first area and has a second length, and the first contact structure has A corresponding first end portion and a second end portion, wherein the second length is smaller than the first length; and a first conductive structure covers the first area and the second area, and the first conductive structure and the first end Ministry contact.

100: Semiconductor Components

102: Substrate

102a: Long side

102b: Short side

103: Semiconductor Stacks

103a: First Region

103b: Second area

103c: Sidewall area

104: first semiconductor layer

106: Light-emitting active layer structure

108: Second semiconductor layer

110: First Contact Structure

1101: The first contact part

1101a: First end

1101b: Second end

1101c: Middle Section

112: Second Contact Structure

112a: second contact part

114: First Protection Structure

114a: first opening

114b: second opening

116: The first conductive structure

116a1: Upper surface

116a2: side surface

1161: Part 1

1162: Part II

116a: first conductive part

116b: first electrode part

118: Second conductive structure

118a: second conductive part

118a1: Upper surface

118a2: side surface

118b: second electrode part

124: Second protective layer

124a: third opening

124b: Fourth opening

200: Semiconductor Components

202: Substrate

202a: Long side

202b: Short side

203: Semiconductor Stacks

203a: First Region

203b: Second area

203c: Sidewall area

203b1: Recess

203b2: convex part

204: first semiconductor layer

205: Etching Platform

206: Active structure

208: Second semiconductor layer

210: First Contact Structure

212: Second Contact Structure

2121: Main body

2122: Extensions

214: First Protection Structure

214a: first opening

214b: Second opening

216: first conductive structure

2161: Part 1

2162: Part II

218: Second Conductive Structure

300: Semiconductor Components

302: Substrate

302a: Long side

302b: Short side

303a: First Region

303b: Second area

303c: Sidewall area

303b1: Part 1

303b2: Second part

303b3: The third part

304: first semiconductor layer

308: second semiconductor layer

310: First Contact Structure

3101: First Contact

3101a: First end

3101b: Second end

3101c: Middle Section

312: Second Contact Structure

316: first conductive structure

316a: first conductive part

316b: first electrode part

3161: Part 1

3162: Part II

318: Second Conductive Structure

318a: second conductive part

318b: second electrode part

A1: First contour

B1: Second contour

A2: The third contour

B2: Fourth contour

C: corner

W1: first width

W2: Second width

F: flat area

F1: First engaging surface

F2: Second bonding surface

D: Spacing

d: distance

D1: width of the first part

D2: The width of the second part

D3: The width of the third part

L1: first length

L2: second length

FIG. 1 is a schematic top view of a first embodiment of the semiconductor device of the application.

FIGS. 2A to 2F are the manufacturing flow charts of the semiconductor device disclosed in the first embodiment of the present application.

Fig. 3 is a side sectional view taken along the AA' section line of Fig. 1 .

FIG. 4 is a side cross-sectional view of a second embodiment of the semiconductor device of the application.

FIG. 5 is a schematic top view of a second embodiment of the semiconductor device of the application.

FIG. 6 is a schematic top view of a third embodiment of the semiconductor device of the application.

Please refer to FIG. 1 to FIG. 3, which show the first embodiment of the semiconductor device 100 of the present application. The substrate 102 is not shown in FIGS. 2A to 2F. The semiconductor device 100 includes a substrate 102 and a semiconductor stack 103 formed on the substrate 102 . The semiconductor stack 103 has a first semiconductor layer 104 on the substrate 102 , an active structure 106 on the first semiconductor layer 104 , and a second semiconductor layer 108 on the active structure 106 . The first semiconductor layer 104 and the second semiconductor layer 108 have a different first conductivity and a second conductivity, respectively, to provide electrons and holes, or provide holes and electrons, respectively. The active structure 106 may comprise a single heterostructure, a double heterostructure, a multi-quantum well, or other structures. The semiconductor stack 103 has a first region 103a and a second region 103b. Different from the first region 103a, the second region 103b protrudes upward from the first region 103b. A region 103a is connected with the first region 103a and the second region 103b by a sidewall region 103c. Specifically, in this embodiment, the first region 103a includes the first semiconductor layer 104, and the second region 103b includes the first semiconductor layer 104, the active structure 106 and the second semiconductor layer 108, so that the height of the second region 103b is higher than that of the second region 103b. A region 103a is high, as shown in FIG. 3 . In addition, as shown in FIGS. 1 and 2A, the first region 103a of the semiconductor device 100 of the present embodiment surrounds the second region 103b, and the semiconductor stack 103 is partially removed to expose the substrate when viewed from above. 102 , making the exposed surface of the substrate 102 surround the first region 103b. Specifically, the first region 103a may be formed by removing a portion of the second semiconductor layer 108 and the active structure 106 and exposing a portion of the first semiconductor layer 104 . In the top view of the semiconductor device of the present application, the range of the first region is represented by gray scales, thereby clearly defining the distribution positions of the first region and the second region.

The substrate 102 can be used to support the semiconductor stack 103 and other layers or structures thereon, and the substrate 102 can include opaque materials, transparent materials, conductive materials, semiconductor materials, or insulating materials. The semiconductor stack 103 can be grown on the substrate 102 or another growth substrate by epitaxial methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). . If the semiconductor stack 103 is grown on a growth substrate, the semiconductor stack 103 can be bonded to the substrate 102 by a substrate transfer technique, and the growth substrate can be selectively removed. In the first embodiment, the semiconductor stack 103 is grown on the growth substrate, and then bonded to the substrate 102 through an adhesive layer (not shown) through a substrate transfer technique. In the present embodiment, the substrate 102 is, for example, a sapphire substrate, which is transparent to the light emitted by the active structure 106 and used as a light emitting structure. In addition, from the top view, the shape of the substrate 102 can be a rectangle, a square, a diamond, a circle, an ellipse or an irregular shape. The substrate 102 in this embodiment is a rectangle and has two long sides 102a and two short sides 102b. And the intersection of each long side 102a and each short side 102b is the corner C of the substrate 102 .

The materials of the first semiconductor layer 104, the second semiconductor layer 108, and the active structure 106 include Group III and V compound semiconductors, such as: GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present disclosure, unless otherwise specified, the above chemical expressions include “compounds that meet stoichiometric doses” and “compounds that do not meet stoichiometric doses”, wherein, “compounds that meet stoichiometric doses” are, for example, Group III elements The total element dosage of , is the same as the total element dosage of the fifth group element. On the contrary, the "non-stoichiometric compound" is, for example, the total element dosage of the third group element is different from the total element dosage of the fifth group element. For example, the chemical expression is AlGaAs, which means that the group 3 elements include aluminum (Al) and/or gallium (Ga), and the group 5 element arsenic (As), wherein the total of the group 3 elements (aluminum and/or gallium) The elemental dose may be the same or different from the total elemental dose of the Group V element (arsenic). In addition, if each compound represented by the above chemical formula is a compound that meets the chemical dose, AlGaAs represents Al _x1 Ga _(1-x1) As, where 0≦x1≦1; AlInP represents Al _x2 In _{(1-x2 )} P, where 0≦x2≦1; AlGaInP represents (Al _y1 Ga _(1-y1) ) _1-x3 In _x3 P, where 0≦x3≦1, 0≦y1≦1; AlGaN represents Al _x4 Ga _{( 1-x4)} N, where 0≦x4≦1; AlAsSb represents AlAs _x5 Sb _(1-x5) , where 0≦x5≦1; InGaP represents In _x Ga _1-x P, where 0≦x6≦1 ; InGaAsP represents In _x Ga _1-x6 As _1-y2 P _y2 , where 0≦x6≦1,0≦y2≦1; InGaAsN represents In _x Ga _1-x8 As _1-y3 N _y3 , where 0≦x8 ≦1, 0≦y3≦1; AlGaAsP represents Al _x9 Ga _1-x9 As _1-y4 P _y4 , where 0≦x9≦1, 0≦y4≦1; InGaAs represents In _x10 Ga _1-x10 As, where, 0≦x10≦1. According to the material of the active structure 106, when the material of the semiconductor stack 100 is AlGaInP series, the active structure 106 can emit infrared light with a peak wavelength (peak wavelength) between 700 and 1700 nm, red light between 610 nm and 700 nm, Or yellow light with a peak wavelength between 530nm and 570nm. When the material of the semiconductor stack 100 is InGaN series, the active structure 106 can emit blue light with peak wavelengths between 400 nm and 490 nm, deep blue light, or green light with peak wavelengths between 490 nm and 550 nm. When the material of the semiconductor stack 100 is AlGaN series, the active structure 106 can emit ultraviolet light with a peak wavelength between 250 nm and 400 nm.

In this embodiment, the material of the semiconductor stack 103 is made of aluminum gallium indium phosphide series. The semiconductor stack 103 is firstly formed on a gallium arsenide growth substrate (not shown) by epitaxial growth. The substrate 102 is connected to the first semiconductor layer 104 through a transparent adhesive layer (not shown), and finally the GaAs growth substrate is removed. The first semiconductor layer 104 may be a p-type semiconductor layer, and the second semiconductor layer 108 may be an n-type semiconductor layer. In another embodiment, the substrate 102 is an epitaxial growth substrate, the first semiconductor layer 104 is an n-type nitride semiconductor layer, and the second semiconductor layer 108 is a p-type nitride semiconductor layer. The material of the substrate 102 can be selected The material can be selected from sapphire (sapphire), glass (glass), silicon (Si), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide (GaAs), phosphide arsenide (GaAs) Gallium (AsGaP), Zinc Selenide (ZnSe), Zinc Sulfide (ZnS) or Silicon Carbide (SiC) etc.

In this embodiment, the semiconductor device 100 further includes a first contact structure 110 located on the first region 103 a of the semiconductor stack 103 and electrically connected to the first semiconductor layer 104 . Referring to FIG. 1, the first contact structure 110 includes two first contact portions 1101 symmetrically located on the left and right sides of the second region 103b to improve the uniform distribution of current, and the first contact portions 1101 are disposed adjacent to the substrate Long side 102a of 102 . Each of the first contact portions 1101 in this embodiment includes a first end portion 1101a, a second end portion 1101b and an intermediate portion 1101c located between the first end portion 1101a and the second end portion 1101b. The first end portion 1101a and the second end portion 1101b are closer to the corner C of the substrate 102 than the middle portion 1101c. In this embodiment, the first contact portion 1101 has a non-uniform width. Specifically, the first end portion 1101a of the first contact portion 1101 has a first width W1, and the middle portion 1101c has a second width W2 different from The first width W1, for example, the second end portion 1101b and the middle portion 110c both have the second width W2 smaller than the first width W1. The external current is injected into the first contact structure 110 through the first end portion 1101a, and the first end portion 1101a with a larger width can withstand higher current density without burning out, thereby improving the durability of the semiconductor device 100 . In another embodiment, the widths of the first end portion 1101a and the second end portion 1101b are greater than the width of the middle portion 110c.

Referring to FIGS. 1 and 2C , the semiconductor device 100 of this embodiment further includes a second contact structure 112 located in the second region 103 b and formed on the second semiconductor layer 108 . The second contact structure 112 is electrically connected to the second semiconductor layer 108 and separated from the first contact structure 110 . From the top view, the second contact structure 112 and the second region 103b in this embodiment have similar contours, and the second contact structure 112 is conformally formed on the second region 103b, and has a top view area smaller than the second region 103b. A top-view area of the second region 103b. The second contact structure 112 in this embodiment is located between the two first contact portions 1101 , and the first contact structure 110 is closer to the long side 102 a or the short side 102 b of the substrate 102 than the second contact structure 112 is. In this embodiment, the second contact structure 112 is continuously formed on the second semiconductor layer 108. However, in another embodiment, as shown in FIG. 2C', the second contact structure 112 includes a plurality of second contact structures separated from each other. The contact portion 112a can further improve the current dispersion effect. The materials of the first contact structure 110 and the second contact structure 112 are conductive, and the materials of the first contact structure 110 and the second contact structure 112 can be selected according to the material of the semiconductor stack 103, so that the first contact structure 110 and the second contact structure 112 can be The two contact structures 112 respectively form good electrical contacts, such as ohmic contacts, with the first semiconductor layer 104 and the second semiconductor layer 108 . For example, the first contact structure 110 can be selected from beryllium gold alloy (BeAu), and the second contact structure 112 can be selected from germanium gold alloy (GeAu). In this embodiment, the top-view area of the first contact structure 110 is smaller than the top-view area of the second contact structure 112 , and the top-view area of the first contact structure 110 accounts for 5%~5% of the top-view area of the second contact structure 112 30%, preferably 8% to 18%, the above-mentioned area ratio of the first contact structure 110 and the second contact structure 112 helps the semiconductor device 100 to achieve better current dispersion effect.

Referring to FIG. 2D and FIG. 3 , the semiconductor device 100 of this embodiment further includes a first protection structure 114 covering the first region 103 a , the second region 103 b and the sidewall region 103 c of the semiconductor stack 103 . The first protection structure 114 can protect the semiconductor stack 103 to increase the mechanical strength of the semiconductor device 100 , and at the same time prevent unintended electrical connection between the subsequent electrodes and the semiconductor stack 103 . The first protection structure 114 of this embodiment covers the semiconductor stack 103 and extends to the surface of the substrate 102 , and forms a first opening 114a on the first region 103a and a second opening 114b on the second region 103b. The first opening 114 a exposes the first end portion 1101 a of the first contact structure 110 and the second opening 114 b exposes the second contact structure 112 . The first protection structure 114 is a dielectric material, and can optionally include magnesium oxide (MgO), SU8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin ( Acrylic Resin), Cyclic Olefin Polymer (COC), Polymethyl Methacrylate (PA), Polyethylene Terephthalate (PET), Polyimide (PI), Polycarbonate (PC), Polyester Polyetherimide, Fluorocarbon Polymer, Glass, Tantalum Oxide (Ta ₂ O ₅ ), Alumina (Al ₂ O ₃ ), Silicon Dioxide (SiO ₂ ), Titanium Oxide (TiO ₂ ), silicon nitride (SiN _x ), spin-on-glass (SOG) or tetraethoxy silicon (TEOS). In another embodiment, the first protection structure 114 includes a plurality of first dielectric layers and a plurality of second dielectric layers (not shown), and the first dielectric layers and the second dielectric layers overlap each other , and the first dielectric layer and the second dielectric layer have different refractive indices to form a distributed Bragg reflector structure, thereby increasing the mechanical strength of the first protective structure 114 to enhance the protection against semiconductors For the protection of the stack 103 , when the semiconductor device 100 emits light from the direction of the substrate 102 , the first protection structure 114 of the distributed Bragg mirror structure also helps to reflect the light to the light-emitting surface to increase the efficiency of the semiconductor device 100 . For example, the first dielectric layer can be selected to be silicon dioxide, the second dielectric layer can be selected to be titanium dioxide, and the first protection structure 114 includes 10 to 50 overlapping layers of the first dielectric layer and the second dielectric layer. layer, and the thickness of the first protection structure 114 is 3um˜20um.

In this embodiment, the semiconductor device 100 further includes a first conductive structure 116 . Referring to FIGS. 1, 2E and 3, the first conductive structure 116 is located on the semiconductor stack 103, and is formed by the first region 103a extends to the second region 103b and covers the sidewall region 103c of the semiconductor stack 103 . Furthermore, the first conductive structure 116 is formed on the first protection structure 114 and is connected to the first contact structure 110 through the first opening 114 a of the first protection structure 114 . The first conductive structure 116 is electrically connected to the first semiconductor layer 104 through the first end portion 1101 a of the first contact structure 110 . Specifically, the first conductive structure 116 includes a first portion 1161 and a second portion 1162 connected to the first portion 1161 . The first portion 1161 is located on the first region 103a of the semiconductor stack 103 and is connected to the first contact structure 110 through the first opening 114a. The second portion 1162 is located on the second region 103b of the semiconductor stack 103 . In this embodiment, the first conductive structure 116 directly contacts the first end portion 1101 a of the first contact structure 110 , and the top-view area of the first portion 1161 is smaller than the top-view area of the second portion 1162 . In this embodiment, the first conductive structure 116 includes a first conductive portion 116a and a first electrode portion 116b located on the first conductive portion 116a, and each of the first conductive portion 116a and the second conductive portion 116b includes several layers A metal stack of metal layers, and the shapes of the first conductive portion 116a and the first electrode portion 116b are respectively defined by two masks; or, in another embodiment, the first conductive structure 116 may include several metal layers A metal stack is formed on the semiconductor stack 103 , and the metal stack is passed through a single mask to define the shape of the first conductive structure 116 . The first electrode portion 116b covers an upper surface 116a1 and a side surface 116a2 of the first conductive portion 116a, and the first electrode portion 116b and the first contact structure 110 are electrically connected to each other through the first conductive portion 116a . More specifically, from a top view, as shown in FIG. 2E, the first conductive portion 116a has a first outline A1, and the first electrode portion 116b has a second outline B1 conformally formed outside the first outline A1 , and the second outline B1 surrounds the first outline A1 , and the top-view area of the first electrode portion 116b is larger than the top-view area of the first conductive portion 116a. By covering the first conductive portion 116a with the first electrode portion 116b, the yield and durability of the semiconductor device 100 can be increased. In detail, due to the height difference of the surface of the semiconductor device 100 , the coverage integrity of the first protection structure 114 in the sidewall region 103c of the semiconductor stack 103 is generally poor, and some gaps often exist in the first protection structure of the sidewall region 103c 114, lead As a result, when the semiconductor element and the carrier board (not shown) are joined, the adhesive or solder penetrates into the gap of the first protection structure 114 to cause electrical failure. The first conductive portion 116a and the first electrode portion 116b covering the first conductive portion 116a in this embodiment can provide double protection to maintain the normal electrical properties of the semiconductor device 100 . More specifically, since the first conductive portion 116a and the first electrode portion 116b are sequentially located on the sidewall region 103c covered with the first protection structure 114, when the subsequent flip chip operation is performed on the semiconductor device 100, the first electrode portion is affected by the first electrode portion. The barrier 116b reduces the probability that the solder damages the first conductive portion 116a and further penetrates into the gap of the first protection structure 114, thereby reducing the risk of device failure during flip chip operation, and improving the durability of the semiconductor device 100 ( reliability) and process yield.

In this embodiment, the semiconductor device 100 further includes a second conductive structure 118 . Referring to FIG. 2E and FIG. 3 , the second conductive structure 118 is located on the second region 103 b and is electrically connected to the second semiconductor layer 108 of the semiconductor stack 103 . Similarly, the second conductive structure 118 can be formed through a single photomask or two photomasks, and the related description can refer to the description of the first conductive structure 116 . In this embodiment, the second conductive structure 118 includes a second conductive portion 118a and a second electrode portion 118b located on the second conductive portion 118a. The second electrode portion 118b covers an upper surface 118a1 and a side surface 118a2 of the second conductive portion 118a, and the second electrode portion 118b is electrically connected to the second conductive portion 118a. The second conductive portion 118a is electrically connected to the second contact structure 112 through the second opening 114b of the first protection structure 114 . More specifically, from a top view, as shown in FIG. 2E, the second conductive portion 118a has a third outline A2, and the second electrode portion 118b has a fourth outline B2 that is conformally located outside the third outline A2, That is, the fourth contour B2 surrounds the third contour A2, so that the top-view area of the second electrode portion 118b is larger than the top-view area of the second conductive portion 118a. Through the second conductive portion 118a and the second electrode portion 118b, the yield and durability of the semiconductor device 100 can be increased. In this embodiment, the first conductive structure 116 and the second conductive structure 118 respectively have a first bonding surface F1 and a second bonding surface F2 away from the semiconductor stack 103 , and the semiconductor element 100 is connected through the first bonding surface F1 and the second bonding surface F2. two The bonding surface F2 is attached to the carrier board. During flip-chip bonding, the first bonding surface F1 and the second bonding surface F2 are in contact with the bonding agent or solder, so that the semiconductor element 100 is electrically connected to the carrier by the bonding agent or the solder, and the light is transmitted from the direction of the substrate 102 Fire out.

The above-mentioned first conductive structure 116 and second conductive structure 118 are separated from each other, so that the first conductive structure 116 and the second conductive structure 118 are electrically connected to the first semiconductor layer 104 and the second semiconductor layer 108 respectively, and the first conductive structure The structure 116 and the second conductive structure 118 have different top view areas. In this embodiment, the top view area of the first conductive structure 116 is larger than that of the second conductive structure 118 . In the present embodiment, the first conductive structure 116 and the second conductive structure 118 have different top-view shapes. For example, the top-view shape of the first conductive structure 116 is irregular, and includes two first portions 1161 . The two portions 1162 extend toward the corner C, and the top-view shape of the second conductive structure 118 is approximately square.

Referring to FIGS. 1 and 2F, the first conductive portion 116a and the second conductive portion 118a in this embodiment are separated, and both can be formed simultaneously by a process, and then the first conductive portion is separated by partial removal portion 116a and the second conductive portion 118a. The first conductive portion 116a and the second conductive portion 118a have different top-view areas. In this embodiment, the top-view area of the first conductive portion 116a is larger than the top-view area of the second conductive portion 118a. In addition, similarly, the first electrode portion 116b and the second electrode portion 118b are also separated from each other, and the two can be simultaneously formed by a process, and then the first electrode portion 116b and the second electrode portion 116b are separated by partial removal. Electrode portion 118b. The first electrode portion 116b and the second electrode portion 118b have different top-view areas. In this embodiment, the top-view area of the first electrode portion 116b is larger than the top-view area of the second electrode portion 118b. The first conductive portion 116a, the second conductive portion 118a, the first electrode portion 116b, and the second electrode portion 118b may have a single-layer or multi-layer structure. In one embodiment, the materials of the first electrode portion 116b and the second electrode portion 118b are different from those of the first conductive portion 116a and the second conductive portion 118a, for example, the first conductive portion 116a and the first electrode portion 116b have at least one difference s material. The first conductive portion 116a and the second conductive portion 118a have substantially the same material, such as metal or composite material. Gold, such as titanium, gold, platinum, nickel and other metals or alloys of the above metals, and the first conductive portion 116a and the second conductive portion 118a may be a stacked structure composed of a plurality of metal layers or alloy layers. The first electrode portion 116b and the second electrode portion 118b have substantially the same material, such as metals or alloys, such as: gold, nickel, titanium, platinum, aluminum, tin and other metals or alloys of the above metals, and the first electrode portion 116b And the second electrode portion 118b may be a laminated structure composed of a plurality of metal layers or alloy layers.

As shown in FIG. 3 , a distance D between the first conductive structures 116 and the second conductive structures 118 separated from each other is 10 μm to 90 μm, so as to form a small-sized semiconductor device 100 . There is a surface between the first conductive structure 116 and the second conductive structure 118 , and the surface is a flat area F. The current semiconductor devices on the market are usually attached to a temporary film (eg, blue film), and a thimble is used to apply force on the temporary film after subsequent processing, and the force point roughly corresponds to the two electrodes of the semiconductor element ( For example, between the first conductive structure 116 and the second conductive structure 118), the semiconductor element is removed in this way. In the semiconductor device 100 of the present invention, since there is a flat area between the first conductive structure 116 and the second conductive structure 118 , when the semiconductor device 100 is removed by the ejector pin, uneven force on the ejector pin due to surface fluctuations can be avoided, The risk of cracking of the semiconductor element 100 is reduced. In addition, since the first protection structure 114 has a plurality of first dielectric layers and a plurality of second dielectric layers overlapping each other, it is also helpful to improve the anti-thimble strength of the semiconductor stack 103 .

In this embodiment, the first bonding surface F1 of the first electrode portion 116a and the second bonding surface F2 of the second electrode portion 118a are coplanar, so when the semiconductor device 100 is fixed on a carrier in a flip-chip manner, the coplanarity is favorable. In order to improve the bonding yield between the semiconductor device 100 and the carrier.

In one embodiment, the total top-view area of the first conductive structure 116 and the second conductive structure 118 may account for more than 25% of the top-view area of the semiconductor stack 103, more preferably 32%-60%. The area of the first conductive structure 116 and the second conductive structure 118 effectively improves the yield of flip chip bonding and the heat dissipation efficiency.

Referring to FIG. 2F and FIG. 3 , the semiconductor device 100 may optionally include a second protective layer 124 covering the sidewall region 103 c of the semiconductor stack 103 , the surface of the first region 103 a and the surface of the second region 103 b . Specifically, the second protective layer 124 covers the semiconductor stack 103 , the first protective structure 114 , the first conductive structure 116 and the second conductive structure 118 . The second protective layer 124 has a third opening 124a to expose the first conductive structure 116, and a fourth opening 124b to expose the second conductive structure 118, so that the semiconductor device 100 can pass through the exposed first conductive structure 116 and the second conductive structure 118. The two conductive structures 118 are electrically connected to a carrier board (eg, a printed circuit board) having a circuit structure by soldering.

In addition, the second protective layer 124 in this embodiment covers the edges of the first conductive structure 116 and the second conductive structure 118 and extends inward by a distance d, for example, the distance d is 3-10 μm to improve reliability. In this embodiment, the material and structure of the second protective layer 124 are different from those of the first protective structure 114. For example, the structure of the first protective structure 114 is a distributed Bragg reflection structure, and the second protective structure 124 can be a single layer or a Double layer. In addition, the material of the second protection structure 124 may include a dielectric material, such as silicon oxide, silicon nitride, or a combination of the two. In one embodiment, the first protection structure 114 and the second protection structure 124 are both distributed Bragg reflector structures.

In one embodiment, the second protection structure 124 may be disposed between the first conductive portion 116a and the first electrode portion 116b, and between the second conductive portion 118a and the second electrode portion 118b, so that the first conductive portion 116a is located between the first conductive portion 116a and the second electrode portion 118b. between the second protective layer 124 and the first protective layer 114 . Compared with the second protective structure 124 formed on the first conductive structure 116 and the second conductive structure 118, when the second protective structure 124 is formed between the first conductive portion 116a and the first electrode portion 116b, and the second conductive portion When between the 118a and the second electrode portion 118b, the first bonding surface F1 and the second bonding surface F2 are completely exposed, so as to increase the bonding area when bonding with the carrier, so as to increase the bonding yield. In addition, the first protection structure 114 and the second protection structure 124 may have different top-view areas. For example, in one embodiment, the first protection structure 114 extends to the upper surface of the substrate 102 and is different from the substrate. 102 contacts, and the edge of the second protection structure 124 stays on the semiconductor stack 103 and does not extend to the substrate 102 .

FIG. 4 is a schematic cross-sectional view of a second embodiment of the semiconductor device 200 of the present application. The components of the semiconductor element 200 and their connection relationships are substantially the same as those of the semiconductor element 100 of the first embodiment. Specifically, the semiconductor device 200 of this embodiment includes: a substrate 202 and a semiconductor stack 203 are formed on the substrate 202 , and the semiconductor stack 203 has a first region 203 a and a second region 203 b which are different from the first region 203 a , and the semiconductor device 200 includes a first contact structure 210 located on the first region 203a, a second contact structure 212 located on the second region 203b, a first protection structure 214 covering the semiconductor stack 203, a first conductive structure 216 Located on the semiconductor stack 203 and extending from the first region 203a to the second region 203b and a second conductive structure 218 is located in the second region 203b.

The main difference between this embodiment and the previous embodiments is that the semiconductor device 200 of this embodiment omits the first conductive portion and the second conductive portion, in other words, the first conductive structure 216 only includes the first electrode equivalent to the first embodiment The structure of the portion 116b, the second conductive structure 218 only includes the structure equivalent to the second electrode portion 118b in the first embodiment. The thickness of the first conductive structure 216 and the second conductive structure 218 is 1~5um (for example: 1.5um, 2um, 3um), so as to prevent the solder from drilling into the possible gaps of the first protection structure 214, and to avoid the occurrence of short circuit in the during flip chip bonding. In addition, in this embodiment, the second protection structure is omitted. When the first protection structure 214 is a Bragg reflector (DBR), the single first protection structure 214 can have high coating uniformity and high structural strength. In order to save the process of forming the second protection structure.

FIG. 5 shows a top view of the semiconductor device 200 of the second embodiment. 4 and 5, the second region 203b of the semiconductor stack 203 is surrounded by the first region 203a, and viewed from above, the second region 203b is surrounded by the first region 203a. The region 203b has a concave portion 203b1 and two convex portions 203b2 located on both sides of the concave portion 203b1 , so that the concave portion 203b1 is away from the long side 202a and the short side 202b of the substrate 202 . The first contact structure 210 is located on the first region 203a, and the second contact structure 212 is located on the second region 203b and has a main body portion 2121 and two extension portions 2122 connected to the main body portion 2121. Each extension portion 2122 extends in a direction away from the main body portion 2121 . The second contact structure 212 is closer to the edge of the substrate 202 than the first contact structure 210 . The first protection structure 214 covers the semiconductor stack 203 and has a first opening 214a and a second opening 214b. The first opening 214a exposes the first contact structure 210 and the second opening 214b exposes the second contact structure 212, whereby the first conductive structure 216 and the second conductive structure 218 pass through the first opening 214a and the second opening 214b, respectively, and The first contact structure 210 and the second contact structure 212 are electrically connected. In the top view, the first opening 214a has an area smaller than that of the first contact structure 210 . The first opening 214a and the second opening 214b each have a first extending direction and a second extending direction. In this embodiment, the first extending direction is different from the second extending direction, and the first extending direction is parallel to the direction shown in FIG. 5 . The X axis and the second extending direction are parallel to the Y axis, so that the first extending direction is perpendicular to the second extending direction; in other embodiments, the first extending direction is the same as the second extending direction.

FIG. 6 shows a top view of a third embodiment of the semiconductor device 300 of the present application. The cross-sectional view corresponding to FIG. 6 may be similar to that of FIG. 3 or FIG. 4, and the present embodiment is based on the first embodiment, and the differences between the present embodiment and the first embodiment will be described.

The elements of the semiconductor device 300 and their connection relationships in this embodiment are similar to those in the first embodiment, but the difference is that the second region 303 b and the first contact structure 310 in this embodiment have special configurations. As shown in FIG. 6 , the second region 303b has a stepped outline when viewed from above, and the width of the second region 303b can be stepped from one end to the other end. For example, the second region 303b in this embodiment has The width of the three segments varies. Specifically, from the top view, the second region 303b has a first portion 303b1 having a first portion width D1, a second portion 303b2 having a second portion width D2 and a third portion The bit 303b3 has a third part width D3, and the second part 303b2 is located between the first part 303b1 and the third part 303b3. The width of the second region 303b decreases or increases in the direction from the first portion 303b1 to the third portion 303b2, and the manner of decreasing or increasing the width may be continuous or segmented. In this embodiment, the width D1 of the first part is smaller than the width D2 of the second part, and the width D3 of the third part is larger than the width D2 of the second part.

A first contact structure 310 is formed on the first region 303a, and the first contact structure 310 includes two first contact portions 3101 symmetrically located on the left and right sides of the second region 303b, and each first contact portion 3101 includes a first end portion 3101a, a second end portion 3101b and a middle portion 3101c are located between the first end portion 3101a and the second end portion 3101b, the width of the first end portion 3101a is larger than that of the second end portion 3101b and the middle portion 3101c, and the first end portion 3101a is wider than the second end portion 3101b and the middle portion 3101c. The portion 3101a is disposed beside the first portion 303b1 of the second region 303b, and the middle portion 3101c and the second end portion 3101b are disposed beside the second portion 303b2. In this embodiment, the first contact structure 310 does not extend to the left and right sides of the third portion 303b3, thereby retaining a larger area of the second semiconductor layer 308 to maintain the uniformity of current distribution and increase the active structure area. In addition, in the direction of the long side 302a of the substrate 302 (ie, along the Y-axis direction), the second region 303b has a first length L1, and the first contact portion 3101 of the first contact structure 310 has a second length L2 less than The first length L1, and the second length L2 is 30%-60% of the first length L1, or the second length L2 is 35%-50% of the first length L1. When the semiconductor element 300 is a light-emitting element and has a miniaturized size (for example, the long side is less than 10 mil), the semiconductor element 300 of this embodiment can have a larger size through the configuration design of the second region 303 b and the first contact structure 310 described above. light-emitting area while maintaining good current dispersion uniformity.

Similar to the first embodiment, the first conductive structure 316 of this embodiment includes a first conductive portion 316a having a first outline A1 and a first electrode portion 316b having a second outline A2, and the second outline B2 conforms to the shape It is formed outside the first outline A1, and the second outline B1 surrounds the first outline A1. However, in another In the embodiment, the first conductive structure 316 can also be patterned by a single mask and formed on the semiconductor stack 303 as shown in the second embodiment, or only include the first electrode portion 316b.

The present application further includes a light-emitting module having the above-mentioned semiconductor element. The light-emitting module includes a plurality of semiconductor elements and a carrier board, the plurality of semiconductor elements can be arranged on the carrier board in a matrix manner, and the carrier board includes a circuit layer and is electrically connected to the plurality of semiconductor elements. Specifically, the light-emitting module includes a plurality of packages disposed on the carrier board, and any package includes semiconductor elements with different light-emitting wavelengths, such as a red light semiconductor element, a green light semiconductor element and a blue light semiconductor element, and an encapsulant (eg, silicone) to cover the semiconductor elements. The dominant wavelengths or peak wavelengths of the above-mentioned various colored semiconductor elements are, for example, between 600 nm to 660 nm, 515 nm to 575 nm, and 430 nm to 490 nm, respectively, to form a package body that emits white light, and the light-emitting module is, for example, As the backlight module of the display.

In another embodiment, the light emitting module can be directly used as a display panel of a display. The light emitting module has a plurality of pixels, and any pixel includes a plurality of semiconductor elements, for example, the pixel includes a red light semiconductor element, a green light semiconductor element and a blue light semiconductor element.

However, the above descriptions are only the preferred embodiments of the present application, and are not intended to limit the scope of the application. Changes and modifications should be included within the scope of the patent application of this application.

100: Semiconductor Components

102: Substrate

103: Semiconductor Stacks

103a: First Region

103b: Second area

103c: Sidewall area

104: first semiconductor layer

106: Active structure

108: Second semiconductor layer

110: First Contact Structure

112: Second Contact Structure

114: First Protection Structure

114a: first opening

114b: second opening

116: The first conductive structure

1161: Part 1

1162: Part II

116a: first electrode part

116a1: Upper surface

116a2: side surface

116b: first conductive part

118: Second conductive structure

118a: second conductive part

118a1: Upper surface

118a2: side surface

118b: second electrode part

124: Second protective layer

124a: third opening

124b: Fourth opening

D: Spacing

F1: First engaging surface

F2: Second bonding surface

Claims (10)

A semiconductor device, comprising: a semiconductor stack including a first region and a second region, the second region protruding from the first region and having a first length, and the first region surrounding the second region; A first contact structure is disposed on the first region and has a second length, the first contact structure has a corresponding first end and a second end, wherein the second length is smaller than the first length; and a first conductive structure covering the first region and the second region, and the first conductive structure is in contact with the first end portion. A semiconductor device as claimed in claim 1, further comprising a second contact structure located on the second region and separated from the first contact structure. A semiconductor device as claimed in claim 2, wherein a top-view area of the second contact structure is larger than a top-view area of the first contact structure. A semiconductor device as claimed in claim 2, further comprising a substrate having a long side and a short side, the semiconductor stack is located on the substrate, wherein, viewed from above, the first contact structure and the long side Having a first shortest distance, the second contact structure and the long side have a second shortest distance greater than the first shortest distance. A semiconductor device as claimed in claim 4, wherein the first end portion is closer to the short side than the second end portion and has a first width, and the second end portion has a second width smaller than the first width. A semiconductor element according to claim 1, wherein the second length is 30%-60% of the first length. A semiconductor device as claimed in claim 5, wherein the second region comprises a first part having a first part width, a second part having a second part width and a third part having a third part width , and the second part is located between the first part and the third part, the width of the first part is smaller than the width of the second part, and the width of the third part is larger than the width of the second part. A semiconductor device as claimed in claim 1, further comprising a second conductive structure covering the second region and being separated from the first conductive structure, wherein the top view area of the first conductive structure and the second conductive structure The sum accounts for 25% to 60% of the top-view area of the semiconductor stack. A semiconductor device as claimed in claim 8, wherein a distance between the first conductive structure and the second conductive structure is 10 μm to 90 μm. The semiconductor device according to claim 1, further comprising a protective layer covering the first region and the second region, and the protective layer is a distributed Bragg mirror structure.

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