TW201929103A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TW201929103A
TW201929103A TW107144142A TW107144142A TW201929103A TW 201929103 A TW201929103 A TW 201929103A TW 107144142 A TW107144142 A TW 107144142A TW 107144142 A TW107144142 A TW 107144142A TW 201929103 A TW201929103 A TW 201929103A
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Taiwan
Prior art keywords
packaging
singulated
integrated circuit
sealing body
substrate
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TW107144142A
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English (en)
Inventor
鍾馨德
莊詠程
林國鼎
林南君
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力成科技股份有限公司
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Publication of TW201929103A publication Critical patent/TW201929103A/zh

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Abstract

一種封裝結構的製造方法，其至少包括以下步驟。提供封裝面板。封裝面板包括第一密封體、多個第一積體電路元件以及多個電性連接於第一積體電路元件的重佈線路圖案。藉由第一密封體密封第一積體電路元件，且重佈線路圖案分佈於第一密封體及第一積體電路元件之上。切割封裝面板的第一密封體以形成多個單體化封裝條。將單體化封裝條中的任一者貼附於基板的貼附區上。基板包括設置於貼附區之外的至少一個定位孔。對貼附於基板上的單體化封裝條進行封裝製程，且藉由定位孔固定基板，以形成封裝結構。

Description

封裝結構及其製造方法
本發明是有關於一種製造方法，且特別是有關於一種封裝結構的製造方法。
一般而言，晶圓級或面板級封裝應理解為包含在執行單體化製程以切割成多個半導體晶粒之前，於晶圓上進行整個封裝、互連結構與其他製程步驟，例如打線接合、晶片接合或是模封製程。然而，執行此類晶圓級或面板級製程需要大型的設備。再者，此類大型設備需要非常大的資金投入，而這種資金投入並不符合成本效益。因此，如何利用現有的設備完成加工步驟以最大限度地降低設備成本和整體製造成本已成為該領域研究人員面臨的挑戰。
本發明提供一種封裝結構的製造方法，其可以提高產量且提供製程穩定性。
本發明提供一種封裝結構的製造方法，其至少包括以下步驟。提供封裝面板，其中封裝面板包括第一密封體、多個第一積體電路元件及電性連接於第一積體電路元件的多個重佈線路圖案，藉由第一密封體密封第一積體電路元件，且重佈線路圖案分佈於第一密封體及第一積體電路元件上。切割封裝面板的第一密封體以形成多個單體化封裝條，其中單體化封裝條中的每一者包括第一單體化密封體、重佈線路圖案中的任一者及至少一個被第一單體化密封體密封的第一積體電路元件。將單體化封裝條中的任一者貼附於基板上的貼附區，其中基板包括設置於貼附區之外的至少一個定位孔。對貼附於基板上的單體化封裝條進行封裝製程，並藉由至少一個定位孔固定基板，以形成封裝結構。
在本發明的一實施例中，封裝製程包括接合製程、模封製程以及單體化製程。
在本發明的一實施例中，基板的面積大於單體化封裝條中的任一者的面積。
在本發明的一實施例中，封裝結構的製造方法還包括在進行封裝製程後，將單體化封裝條從基板剝離。
本發明提供一種封裝結構的製造方法，其至少包括以下步驟。於第一製程腔體內提供封裝面板，其中封裝面板包括第一密封體、多個第一積體電路元件以及電性連接於第一積體電路元件的多個重佈線路圖案，藉由第一密封體密封第一積體電路元件，且重佈線路圖案分佈於第一密封體及第一積體電路元件上。於第一製程腔體內切割封裝面板的第一密封體，以形成多個單體化封裝條，其中單體化封裝條中的每一者包括第一單體化密封體、重佈線路圖案中的任一者及至少一個被第一單體化密封體密封的第一積體電路元件。將單體化封裝條轉移至第二製程腔體內，其中至少一個固持裝置設置於第二製程腔體內。於第二製程腔體內，將單體化封裝條中的任一者貼附於基板上的貼附區，其中基板包括設置於貼附區之外的至少一個定位孔。於第二製程腔體內，藉由至少一固持裝置固定基板，其中至少一個固持裝置對應於基板上的至少一個定位孔。對貼附於基板上的單體化封裝條進行封裝製程，以於第二製程腔體內形成封裝結構。
在本發明的一實施例中，用來提供封裝面板的第一製程腔體的設備規模大於用來進行封裝製程的第二製程腔體的設備規模。
在本發明的一實施例中，封裝製程包括接合製程、模封製程以及單體化製程。
在本發明的一實施例中，基板的面積大於單體化封裝條中的任一者的面積。
在本發明的一實施例中，封裝結構的製造方法還包括於進行封裝製程之後，從單體化封裝條移除黏著層。
基於上述，於進行封裝製程之前，切割封裝面板以形成單體化封裝條，藉此避免使用大規模的設備來進行此類封裝製程。因此，現有的設備可以隨製造流程的改變而被充分利用並兼容於製造流程中，並且維持穩定的製造過程，其可根據封裝的實際應用而可獲得最佳化的成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下將參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。請參照圖1，圖1僅示出製造過程的中間階段的封裝結構的一部分。多個重佈線路圖案（redistribution circuit pattern）120形成於載體110a上。載體110a例如是玻璃基板或是其他適合的基板材料，只要該基板材料能夠承受形成於其上的封裝結構的後續製程，則本發明不限於此。重佈線路圖案120包括第一表面120a以及相對於第一表面120a的第二表面120b。第二表面120b朝向載體110a且貼附至載體110a。多個導電端子150藉由放置製程（placement process）及/或回流製程（reflow process）形成於重佈線路圖案120的第一表面120a上，以電性連接於重佈線路圖案120。舉例來說，導電端子150可以是導電凸塊、導電柱或是其他可能的形式及形狀，但本發明不限於此。
在本實施例中，多個第一積體電路元件（integrated circuit components）130形成於重佈線路圖案120的第一表面120a上，且導電端子150圍繞於第一積體電路元件130的周圍。進一步來說，第一積體電路元件130具有背面130a以及相對於背面130a的主動面130b。第一積體電路元件130的主動面130b藉由凸塊130c電性連接於重佈線路圖案120。舉例來說，第一積體電路元件130可以是特殊應用積體電路（Application-Specific Integrated Circuit，ASIC）或是其他適合的主動元件，但本發明不限於此。在一些實施例中，第一積體電路元件130的晶片接合製程（chip bonding process）在形成導電端子150之前執行。在一些替代性的實施例中，第一積體電路元件130的晶片接合製程也可以在形成導電端子150後進行。此外，第一密封體140形成於重佈線路圖案120的第一表面120a上，以密封第一積體電路元件130以及導電端子150。舉例而言，第一密封體140可以是藉由模封製程形成的模塑化合物（molding compound）。在一些實施例中，第一密封體140可以是由絕緣材料，例如環氧樹脂或是其他適合的絕緣的樹脂來形成，但本發明不限於此。
再者，可以藉由化學機械研磨（Chemical Mechanical Polishing，CMP）或是其他適合的研磨技術來研磨第一密封體140，以暴露出導電端子150且減少封裝結構400的整體厚度（如圖3D所示）。在一實施例中，在研磨製程之後，可同時暴露出第一積體電路元件130的背面130a以及導電端子150的表面。進一步來說，在研磨之後，暴露出的第一積體電路元件130的背面130a可以切齊於暴露出的導電端子150的表面。在另一實施例中，在研磨製程之後，可暴露出導電端子150，而第一積體電路元件130的背面130a仍被第一密封體140所覆蓋。進一步來說，第一積體電路元件130的厚度例如是小於被研磨後的導電端子150的直徑（或厚度）。在一些實施例中，根據製程設計的要求可以省略研磨製程。接著，重佈線路圖案120的第二表面120b可以經由物理處理（例如雷射掀離製程）或是化學處理（例如化學蝕刻）從載體110a上剝離（de-bond）。在一實施例中，離型層（未繪示）可以放置於重佈線路圖案120的第二表面120b以及載體110a之間。換句話說，離型層（未繪示）可以先形成於載體110a上，之後再形成重佈線路圖案120。因此，重佈線路圖案120以及載體110a之間的剝離製程可藉由從重佈線路圖案120或是載體110a剝除離型層來執行。
圖2A是依據本發明一實施例的封裝結構的製造方法的俯視示意圖。圖2B是圖2A的封裝結構的製造方法沿A-A線的剖面示意圖。請參照圖2A及圖2B，在將重佈線路圖案120的第二表面120b從載體110a剝離後，將圖1所示之結構上下翻轉並放置於載體110b上，以形成封裝面板200。因此，封裝面板200具有面朝上的第二表面120b。值得注意的是，第一積體電路元件130可以在載體110b上排列成陣列。
圖3A是依據本發明一實施例的封裝結構的製造方法的俯視示意圖。圖3B是圖3A的封裝結構的製造方法沿A-A線的剖面示意圖。請參照圖3A及圖3B，將被第一密封體140密封的封裝面板200沿著切割線（scribe line）切割成條狀等級（strip level），以形成多個單體化封裝條300。舉例來說，二維陣列的切割製程可以藉由旋轉刀片（rotating blade）或雷射光束（laser beam）來進行一組行切割以及列切割，但本發明不限於此。此外，單體化封裝條300中的每一者包含第一單體化密封體240、重佈線路圖案120中的任一者以及至少一個被第一單體化密封體240密封的第一積體電路元件130。上述製程可以在具有大型設備的第一製程腔體（未繪示）中進行。在切割製程之後，單體化封裝條300可以被轉移至具有相對小型設備的第二製程腔體（未繪示）內，以進行後續的製程。進一步來說，第一製程腔體以及第二製程腔體可以是彼此獨立或是結合在一起，本發明不限於此。
舉例來說，第一製程腔體的設備可以進行晶圓等級或是面板等級的封裝製程，而第二製程腔體的設備可以進行條狀等級或是塊狀等級（block level）的封裝製程，以進行有效的組裝。因此，現有的組裝技術以及現有的設備可以兼容以執行後續的製程，而不是使用大型設備來進行大部份或甚至全部的封裝製程。
單體化封裝條300貼附於基板310的貼附區310a。基板310例如是玻璃或是其他適合的材料。值的注意的是，只要基板310能承載形成於其上的封裝結構，並能承受後續的製程，則基板的形狀、材料以及厚度不造成限制。在一實施例中，至少在基板310的貼附區310a上形成黏著層330，以增強單體化封裝條300與基板310之間的黏著性。可以在轉移單體化封裝條300的製程之前或是之後，在基板310上形成黏著層330。在一實施例中，在貼附單體化封裝條300中的任一者至基板310的貼附區310a上之前，形成黏著層330在基板310上。黏著層330例如是藉由貼附薄膜、塗佈黏膏或黏膠或是其他適合的材料及方式來形成，但本發明不限於此。
在本實施例中，基板310的面積大於單體化封裝條300的面積。此外，基板310包括設置於貼附區310a之外的至少一個定位孔320。換句話說，定位孔320可以是分佈於圍繞在貼附區310a的周邊區域。定位孔320可以在後續製程中用於對齊或是固定（affixation）基板310。值得注意的是，雖然圖3A中繪示三個定位孔320，但定位孔320的數量並不限於此。在一實施例中，定位孔320可以是位於和黏著層330不同的平面上。舉例來說，定位孔320可以設置於基板310的側壁上。定位孔320的配置並不限於此。
舉例來說，第二製程腔體內的製程設備可以藉由對位（positioning）定位孔320以對齊基板310上單體化封裝條300的位置來進行後續的製程。再者，為了後續製程的穩定性，可以藉由將定位孔320固定於固持裝置（holding fixture）（未繪示），以固定基板310。固持裝置可提供基板310機械支撐。舉例來說，固持裝置可以配置於第二製程腔體內或是配置於轉移設備，以確保在穩定的狀態下執行製程。固持裝置可以定位於基板310的定位孔320處。舉例來說，固持裝置可以包含對應於定位孔320的多個插銷（pins）。當轉移基板310或是對基板310進行加工製程時，固持裝置的插銷會被插入定位孔320中，以避免基板310產生不必要的動作或位移。在一實施例中，固持裝置可以是真空固定件或是夾具，只要在轉移或是後續製程中可以固定基板310，且不會對單體化封裝條300造成破壞，則本發明不限於此。
圖3C至圖3D是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。請參照圖3C及圖3D，多個被動元件340形成於重佈線路圖案120的第二表面120b上。此外，被動元件340可以例如是設置於對應的導電端子150上。值得注意的是，只要被動元件340可以電性連接於重佈線路圖案120，則可以用任何方式設置被動元件340。被動元件340例如是電容器、電阻器、電感器等。進一步來說，至少一個第二積體電路元件350也是藉由接合製程形成於重佈線路圖案120的第二表面120b上。舉例來說，第二積體電路元件350可以是記憶體裝置，例如NAND快閃晶粒或是其他適合的晶片，但本發明不限於此。此外，第二積體電路元件350透過打線接合製程將導線電性連接至重佈線路圖案120。也就是說，第二積體電路元件350透過導線電性連接導電端子150。在一些實施例中，被動元件340的接合製程可以在第二積體電路元件350的接合製程之前執行。在一些替代性的實施例中，被動元件340的接合製程可以於第二積體電路元件350的接合製程之後執行。本發明並不限制被動元件340以及第二積體電路元件350的接合製程的先後順序。
在本實施例中，形成第二密封體360以密封被動元件340以及第二積體電路元件350。類似於第一密封體140，第二密封體360可以是藉由模封製程形成的模塑化合物或是絕緣材料。可以理解的是，其他元件亦可以組裝至基板310上，例如是製造系統級封裝體。隨後，對單體化封裝條300進行單體化製程，以形成多個封裝結構400。進一步來說，封裝結構400中的每一者包括第二單體化密封體360a、被動元件340以及至少一個第二積體電路元件350。此外，第二積體電路元件350電性連接於單體化封裝條300的重佈線路圖案120。第二單體化密封體360a密封被動元件340以及第二積體電路元件350。再者，單體化製程可以例如是藉由旋轉刀片或雷射光束進行切割或是其他適合的技術，但本發明不限於此。
請參照圖3D，在上述的單體化製程之後，從封裝結構400移除黏著層330以及基板310。舉例來說，可以藉由施加外部能量（例如是UV雷射、可見光或是熱）於基板310，以使基板310從封裝結構400剝離。可視黏著層330的結構以及材料而採用其他適合的技術，本發明不以此為限。在一實施例中，在移除黏著層330之後，可以進一步形成環氧樹脂模塑化合物（epoxy mold compound，EMC）層於背面130a，以密封第一積體電路元件130。進一步來說，具有定位孔320的基板310可以在從封裝結構400移除後重複使用，進而降低封裝成本。
綜上所述，在進行封裝製程之前，切割封裝面板形成單體化封裝條，以避免採用大型的設備來進行封裝製程。此外，封裝製程在條狀形式下更有效率。另外，對藉由定位孔被固定的基板進行封裝製程，可以確保製造過程的穩定性。因此，現有的設備可以隨製造流程的改變而被充分利用並兼容於製造流程中，並且維持穩定的製造過程以及改善產品良率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
110a、110b‧‧‧載體
120‧‧‧重佈線路圖案
120a‧‧‧第一表面
120b‧‧‧第二表面
130‧‧‧第一積體電路元件
130a‧‧‧背面
130b‧‧‧主動面
130c‧‧‧凸塊
140‧‧‧第一密封體
150‧‧‧導電端子
200‧‧‧封裝面板
240‧‧‧第一單體化密封體
300‧‧‧單體化封裝條
310‧‧‧基板
310a‧‧‧貼附區
320‧‧‧定位孔
330‧‧‧黏著層
340‧‧‧被動元件
350‧‧‧第二積體電路元件
360‧‧‧第二密封體
360a‧‧‧第二單體化密封體
400‧‧‧封裝結構
A-A‧‧‧線
圖1是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。 圖2A是依據本發明一實施例的封裝結構的製造方法的俯視示意圖。 圖2B是圖2A的封裝結構的製造方法沿A-A線的剖面示意圖。 圖3A是依據本發明一實施例的封裝結構的製造方法的俯視示意圖。 圖3B是圖3A的封裝結構的製造方法沿A-A線的剖面示意圖。 圖3C至圖3D是依據本發明一實施例的封裝結構的製造方法的剖面示意圖。

Claims (10)

  1. 一種封裝結構的製造方法，包括： 提供封裝面板，其中所述封裝面板包括第一密封體、多個第一積體電路元件及電性連接於所述第一積體電路元件的多個重佈線路圖案，藉由所述第一密封體密封所述第一積體電路元件，且所述重佈線路圖案分佈於所述第一密封體及所述第一積體電路元件上； 切割所述封裝面板的所述第一密封體，以形成多個單體化封裝條，其中所述單體化封裝條中的每一者包括第一單體化密封體、所述重佈線路圖案中的任一者及至少一個被所述第一單體化密封體密封的所述第一積體電路元件； 將所述單體化封裝條中的任一者貼附於基板上的貼附區，其中所述基板包括設置於所述貼附區之外的至少一個定位孔；以及 對貼附於所述基板上的所述單體化封裝條進行封裝製程，並藉由所述至少一個定位孔固定所述基板，以形成封裝結構。
  2. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述封裝製程包括： 形成多個被動元件及至少一個第二積體電路元件於所述單體化封裝條上，其中所述被動元件及所述至少一個第二積體電路元件電性連接至所述單體化封裝條的所述重佈線路圖案；以及 藉由第二密封體密封所述被動元件及所述至少一個第二積體電路元件。
  3. 如申請專利範圍第2項所述的封裝結構的製造方法，其中所述封裝製程還包括： 單體化所述第二密封體，以形成多個所述封裝結構，其中所述封裝結構中的每一者包括第二單體化密封體、多個所述被動元件及電性連接至所述單體化封裝條的所述重佈線路圖案的所述至少一個第二積體電路元件，且藉由所述第二單體化密封體密封所述被動元件及所述至少一個第二積體電路元件。
  4. 如申請專利範圍第1項所述的封裝結構的製造方法，還包括： 在將所述單體化封裝條貼附於所述基板上的所述貼附區之前，形成黏著層於所述基板上；以及 在進行所述封裝製程之後，從所述單體化封裝條移除所述黏著層。
  5. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述封裝面板還包括電性連接於所述重佈線路圖案的多個導電端子，且所述單體化封裝條中的每一者包括被所述第一單體化密封體密封的所述導電端子。
  6. 一種封裝結構的製造方法，包括： 於第一製程腔體內提供封裝面板，其中所述封裝面板包括第一密封體、多個第一積體電路元件及電性連接於所述第一積體電路元件的多個重佈線路圖案，藉由所述第一密封體密封所述第一積體電路元件，且所述重佈線路圖案分佈於所述第一密封體及所述第一積體電路元件上； 於所述第一製程腔體內切割所述封裝面板的所述第一密封體，以形成多個單體化封裝條，其中所述單體化封裝條中的每一者包括第一單體化密封體、所述重佈線路圖案中的任一者及至少一個被所述第一單體化密封體密封的所述第一積體電路元件； 將所述單體化封裝條轉移至第二製程腔體內，其中至少一個固持裝置設置於所述第二製程腔體內； 於所述第二製程腔體內，將所述單體化封裝條中的任一者貼附於基板上的貼附區，其中所述基板包括設置於所述貼附區之外的至少一個定位孔； 於所述第二製程腔體內，藉由所述至少一個固持裝置固定所述基板，其中所述至少一個固持裝置對應於所述基板上的所述至少一個定位孔；以及 對貼附於所述基板上的所述單體化封裝條進行封裝製程，以於所述第二製程腔體內形成封裝結構。
  7. 如申請專利範圍第6項所述的封裝結構的製造方法，其中所述封裝製程包括： 形成多個被動元件及至少一個第二積體電路元件於所述單體化封裝條上，其中所述被動元件及所述至少一個第二積體電路元件電性連接至所述單體化封裝條的所述重佈線路圖案；以及 藉由第二密封體密封所述被動元件及所述至少一個第二積體電路元件。
  8. 如申請專利範圍第7項所述的封裝結構的製造方法，其中所述封裝製程還包括： 單體化所述第二密封體，以形成多個所述封裝結構，其中所述封裝結構中的每一者包括第二單體化密封體、多個所述被動元件及電性連接至所述單體化封裝條的所述重佈線路圖案的所述至少一個第二積體電路元件，且藉由所述第二單體化密封體密封所述被動元件及所述至少一個第二積體電路元件。
  9. 如申請專利範圍第6項所述的封裝結構的製造方法，還包括： 在將所述單體化封裝條貼附於所述基板上的所述貼附區之前，形成黏著層於所述基板上；以及 在進行所述封裝製程之後，將所述單體化封裝條中的任一者從所述基板剝離。
  10. 如申請專利範圍第6項所述的封裝結構的製造方法，其中所述封裝面板還包括電性連接於所述重佈線路圖案的多個導電端子，且所述單體化封裝條中的每一者包括被所述第一單體化密封體密封的所述導電端子。
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US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
CN101009230A (zh) 2006-01-24 2007-08-01 探微科技股份有限公司 晶片级封装和切割的方法
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US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8367475B2 (en) * 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
US9679836B2 (en) 2011-11-16 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
US9831170B2 (en) * 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
JP5949193B2 (ja) * 2012-06-12 2016-07-06 富士通株式会社 電子装置の製造方法
US9704780B2 (en) 2012-12-11 2017-07-11 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
TWI635585B (zh) 2013-07-10 2018-09-11 矽品精密工業股份有限公司 半導體封裝件及其製法
CN106164330B (zh) * 2014-04-02 2021-01-26 应用材料公司 真空处理系统以及用于装配处理系统的方法
US9799622B2 (en) * 2014-06-18 2017-10-24 Dyi-chung Hu High density film for IC package
US9947625B2 (en) * 2014-12-15 2018-04-17 Bridge Semiconductor Corporation Wiring board with embedded component and integrated stiffener and method of making the same
US9502272B2 (en) * 2014-12-29 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Devices and methods of packaging semiconductor devices
US9461018B1 (en) * 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
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