TW201924006A - Wiring substrate - Google Patents
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- TW201924006A TW201924006A TW107133418A TW107133418A TW201924006A TW 201924006 A TW201924006 A TW 201924006A TW 107133418 A TW107133418 A TW 107133418A TW 107133418 A TW107133418 A TW 107133418A TW 201924006 A TW201924006 A TW 201924006A
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Abstract
Description
本發明關於一種配線基板。 The present invention relates to a wiring substrate.
目前,已開發出了微細的配線導體高密度地位在絕緣層的配線基板。此種配線基係使用於以伺服器或超級電腦等為代表的高性能的電子設備。另外,此種配線基板所使用的絕緣層係包含絕緣樹脂以及分散地位於絕緣樹脂中的絕緣粒子。 At present, a wiring board having a high density of wiring conductors in an insulating layer has been developed. Such a wiring base is used for a high-performance electronic device typified by a server or a supercomputer. Further, the insulating layer used in such a wiring board contains an insulating resin and insulating particles dispersed in the insulating resin.
特別是就高效率地傳送高頻信號而言,配線基板的配線導體希望配線導體的表面能為平坦狀。另一方面,就使配線導體與絕緣層牢固地密著而言,配線基板的配線導體希望絕緣樹脂能粗面化。為了使此種配線基板的配線導體與絕緣層牢固地密著,日本特開2013-012726號公報提出了一種絕緣層形成用的組成物,係相對於100重量部的環氧樹脂含有10~60重量部的兩種無機填料。 In particular, in order to efficiently transmit a high-frequency signal, the wiring conductor of the wiring board desirably has a flat surface energy of the wiring conductor. On the other hand, in order to firmly adhere the wiring conductor and the insulating layer, the wiring conductor of the wiring board is expected to be roughened by the insulating resin. In order to make the wiring conductor of the wiring board and the insulating layer firmly adhered, Japanese Laid-Open Patent Publication No. 2013-012726 proposes a composition for forming an insulating layer, which contains 10 to 60 with respect to 100 parts by weight of the epoxy resin. Two inorganic fillers in the weight section.
如上述的配線基板所使用的絕緣層,為了抑制配線基板的熱膨脹率以防止配線導體的斷線,有時會具有高密度地分散的絕緣粒子。此情況下,如果為了抑制由絕緣粒子產生的凹凸的影響而減小絕緣樹脂的粗面化,則 配線導體的密接強度降低。另一方面,如果為了提高密接強度而增大絕緣樹脂的粗面化,則配線導體的表面的凹凸變大而導致高頻信號的傳送特性降低。如此,存在有難以兼顧傳送特性與密接性的可能性。 The insulating layer used in the wiring board described above may have insulating particles dispersed at a high density in order to suppress the thermal expansion coefficient of the wiring substrate and prevent disconnection of the wiring conductor. In this case, if the surface of the insulating resin is reduced in order to suppress the influence of the unevenness caused by the insulating particles, the adhesion strength of the wiring conductor is lowered. On the other hand, if the surface of the wiring conductor is increased in thickness in order to increase the adhesion strength, the unevenness of the surface of the wiring conductor is increased, and the transmission characteristics of the high-frequency signal are lowered. As described above, there is a possibility that it is difficult to achieve both the transmission characteristics and the adhesion.
本揭示的配線基板係具有:第一絕緣層;第二絕緣層,係層疊於前述第一絕緣層,且包含與第一絕緣層相同種類的絕緣材料;多個絕緣粒子,係以40~80wt%的比例,分別包含於第一絕緣層及第二絕緣層,且包括部分露出粒子,該部分露出粒子係表面的一部分從第一絕緣層的表面及第二絕緣層的表面露出;第一基底金屬層,係位於第一絕緣層的表面起至表層內;第二基底金屬層,係位於第二絕緣層的表面起至表層內;第一配線導體,係位於第一基底金屬層的表面;以及第二配線導體,係位於第二基底金屬層的表面。第二絕緣層的表面中的第二配線導體所在的區域的凹凸的第二高低差,小於第一絕緣層的表面中的第一配線導體所在的區域的凹凸的第一高低差,且第二高低差為絕緣粒子的平均粒徑的2/5以下。 The wiring substrate of the present disclosure has a first insulating layer, a second insulating layer laminated on the first insulating layer, and comprising the same kind of insulating material as the first insulating layer; and a plurality of insulating particles, 40 to 80 wt. The ratio of % is included in the first insulating layer and the second insulating layer, respectively, and includes partially exposed particles, the portion exposing a portion of the surface of the particle system being exposed from the surface of the first insulating layer and the surface of the second insulating layer; the first substrate The metal layer is located on the surface of the first insulating layer and extends into the surface layer; the second base metal layer is located in the surface of the second insulating layer to the surface layer; the first wiring conductor is located on the surface of the first base metal layer; And a second wiring conductor located on a surface of the second base metal layer. a second height difference of the unevenness of the region where the second wiring conductor is located in the surface of the second insulating layer is smaller than a first height difference of the unevenness of the region where the first wiring conductor is located in the surface of the first insulating layer, and the second The height difference is 2/5 or less of the average particle diameter of the insulating particles.
本揭示的配線基板係具有優異的高頻信號的傳送特性以及配線導體與絕緣層的密著性。 The wiring board of the present invention has excellent transmission characteristics of a high-frequency signal and adhesion of a wiring conductor to an insulating layer.
1‧‧‧芯用絕緣層 1‧‧ ‧ core insulation
2‧‧‧積層用絕緣層 2‧‧‧Insulation layer for laminate
2a‧‧‧第一絕緣層 2a‧‧‧first insulation
2b‧‧‧第二絕緣層 2b‧‧‧Second insulation
3‧‧‧絕緣粒子 3‧‧‧Insulating particles
3a‧‧‧部分露出粒子 3a‧‧‧Partially exposed particles
4‧‧‧基底金屬層 4‧‧‧Base metal layer
4a‧‧‧第一基底金屬層 4a‧‧‧First base metal layer
4b‧‧‧第二基底金屬層 4b‧‧‧Second base metal layer
5‧‧‧配線導體 5‧‧‧Wiring conductor
5a‧‧‧第一配線導體 5a‧‧‧First wiring conductor
5b‧‧‧第二配線導體 5b‧‧‧Second wiring conductor
6‧‧‧阻焊層 6‧‧‧solder layer
6a‧‧‧開口 6a‧‧‧ openings
6b‧‧‧開口 6b‧‧‧ openings
7‧‧‧通孔 7‧‧‧through hole
8‧‧‧貫孔 8‧‧‧through holes
8a‧‧‧第一貫孔 8a‧‧‧first through hole
8b‧‧‧第二貫孔 8b‧‧‧second through hole
9‧‧‧中間層 9‧‧‧Intermediate
20‧‧‧配線基板 20‧‧‧Wiring substrate
L1‧‧‧第一高低差 L1‧‧‧ first high and low difference
L2‧‧‧第二高低差 L2‧‧‧second height difference
M‧‧‧寬頻域記憶體 M‧‧‧ wide frequency domain memory
S‧‧‧高性能積體電路 S‧‧‧High-performance integrated circuit
第1圖是顯示本揭示的一實施型態的配線基板的概略剖視圖。 Fig. 1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present disclosure.
第2圖是本揭示的一實施型態的配線基板的第一絕緣層的放大剖視圖。 Fig. 2 is an enlarged cross-sectional view showing a first insulating layer of a wiring board according to an embodiment of the present disclosure.
第3圖是本揭示的一實施型態的配線基板的第二絕緣層的放大剖視圖。 Fig. 3 is an enlarged cross-sectional view showing a second insulating layer of a wiring board according to an embodiment of the present disclosure.
第4圖是本揭示的一實施型態的配線基板的配線導體及其周邊的放大剖視圖。 Fig. 4 is an enlarged cross-sectional view showing a wiring conductor of a wiring board according to an embodiment of the present disclosure and its periphery.
第5圖是顯示本揭示的配線基板的另一實施型態的概略剖視圖。 Fig. 5 is a schematic cross-sectional view showing another embodiment of the wiring board of the present disclosure.
依據第1圖~第4圖,說明本揭示的一實施型態的配線基板。配線基板20係具有芯用絕緣層1、積層(build up)用絕緣層2、絕緣粒子3、基底金屬層4、配線導體5、以及阻焊層6。配線基板20係例如在上表面搭載高性能積體電路S及多個寬頻域記憶體M。 A wiring board according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 4 . The wiring board 20 has a core insulating layer 1 , a build-up insulating layer 2 , insulating particles 3 , an underlying metal layer 4 , a wiring conductor 5 , and a solder resist layer 6 . In the wiring board 20, for example, a high performance integrated circuit S and a plurality of wide frequency domain memories M are mounted on the upper surface.
芯用絕緣層1係包含例如使環氧樹脂、雙馬來醯亞胺三嗪樹脂等含浸於補強用的玻璃布而成的絕緣材料。芯用絕緣層1係具有作為配線基板20中的補強用的支持體的功能。芯用絕緣層1係具有上下貫通的多個通孔(through hole)7。芯用絕緣層1的厚度係設定為例如200~1200μm。通孔7的直徑係設定為例如50~200μm。俯視觀察下,配線基板20為四邊形的平板狀。配線基板20的一邊的長度為20~80mm左右,厚度為0.3~1.6mm左右。 The core insulating layer 1 includes, for example, an insulating material obtained by impregnating an epoxy resin, a bismaleimide triazine resin, or the like with a glass cloth for reinforcement. The core insulating layer 1 has a function as a support for reinforcement in the wiring substrate 20. The core insulating layer 1 has a plurality of through holes 7 penetrating vertically. The thickness of the core insulating layer 1 is set to, for example, 200 to 1200 μm. The diameter of the through hole 7 is set to, for example, 50 to 200 μm. The wiring board 20 has a rectangular plate shape in plan view. The length of one side of the wiring board 20 is about 20 to 80 mm, and the thickness is about 0.3 to 1.6 mm.
芯用絕緣層1係將使環氧樹脂、雙馬來醯亞胺三嗪樹脂等熱固性樹脂含浸於強化用的玻璃布而成的預 浸料層疊多個,並在加熱下進行加壓加工,藉此形成為平板狀。通孔7係通過對芯用絕緣層1進行鑽孔加工、雷射加工或噴砂加工等處理而形成。芯用絕緣層1的上下表面的配線導體5彼此經由通孔7內的配線導體5而電性連接。 In the core insulating layer 1 , a plurality of prepregs obtained by impregnating a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin into a glass cloth for reinforcement are laminated, and subjected to press processing under heating. Thereby, it is formed into a flat shape. The through hole 7 is formed by performing a process such as drilling, laser processing, or sand blasting on the core insulating layer 1. The wiring conductors 5 on the upper and lower surfaces of the core insulating layer 1 are electrically connected to each other via the wiring conductor 5 in the through hole 7.
積層用絕緣層2係包含第一絕緣層2a及第二絕緣層2b。主要用於將高性能積體電路S與位於配線基板20下表面的配線導體5連結的配線導體5係位於芯用絕緣層1的上側的第一絕緣層2a的上表面。用於將高性能積體電路S與寬頻域記憶體M連結的配線導體5係位於第一絕緣層2a的上側的第二絕緣層2b的上表面。第一絕緣層2a及第二絕緣層2b係分別具有包含凹凸的表面。 The insulating layer 2 for laminated layers includes the first insulating layer 2a and the second insulating layer 2b. The wiring conductor 5 mainly used to connect the high-performance integrated circuit S to the wiring conductor 5 located on the lower surface of the wiring substrate 20 is placed on the upper surface of the first insulating layer 2a on the upper side of the core insulating layer 1. The wiring conductor 5 for connecting the high performance integrated circuit S and the wide frequency domain memory M is located on the upper surface of the second insulating layer 2b on the upper side of the first insulating layer 2a. The first insulating layer 2a and the second insulating layer 2b each have a surface including irregularities.
第一絕緣層2a及第二絕緣層2b係包含例如環氧樹脂、酚樹脂、氰酸酯等相同種類的絕緣材料。由此,能夠抑制第一絕緣層2a與第二絕緣層2b之間的熱伸縮差,有利於配線基板20的翹曲的抑制等。相同種類的絕緣材料是指基本上第一絕緣層2a與第二絕緣層2b為相同的樹脂組成物。惟,若是可形成以上述樹脂為主成分之網狀聚合物的組合即可。若為由此種網狀聚合物構成的任一個組合即可。 The first insulating layer 2a and the second insulating layer 2b contain the same kind of insulating material such as an epoxy resin, a phenol resin, or a cyanate ester. Thereby, it is possible to suppress a difference in thermal expansion and contraction between the first insulating layer 2a and the second insulating layer 2b, and it is advantageous in suppressing warpage of the wiring substrate 20 and the like. The same kind of insulating material means that the first insulating layer 2a and the second insulating layer 2b are substantially the same resin composition. However, a combination of a network polymer containing the above resin as a main component may be formed. Any combination of such a network polymer may be used.
積層用絕緣層2係在芯用絕緣層1的上下表面覆蓋後述的配線導體5,而具有確保相互相鄰的配線導體5彼此的絕緣性之功能。積層用絕緣層2係具有將配線導體5作為底部的多個貫孔(via hole)8。貫孔8係具有位於第一絕緣層2a的第一貫孔8a及位於第二絕緣層2b 的第二貫孔8b。 The laminated insulating layer 2 has a function of ensuring insulation between the adjacent wiring conductors 5 by covering the wiring conductors 5 to be described later on the upper and lower surfaces of the core insulating layer 1. The laminated insulating layer 2 has a plurality of via holes 8 having the wiring conductor 5 as a bottom. The through hole 8 has a first through hole 8a located in the first insulating layer 2a and a second through hole 8b in the second insulating layer 2b.
第一絕緣層2a的厚度係設定為例如30~40μm。第一絕緣層2a係具有將配線導體5作為底部的多個第一貫孔8a。第一貫孔8a的直徑係設定為例如30~60μm。 The thickness of the first insulating layer 2a is set to, for example, 30 to 40 μm. The first insulating layer 2a has a plurality of first through holes 8a having the wiring conductor 5 as a bottom. The diameter of the first constant hole 8a is set to, for example, 30 to 60 μm.
第二絕緣層2b的厚度係設定為例如5~15μm。第二絕緣層2b係具有將配線導體5作為底部的多個第二貫孔8b。第二貫孔8b的直徑係設定為例如10~20μm。 The thickness of the second insulating layer 2b is set to, for example, 5 to 15 μm. The second insulating layer 2b has a plurality of second through holes 8b having the wiring conductor 5 as a bottom. The diameter of the second through hole 8b is set to, for example, 10 to 20 μm.
積層用絕緣層2係例如在真空下,將使絕緣粒子3分散於環氧樹脂等熱固性樹脂中的絕緣層用的膜,以覆蓋配線導體5的方式,附著於芯用絕緣層1的上下表面並進行熱固化,而藉此形成。 The insulating layer 2 for the laminate is a film for an insulating layer in which the insulating particles 3 are dispersed in a thermosetting resin such as an epoxy resin, and adheres to the upper and lower surfaces of the core insulating layer 1 so as to cover the wiring conductor 5, for example. And it is formed by heat curing.
絕緣粒子3係位於第一絕緣層2a及第二絕緣層2b。絕緣粒子3可列舉例如二氧化矽(SiO2)、玻璃、氧化鋁等。絕緣粒子3係具有例如球狀的形狀,平均粒徑係設定為例如0.1~0.5μm。第一絕緣層2a及第二絕緣層2b中的絕緣粒子3的含有比例係設定為例如40~80wt%。球狀的形狀係有利於高密度地含有絕緣粒子3。第一絕緣層2a及第二絕緣層2b中,絕緣粒子3係具有減小熱膨脹係數以抑制配線導體5的斷線等的作用。 The insulating particles 3 are located on the first insulating layer 2a and the second insulating layer 2b. Examples of the insulating particles 3 include cerium oxide (SiO 2 ), glass, alumina, and the like. The insulating particles 3 have a spherical shape, for example, and the average particle diameter is set to, for example, 0.1 to 0.5 μm. The content ratio of the insulating particles 3 in the first insulating layer 2a and the second insulating layer 2b is set to, for example, 40 to 80% by weight. The spherical shape is advantageous for containing the insulating particles 3 at a high density. In the first insulating layer 2a and the second insulating layer 2b, the insulating particles 3 have an effect of reducing the thermal expansion coefficient to suppress disconnection of the wiring conductor 5 and the like.
絕緣粒子3係包含部分露出粒子3a,該部分露出粒子3a係表面的一部分露出第一絕緣層2a的表面及第二絕緣層2b的表面。俯視觀察下,佔第一絕緣層2a的表面的部分露出粒子3a的露出部分的面積比例係設定為 例如20~30%。如第2圖所示,剖視觀察下,絕緣粒子3所致的第一絕緣層2a的凹凸的第一高低差L1,係設定為例如160~600nm。面積比例是指俯視觀察下的部分露出粒子3a的露出部分的面積(A)在第一絕緣層2a或第二絕緣層2b的表面(包含上述A)所佔的比例。 The insulating particles 3 include partially exposed particles 3a which expose a portion of the surface of the first insulating layer 2a and a surface of the second insulating layer 2b. The area ratio of the exposed portion of the exposed portion of the particles 3a in the portion of the surface of the first insulating layer 2a is set to, for example, 20 to 30% in plan view. As shown in Fig. 2, the first height difference L1 of the unevenness of the first insulating layer 2a due to the insulating particles 3 is set to, for example, 160 to 600 nm in a cross-sectional view. The area ratio refers to the ratio of the area (A) of the exposed portion of the partially exposed particles 3a in plan view to the surface of the first insulating layer 2a or the second insulating layer 2b (including the above A).
俯視觀察下,佔第二絕緣層2b的表面的部分露出粒子3a的露出部分的面積比例係設定為例如5~12%。如第3圖所示,剖視觀察下,絕緣粒子3所致的第二絕緣層2b的凹凸的第二高低差L2,係設定為例如10~100nm。如上述的部分露出粒子3a的面積比例能夠藉由例如X射線光電子光譜(XPS)分析而算出。 The area ratio of the exposed portion of the exposed portion of the particles 3a to the surface of the second insulating layer 2b is set to, for example, 5 to 12% in plan view. As shown in Fig. 3, the second height difference L2 of the unevenness of the second insulating layer 2b due to the insulating particles 3 is set to, for example, 10 to 100 nm in a cross-sectional view. The area ratio of the partially exposed particles 3a as described above can be calculated by, for example, X-ray photoelectron spectroscopy (XPS) analysis.
為了使絕緣粒子3露出此種第一絕緣層2a的表面及第二絕緣層2b的表面,可進行例如氧電漿、氮電漿或氬電漿處理。相較於蝕刻液的處理,電漿處理較花費處理時間,但由於能夠進行微細的研磨,因此有利於提高絕緣粒子3的露出量的精度。 In order to expose the insulating particles 3 to the surface of the first insulating layer 2a and the surface of the second insulating layer 2b, for example, oxygen plasma, nitrogen plasma or argon plasma treatment may be performed. The plasma treatment takes a longer processing time than the treatment of the etching liquid. However, since fine polishing can be performed, it is advantageous to improve the precision of the exposure amount of the insulating particles 3.
如第4圖所示,基底金屬層4係包含第一基底金屬層4a及第二基底金屬層4b。基底金屬層4係位於積層用絕緣層2的表面起至表層內,該積層用絕緣層2係位於後述的配線導體5的下側。而且,基底金屬層4亦位於露出於貫孔8的底部的配線導體5的表面。 As shown in FIG. 4, the base metal layer 4 includes a first base metal layer 4a and a second base metal layer 4b. The underlying metal layer 4 is located in the surface layer from the surface of the insulating layer 2 for the buildup, and the insulating layer 2 for the buildup is placed on the lower side of the wiring conductor 5 to be described later. Further, the underlying metal layer 4 is also located on the surface of the wiring conductor 5 exposed at the bottom of the through hole 8.
第一基底金屬層4a係包含例如銅等良導電性金屬。此種第一基底金屬層4a係藉由例如無電鍍敷法而形成。此種鍍敷法因加工時間較短而較有利。 The first base metal layer 4a contains a good conductive metal such as copper. Such a first base metal layer 4a is formed by, for example, electroless plating. This plating method is advantageous because of the short processing time.
第二基底金屬層4b係位於與後述的第二配線導體5b的下側對應的積層用絕緣層2的表面起至表層內。而且,第二基底金屬層4b亦位於露出於貫孔8的底部的配線導體5的表面。 The second base metal layer 4b is located in the surface layer from the surface of the build-up insulating layer 2 corresponding to the lower side of the second wiring conductor 5b to be described later. Further, the second base metal layer 4b is also located on the surface of the wiring conductor 5 exposed at the bottom of the through hole 8.
第二基底金屬層4b係包括:金屬層,係包含例如鈦等屬元素週期表中的第4族的金屬或者鉻及鉬等屬元素週期表中的第6族的金屬;以及位於該金屬層上的銅層。該金屬層的厚度係設定為例如20~25nm。銅層的厚度係設定為例如200~220nm。由於將金屬層的厚度設為比銅層的厚度薄,故能夠由沒有結晶粒的凝聚之連續且均質的結晶粒來構成位於第二基底金屬層4b上的第二配線導體5b。 The second base metal layer 4b includes: a metal layer containing a metal of Group 4 of the periodic table of elements such as titanium or a metal of Group 6 of the periodic table of elements such as chromium and molybdenum; and the metal layer The copper layer on it. The thickness of the metal layer is set to, for example, 20 to 25 nm. The thickness of the copper layer is set to, for example, 200 to 220 nm. Since the thickness of the metal layer is made thinner than the thickness of the copper layer, the second wiring conductor 5b located on the second underlying metal layer 4b can be formed of continuous and homogeneous crystal grains having no aggregation of crystal grains.
此外,金屬層係有利於例如抑制作為構成配線導體5的材料而使用的銅的擴散。由此,能夠謀求配線導體5與絕緣層的密著強度的提高、抑制由於銅在絕緣層內擴散而產生的遷移。 Further, the metal layer is advantageous for, for example, suppressing diffusion of copper used as a material constituting the wiring conductor 5. Thereby, it is possible to improve the adhesion strength between the wiring conductor 5 and the insulating layer, and to suppress migration due to diffusion of copper in the insulating layer.
第二基底金屬層4b係位於積層用絕緣層2的表面起,至厚度方向小於200nm的深度的表層內。上述的第二基底金屬層4b的厚度能夠藉由例如歐傑(Auger)分析而算出。 The second underlying metal layer 4b is located in the surface layer of the thickness of the insulating layer 2 for the buildup layer to a depth of less than 200 nm in the thickness direction. The thickness of the second base metal layer 4b described above can be calculated by, for example, Auger analysis.
包含第4族或第6族的金屬的金屬層以及位於該金屬層上的銅層,係藉由例如濺鍍法來形成。此種濺鍍法由於進行將第4族或第6族的金屬層及銅層從積層用絕緣層2的表面向表層內擊入的處理,故相較於無電鍍敷法,有利於提高積層用絕緣層2與第二基底金屬層4b的密 著強度。由此,特別是第二配線導體5b為微細配線時,有利於提高第二配線導體5b與積層用絕緣層2的密著強度。 The metal layer containing the metal of Group 4 or Group 6 and the copper layer on the metal layer are formed by, for example, sputtering. In such a sputtering method, since the metal layer of the Group 4 or the group 6 and the copper layer are struck from the surface of the insulating layer 2 for the buildup layer into the surface layer, it is advantageous to increase the buildup compared to the electroless plating method. The adhesion strength between the insulating layer 2 and the second base metal layer 4b is used. Therefore, in particular, when the second wiring conductor 5b is a fine wiring, it is advantageous to increase the adhesion strength between the second wiring conductor 5b and the laminated insulating layer 2.
配線導體5所在的區域以外的基底金屬層4,為了防止短路而藉由蝕刻來除去。 The underlying metal layer 4 other than the region where the wiring conductor 5 is located is removed by etching in order to prevent short-circuiting.
配線導體5係位於芯用絕緣層1的上下表面、通孔7內、積層用絕緣層2的表面及貫孔8內。配線導體5係包括第一配線導體5a及第二配線導體5b。配線導體5係藉由例如半加成法等鍍敷法來形成,包含銅等良導電性金屬。 The wiring conductor 5 is located on the upper and lower surfaces of the core insulating layer 1, the inside of the through hole 7, the surface of the insulating layer 2 for lamination, and the through hole 8. The wiring conductor 5 includes a first wiring conductor 5a and a second wiring conductor 5b. The wiring conductor 5 is formed by a plating method such as a semi-additive method, and includes a good conductive metal such as copper.
第一配線導體5a係位於第一絕緣層2a的表面及第一貫孔8a內,如上所述,主要具有將高性能積體電路S與位於配線基板20下表面的配線導體5連結的作用。第一配線導體5a的線寬係設定為例如15~20μm,厚度係設定為例如10~20μm。如此,第一配線導體5a係具有較大的線寬及厚度,因此即使上述的第一絕緣層2a的凹凸的第一高低差L1為160~600nm之較大的值,也難以受到凹凸的影響。 The first wiring conductor 5a is located on the surface of the first insulating layer 2a and the first through hole 8a. As described above, it mainly has a function of connecting the high-performance integrated circuit S to the wiring conductor 5 located on the lower surface of the wiring substrate 20. The line width of the first wiring conductor 5a is set to, for example, 15 to 20 μm, and the thickness is set to, for example, 10 to 20 μm. As described above, since the first wiring conductor 5a has a large line width and a thickness, even if the first height difference L1 of the unevenness of the first insulating layer 2a is a large value of 160 to 600 nm, it is difficult to be affected by the unevenness. .
第二配線導體5b係位於第二絕緣層2b的表面及第二貫孔8b內,如上所述,主要具有將高性能積體電路S與寬頻域記憶體M連結的作用。第二配線導體5b的線寬係設定為例如2~6μm,厚度係設定為例如2~15μm。如此,第二配線導體5b係具有微細的線寬及厚度,但由於上述的第二絕緣層2b的凹凸的第二高低差L2為10~100nm之較小的值,因此凹凸的影響小。 The second wiring conductor 5b is located on the surface of the second insulating layer 2b and the second through hole 8b. As described above, it mainly has a function of connecting the high performance integrated circuit S and the wide frequency domain memory M. The line width of the second wiring conductor 5b is set to, for example, 2 to 6 μm, and the thickness is set to, for example, 2 to 15 μm. As described above, the second wiring conductor 5b has a fine line width and a thickness. However, since the second height difference L2 of the unevenness of the second insulating layer 2b is a small value of 10 to 100 nm, the influence of the unevenness is small.
阻焊層6係位於配線基板20的最上層及最下層的第二絕緣層2b表面。阻焊層6係具有使最上層的第二配線導體5b露出的開口6a及使最下層的第二配線導體5b露出的開口6b。阻焊層6係例如將丙烯酸改性環氧樹脂等具有感光性的熱固性樹脂的膜貼附於第二絕緣層2b的表面,藉由曝光及顯影來形成開口6a、6b,並進行熱固化而藉此形成。 The solder resist layer 6 is located on the surface of the uppermost layer of the wiring substrate 20 and the second insulating layer 2b of the lowermost layer. The solder resist layer 6 has an opening 6a that exposes the uppermost second wiring conductor 5b and an opening 6b that exposes the lowermost second wiring conductor 5b. The solder resist layer 6 is, for example, a film having a photosensitive thermosetting resin such as an acrylic modified epoxy resin attached to the surface of the second insulating layer 2b, and the openings 6a and 6b are formed by exposure and development, and thermally cured. This is formed.
如上所述,本揭示的配線基板20中,第二絕緣層2b表面的凹凸的第二高低差L2係小於第一絕緣層2a表面的凹凸的第一高低差L1。並且,第二高低差L2係抑制於絕緣粒子的平均粒徑的2/5以下。由此,能夠使較第一配線導體5a的配線寬度及厚度更微細且具有平坦狀的表面的第二配線導體5b,位於第二絕緣層2b的表面。 As described above, in the wiring substrate 20 of the present disclosure, the second height difference L2 of the unevenness on the surface of the second insulating layer 2b is smaller than the first height difference L1 of the unevenness on the surface of the first insulating layer 2a. Further, the second height difference L2 is suppressed to 2/5 or less of the average particle diameter of the insulating particles. Thereby, the second wiring conductor 5b having a finer wiring width and thickness than the first wiring conductor 5a and having a flat surface can be positioned on the surface of the second insulating layer 2b.
若第二高低差L2為絕緣粒子3的平均粒徑的2/5以下(也包括L2=0),就平均值而言,絕緣粒子3(特別是部分露出粒子3a)之中,位於第二絕緣層2b內的部分大於露出的部分,而有利於抑制絕緣粒子3的脫落。 If the second height difference L2 is 2/5 or less of the average particle diameter of the insulating particles 3 (including L2 = 0), the average value of the insulating particles 3 (particularly partially exposed particles 3a) is in the second The portion in the insulating layer 2b is larger than the exposed portion, and it is advantageous to suppress the falling off of the insulating particles 3.
若第二高低差L2未達絕緣粒子3的平均粒徑的1/10,則會強烈受到將第二絕緣層2b熱固化時產生的脆弱的表面層的影響,而可能導致第二配線導體5b與第二絕緣層2b的密接性變得不充分。而且,在藉由蝕刻來除去第二絕緣層2b表面的第二基底金屬層4b時,蝕刻液容易侵入第二配線導體5b正下方的第二基底金屬層4b,而有第二配線導體5b變得容易剝落的可能性。 If the second height difference L2 does not reach 1/10 of the average particle diameter of the insulating particles 3, it is strongly affected by the fragile surface layer generated when the second insulating layer 2b is thermally cured, and may cause the second wiring conductor 5b. The adhesion to the second insulating layer 2b is insufficient. Further, when the second base metal layer 4b on the surface of the second insulating layer 2b is removed by etching, the etching liquid easily intrudes into the second base metal layer 4b directly under the second wiring conductor 5b, and the second wiring conductor 5b becomes The possibility of being easily peeled off.
若第二高低差L2為絕緣粒子3的平均粒徑的2/5以下且1/10以上,則能夠得到適於在第二絕緣層2b的表面形成第二配線導體5b的樹脂表面狀態。因此,有利於謀求提高第二絕緣層2b與第二配線導體5b的密著強度且形成高頻信號的傳送特性優異的配線。 When the second height difference L2 is 2/5 or less and 1/10 or more of the average particle diameter of the insulating particles 3, a resin surface state suitable for forming the second wiring conductor 5b on the surface of the second insulating layer 2b can be obtained. Therefore, it is advantageous to improve the adhesion strength between the second insulating layer 2b and the second wiring conductor 5b and to form a wiring having excellent transmission characteristics of a high-frequency signal.
若第二高低差L2超過絕緣粒子3的平均粒徑的2/5,則位於第二絕緣層2b的絕緣粒子3容易脫落。此時,第二絕緣層2b的表層的凹凸變大,微細配線加工變得困難。而且,會強烈受到第二絕緣層2b的表層的凹凸的影響,導致第二配線導體5b表面的凹凸變大,而有高頻信號的傳送特性下降的可能。 When the second height difference L2 exceeds 2/5 of the average particle diameter of the insulating particles 3, the insulating particles 3 located in the second insulating layer 2b are liable to fall off. At this time, the unevenness of the surface layer of the second insulating layer 2b is increased, and the fine wiring processing becomes difficult. Further, it is strongly affected by the unevenness of the surface layer of the second insulating layer 2b, and the unevenness of the surface of the second wiring conductor 5b is increased, and the transmission characteristics of the high-frequency signal may be lowered.
第一高低差L1可相對於絕緣粒子3的粒徑任意設定。從抑制位於第一絕緣層2a的絕緣粒子3的脫落的觀點來考量,較佳為絕緣粒子3的平均粒徑的4/5以下。 The first height difference L1 can be arbitrarily set with respect to the particle diameter of the insulating particles 3. From the viewpoint of suppressing the fall of the insulating particles 3 located in the first insulating layer 2a, it is preferable that the insulating particles 3 have an average particle diameter of 4/5 or less.
本揭示的配線基板20由於第二基底金屬層4b位於積層用絕緣層2的表面起至表層內,因此積層用絕緣層2與第二基底金屬層4b的密著強度強。由此,位於第二基底金屬層4b上的第二配線導體5b與積層用絕緣層2的密著強度也變強。 In the wiring board 20 of the present disclosure, since the second base metal layer 4b is located in the surface layer of the surface of the insulating layer 2 for the buildup layer, the adhesion strength between the insulating layer 2 for the buildup layer and the second base metal layer 4b is strong. Thereby, the adhesion strength between the second wiring conductor 5b located on the second underlying metal layer 4b and the insulating layer for the buildup layer also becomes strong.
上述的實施型態的一例中,揭示了第一基底金屬層4a由無電鍍銅構成的一例,但也可與第二基底金屬層4b同樣地包括金屬層,該金屬層係例如包含鈦等屬元素週期表中的第4族的金屬或鉻及鉬等屬元素週期表中的第6族的金屬。 In an example of the above-described embodiment, the first base metal layer 4a is exemplified by electroless copper plating. However, the second base metal layer 4a may include a metal layer similar to the second base metal layer 4b, and the metal layer may include, for example, titanium. The metal of Group 4 of the periodic table or the metal of Group 6 of the periodic table of elements such as chromium and molybdenum.
第一基底金屬層4a包括屬第4族或第6族的金屬層的情況下,第一基底金屬層4a係位於第一絕緣層2a的表面起,至厚度方向小於600nm的深度的表層內。此情況下,有利於提高第一絕緣層2a與第一配線導體5a的密著強度。 In the case where the first base metal layer 4a includes a metal layer belonging to Group 4 or Group 6, the first base metal layer 4a is located in the surface layer of the first insulating layer 2a to a depth of less than 600 nm in the thickness direction. In this case, it is advantageous to increase the adhesion strength between the first insulating layer 2a and the first wiring conductor 5a.
如第5圖所示,亦可在第二貫孔8b的壁面與第二基底金屬層4b之間設置中間層9。中間層9係包含例如第二絕緣層2b的一部分、絕緣粒子3、及含有銅的金屬層。含有銅的金屬層係包括構成位於第二貫孔8b內的第二配線導體5b的金屬層的一部分。第二貫孔8b的壁面中,隔著第二基底金屬層4b來設置皆含有銅的第二配線導體5b與中間層9。中間層9中的金屬層僅存在於與中間層9整體相同程度的範圍,因此省略圖示。 As shown in Fig. 5, an intermediate layer 9 may be provided between the wall surface of the second through hole 8b and the second base metal layer 4b. The intermediate layer 9 includes, for example, a part of the second insulating layer 2b, insulating particles 3, and a metal layer containing copper. The copper-containing metal layer includes a portion of the metal layer constituting the second wiring conductor 5b located in the second through hole 8b. In the wall surface of the second through hole 8b, the second wiring conductor 5b and the intermediate layer 9 both containing copper are provided via the second base metal layer 4b. The metal layer in the intermediate layer 9 exists only in the same extent as the entire intermediate layer 9, and thus the illustration is omitted.
中間層9的厚度係設定為例如100~1000nm左右。若小於100nm時,可能無法期望第二配線導體5b與第二貫孔8b的密著力的提高。若大於1000nm時,第二貫孔8b彼此之間的絕緣可靠性可能會下降。 The thickness of the intermediate layer 9 is set to, for example, about 100 to 1000 nm. If it is less than 100 nm, the adhesion of the second wiring conductor 5b and the second through hole 8b may not be expected to be improved. If it is more than 1000 nm, the insulation reliability of the second through holes 8b may be lowered from each other.
此種中間層9可如下地形成。首先,藉由雷射加工,於第二絕緣層2b形成以配線導體5為底面的孔。此時,由於雷射加工時的熱而,在孔的壁面形成微細的凹凸。凹凸的表面係由第二絕緣層2b及絕緣粒子3構成。凹凸的程度係設定成最大高度為300~500nm左右。雷射加工條件係例如將照射能量設定為0.05~0.7W。而且,若進一步限定,則於0.1~0.3W的範圍,能夠更顯著地顯現本 案技術。 Such an intermediate layer 9 can be formed as follows. First, a hole having the wiring conductor 5 as a bottom surface is formed in the second insulating layer 2b by laser processing. At this time, fine irregularities are formed on the wall surface of the hole due to heat during laser processing. The surface of the unevenness is composed of the second insulating layer 2b and the insulating particles 3. The degree of unevenness is set to a maximum height of about 300 to 500 nm. The laser processing conditions are, for example, setting the irradiation energy to 0.05 to 0.7 W. Further, if it is further limited, the present technique can be more prominently exhibited in the range of 0.1 to 0.3 W.
接下來,藉由除污處理清洗孔的內表面,而形成第二貫孔8b。除污處理條件係例如將包含濃度0.2~0.5mol/l的過猛酸鹽與鹼金屬氫氧化物的藥液調整成溫度30~80℃,進行時間為0.5~10分鐘的處理。 Next, the inner surface of the cleaning hole is cleaned by the desmear process to form the second through hole 8b. The desmear treatment conditions are, for example, a treatment containing a perchloric acid salt having a concentration of 0.2 to 0.5 mol/l and an alkali metal hydroxide to a temperature of 30 to 80 ° C, and a treatment time of 0.5 to 10 minutes.
接下來,在第二貫孔8b的壁面及配線導體5的表面形成第二基底金屬層4b。第二基底金屬層4b的厚度係以不會完全覆蓋孔的壁面的凹凸之方式,將元素週期表中屬第4族或第6族的金屬層的厚度設定為例如5~20nm左右,將銅的厚度設定為50~150nm左右。 Next, a second base metal layer 4b is formed on the wall surface of the second through hole 8b and the surface of the wiring conductor 5. The thickness of the second base metal layer 4b is such that the thickness of the metal layer belonging to Group 4 or Group 6 of the periodic table is set to, for example, about 5 to 20 nm, so as not to completely cover the unevenness of the wall surface of the hole. The thickness is set to be about 50 to 150 nm.
最後,藉由半加成法,在第二貫孔8b內形成含有銅的第二配線導體5b。此時,構成第二配線導體5b的金屬層的一部分也經由第二基底金屬層4b而進入孔的壁面的凹凸,密著於構成凹凸表面的第二絕緣層2b及絕緣粒子3。此第二絕緣層2b的凹凸部分、絕緣粒子3及進入的金屬層成為層狀。由此,形成包含第二絕緣層2b的一部分、絕緣粒子3及含有銅的金屬層的中間層9。 Finally, a second wiring conductor 5b containing copper is formed in the second through hole 8b by a semi-additive method. At this time, a part of the metal layer constituting the second wiring conductor 5b also enters the unevenness on the wall surface of the hole via the second base metal layer 4b, and adheres to the second insulating layer 2b and the insulating particles 3 constituting the uneven surface. The uneven portion of the second insulating layer 2b, the insulating particles 3, and the incoming metal layer are layered. Thereby, the intermediate layer 9 including a part of the second insulating layer 2b, the insulating particles 3, and the metal layer containing copper is formed.
如此,構成第二配線導體5b的金屬層的一部分係以經由第二基底金屬層4b而密著於第二絕緣層2b及絕緣粒子3的狀態而位於中間層9中。位於中間層9的金屬層與構成第二配線導體5b的金屬層係由連續的結晶構成。因此,即使是如第二貫孔8b之接觸面積小的小徑貫孔8,第二配線導體5b也能夠以較大的密著力位於其中。 As described above, a part of the metal layer constituting the second wiring conductor 5b is placed in the intermediate layer 9 in a state of being adhered to the second insulating layer 2b and the insulating particles 3 via the second underlying metal layer 4b. The metal layer located in the intermediate layer 9 and the metal layer constituting the second wiring conductor 5b are composed of continuous crystals. Therefore, even if the small through hole 8 having a small contact area with the second through hole 8b, the second wiring conductor 5b can be positioned with a large adhesion.
中間層9除了位於第二貫孔8b的壁面之外, 也可位於底面的周邊。此種底面周邊的中間層9係存在於例如距底面最大為6μm的範圍內。這種情況下,有利於提高第二配線導體5b與第二貫孔8b的密著力。 The intermediate layer 9 may be located at the periphery of the bottom surface in addition to the wall surface of the second through hole 8b. The intermediate layer 9 around the bottom surface is present, for example, in a range of up to 6 μm from the bottom surface. In this case, it is advantageous to increase the adhesion of the second wiring conductor 5b and the second through hole 8b.
中間層9也可位於第一貫孔8a的壁面與第一基底金屬層4a之間。這種情況下,有利於提高第一配線導體5a與第一貫孔8a的密著力。 The intermediate layer 9 may also be located between the wall surface of the first through hole 8a and the first base metal layer 4a. In this case, it is advantageous to increase the adhesion of the first wiring conductor 5a and the first through hole 8a.
本揭示不限於上述的實施型態的一例,在申請專利範圍所記載的範圍內,能夠進行各種變更、改良。 The present disclosure is not limited to the above-described embodiment, and various modifications and improvements can be made within the scope of the claims.
Claims (11)
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JP2017-207874 | 2017-10-27 | ||
JP2017207874 | 2017-10-27 | ||
JP2018-009458 | 2018-01-24 | ||
JP2018009458A JP7011946B2 (en) | 2017-10-27 | 2018-01-24 | Wiring board |
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TW201924006A true TW201924006A (en) | 2019-06-16 |
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TW107133418A TWI665772B (en) | 2017-10-27 | 2018-09-21 | Wiring substrate |
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JP7273660B2 (en) * | 2019-08-30 | 2023-05-15 | キオクシア株式会社 | Semiconductor manufacturing equipment and method for manufacturing semiconductor device |
CN221353197U (en) * | 2021-05-31 | 2024-07-16 | 株式会社村田制作所 | Terminal structure and electronic component |
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EP1843649A3 (en) * | 1998-09-03 | 2007-10-31 | Ibiden Co., Ltd. | Multilayered printed circuit board and manufacturing method therefor |
JP4392157B2 (en) * | 2001-10-26 | 2009-12-24 | パナソニック電工株式会社 | WIRING BOARD SHEET MATERIAL AND ITS MANUFACTURING METHOD, AND MULTILAYER BOARD AND ITS MANUFACTURING METHOD |
JP2004328006A (en) * | 2004-06-07 | 2004-11-18 | Ngk Spark Plug Co Ltd | Wiring board and manufacturing method for the same |
JP2007189216A (en) * | 2005-12-16 | 2007-07-26 | Sumitomo Bakelite Co Ltd | Method of manufacturing multilayer wiring board |
JP5562121B2 (en) * | 2010-05-28 | 2014-07-30 | 京セラ株式会社 | Interposer and mounting structure using the same |
KR20130001981A (en) * | 2011-06-28 | 2013-01-07 | 삼성전기주식회사 | Dielectirc composition, multilayered printed circuit board comprising dielectric layer manufactured thereof, and method for preparing the multilayered printed circuit board |
JP2013149810A (en) * | 2012-01-20 | 2013-08-01 | Ngk Spark Plug Co Ltd | Manufacturing method of multilayer wiring board |
JP2014175485A (en) * | 2013-03-08 | 2014-09-22 | Ibiden Co Ltd | Wiring board and manufacturing method of the same |
JP6169955B2 (en) * | 2013-04-17 | 2017-07-26 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
JP2016025217A (en) * | 2014-07-22 | 2016-02-08 | 日立化成株式会社 | Printed wiring board, method for manufacturing the same, thermosetting resin composition, and resin film |
JP6409390B2 (en) * | 2014-07-28 | 2018-10-24 | 住友ベークライト株式会社 | Wiring board, semiconductor package, electronic device, manufacturing method of wiring board, and manufacturing method of semiconductor package |
JP6473619B2 (en) * | 2014-12-25 | 2019-02-20 | イビデン株式会社 | Manufacturing method of wiring board with cavity |
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TWI665772B (en) | 2019-07-11 |
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